target/linux/ramips/dts/mt7621.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/mips-gic.h>
   4 #include <dt-bindings/clock/mt7621-clk.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6
   7 / {
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         compatible = "mediatek,mt7621-soc";
  11
  12         aliases {
  13                 serial0 = &uartlite;
  14         };
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "mips,mips1004Kc";
  23                         reg = <0>;
  24                 };
  25
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "mips,mips1004Kc";
  29                         reg = <1>;
  30                 };
  31         };
  32
  33         cpuintc: cpuintc {
  34                 #address-cells = <0>;
  35                 #interrupt-cells = <1>;
  36                 interrupt-controller;
  37                 compatible = "mti,cpu-interrupt-controller";
  38         };
  39
  40         chosen {
  41                 bootargs = "console=ttyS0,57600";
  42         };
  43
  44 #ifdef DTS_LEGACY
  45         pll: pll {
  46                 compatible = "mediatek,mt7621-pll", "syscon";
  47
  48                 #clock-cells = <1>;
  49                 clock-output-names = "cpu", "bus";
  50         };
  51 #endif
  52
  53         sysclock: sysclock {
  54                 #clock-cells = <0>;
  55                 compatible = "fixed-clock";
  56
  57                 /* FIXME: there should be way to detect this */
  58                 clock-frequency = <50000000>;
  59         };
  60
  61         palmbus: palmbus@1e000000 {
  62                 compatible = "palmbus";
  63                 reg = <0x1e000000 0x100000>;
  64                 ranges = <0x0 0x1e000000 0x0fffff>;
  65
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68
  69                 sysc: syscon@0 {
  70 #ifdef DTS_LEGACY
  71                         compatible = "mtk,mt7621-sysc", "syscon";
  72 #else
  73                         compatible = "mediatek,mt7621-sysc", "syscon";
  74                         #clock-cells = <1>;
  75                         ralink,memctl = <&memc>;
  76                         clock-output-names = "xtal", "cpu", "bus",
  77                                              "50m", "125m", "150m",
  78                                              "250m", "270m";
  79 #endif
  80                         reg = <0x0 0x100>;
  81                 };
  82
  83                 wdt: wdt@100 {
  84                         compatible = "mediatek,mt7621-wdt";
  85                         reg = <0x100 0x100>;
  86                 };
  87
  88                 gpio: gpio@600 {
  89                         #gpio-cells = <2>;
  90                         #interrupt-cells = <2>;
  91                         compatible = "mediatek,mt7621-gpio";
  92                         gpio-controller;
  93                         gpio-ranges = <&pinctrl 0 0 95>;
  94                         interrupt-controller;
  95                         reg = <0x600 0x100>;
  96                         interrupt-parent = <&gic>;
  97                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  98                 };
  99
 100                 i2c: i2c@900 {
 101                         compatible = "mediatek,mt7621-i2c";
 102                         reg = <0x900 0x100>;
 103
 104                         clocks = <&sysclock>;
 105
 106                         resets = <&rstctrl 16>;
 107                         reset-names = "i2c";
 108
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111
 112                         status = "disabled";
 113
 114                         pinctrl-names = "default";
 115                         pinctrl-0 = <&i2c_pins>;
 116                 };
 117
 118                 i2s: i2s@a00 {
 119                         compatible = "mediatek,mt7621-i2s";
 120                         reg = <0xa00 0x100>;
 121
 122                         clocks = <&sysclock>;
 123
 124                         resets = <&rstctrl 17>;
 125                         reset-names = "i2s";
 126
 127                         interrupt-parent = <&gic>;
 128                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 129
 130                         txdma-req = <2>;
 131                         rxdma-req = <3>;
 132
 133                         dmas = <&gdma 4>,
 134                                 <&gdma 6>;
 135                         dma-names = "tx", "rx";
 136
 137                         status = "disabled";
 138                 };
 139
 140                 systick: systick@500 {
 141                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 142                         reg = <0x500 0x10>;
 143
 144                         resets = <&rstctrl 28>;
 145                         reset-names = "intc";
 146
 147                         interrupt-parent = <&gic>;
 148                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 149                 };
 150
 151                 memc: syscon@5000 {
 152 #ifdef DTS_LEGACY
 153                         compatible = "mtk,mt7621-memc", "syscon";
 154 #else
 155                         compatible = "mediatek,mt7621-memc", "syscon";
 156 #endif
 157                         reg = <0x5000 0x1000>;
 158                 };
 159
 160                 uartlite: uartlite@c00 {
 161                         compatible = "ns16550a";
 162                         reg = <0xc00 0x100>;
 163
 164                         clock-frequency = <50000000>;
 165
 166                         interrupt-parent = <&gic>;
 167                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 168
 169                         reg-shift = <2>;
 170                         reg-io-width = <4>;
 171                         no-loopback-test;
 172                 };
 173
 174                 uartlite2: uartlite2@d00 {
 175                         compatible = "ns16550a";
 176                         reg = <0xd00 0x100>;
 177
 178                         clock-frequency = <50000000>;
 179
 180                         interrupt-parent = <&gic>;
 181                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 182
 183                         reg-shift = <2>;
 184                         reg-io-width = <4>;
 185
 186                         pinctrl-names = "default";
 187                         pinctrl-0 = <&uart2_pins>;
 188
 189                         status = "disabled";
 190                 };
 191
 192                 uartlite3: uartlite3@e00 {
 193                         compatible = "ns16550a";
 194                         reg = <0xe00 0x100>;
 195
 196                         clock-frequency = <50000000>;
 197
 198                         interrupt-parent = <&gic>;
 199                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 200
 201                         reg-shift = <2>;
 202                         reg-io-width = <4>;
 203
 204                         pinctrl-names = "default";
 205                         pinctrl-0 = <&uart3_pins>;
 206
 207                         status = "disabled";
 208                 };
 209
 210                 spi0: spi@b00 {
 211                         status = "disabled";
 212
 213                         compatible = "ralink,mt7621-spi";
 214                         reg = <0xb00 0x100>;
 215
 216 #ifdef DTS_LEGACY
 217                         clocks = <&pll MT7621_CLK_BUS>;
 218 #else
 219                         clocks = <&sysc MT7621_CLK_BUS>;
 220 #endif
 221
 222                         resets = <&rstctrl 18>;
 223                         reset-names = "spi";
 224
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227
 228                         pinctrl-names = "default";
 229                         pinctrl-0 = <&spi_pins>;
 230                 };
 231
 232                 gdma: gdma@2800 {
 233                         compatible = "ralink,rt3883-gdma";
 234                         reg = <0x2800 0x800>;
 235
 236                         resets = <&rstctrl 14>;
 237                         reset-names = "dma";
 238
 239                         interrupt-parent = <&gic>;
 240                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 241
 242                         #dma-cells = <1>;
 243                         #dma-channels = <16>;
 244                         #dma-requests = <16>;
 245
 246                         status = "disabled";
 247                 };
 248
 249                 hsdma: hsdma@7000 {
 250                         compatible = "mediatek,mt7621-hsdma";
 251                         reg = <0x7000 0x1000>;
 252
 253                         resets = <&rstctrl 5>;
 254                         reset-names = "hsdma";
 255
 256                         interrupt-parent = <&gic>;
 257                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 258
 259                         #dma-cells = <1>;
 260                         #dma-channels = <1>;
 261                         #dma-requests = <1>;
 262
 263                         status = "disabled";
 264                 };
 265         };
 266
 267         pinctrl: pinctrl {
 268                 compatible = "ralink,rt2880-pinmux";
 269                 pinctrl-names = "default";
 270                 pinctrl-0 = <&state_default>;
 271
 272                 state_default: pinctrl0 {
 273                 };
 274
 275                 i2c_pins: i2c_pins {
 276                         i2c_pins {
 277                                 groups = "i2c";
 278                                 function = "i2c";
 279                         };
 280                 };
 281
 282                 spi_pins: spi_pins {
 283                         spi_pins {
 284                                 groups = "spi";
 285                                 function = "spi";
 286                         };
 287                 };
 288
 289                 uart1_pins: uart1 {
 290                         uart1 {
 291                                 groups = "uart1";
 292                                 function = "uart1";
 293                         };
 294                 };
 295
 296                 uart2_pins: uart2 {
 297                         uart2 {
 298                                 groups = "uart2";
 299                                 function = "uart2";
 300                         };
 301                 };
 302
 303                 uart3_pins: uart3 {
 304                         uart3 {
 305                                 groups = "uart3";
 306                                 function = "uart3";
 307                         };
 308                 };
 309
 310                 rgmii1_pins: rgmii1 {
 311                         rgmii1 {
 312                                 groups = "rgmii1";
 313                                 function = "rgmii1";
 314                         };
 315                 };
 316
 317                 rgmii2_pins: rgmii2 {
 318                         rgmii2 {
 319                                 groups = "rgmii2";
 320                                 function = "rgmii2";
 321                         };
 322                 };
 323
 324                 mdio_pins: mdio {
 325                         mdio {
 326                                 groups = "mdio";
 327                                 function = "mdio";
 328                         };
 329                 };
 330
 331                 pcie_pins: pcie {
 332                         pcie {
 333                                 groups = "pcie";
 334                                 function = "gpio";
 335                         };
 336                 };
 337
 338                 nand_pins: nand {
 339                         spi-nand {
 340                                 groups = "spi";
 341                                 function = "nand1";
 342                         };
 343
 344                         sdhci-nand {
 345                                 groups = "sdhci";
 346                                 function = "nand2";
 347                         };
 348                 };
 349
 350                 sdhci_pins: sdhci {
 351                         sdhci {
 352                                 groups = "sdhci";
 353                                 function = "sdhci";
 354                         };
 355                 };
 356         };
 357
 358         rstctrl: rstctrl {
 359                 compatible = "ralink,rt2880-reset";
 360                 #reset-cells = <1>;
 361         };
 362
 363         clkctrl: clkctrl {
 364                 compatible = "ralink,rt2880-clock";
 365                 #clock-cells = <1>;
 366         };
 367
 368         sdhci: sdhci@1e130000 {
 369                 status = "disabled";
 370
 371                 compatible = "ralink,mt7620-sdhci";
 372                 reg = <0x1e130000 0x4000>;
 373
 374                 interrupt-parent = <&gic>;
 375                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 376
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&sdhci_pins>;
 379         };
 380
 381         xhci: xhci@1e1c0000 {
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384
 385                 compatible = "mediatek,mt8173-xhci";
 386                 reg = <0x1e1c0000 0x1000
 387                        0x1e1d0700 0x0100>;
 388                 reg-names = "mac", "ippc";
 389
 390                 clocks = <&sysclock>;
 391                 clock-names = "sys_ck";
 392
 393                 interrupt-parent = <&gic>;
 394                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 395
 396                 /*
 397                  * Port 1 of both hubs is one usb slot and referenced here.
 398                  * The binding doesn't allow to address individual hubs.
 399                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 400                  */
 401                 xhci_ehci_port1: port@1 {
 402                         reg = <1>;
 403                         #trigger-source-cells = <0>;
 404                 };
 405
 406                 /*
 407                  * Only the second usb hub has a second port. That port serves
 408                  * ehci and ohci.
 409                  */
 410                 ehci_port2: port@2 {
 411                         reg = <2>;
 412                         #trigger-source-cells = <0>;
 413                 };
 414         };
 415
 416         gic: interrupt-controller@1fbc0000 {
 417                 compatible = "mti,gic";
 418                 reg = <0x1fbc0000 0x2000>;
 419
 420                 interrupt-controller;
 421                 #interrupt-cells = <3>;
 422
 423                 mti,reserved-cpu-vectors = <7>;
 424
 425                 timer {
 426                         compatible = "mti,gic-timer";
 427                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 428 #ifdef DTS_LEGACY
 429                         clocks = <&pll MT7621_CLK_CPU>;
 430 #else
 431                         clocks = <&sysc MT7621_CLK_CPU>;
 432 #endif
 433                 };
 434         };
 435
 436         nficlock: nficlock {
 437                 #clock-cells = <0>;
 438                 compatible = "fixed-clock";
 439
 440                 clock-frequency = <125000000>;
 441         };
 442
 443         cpc: cpc@1fbf0000 {
 444                 compatible = "mti,mips-cpc";
 445                 reg = <0x1fbf0000 0x8000>;
 446         };
 447
 448         mc: mc@1fbf8000 {
 449                 compatible = "mti,mips-cdmm";
 450                 reg = <0x1fbf8000 0x8000>;
 451         };
 452
 453         nand: nand@1e003000 {
 454                 status = "disabled";
 455
 456                 compatible = "mediatek,mt7621-nfc";
 457                 reg = <0x1e003000 0x800
 458                         0x1e003800 0x800>;
 459                 reg-names = "nfi", "ecc";
 460
 461                 clocks = <&nficlock>;
 462                 clock-names = "nfi_clk";
 463         };
 464
 465         ethernet: ethernet@1e100000 {
 466                 compatible = "mediatek,mt7621-eth";
 467                 reg = <0x1e100000 0x10000>;
 468
 469 #ifdef DTS_LEGACY
 470                 clocks = <&sysclock>;
 471                 clock-names = "ethif";
 472 #else
 473                 clocks = <&sysc MT7621_CLK_FE>,
 474                          <&sysc MT7621_CLK_ETH>;
 475                 clock-names = "fe", "ethif";
 476 #endif
 477
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480
 481                 resets = <&rstctrl 6>, <&rstctrl 23>;
 482                 reset-names = "fe", "eth";
 483
 484                 interrupt-parent = <&gic>;
 485                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 486
 487                 mediatek,ethsys = <&sysc>;
 488
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
 491
 492                 gmac0: mac@0 {
 493                         compatible = "mediatek,eth-mac";
 494                         reg = <0>;
 495                         phy-mode = "rgmii";
 496
 497                         fixed-link {
 498                                 speed = <1000>;
 499                                 full-duplex;
 500                                 pause;
 501                         };
 502                 };
 503
 504                 gmac1: mac@1 {
 505                         compatible = "mediatek,eth-mac";
 506                         reg = <1>;
 507                         status = "disabled";
 508                         phy-mode = "rgmii";
 509                 };
 510
 511                 mdio: mdio-bus {
 512                         #address-cells = <1>;
 513                         #size-cells = <0>;
 514
 515                         switch0: switch@1f {
 516                                 compatible = "mediatek,mt7621";
 517                                 reg = <0x1f>;
 518                                 mediatek,mcm;
 519                                 resets = <&rstctrl 2>;
 520                                 reset-names = "mcm";
 521                                 interrupt-controller;
 522                                 #interrupt-cells = <1>;
 523                                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 524
 525                                 ports {
 526                                         #address-cells = <1>;
 527                                         #size-cells = <0>;
 528
 529                                         port@0 {
 530                                                 status = "disabled";
 531                                                 reg = <0>;
 532                                                 label = "lan0";
 533                                         };
 534
 535                                         port@1 {
 536                                                 status = "disabled";
 537                                                 reg = <1>;
 538                                                 label = "lan1";
 539                                         };
 540
 541                                         port@2 {
 542                                                 status = "disabled";
 543                                                 reg = <2>;
 544                                                 label = "lan2";
 545                                         };
 546
 547                                         port@3 {
 548                                                 status = "disabled";
 549                                                 reg = <3>;
 550                                                 label = "lan3";
 551                                         };
 552
 553                                         port@4 {
 554                                                 status = "disabled";
 555                                                 reg = <4>;
 556                                                 label = "lan4";
 557                                         };
 558
 559                                         port@6 {
 560                                                 reg = <6>;
 561                                                 ethernet = <&gmac0>;
 562                                                 phy-mode = "rgmii";
 563
 564                                                 fixed-link {
 565                                                         speed = <1000>;
 566                                                         full-duplex;
 567                                                         pause;
 568                                                 };
 569                                         };
 570                                 };
 571                         };
 572                 };
 573         };
 574
 575         pcie: pcie@1e140000 {
 576                 compatible = "mediatek,mt7621-pci";
 577                 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
 578                       <0x1e142000 0x100>, /* pcie port 0 RC control registers */
 579                       <0x1e143000 0x100>, /* pcie port 1 RC control registers */
 580                       <0x1e144000 0x100>; /* pcie port 2 RC control registers */
 581                 #address-cells = <3>;
 582                 #size-cells = <2>;
 583
 584                 pinctrl-names = "default";
 585                 pinctrl-0 = <&pcie_pins>;
 586
 587                 device_type = "pci";
 588
 589 #ifdef DTS_LEGACY
 590                 ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */
 591                          <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
 592 #else
 593                 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
 594                          <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
 595 #endif
 596
 597                 status = "disabled";
 598
 599 #ifdef DTS_LEGACY
 600                 interrupt-parent = <&gic>;
 601                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 602                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 603                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 604
 605
 606                 resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;
 607                 reset-names = "pcie0", "pcie1", "pcie2";
 608                 clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>;
 609                 clock-names = "pcie0", "pcie1", "pcie2";
 610                 phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
 611                 phy-names = "pcie-phy0", "pcie-phy2";
 612 #else
 613                 #interrupt-cells = <1>;
 614                 interrupt-map-mask = <0xF800 0 0 0>;
 615                 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
 616                                 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
 617                                 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 618 #endif
 619
 620                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 621
 622                 pcie0: pcie@0,0 {
 623                         reg = <0x0000 0 0 0 0>;
 624                         #address-cells = <3>;
 625                         #size-cells = <2>;
 626                         device_type = "pci";
 627                         ranges;
 628 #ifndef DTS_LEGACY
 629                         #interrupt-cells = <1>;
 630                         interrupt-map-mask = <0 0 0 0>;
 631                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
 632                         resets = <&rstctrl 24>;
 633                         clocks = <&sysc MT7621_CLK_PCIE0>;
 634                         phys = <&pcie0_phy 1>;
 635                         phy-names = "pcie-phy0";
 636 #endif
 637                 };
 638
 639                 pcie1: pcie@1,0 {
 640                         reg = <0x0800 0 0 0 0>;
 641                         #address-cells = <3>;
 642                         #size-cells = <2>;
 643                         device_type = "pci";
 644                         ranges;
 645 #ifndef DTS_LEGACY
 646                         #interrupt-cells = <1>;
 647                         interrupt-map-mask = <0 0 0 0>;
 648                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
 649                         resets = <&rstctrl 25>;
 650                         clocks = <&sysc MT7621_CLK_PCIE1>;
 651                         phys = <&pcie0_phy 1>;
 652                         phy-names = "pcie-phy1";
 653 #endif
 654                 };
 655
 656                 pcie2: pcie@2,0 {
 657                         reg = <0x1000 0 0 0 0>;
 658                         #address-cells = <3>;
 659                         #size-cells = <2>;
 660                         device_type = "pci";
 661                         ranges;
 662 #ifndef DTS_LEGACY
 663                         #interrupt-cells = <1>;
 664                         interrupt-map-mask = <0 0 0 0>;
 665                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 666                         resets = <&rstctrl 26>;
 667                         clocks = <&sysc MT7621_CLK_PCIE2>;
 668                         phys = <&pcie2_phy 0>;
 669                         phy-names = "pcie-phy2";
 670 #endif
 671                 };
 672         };
 673
 674         pcie0_phy: pcie-phy@1e149000 {
 675                 compatible = "mediatek,mt7621-pci-phy";
 676                 reg = <0x1e149000 0x0700>;
 677 #ifndef DTS_LEGACY
 678                 clocks = <&sysc MT7621_CLK_XTAL>;
 679 #endif
 680                 #phy-cells = <1>;
 681         };
 682
 683         pcie2_phy: pcie-phy@1e14a000 {
 684                 compatible = "mediatek,mt7621-pci-phy";
 685                 reg = <0x1e14a000 0x0700>;
 686 #ifndef DTS_LEGACY
 687                 clocks = <&sysc MT7621_CLK_XTAL>;
 688 #endif
 689                 #phy-cells = <1>;
 690         };
 691 };