bf25140e971111f01f2b8113df3d93f7d94a78c9
[openwrt/staging/dedeckeh.git] / target / linux / realtek / dts-5.10 / rtl8382_d-link_dgs-1210-28.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "rtl8382_d-link_dgs-1210.dtsi"
4
5 / {
6 compatible = "d-link,dgs-1210-28", "realtek,rtl838x-soc";
7 model = "D-Link DGS-1210-28";
8
9 keys {
10 compatible = "gpio-keys-polled";
11 poll-interval = <20>;
12
13 reset {
14 label = "reset";
15 gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
16 linux,code = <KEY_RESTART>;
17 };
18 };
19
20 gpio1: rtl8231-gpio {
21 compatible = "realtek,rtl8231-gpio";
22 #gpio-cells = <2>;
23 gpio-controller;
24 indirect-access-bus-id = <0>;
25 };
26 };
27
28 &ethernet0 {
29 mdio: mdio-bus {
30 compatible = "realtek,rtl838x-mdio";
31 regmap = <&ethernet0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 EXTERNAL_PHY(0)
36 EXTERNAL_PHY(1)
37 EXTERNAL_PHY(2)
38 EXTERNAL_PHY(3)
39 EXTERNAL_PHY(4)
40 EXTERNAL_PHY(5)
41 EXTERNAL_PHY(6)
42 EXTERNAL_PHY(7)
43
44 INTERNAL_PHY(8)
45 INTERNAL_PHY(9)
46 INTERNAL_PHY(10)
47 INTERNAL_PHY(11)
48 INTERNAL_PHY(12)
49 INTERNAL_PHY(13)
50 INTERNAL_PHY(14)
51 INTERNAL_PHY(15)
52
53 EXTERNAL_PHY(16)
54 EXTERNAL_PHY(17)
55 EXTERNAL_PHY(18)
56 EXTERNAL_PHY(19)
57 EXTERNAL_PHY(20)
58 EXTERNAL_PHY(21)
59 EXTERNAL_PHY(22)
60 EXTERNAL_PHY(23)
61
62 EXTERNAL_SFP_PHY(24)
63 EXTERNAL_SFP_PHY(25)
64 EXTERNAL_SFP_PHY(26)
65 EXTERNAL_SFP_PHY(27)
66 };
67 };
68
69 &switch0 {
70 ports {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 SWITCH_PORT(0, 1, qsgmii)
75 SWITCH_PORT(1, 2, qsgmii)
76 SWITCH_PORT(2, 3, qsgmii)
77 SWITCH_PORT(3, 4, qsgmii)
78 SWITCH_PORT(4, 5, qsgmii)
79 SWITCH_PORT(5, 6, qsgmii)
80 SWITCH_PORT(6, 7, qsgmii)
81 SWITCH_PORT(7, 8, qsgmii)
82
83 SWITCH_PORT(8, 9, internal)
84 SWITCH_PORT(9, 10, internal)
85 SWITCH_PORT(10, 11, internal)
86 SWITCH_PORT(11, 12, internal)
87 SWITCH_PORT(12, 13, internal)
88 SWITCH_PORT(13, 14, internal)
89 SWITCH_PORT(14, 15, internal)
90 SWITCH_PORT(15, 16, internal)
91
92 SWITCH_PORT(16, 17, qsgmii)
93 SWITCH_PORT(17, 18, qsgmii)
94 SWITCH_PORT(18, 19, qsgmii)
95 SWITCH_PORT(19, 20, qsgmii)
96 SWITCH_PORT(20, 21, qsgmii)
97 SWITCH_PORT(21, 22, qsgmii)
98 SWITCH_PORT(22, 23, qsgmii)
99 SWITCH_PORT(23, 24, qsgmii)
100
101 SWITCH_PORT(24, 25, qsgmii)
102 SWITCH_PORT(25, 26, qsgmii)
103 SWITCH_PORT(26, 27, qsgmii)
104 SWITCH_PORT(27, 28, qsgmii)
105
106 port@28 {
107 ethernet = <&ethernet0>;
108 reg = <28>;
109 phy-mode = "internal";
110 fixed-link {
111 speed = <1000>;
112 full-duplex;
113 };
114 };
115 };
116 };