uclibc: disable rpc support - replaced by the external librpc, saves ~80k
[openwrt/staging/dedeckeh.git] / toolchain / uClibc / patches-0.9.32 / 910-thumb_blind_options.patch
1 Add three new blind options to set use of Thumb mode:
2 - COMPILE_IN_THUMB_MODE
3 - if set, CFLAGS will contain -mthumb
4 - if unset, the compiler's default is used
5 - HAS_THUMB
6 - CPUS with Thumb instruction set can select this
7 - use of BX depends on this
8 - FORCE_THUMB
9 - CPUs that are Thumb-only must select this
10 - this selects: HAS_THUMB, COMPILE_IN_THUMB_MODE and USE_BX
11
12 Also, remove leading space in Rules.mak.
13
14 Signed-off-by: "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
15 Cc: Khem Raj <raj.khem@gmail.com>
16 Cc: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
17 Cc: Carmelo AMOROSO <carmelo.amoroso@st.com>
18 ---
19 Rules.mak | 7 ++++---
20 extra/Configs/Config.arm | 31 ++++++++++++++++++++++++++++---
21 2 files changed, 32 insertions(+), 6 deletions(-)
22
23 diff --git a/Rules.mak b/Rules.mak
24 index eecdc64..2a16908 100644
25 --- a/Rules.mak
26 +++ b/Rules.mak
27 @@ -348,9 +348,10 @@ ifeq ($(TARGET_ARCH),arm)
28 CPU_CFLAGS-$(CONFIG_ARM_SA1100)+=-mtune=strongarm1100 -march=armv4
29 CPU_CFLAGS-$(CONFIG_ARM_XSCALE)+=$(call check_gcc,-mtune=xscale,-mtune=strongarm110)
30 CPU_CFLAGS-$(CONFIG_ARM_XSCALE)+=-march=armv5te -Wa,-mcpu=xscale
31 - CPU_CFLAGS-$(CONFIG_ARM_IWMMXT)+=-march=iwmmxt -Wa,-mcpu=iwmmxt -mabi=iwmmxt
32 - CPU_CFLAGS-$(CONFIG_ARM_CORTEX_M3)+=-mcpu=cortex-m3 -mthumb
33 - CPU_CFLAGS-$(CONFIG_ARM_CORTEX_M1)+=-mcpu=cortex-m1 -mthumb
34 + CPU_CFLAGS-$(CONFIG_ARM_IWMMXT)+=-march=iwmmxt -Wa,-mcpu=iwmmxt -mabi=iwmmxt
35 + CPU_CFLAGS-$(CONFIG_ARM_CORTEX_M3)+=-mcpu=cortex-m3
36 + CPU_CFLAGS-$(CONFIG_ARM_CORTEX_M1)+=-mcpu=cortex-m1
37 + CPU_CFLAGS-$(COMPILE_IN_THUMB_MODE)+=-mthumb
38 endif
39
40 ifeq ($(TARGET_ARCH),mips)
41 diff --git a/extra/Configs/Config.arm b/extra/Configs/Config.arm
42 index 3b90e67..c9c40d4 100644
43 --- a/extra/Configs/Config.arm
44 +++ b/extra/Configs/Config.arm
45 @@ -64,70 +64,95 @@ config CONFIG_ARM710
46 config CONFIG_ARM7TDMI
47 bool "Arm 7TDMI"
48 select ARCH_HAS_NO_MMU
49 + select HAS_THUMB
50
51 config CONFIG_ARM720T
52 bool "Arm 720T"
53 select ARCH_HAS_MMU
54 + select HAS_THUMB
55
56 config CONFIG_ARM920T
57 bool "Arm 920T"
58 select ARCH_HAS_MMU
59 + select HAS_THUMB
60
61 config CONFIG_ARM922T
62 bool "Arm 922T"
63 select ARCH_HAS_MMU
64 + select HAS_THUMB
65
66 config CONFIG_ARM926T
67 bool "Arm 926T"
68 select ARCH_HAS_MMU
69 + select HAS_THUMB
70
71 config CONFIG_ARM10T
72 bool "Arm 10T"
73 select ARCH_HAS_MMU
74 + select HAS_THUMB
75
76 config CONFIG_ARM1136JF_S
77 bool "Arm 1136JF-S"
78 select ARCH_HAS_MMU
79 + select HAS_THUMB
80
81 config CONFIG_ARM1176JZ_S
82 bool "Arm 1176JZ-S"
83 select ARCH_HAS_MMU
84 + select HAS_THUMB
85
86 config CONFIG_ARM1176JZF_S
87 bool "Arm 1176JZF-S"
88 select ARCH_HAS_MMU
89 + select HAS_THUMB
90
91 config CONFIG_ARM_CORTEX_M3
92 bool "Arm Cortex-M3"
93 select ARCH_HAS_NO_MMU
94 - select USE_BX
95 + select FORCE_THUMB
96
97 config CONFIG_ARM_CORTEX_M1
98 bool "Arm Cortex-M1"
99 select ARCH_HAS_NO_MMU
100 - select USE_BX
101 + select FORCE_THUMB
102
103 config CONFIG_ARM_SA110
104 bool "Intel StrongArm SA-110"
105 select ARCH_HAS_MMU
106 + select HAS_THUMB
107
108 config CONFIG_ARM_SA1100
109 bool "Intel StrongArm SA-1100"
110 select ARCH_HAS_MMU
111 + select HAS_THUMB
112
113 config CONFIG_ARM_XSCALE
114 bool "Intel Xscale"
115 select ARCH_HAS_MMU
116 + select HAS_THUMB
117
118 config CONFIG_ARM_IWMMXT
119 bool "Intel Xscale With WMMX PXA27x"
120 select ARCH_HAS_MMU
121 + select HAS_THUMB
122
123 endchoice
124
125 +config HAS_THUMB
126 + bool
127 +
128 +config FORCE_THUMB
129 + bool
130 + select HAS_THUMB
131 + select COMPILE_IN_THUMB_MODE
132 + select USE_BX
133 +
134 +config COMPILE_IN_THUMB_MODE
135 + bool
136 +
137 config USE_BX
138 bool "Use BX in function return"
139 default y
140 - depends on !CONFIG_GENERIC_ARM && !CONFIG_ARM610 && !CONFIG_ARM710
141 + depends on HAS_THUMB
142 help
143 Use BX instruction for THUMB aware architectures.
144 --
145 1.7.1
146