2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include <linux/tcp.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
41 #include <net/mac80211.h>
52 /* An attempt will be made to merge these link list helpers upstream
55 static inline void __list_splice_tail(const struct list_head
*list
,
56 struct list_head
*head
)
58 struct list_head
*first
= list
->next
;
59 struct list_head
*last
= list
->prev
;
60 struct list_head
*current_tail
= head
->prev
;
62 current_tail
->next
= first
;
65 first
->prev
= current_tail
;
68 static inline void __list_cut_position(struct list_head
*list
,
69 struct list_head
*head
, struct list_head
*entry
)
71 struct list_head
*new_first
=
72 (entry
->next
!= head
) ? entry
->next
: head
;
73 list
->next
= head
->next
;
74 list
->next
->prev
= list
;
77 head
->next
= new_first
;
78 new_first
->prev
= head
;
82 * list_splice_tail - join two lists, each list being a queue
83 * @list: the new list to add.
84 * @head: the place to add it in the first list.
86 static inline void list_splice_tail(const struct list_head
*list
,
87 struct list_head
*head
)
89 if (!list_empty(list
))
90 __list_splice_tail(list
, head
);
94 * list_splice_tail_init - join two lists, each list being a queue, and
95 * reinitialise the emptied list.
96 * @list: the new list to add.
97 * @head: the place to add it in the first list.
99 * The list at @list is reinitialised
101 static inline void list_splice_tail_init(struct list_head
*list
,
102 struct list_head
*head
)
104 if (!list_empty(list
)) {
105 __list_splice_tail(list
, head
);
106 INIT_LIST_HEAD(list
);
111 * list_cut_position - cut a list into two
112 * @list: a new list to add all removed entries
113 * @head: a list with entries
114 * @entry: an entry within head, could be the head itself
115 * and if so we won't won't cut the list
117 static inline void list_cut_position(struct list_head
*list
,
118 struct list_head
*head
, struct list_head
*entry
)
120 BUG_ON(list_empty(head
));
121 if (list_is_singular(head
))
122 BUG_ON(head
->next
!= entry
&& head
!= entry
);
124 INIT_LIST_HEAD(list
);
126 __list_cut_position(list
, head
, entry
);
129 /* Macro to expand scalars to 64-bit objects */
131 #define ito64(x) (sizeof(x) == 8) ? \
132 (((unsigned long long int)(x)) & (0xff)) : \
133 (sizeof(x) == 16) ? \
134 (((unsigned long long int)(x)) & 0xffff) : \
135 ((sizeof(x) == 32) ? \
136 (((unsigned long long int)(x)) & 0xffffffff) : \
137 (unsigned long long int)(x))
139 /* increment with wrap-around */
140 #define INCR(_l, _sz) do { \
142 (_l) &= ((_sz) - 1); \
145 /* decrement with wrap-around */
146 #define DECR(_l, _sz) do { \
148 (_l) &= ((_sz) - 1); \
151 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
153 #define ASSERT(exp) do { \
154 if (unlikely(!(exp))) { \
160 #define memzero(_buf, _len) memset(_buf, 0, _len)
162 #define get_dma_mem_context(var, field) (&((var)->field))
163 #define copy_dma_mem_context(dst, src) (*dst = *src)
165 #define ATH9K_BH_STATUS_INTACT 0
166 #define ATH9K_BH_STATUS_CHANGE 1
168 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
170 static inline unsigned long get_timestamp(void)
172 return ((jiffies
/ HZ
) * 1000) + (jiffies
% HZ
) * (1000 / HZ
);
180 ATH_DBG_RESET
= 0x00000001,
181 ATH_DBG_PHY_IO
= 0x00000002,
182 ATH_DBG_REG_IO
= 0x00000004,
183 ATH_DBG_QUEUE
= 0x00000008,
184 ATH_DBG_EEPROM
= 0x00000010,
185 ATH_DBG_NF_CAL
= 0x00000020,
186 ATH_DBG_CALIBRATE
= 0x00000040,
187 ATH_DBG_CHANNEL
= 0x00000080,
188 ATH_DBG_INTERRUPT
= 0x00000100,
189 ATH_DBG_REGULATORY
= 0x00000200,
190 ATH_DBG_ANI
= 0x00000400,
191 ATH_DBG_POWER_MGMT
= 0x00000800,
192 ATH_DBG_XMIT
= 0x00001000,
193 ATH_DBG_BEACON
= 0x00002000,
194 ATH_DBG_RATE
= 0x00004000,
195 ATH_DBG_CONFIG
= 0x00008000,
196 ATH_DBG_KEYCACHE
= 0x00010000,
197 ATH_DBG_AGGR
= 0x00020000,
198 ATH_DBG_FATAL
= 0x00040000,
199 ATH_DBG_ANY
= 0xffffffff
202 #define DBG_DEFAULT (ATH_DBG_FATAL)
204 #define DPRINTF(sc, _m, _fmt, ...) do { \
205 if (sc->sc_debug & (_m)) \
206 printk(_fmt , ##__VA_ARGS__); \
209 /***************************/
210 /* Load-time Configuration */
211 /***************************/
213 /* Per-instance load-time (note: NOT run-time) configurations
214 * for Atheros Device */
218 u16 txpowlimit_override
;
219 u8 cabqReadytime
; /* Cabq Readytime % */
220 u8 swBeaconProcess
; /* Process received beacons
224 /***********************/
225 /* Chainmask Selection */
226 /***********************/
228 #define ATH_CHAINMASK_SEL_TIMEOUT 6000
229 /* Default - Number of last RSSI values that is used for
230 * chainmask selection */
231 #define ATH_CHAINMASK_SEL_RSSI_CNT 10
232 /* Means use 3x3 chainmask instead of configured chainmask */
233 #define ATH_CHAINMASK_SEL_3X3 7
234 /* Default - Rssi threshold below which we have to switch to 3x3 */
235 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
236 /* Default - Rssi threshold above which we have to switch to
237 * user configured values */
238 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
239 /* Struct to store the chainmask select related info */
240 struct ath_chainmask_sel
{
241 struct timer_list timer
;
242 int cur_tx_mask
; /* user configured or 3x3 */
243 int cur_rx_mask
; /* user configured or 3x3 */
245 u8 switch_allowed
:1, /* timer will set this */
249 int ath_chainmask_sel_logic(struct ath_softc
*sc
, struct ath_node
*an
);
250 void ath_update_chainmask(struct ath_softc
*sc
, int is_ht
);
252 /*************************/
253 /* Descriptor Management */
254 /*************************/
256 /* Number of descriptors per buffer. The only case where we see skbuff
257 chains is due to FF aggregation in the driver. */
259 /* if there's more fragment for this MSDU */
260 #define ATH_BF_MORE_MPDU 1
261 #define ATH_TXBUF_RESET(_bf) do { \
262 (_bf)->bf_status = 0; \
263 (_bf)->bf_lastbf = NULL; \
264 (_bf)->bf_lastfrm = NULL; \
265 (_bf)->bf_next = NULL; \
266 memzero(&((_bf)->bf_state), \
267 sizeof(struct ath_buf_state)); \
270 struct ath_buf_state
{
271 int bfs_nframes
; /* # frames in aggregate */
272 u16 bfs_al
; /* length of aggregate */
273 u16 bfs_frmlen
; /* length of frame */
274 int bfs_seqno
; /* sequence number */
275 int bfs_tidno
; /* tid of this frame */
276 int bfs_retries
; /* current retries */
277 struct ath_rc_series bfs_rcs
[4]; /* rate series */
278 u8 bfs_isdata
:1; /* is a data frame/aggregate */
279 u8 bfs_isaggr
:1; /* is an aggregate */
280 u8 bfs_isampdu
:1; /* is an a-mpdu, aggregate or not */
281 u8 bfs_ht
:1; /* is an HT frame */
282 u8 bfs_isretried
:1; /* is retried */
283 u8 bfs_isxretried
:1; /* is excessive retried */
284 u8 bfs_shpreamble
:1; /* is short preamble */
285 u8 bfs_isbar
:1; /* is a BAR */
286 u8 bfs_ispspoll
:1; /* is a PS-Poll */
287 u8 bfs_aggrburst
:1; /* is a aggr burst */
288 u8 bfs_calcairtime
:1; /* requests airtime be calculated
289 when set for tx frame */
290 int bfs_rifsburst_elem
; /* RIFS burst/bar */
291 int bfs_nrifsubframes
; /* # of elements in burst */
292 /* key type use to encrypt this frame */
293 enum ath9k_key_type bfs_keytype
;
296 #define bf_nframes bf_state.bfs_nframes
297 #define bf_al bf_state.bfs_al
298 #define bf_frmlen bf_state.bfs_frmlen
299 #define bf_retries bf_state.bfs_retries
300 #define bf_seqno bf_state.bfs_seqno
301 #define bf_tidno bf_state.bfs_tidno
302 #define bf_rcs bf_state.bfs_rcs
303 #define bf_isdata bf_state.bfs_isdata
304 #define bf_isaggr bf_state.bfs_isaggr
305 #define bf_isampdu bf_state.bfs_isampdu
306 #define bf_ht bf_state.bfs_ht
307 #define bf_isretried bf_state.bfs_isretried
308 #define bf_isxretried bf_state.bfs_isxretried
309 #define bf_shpreamble bf_state.bfs_shpreamble
310 #define bf_rifsburst_elem bf_state.bfs_rifsburst_elem
311 #define bf_nrifsubframes bf_state.bfs_nrifsubframes
312 #define bf_keytype bf_state.bfs_keytype
313 #define bf_isbar bf_state.bfs_isbar
314 #define bf_ispspoll bf_state.bfs_ispspoll
315 #define bf_aggrburst bf_state.bfs_aggrburst
316 #define bf_calcairtime bf_state.bfs_calcairtime
319 * Abstraction of a contiguous buffer to transmit/receive. There is only
320 * a single hw descriptor encapsulated here.
324 struct list_head list
;
325 struct list_head
*last
;
326 struct ath_buf
*bf_lastbf
; /* last buf of this unit (a frame or
328 struct ath_buf
*bf_lastfrm
; /* last buf of this frame */
329 struct ath_buf
*bf_next
; /* next subframe in the aggregate */
330 struct ath_buf
*bf_rifslast
; /* last buf for RIFS burst */
331 void *bf_mpdu
; /* enclosing frame structure */
332 void *bf_node
; /* pointer to the node */
333 struct ath_desc
*bf_desc
; /* virtual addr of desc */
334 dma_addr_t bf_daddr
; /* physical addr of desc */
335 dma_addr_t bf_buf_addr
; /* physical addr of data buffer */
337 u16 bf_flags
; /* tx descriptor flags */
338 struct ath_buf_state bf_state
; /* buffer state */
339 dma_addr_t bf_dmacontext
;
343 * reset the rx buffer.
344 * any new fields added to the athbuf and require
345 * reset need to be added to this macro.
346 * currently bf_status is the only one requires that
349 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
351 /* hw processing complete, desc processed by hal */
352 #define ATH_BUFSTATUS_DONE 0x00000001
353 /* hw processing complete, desc hold for hw */
354 #define ATH_BUFSTATUS_STALE 0x00000002
355 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
356 #define ATH_BUFSTATUS_FREE 0x00000004
358 /* DMA state for tx/rx descriptors */
362 struct ath_desc
*dd_desc
; /* descriptors */
363 dma_addr_t dd_desc_paddr
; /* physical addr of dd_desc */
364 u32 dd_desc_len
; /* size of dd_desc */
365 struct ath_buf
*dd_bufptr
; /* associated buffers */
366 dma_addr_t dd_dmacontext
;
369 /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
371 struct ath_rx_context
{
372 struct ath_buf
*ctx_rxbuf
; /* associated ath_buf for rx */
374 #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
376 int ath_descdma_setup(struct ath_softc
*sc
,
377 struct ath_descdma
*dd
,
378 struct list_head
*head
,
382 int ath_desc_alloc(struct ath_softc
*sc
);
383 void ath_desc_free(struct ath_softc
*sc
);
384 void ath_descdma_cleanup(struct ath_softc
*sc
,
385 struct ath_descdma
*dd
,
386 struct list_head
*head
);
392 #define ATH_MAX_ANTENNA 3
393 #define ATH_RXBUF 512
394 #define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
395 #define WME_NUM_TID 16
396 #define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
397 #define IEEE80211_BAR_CTL_TID_S 2 /* tid shift */
400 ATH_RX_NON_CONSUMED
= 0,
404 /* per frame rx status block */
405 struct ath_recv_status
{
406 u64 tsf
; /* mac tsf */
407 int8_t rssi
; /* RSSI (noise floor ajusted) */
408 int8_t rssictl
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
409 int8_t rssiextn
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
410 int8_t abs_rssi
; /* absolute RSSI */
411 u8 rateieee
; /* data rate received (IEEE rate code) */
412 u8 ratecode
; /* phy rate code */
413 int rateKbps
; /* data rate received (Kbps) */
414 int antenna
; /* rx antenna */
415 int flags
; /* status of associated skb */
416 #define ATH_RX_FCS_ERROR 0x01
417 #define ATH_RX_MIC_ERROR 0x02
418 #define ATH_RX_DECRYPT_ERROR 0x04
419 #define ATH_RX_RSSI_VALID 0x08
420 /* if any of ctl,extn chainrssis are valid */
421 #define ATH_RX_CHAIN_RSSI_VALID 0x10
422 /* if extn chain rssis are valid */
423 #define ATH_RX_RSSI_EXTN_VALID 0x20
424 /* set if 40Mhz, clear if 20Mhz */
425 #define ATH_RX_40MHZ 0x40
426 /* set if short GI, clear if full GI */
427 #define ATH_RX_SHORT_GI 0x80
431 struct sk_buff
*rx_wbuf
; /* buffer */
432 unsigned long rx_time
; /* system time when received */
433 struct ath_recv_status rx_status
; /* cached rx status */
436 /* Per-TID aggregate receiver state for a node */
438 struct ath_node
*an
; /* parent ath node */
439 struct ath_rxbuf
*rxbuf
; /* re-ordering buffer */
440 struct timer_list timer
;
441 spinlock_t tidlock
; /* lock to protect this TID structure */
442 int baw_head
; /* seq_next at head */
443 int baw_tail
; /* tail of block-ack window */
444 int seq_reset
; /* need to reset start sequence */
445 int addba_exchangecomplete
;
446 u16 seq_next
; /* next expected sequence */
447 u16 baw_size
; /* block-ack window size */
450 /* Per-node receiver aggregate state */
452 struct ath_arx_tid tid
[WME_NUM_TID
];
455 int ath_startrecv(struct ath_softc
*sc
);
456 bool ath_stoprecv(struct ath_softc
*sc
);
457 void ath_flushrecv(struct ath_softc
*sc
);
458 u32
ath_calcrxfilter(struct ath_softc
*sc
);
459 void ath_rx_node_init(struct ath_softc
*sc
, struct ath_node
*an
);
460 void ath_rx_node_free(struct ath_softc
*sc
, struct ath_node
*an
);
461 void ath_rx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
);
462 void ath_handle_rx_intr(struct ath_softc
*sc
);
463 int ath_rx_init(struct ath_softc
*sc
, int nbufs
);
464 void ath_rx_cleanup(struct ath_softc
*sc
);
465 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
);
466 int ath_rx_input(struct ath_softc
*sc
,
467 struct ath_node
*node
,
470 struct ath_recv_status
*rx_status
,
471 enum ATH_RX_TYPE
*status
);
472 int ath__rx_indicate(struct ath_softc
*sc
,
474 struct ath_recv_status
*status
,
476 int ath_rx_subframe(struct ath_node
*an
, struct sk_buff
*skb
,
477 struct ath_recv_status
*status
);
483 #define ATH_FRAG_PER_MSDU 1
484 #define ATH_TXBUF (512/ATH_FRAG_PER_MSDU)
485 /* max number of transmit attempts (tries) */
486 #define ATH_TXMAXTRY 13
487 /* max number of 11n transmit attempts (tries) */
488 #define ATH_11N_TXMAXTRY 10
489 /* max number of tries for management and control frames */
490 #define ATH_MGT_TXMAXTRY 4
491 #define WME_BA_BMP_SIZE 64
492 #define WME_MAX_BA WME_BA_BMP_SIZE
493 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
494 #define TID_TO_WME_AC(_tid) \
495 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
496 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
497 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
501 /* Wireless Multimedia Extension Defines */
502 #define WME_AC_BE 0 /* best effort */
503 #define WME_AC_BK 1 /* background */
504 #define WME_AC_VI 2 /* video */
505 #define WME_AC_VO 3 /* voice */
510 ATH_SM_PWRSAV_STATIC
,
511 ATH_SM_PWRSAV_DYNAMIC
,
515 * Data transmit queue state. One of these exists for each
516 * hardware transmit queue. Packets sent to us from above
517 * are assigned to queues based on their priority. Not all
518 * devices support a complete set of hardware transmit queues.
519 * For those devices the array sc_ac2q will map multiple
520 * priorities to fewer hardware queues (typically all to one
524 u32 axq_qnum
; /* hardware q number */
525 u32
*axq_link
; /* link ptr in last TX desc */
526 struct list_head axq_q
; /* transmit queue */
527 spinlock_t axq_lock
; /* lock on q and link */
528 unsigned long axq_lockflags
; /* intr state when must cli */
529 u32 axq_depth
; /* queue depth */
530 u8 axq_aggr_depth
; /* aggregates queued */
531 u32 axq_totalqueued
;/* total ever queued */
532 u32 axq_intrcnt
; /* count to determine
533 if descriptor should generate
535 bool stopped
; /* Is mac80211 queue
537 /* State for patching up CTS when bursting */
538 struct ath_buf
*axq_linkbuf
; /* virtual addr of last buffer*/
539 struct ath_desc
*axq_lastdsWithCTS
; /* first desc of the
540 last descriptor that contains CTS */
541 struct ath_desc
*axq_gatingds
; /* final desc of the gating desc
542 * that determines whether lastdsWithCTS has
543 * been DMA'ed or not */
544 struct list_head axq_acq
;
547 /* per TID aggregate tx state for a destination */
549 struct list_head list
; /* round-robin tid entry */
550 struct list_head buf_q
; /* pending buffers */
551 struct ath_node
*an
; /* parent node structure */
552 struct ath_atx_ac
*ac
; /* parent access category */
553 struct ath_buf
*tx_buf
[ATH_TID_MAX_BUFS
];/* active tx frames */
554 u16 seq_start
; /* starting seq of BA window */
555 u16 seq_next
; /* next seq to be used */
556 u16 baw_size
; /* BA window size */
557 int tidno
; /* TID number */
558 int baw_head
; /* first un-acked tx buffer */
559 int baw_tail
; /* next unused tx buffer slot */
560 int sched
; /* TID is scheduled */
561 int paused
; /* TID is paused */
562 int cleanup_inprogress
; /* aggr of this TID is
564 u32 addba_exchangecomplete
:1; /* ADDBA state */
565 int32_t addba_exchangeinprogress
;
566 int addba_exchangeattempts
;
569 /* per access-category aggregate tx state for a destination */
571 int sched
; /* dest-ac is scheduled */
572 int qnum
; /* H/W queue number associated
574 struct list_head list
; /* round-robin txq entry */
575 struct list_head tid_q
; /* queue of TIDs with buffers */
578 /* per dest tx state */
580 struct ath_atx_tid tid
[WME_NUM_TID
];
581 struct ath_atx_ac ac
[WME_NUM_AC
];
584 /* per-frame tx control block */
585 struct ath_tx_control
{
586 struct ath_node
*an
; /* destination to sent to */
587 int if_id
; /* only valid for cab traffic */
588 int qnum
; /* h/w queue number */
589 u32 ht
:1; /* if it can be transmitted using HT */
590 u32 ps
:1; /* if one or more stations are in PS mode */
591 u32 use_minrate
:1; /* if this frame should transmitted using
593 enum ath9k_pkt_type atype
; /* Atheros packet type */
594 enum ath9k_key_type keytype
; /* key type */
595 u32 flags
; /* HAL flags */
596 u16 seqno
; /* sequence number */
597 u16 tidno
; /* tid number */
598 u16 txpower
; /* transmit power */
599 u16 frmlen
; /* frame length */
600 u32 keyix
; /* key index */
601 int min_rate
; /* minimum rate */
602 int mcast_rate
; /* multicast rate */
603 u16 nextfraglen
; /* next fragment length */
604 /* below is set only by ath_dev */
605 struct ath_softc
*dev
; /* device handle */
606 dma_addr_t dmacontext
;
609 /* per frame tx status block */
610 struct ath_xmit_status
{
611 int retries
; /* number of retries to successufully
612 transmit this frame */
613 int flags
; /* status of transmit */
614 #define ATH_TX_ERROR 0x01
615 #define ATH_TX_XRETRY 0x02
616 #define ATH_TX_BAR 0x04
620 int rssi
; /* RSSI (noise floor ajusted) */
621 int rssictl
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
622 int rssiextn
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
623 int rateieee
; /* data rate xmitted (IEEE rate code) */
624 int rateKbps
; /* data rate xmitted (Kbps) */
625 int ratecode
; /* phy rate code */
626 int flags
; /* validity flags */
627 /* if any of ctl,extn chain rssis are valid */
628 #define ATH_TX_CHAIN_RSSI_VALID 0x01
629 /* if extn chain rssis are valid */
630 #define ATH_TX_RSSI_EXTN_VALID 0x02
631 u32 airtime
; /* time on air per final tx rate */
634 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
);
635 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
);
636 int ath_tx_setup(struct ath_softc
*sc
, int haltype
);
637 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
);
638 void ath_tx_draintxq(struct ath_softc
*sc
,
639 struct ath_txq
*txq
, bool retry_tx
);
640 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
);
641 void ath_tx_node_cleanup(struct ath_softc
*sc
,
642 struct ath_node
*an
, bool bh_flag
);
643 void ath_tx_node_free(struct ath_softc
*sc
, struct ath_node
*an
);
644 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
);
645 int ath_tx_init(struct ath_softc
*sc
, int nbufs
);
646 int ath_tx_cleanup(struct ath_softc
*sc
);
647 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
);
648 int ath_txq_update(struct ath_softc
*sc
, int qnum
, struct ath9k_txq_info
*q
);
649 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
);
650 void ath_tx_tasklet(struct ath_softc
*sc
);
651 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
);
652 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
);
653 void ath_notify_txq_status(struct ath_softc
*sc
, u16 queue_depth
);
654 void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
655 struct ath_xmit_status
*tx_status
, struct ath_node
*an
);
657 /**********************/
658 /* Node / Aggregation */
659 /**********************/
661 /* indicates the node is clened up */
662 #define ATH_NODE_CLEAN 0x1
663 /* indicates the node is 80211 power save */
664 #define ATH_NODE_PWRSAVE 0x2
666 #define ADDBA_TIMEOUT 200 /* 200 milliseconds */
667 #define ADDBA_EXCHANGE_ATTEMPTS 10
668 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
669 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
670 /* number of delimiters for encryption padding */
671 #define ATH_AGGR_ENCRYPTDELIM 10
672 /* minimum h/w qdepth to be sustained to maximize aggregation */
673 #define ATH_AGGR_MIN_QDEPTH 2
674 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
675 #define IEEE80211_SEQ_SEQ_SHIFT 4
676 #define IEEE80211_SEQ_MAX 4096
677 #define IEEE80211_MIN_AMPDU_BUF 0x8
679 /* return whether a bit at index _n in bitmap _bm is set
680 * _sz is the size of the bitmap */
681 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
682 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
684 /* return block-ack bitmap index given sequence and starting sequence */
685 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
687 /* returns delimiter padding required given the packet length */
688 #define ATH_AGGR_GET_NDELIM(_len) \
689 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
690 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
692 #define BAW_WITHIN(_start, _bawsz, _seqno) \
693 ((((_seqno) - (_start)) & 4095) < (_bawsz))
695 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
696 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
697 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
698 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
700 enum ATH_AGGR_STATUS
{
708 enum ATH_AGGR_CHECK
{
711 AGGR_CLEANUP_PROGRESS
,
712 AGGR_EXCHANGE_PROGRESS
,
716 struct aggr_rifs_param
{
717 int param_max_frames
;
721 struct ath_rc_series
*param_rcs
;
724 /* Per-node aggregation state */
725 struct ath_node_aggr
{
726 struct ath_atx tx
; /* node transmit state */
727 struct ath_arx rx
; /* node receive state */
730 /* driver-specific node state */
732 struct list_head list
;
733 struct ath_softc
*an_sc
; /* back pointer */
735 struct ath_chainmask_sel an_chainmask_sel
;
736 struct ath_node_aggr an_aggr
; /* A-MPDU aggregation state */
737 u8 an_smmode
; /* SM Power save mode */
739 u8 an_addr
[ETH_ALEN
];
742 void ath_tx_resume_tid(struct ath_softc
*sc
,
743 struct ath_atx_tid
*tid
);
744 enum ATH_AGGR_CHECK
ath_tx_aggr_check(struct ath_softc
*sc
,
745 struct ath_node
*an
, u8 tidno
);
746 void ath_tx_aggr_teardown(struct ath_softc
*sc
,
747 struct ath_node
*an
, u8 tidno
);
748 void ath_rx_aggr_teardown(struct ath_softc
*sc
,
749 struct ath_node
*an
, u8 tidno
);
750 int ath_rx_aggr_start(struct ath_softc
*sc
,
754 int ath_rx_aggr_stop(struct ath_softc
*sc
,
757 int ath_tx_aggr_start(struct ath_softc
*sc
,
761 int ath_tx_aggr_stop(struct ath_softc
*sc
,
764 void ath_newassoc(struct ath_softc
*sc
,
765 struct ath_node
*node
, int isnew
, int isuapsd
);
766 struct ath_node
*ath_node_attach(struct ath_softc
*sc
,
767 u8 addr
[ETH_ALEN
], int if_id
);
768 void ath_node_detach(struct ath_softc
*sc
, struct ath_node
*an
, bool bh_flag
);
769 struct ath_node
*ath_node_get(struct ath_softc
*sc
, u8 addr
[ETH_ALEN
]);
770 void ath_node_put(struct ath_softc
*sc
, struct ath_node
*an
, bool bh_flag
);
771 struct ath_node
*ath_node_find(struct ath_softc
*sc
, u8
*addr
);
773 /*******************/
774 /* Beacon Handling */
775 /*******************/
778 * Regardless of the number of beacons we stagger, (i.e. regardless of the
779 * number of BSSIDs) if a given beacon does not go out even after waiting this
780 * number of beacon intervals, the game's up.
782 #define BSTUCK_THRESH (9 * ATH_BCBUF)
783 #define ATH_BCBUF 4 /* number of beacon buffers */
784 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
785 #define ATH_DEFAULT_BMISS_LIMIT 10
786 #define ATH_BEACON_AIFS_DEFAULT 0 /* Default aifs for ap beacon q */
787 #define ATH_BEACON_CWMIN_DEFAULT 0 /* Default cwmin for ap beacon q */
788 #define ATH_BEACON_CWMAX_DEFAULT 0 /* Default cwmax for ap beacon q */
789 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
791 /* beacon configuration */
792 struct ath_beacon_config
{
802 } u
; /* last received beacon/probe response timestamp of this BSS. */
805 /* offsets in a beacon frame for
806 * quick acess of beacon content by low-level driver */
807 struct ath_beacon_offset
{
808 u8
*bo_tim
; /* start of atim/dtim */
811 void ath9k_beacon_tasklet(unsigned long data
);
812 void ath_beacon_config(struct ath_softc
*sc
, int if_id
);
813 int ath_beaconq_setup(struct ath_hal
*ah
);
814 int ath_beacon_alloc(struct ath_softc
*sc
, int if_id
);
815 void ath_bstuck_process(struct ath_softc
*sc
);
816 void ath_beacon_tasklet(struct ath_softc
*sc
, int *needmark
);
817 void ath_beacon_free(struct ath_softc
*sc
);
818 void ath_beacon_return(struct ath_softc
*sc
, struct ath_vap
*avp
);
819 void ath_beacon_sync(struct ath_softc
*sc
, int if_id
);
820 void ath_update_beacon_info(struct ath_softc
*sc
, int avgbrssi
);
821 void ath_get_beaconconfig(struct ath_softc
*sc
,
823 struct ath_beacon_config
*conf
);
824 int ath_update_beacon(struct ath_softc
*sc
,
826 struct ath_beacon_offset
*bo
,
833 #define ATH_IF_HW_OFF 0x0001 /* hardware state needs to turn off */
834 #define ATH_IF_HW_ON 0x0002 /* hardware state needs to turn on */
835 /* STA only: the associated AP is HT capable */
836 #define ATH_IF_HT 0x0004
837 /* AP/IBSS only: current BSS has privacy on */
838 #define ATH_IF_PRIVACY 0x0008
839 #define ATH_IF_BEACON_ENABLE 0x0010 /* AP/IBSS only: enable beacon */
840 #define ATH_IF_BEACON_SYNC 0x0020 /* IBSS only: need to sync beacon */
843 * Define the scheme that we select MAC address for multiple
844 * BSS on the same radio. The very first VAP will just use the MAC
845 * address from the EEPROM. For the next 3 VAPs, we set the
846 * U/L bit (bit 1) in MAC address, and use the next two bits as the
850 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
851 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
853 /* VAP configuration (from protocol layer) */
854 struct ath_vap_config
{
855 u32 av_fixed_rateset
;
856 u32 av_fixed_retryset
;
859 /* driver-specific vap state */
861 struct ieee80211_vif
*av_if_data
; /* interface(vap)
862 instance from 802.11 protocal layer */
863 enum ath9k_opmode av_opmode
; /* VAP operational mode */
864 struct ath_buf
*av_bcbuf
; /* beacon buffer */
865 struct ath_beacon_offset av_boff
; /* dynamic update state */
866 struct ath_tx_control av_btxctl
; /* tx control information
868 int av_bslot
; /* beacon slot index */
869 struct ath_txq av_mcastq
; /* multicast
871 struct ath_vap_config av_config
; /* vap configuration
872 parameters from 802.11 protocol layer*/
873 struct ath_rate_node
*rc_node
;
876 int ath_vap_attach(struct ath_softc
*sc
,
878 struct ieee80211_vif
*if_data
,
879 enum ath9k_opmode opmode
);
880 int ath_vap_detach(struct ath_softc
*sc
, int if_id
);
881 int ath_vap_config(struct ath_softc
*sc
,
882 int if_id
, struct ath_vap_config
*if_config
);
883 int ath_vap_listen(struct ath_softc
*sc
, int if_id
);
885 /*********************/
886 /* Antenna diversity */
887 /*********************/
889 #define ATH_ANT_DIV_MAX_CFG 2
890 #define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
891 #define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
893 enum ATH_ANT_DIV_STATE
{
895 ATH_ANT_DIV_SCAN
, /* evaluating antenna */
899 struct ath_softc
*antdiv_sc
;
901 enum ATH_ANT_DIV_STATE antdiv_state
;
902 u8 antdiv_num_antcfg
;
905 int32_t antdivf_rssitrig
;
906 int32_t antdiv_lastbrssi
[ATH_ANT_DIV_MAX_CFG
];
907 u64 antdiv_lastbtsf
[ATH_ANT_DIV_MAX_CFG
];
908 u64 antdiv_laststatetsf
;
909 u8 antdiv_bssid
[ETH_ALEN
];
912 void ath_slow_ant_div_init(struct ath_antdiv
*antdiv
,
913 struct ath_softc
*sc
, int32_t rssitrig
);
914 void ath_slow_ant_div_start(struct ath_antdiv
*antdiv
,
917 void ath_slow_ant_div_stop(struct ath_antdiv
*antdiv
);
918 void ath_slow_ant_div(struct ath_antdiv
*antdiv
,
919 struct ieee80211_hdr
*wh
,
920 struct ath_rx_status
*rx_stats
);
921 void ath_setdefantenna(void *sc
, u32 antenna
);
923 /********************/
924 /* Main driver core */
925 /********************/
928 * Default cache line size, in bytes.
929 * Used when PCI device not fully initialized by bootrom/BIOS
931 #define DEFAULT_CACHELINE 32
932 #define ATH_DEFAULT_NOISE_FLOOR -95
933 #define ATH_REGCLASSIDS_MAX 10
934 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
935 #define ATH_PREAMBLE_SHORT (1<<0)
936 #define ATH_PROTECT_ENABLE (1<<1)
937 #define ATH_MAX_SW_RETRIES 10
938 /* Num farmes difference in tx to flip default recv */
939 #define ATH_ANTENNA_DIFF 2
940 #define ATH_CHAN_MAX 255
941 #define IEEE80211_WEP_NKID 4 /* number of key ids */
942 #define IEEE80211_RATE_VAL 0x7f
944 * The key cache is used for h/w cipher state and also for
945 * tracking station state such as the current tx antenna.
946 * We also setup a mapping table between key cache slot indices
947 * and station state to short-circuit node lookups on rx.
948 * Different parts have different size key caches. We handle
949 * up to ATH_KEYMAX entries (could dynamically allocate state).
951 #define ATH_KEYMAX 128 /* max key cache size we handle */
953 #define RESET_RETRY_TXQ 0x00000001
954 #define ATH_IF_ID_ANY 0xff
956 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
958 #define RSSI_LPF_THRESHOLD -20
959 #define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
960 #define ATH_RATE_DUMMY_MARKER 0
961 #define ATH_RSSI_LPF_LEN 10
962 #define ATH_RSSI_DUMMY_MARKER 0x127
964 #define ATH_EP_MUL(x, mul) ((x) * (mul))
965 #define ATH_EP_RND(x, mul) \
966 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
967 #define ATH_RSSI_OUT(x) \
968 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
969 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
970 #define ATH_RSSI_IN(x) \
971 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
972 #define ATH_LPF_RSSI(x, y, len) \
973 ((x != ATH_RSSI_DUMMY_MARKER) ? \
974 (((x) * ((len) - 1) + (y)) / (len)) : (y))
975 #define ATH_RSSI_LPF(x, y) do { \
976 if ((y) >= RSSI_LPF_THRESHOLD) \
977 x = ATH_LPF_RSSI((x), \
978 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
995 enum ath9k_ht_macmode tx_chan_width
;
1002 struct ieee80211_hw
*hw
; /* mac80211 instance */
1003 struct pci_dev
*pdev
; /* Bus handle */
1004 void __iomem
*mem
; /* address of the device */
1005 struct tasklet_struct intr_tq
; /* General tasklet */
1006 struct tasklet_struct bcon_tasklet
; /* Beacon tasklet */
1007 struct ath_config sc_config
; /* per-instance load-time
1009 int sc_debug
; /* Debug masks */
1010 struct ath_hal
*sc_ah
; /* HAL Instance */
1011 struct ath_rate_softc
*sc_rc
; /* tx rate control support */
1012 u32 sc_intrstatus
; /* HAL_STATUS */
1013 enum ath9k_opmode sc_opmode
; /* current operating mode */
1015 /* Properties, Config */
1016 u8 sc_invalid
; /* being detached */
1017 u8 sc_beacons
; /* beacons running */
1018 u8 sc_scanning
; /* scanning active */
1019 u8 sc_txaggr
; /* enable 11n tx aggregation */
1020 u8 sc_rxaggr
; /* enable 11n rx aggregation */
1021 u8 sc_update_chainmask
; /* change chain mask */
1022 u8 sc_full_reset
; /* force full reset */
1023 enum wireless_mode sc_curmode
; /* current phy mode */
1024 u16 sc_curtxpow
; /* current tx power limit */
1025 u16 sc_curaid
; /* current association id */
1026 u8 sc_curbssid
[ETH_ALEN
];
1027 u8 sc_myaddr
[ETH_ALEN
];
1028 enum PROT_MODE sc_protmode
; /* protection mode */
1029 u8 sc_mcastantenna
;/* Multicast antenna number */
1030 u8 sc_txantenna
; /* data tx antenna
1032 u8 sc_nbcnvaps
; /* # of vaps sending beacons */
1033 u16 sc_nvaps
; /* # of active virtual ap's */
1034 struct ath_vap
*sc_vaps
[ATH_BCBUF
]; /* interface id
1036 enum ath9k_int sc_imask
; /* interrupt mask copy */
1037 u8 sc_bssidmask
[ETH_ALEN
];
1038 u8 sc_defant
; /* current default antenna */
1039 u8 sc_rxotherant
; /* rx's on non-default antenna*/
1040 u16 sc_cachelsz
; /* cache line size */
1041 int sc_slotupdate
; /* slot to next advance fsm */
1042 int sc_slottime
; /* slot time */
1044 int sc_bslot
[ATH_BCBUF
];/* beacon xmit slots */
1045 struct ath9k_node_stats sc_halstats
; /* station-mode rssi stats */
1046 struct list_head node_list
;
1047 struct ath_ht_info sc_ht_info
;
1048 int16_t sc_noise_floor
; /* signal noise floor in dBm */
1049 enum ath9k_ht_extprotspacing sc_ht_extprotspacing
;
1052 u8 sc_rxchaindetect_ref
;
1053 u8 sc_rxchaindetect_thresh5GHz
;
1054 u8 sc_rxchaindetect_thresh2GHz
;
1055 u8 sc_rxchaindetect_delta5GHz
;
1056 u8 sc_rxchaindetect_delta2GHz
;
1057 u32 sc_rtsaggrlimit
; /* Chipset specific
1060 #ifdef CONFIG_SLOW_ANT_DIV
1061 /* Slow antenna diversity */
1062 struct ath_antdiv sc_antdiv
;
1065 OK
, /* no change needed */
1066 UPDATE
, /* update pending */
1067 COMMIT
/* beacon sent, commit change */
1068 } sc_updateslot
; /* slot time update fsm */
1071 u32 sc_keymax
; /* size of key cache */
1072 DECLARE_BITMAP (sc_keymap
, ATH_KEYMAX
);/* key use bit map */
1073 u8 sc_splitmic
; /* split TKIP MIC keys */
1074 int sc_keytype
; /* type of the key being used */
1077 struct list_head sc_rxbuf
; /* receive buffer */
1078 struct ath_descdma sc_rxdma
; /* RX descriptors */
1079 int sc_rxbufsize
; /* rx size based on mtu */
1080 u32
*sc_rxlink
; /* link ptr in last RX desc */
1081 u32 sc_rxflush
; /* rx flush in progress */
1082 u64 sc_lastrx
; /* tsf of last rx'd frame */
1085 struct list_head sc_txbuf
; /* transmit buffer */
1086 struct ath_txq sc_txq
[ATH9K_NUM_TX_QUEUES
];
1087 struct ath_descdma sc_txdma
; /* TX descriptors */
1088 u32 sc_txqsetup
; /* h/w queues setup */
1089 u32 sc_txintrperiod
;/* tx interrupt batching */
1090 int sc_haltype2q
[ATH9K_WME_AC_VO
+1]; /* HAL WME
1092 u32 sc_ant_tx
[8]; /* recent tx frames/antenna */
1095 struct ath9k_txq_info sc_beacon_qi
; /* adhoc only: beacon
1097 struct ath_descdma sc_bdma
; /* beacon descriptors */
1098 struct ath_txq
*sc_cabq
; /* tx q for cab frames */
1099 struct list_head sc_bbuf
; /* beacon buffers */
1100 u32 sc_bhalq
; /* HAL q for outgoing beacons */
1101 u32 sc_bmisscount
; /* missed beacon transmits */
1102 u32 ast_be_xmit
; /* beacons transmitted */
1105 struct ieee80211_rate rates
[IEEE80211_NUM_BANDS
][ATH_RATE_MAX
];
1106 const struct ath9k_rate_table
*sc_rates
[WIRELESS_MODE_MAX
];
1107 const struct ath9k_rate_table
*sc_currates
; /* current rate table */
1108 u8 sc_rixmap
[256]; /* IEEE to h/w
1110 u8 sc_minrateix
; /* min h/w rate index */
1111 u8 sc_protrix
; /* protection rate index */
1113 u32 rateKbps
; /* transfer rate in kbs */
1114 u8 ieeerate
; /* IEEE rate */
1115 } sc_hwmap
[256]; /* h/w rate ix mappings */
1118 struct ieee80211_channel channels
[IEEE80211_NUM_BANDS
][ATH_CHAN_MAX
];
1119 struct ieee80211_supported_band sbands
[IEEE80211_NUM_BANDS
];
1120 struct ath9k_channel sc_curchan
; /* current h/w channel */
1123 spinlock_t sc_rxflushlock
; /* lock of RX flush */
1124 spinlock_t sc_rxbuflock
; /* rxbuf lock */
1125 spinlock_t sc_txbuflock
; /* txbuf lock */
1126 spinlock_t sc_resetlock
;
1127 spinlock_t node_lock
;
1130 int ath_init(u16 devid
, struct ath_softc
*sc
);
1131 void ath_deinit(struct ath_softc
*sc
);
1132 int ath_open(struct ath_softc
*sc
, struct ath9k_channel
*initial_chan
);
1133 int ath_suspend(struct ath_softc
*sc
);
1134 irqreturn_t
ath_isr(int irq
, void *dev
);
1135 int ath_reset(struct ath_softc
*sc
);
1136 void ath_scan_start(struct ath_softc
*sc
);
1137 void ath_scan_end(struct ath_softc
*sc
);
1138 int ath_set_channel(struct ath_softc
*sc
, struct ath9k_channel
*hchan
);
1139 void ath_setup_rate(struct ath_softc
*sc
,
1140 enum wireless_mode wMode
,
1141 enum RATE_TYPE type
,
1142 const struct ath9k_rate_table
*rt
);
1144 /*********************/
1145 /* Utility Functions */
1146 /*********************/
1148 void ath_key_reset(struct ath_softc
*sc
, u16 keyix
, int freeslot
);
1149 int ath_keyset(struct ath_softc
*sc
,
1151 struct ath9k_keyval
*hk
,
1152 const u8 mac
[ETH_ALEN
]);
1153 int ath_get_hal_qnum(u16 queue
, struct ath_softc
*sc
);
1154 int ath_get_mac80211_qnum(u32 queue
, struct ath_softc
*sc
);
1155 void ath_setslottime(struct ath_softc
*sc
);
1156 void ath_update_txpow(struct ath_softc
*sc
);
1157 int ath_cabq_update(struct ath_softc
*);
1158 void ath_get_currentCountry(struct ath_softc
*sc
,
1159 struct ath9k_country_entry
*ctry
);
1160 u64
ath_extend_tsf(struct ath_softc
*sc
, u32 rstamp
);
1161 void ath_internal_reset(struct ath_softc
*sc
);
1162 u32
ath_chan2flags(struct ieee80211_channel
*chan
, struct ath_softc
*sc
);
1163 dma_addr_t
ath_skb_map_single(struct ath_softc
*sc
,
1164 struct sk_buff
*skb
,
1167 void ath_skb_unmap_single(struct ath_softc
*sc
,
1168 struct sk_buff
*skb
,
1171 void ath_mcast_merge(struct ath_softc
*sc
, u32 mfilt
[2]);
1172 enum ath9k_ht_macmode
ath_cwm_macmode(struct ath_softc
*sc
);