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compute rootfs crc32 required for brcm63xx web upgrades
[openwrt/staging/florian.git] / package / mac80211 / patches / 303-rt2x00-Implement-support-for-rt2800usb.patch
1 From 101b65d221593c1bdeacf0c6085d885ea5447c4c Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Sat, 14 Mar 2009 20:46:40 +0100
4 Subject: [PATCH] rt2x00: Implement support for rt2800usb
5
6 Add support for the rt2800usb chipset.
7
8 Includes various patches from Mattias, Felix, Xose and Axel.
9
10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
11 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
12 Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
13 Signed-off-by: Axel Kollhofer <rain_maker@root-forum.org>
14 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
15 ---
16 drivers/net/wireless/rt2x00/Kconfig | 14 +
17 drivers/net/wireless/rt2x00/Makefile | 1 +
18 drivers/net/wireless/rt2x00/rt2800usb.c | 3032 +++++++++++++++++++++++++++++++
19 drivers/net/wireless/rt2x00/rt2800usb.h | 1934 ++++++++++++++++++++
20 drivers/net/wireless/rt2x00/rt2x00.h | 7 +
21 5 files changed, 4988 insertions(+), 0 deletions(-)
22 create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.c
23 create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.h
24
25 --- a/drivers/net/wireless/rt2x00/Makefile
26 +++ b/drivers/net/wireless/rt2x00/Makefile
27 @@ -19,3 +19,4 @@ obj-$(CONFIG_RT61PCI) += rt61pci.o
28 obj-$(CONFIG_RT2800PCI) += rt2800pci.o
29 obj-$(CONFIG_RT2500USB) += rt2500usb.o
30 obj-$(CONFIG_RT73USB) += rt73usb.o
31 +obj-$(CONFIG_RT2800USB) += rt2800usb.o
32 --- /dev/null
33 +++ b/drivers/net/wireless/rt2x00/rt2800usb.c
34 @@ -0,0 +1,3032 @@
35 +/*
36 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
37 + <http://rt2x00.serialmonkey.com>
38 +
39 + This program is free software; you can redistribute it and/or modify
40 + it under the terms of the GNU General Public License as published by
41 + the Free Software Foundation; either version 2 of the License, or
42 + (at your option) any later version.
43 +
44 + This program is distributed in the hope that it will be useful,
45 + but WITHOUT ANY WARRANTY; without even the implied warranty of
46 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
47 + GNU General Public License for more details.
48 +
49 + You should have received a copy of the GNU General Public License
50 + along with this program; if not, write to the
51 + Free Software Foundation, Inc.,
52 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
53 + */
54 +
55 +/*
56 + Module: rt2800usb
57 + Abstract: rt2800usb device specific routines.
58 + Supported chipsets: RT2800U.
59 + */
60 +
61 +#include <linux/crc-ccitt.h>
62 +#include <linux/delay.h>
63 +#include <linux/etherdevice.h>
64 +#include <linux/init.h>
65 +#include <linux/kernel.h>
66 +#include <linux/module.h>
67 +#include <linux/usb.h>
68 +
69 +#include "rt2x00.h"
70 +#include "rt2x00usb.h"
71 +#include "rt2800usb.h"
72 +
73 +/*
74 + * Allow hardware encryption to be disabled.
75 + */
76 +static int modparam_nohwcrypt = 0;
77 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
78 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
79 +
80 +/*
81 + * Register access.
82 + * All access to the CSR registers will go through the methods
83 + * rt2x00usb_register_read and rt2x00usb_register_write.
84 + * BBP and RF register require indirect register access,
85 + * and use the CSR registers BBPCSR and RFCSR to achieve this.
86 + * These indirect registers work with busy bits,
87 + * and we will try maximal REGISTER_BUSY_COUNT times to access
88 + * the register while taking a REGISTER_BUSY_DELAY us delay
89 + * between each attampt. When the busy bit is still set at that time,
90 + * the access attempt is considered to have failed,
91 + * and we will print an error.
92 + * The _lock versions must be used if you already hold the csr_mutex
93 + */
94 +#define WAIT_FOR_BBP(__dev, __reg) \
95 + rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
96 +#define WAIT_FOR_RFCSR(__dev, __reg) \
97 + rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
98 +#define WAIT_FOR_RF(__dev, __reg) \
99 + rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
100 +#define WAIT_FOR_MCU(__dev, __reg) \
101 + rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
102 + H2M_MAILBOX_CSR_OWNER, (__reg))
103 +
104 +static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
105 + const unsigned int word, const u8 value)
106 +{
107 + u32 reg;
108 +
109 + mutex_lock(&rt2x00dev->csr_mutex);
110 +
111 + /*
112 + * Wait until the BBP becomes available, afterwards we
113 + * can safely write the new data into the register.
114 + */
115 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
116 + reg = 0;
117 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
118 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
119 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
120 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
121 +
122 + rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
123 + }
124 +
125 + mutex_unlock(&rt2x00dev->csr_mutex);
126 +}
127 +
128 +static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
129 + const unsigned int word, u8 *value)
130 +{
131 + u32 reg;
132 +
133 + mutex_lock(&rt2x00dev->csr_mutex);
134 +
135 + /*
136 + * Wait until the BBP becomes available, afterwards we
137 + * can safely write the read request into the register.
138 + * After the data has been written, we wait until hardware
139 + * returns the correct value, if at any time the register
140 + * doesn't become available in time, reg will be 0xffffffff
141 + * which means we return 0xff to the caller.
142 + */
143 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
144 + reg = 0;
145 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
146 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
147 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
148 +
149 + rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
150 +
151 + WAIT_FOR_BBP(rt2x00dev, &reg);
152 + }
153 +
154 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
155 +
156 + mutex_unlock(&rt2x00dev->csr_mutex);
157 +}
158 +
159 +static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
160 + const unsigned int word, const u8 value)
161 +{
162 + u32 reg;
163 +
164 + mutex_lock(&rt2x00dev->csr_mutex);
165 +
166 + /*
167 + * Wait until the RFCSR becomes available, afterwards we
168 + * can safely write the new data into the register.
169 + */
170 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
171 + reg = 0;
172 + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
173 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
174 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
175 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
176 +
177 + rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
178 + }
179 +
180 + mutex_unlock(&rt2x00dev->csr_mutex);
181 +}
182 +
183 +static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
184 + const unsigned int word, u8 *value)
185 +{
186 + u32 reg;
187 +
188 + mutex_lock(&rt2x00dev->csr_mutex);
189 +
190 + /*
191 + * Wait until the RFCSR becomes available, afterwards we
192 + * can safely write the read request into the register.
193 + * After the data has been written, we wait until hardware
194 + * returns the correct value, if at any time the register
195 + * doesn't become available in time, reg will be 0xffffffff
196 + * which means we return 0xff to the caller.
197 + */
198 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
199 + reg = 0;
200 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
201 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
202 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
203 +
204 + rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
205 +
206 + WAIT_FOR_RFCSR(rt2x00dev, &reg);
207 + }
208 +
209 + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
210 +
211 + mutex_unlock(&rt2x00dev->csr_mutex);
212 +}
213 +
214 +static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
215 + const unsigned int word, const u32 value)
216 +{
217 + u32 reg;
218 +
219 + mutex_lock(&rt2x00dev->csr_mutex);
220 +
221 + /*
222 + * Wait until the RF becomes available, afterwards we
223 + * can safely write the new data into the register.
224 + */
225 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
226 + reg = 0;
227 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
228 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
229 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
230 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
231 +
232 + rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
233 + rt2x00_rf_write(rt2x00dev, word, value);
234 + }
235 +
236 + mutex_unlock(&rt2x00dev->csr_mutex);
237 +}
238 +
239 +static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
240 + const u8 command, const u8 token,
241 + const u8 arg0, const u8 arg1)
242 +{
243 + u32 reg;
244 +
245 + mutex_lock(&rt2x00dev->csr_mutex);
246 +
247 + /*
248 + * Wait until the MCU becomes available, afterwards we
249 + * can safely write the new data into the register.
250 + */
251 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
252 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
253 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
254 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
255 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
256 + rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
257 +
258 + reg = 0;
259 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
260 + rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
261 + }
262 +
263 + mutex_unlock(&rt2x00dev->csr_mutex);
264 +}
265 +
266 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
267 +static const struct rt2x00debug rt2800usb_rt2x00debug = {
268 + .owner = THIS_MODULE,
269 + .csr = {
270 + .read = rt2x00usb_register_read,
271 + .write = rt2x00usb_register_write,
272 + .flags = RT2X00DEBUGFS_OFFSET,
273 + .word_base = CSR_REG_BASE,
274 + .word_size = sizeof(u32),
275 + .word_count = CSR_REG_SIZE / sizeof(u32),
276 + },
277 + .eeprom = {
278 + .read = rt2x00_eeprom_read,
279 + .write = rt2x00_eeprom_write,
280 + .word_base = EEPROM_BASE,
281 + .word_size = sizeof(u16),
282 + .word_count = EEPROM_SIZE / sizeof(u16),
283 + },
284 + .bbp = {
285 + .read = rt2800usb_bbp_read,
286 + .write = rt2800usb_bbp_write,
287 + .word_base = BBP_BASE,
288 + .word_size = sizeof(u8),
289 + .word_count = BBP_SIZE / sizeof(u8),
290 + },
291 + .rf = {
292 + .read = rt2x00_rf_read,
293 + .write = rt2800usb_rf_write,
294 + .word_base = RF_BASE,
295 + .word_size = sizeof(u32),
296 + .word_count = RF_SIZE / sizeof(u32),
297 + },
298 +};
299 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
300 +
301 +#ifdef CONFIG_RT2X00_LIB_RFKILL
302 +static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
303 +{
304 + u32 reg;
305 +
306 + rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
307 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
308 +}
309 +#else
310 +#define rt2800usb_rfkill_poll NULL
311 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
312 +
313 +#ifdef CONFIG_RT2X00_LIB_LEDS
314 +static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
315 + enum led_brightness brightness)
316 +{
317 + struct rt2x00_led *led =
318 + container_of(led_cdev, struct rt2x00_led, led_dev);
319 + unsigned int enabled = brightness != LED_OFF;
320 + unsigned int bg_mode =
321 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
322 + unsigned int polarity =
323 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
324 + EEPROM_FREQ_LED_POLARITY);
325 + unsigned int ledmode =
326 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
327 + EEPROM_FREQ_LED_MODE);
328 +
329 + if (led->type == LED_TYPE_RADIO) {
330 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
331 + enabled ? 0x20 : 0);
332 + } else if (led->type == LED_TYPE_ASSOC) {
333 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
334 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
335 + } else if (led->type == LED_TYPE_QUALITY) {
336 + /*
337 + * The brightness is divided into 6 levels (0 - 5),
338 + * The specs tell us the following levels:
339 + * 0, 1 ,3, 7, 15, 31
340 + * to determine the level in a simple way we can simply
341 + * work with bitshifting:
342 + * (1 << level) - 1
343 + */
344 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
345 + (1 << brightness / (LED_FULL / 6)) - 1,
346 + polarity);
347 + }
348 +}
349 +
350 +static int rt2800usb_blink_set(struct led_classdev *led_cdev,
351 + unsigned long *delay_on,
352 + unsigned long *delay_off)
353 +{
354 + struct rt2x00_led *led =
355 + container_of(led_cdev, struct rt2x00_led, led_dev);
356 + u32 reg;
357 +
358 + rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
359 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
360 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
361 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
362 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
363 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
364 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
365 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
366 + rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
367 +
368 + return 0;
369 +}
370 +
371 +static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
372 + struct rt2x00_led *led,
373 + enum led_type type)
374 +{
375 + led->rt2x00dev = rt2x00dev;
376 + led->type = type;
377 + led->led_dev.brightness_set = rt2800usb_brightness_set;
378 + led->led_dev.blink_set = rt2800usb_blink_set;
379 + led->flags = LED_INITIALIZED;
380 +}
381 +#endif /* CONFIG_RT2X00_LIB_LEDS */
382 +
383 +/*
384 + * Configuration handlers.
385 + */
386 +static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
387 + struct rt2x00lib_crypto *crypto,
388 + struct ieee80211_key_conf *key)
389 +{
390 + struct mac_wcid_entry wcid_entry;
391 + struct mac_iveiv_entry iveiv_entry;
392 + u32 offset;
393 + u32 reg;
394 +
395 + offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
396 +
397 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
398 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
399 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
400 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
401 + (crypto->cmd == SET_KEY) * crypto->cipher);
402 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
403 + (crypto->cmd == SET_KEY) * crypto->bssidx);
404 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
405 + rt2x00usb_register_write(rt2x00dev, offset, reg);
406 +
407 + offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
408 +
409 + memset(&iveiv_entry, 0, sizeof(iveiv_entry));
410 + if ((crypto->cipher == CIPHER_TKIP) ||
411 + (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
412 + (crypto->cipher == CIPHER_AES))
413 + iveiv_entry.iv[3] |= 0x20;
414 + iveiv_entry.iv[3] |= key->keyidx << 6;
415 + rt2x00usb_register_multiwrite(rt2x00dev, offset,
416 + &iveiv_entry, sizeof(iveiv_entry));
417 +
418 + offset = MAC_WCID_ENTRY(key->hw_key_idx);
419 +
420 + memset(&wcid_entry, 0, sizeof(wcid_entry));
421 + if (crypto->cmd == SET_KEY)
422 + memcpy(&wcid_entry, crypto->address, ETH_ALEN);
423 + rt2x00usb_register_multiwrite(rt2x00dev, offset,
424 + &wcid_entry, sizeof(wcid_entry));
425 +}
426 +
427 +static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
428 + struct rt2x00lib_crypto *crypto,
429 + struct ieee80211_key_conf *key)
430 +{
431 + struct hw_key_entry key_entry;
432 + struct rt2x00_field32 field;
433 + int timeout;
434 + u32 offset;
435 + u32 reg;
436 +
437 + if (crypto->cmd == SET_KEY) {
438 + key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
439 +
440 + memcpy(key_entry.key, crypto->key,
441 + sizeof(key_entry.key));
442 + memcpy(key_entry.tx_mic, crypto->tx_mic,
443 + sizeof(key_entry.tx_mic));
444 + memcpy(key_entry.rx_mic, crypto->rx_mic,
445 + sizeof(key_entry.rx_mic));
446 +
447 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
448 + timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
449 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
450 + USB_VENDOR_REQUEST_OUT,
451 + offset, &key_entry,
452 + sizeof(key_entry),
453 + timeout);
454 + }
455 +
456 + /*
457 + * The cipher types are stored over multiple registers
458 + * starting with SHARED_KEY_MODE_BASE each word will have
459 + * 32 bits and contains the cipher types for 2 bssidx each.
460 + * Using the correct defines correctly will cause overhead,
461 + * so just calculate the correct offset.
462 + */
463 + field.bit_offset = 4 * (key->hw_key_idx % 8);
464 + field.bit_mask = 0x7 << field.bit_offset;
465 +
466 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
467 +
468 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
469 + rt2x00_set_field32(&reg, field,
470 + (crypto->cmd == SET_KEY) * crypto->cipher);
471 + rt2x00usb_register_write(rt2x00dev, offset, reg);
472 +
473 + /*
474 + * Update WCID information
475 + */
476 + rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
477 +
478 + return 0;
479 +}
480 +
481 +static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
482 + struct rt2x00lib_crypto *crypto,
483 + struct ieee80211_key_conf *key)
484 +{
485 + struct hw_key_entry key_entry;
486 + int timeout;
487 + u32 offset;
488 +
489 + if (crypto->cmd == SET_KEY) {
490 + /*
491 + * 1 pairwise key is possible per AID, this means that the AID
492 + * equals our hw_key_idx. Make sure the WCID starts _after_ the
493 + * last possible shared key entry.
494 + */
495 + if (crypto->aid > (256 - 32))
496 + return -ENOSPC;
497 +
498 + key->hw_key_idx = 32 + crypto->aid;
499 +
500 + memcpy(key_entry.key, crypto->key,
501 + sizeof(key_entry.key));
502 + memcpy(key_entry.tx_mic, crypto->tx_mic,
503 + sizeof(key_entry.tx_mic));
504 + memcpy(key_entry.rx_mic, crypto->rx_mic,
505 + sizeof(key_entry.rx_mic));
506 +
507 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
508 + timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
509 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
510 + USB_VENDOR_REQUEST_OUT,
511 + offset, &key_entry,
512 + sizeof(key_entry),
513 + timeout);
514 + }
515 +
516 + /*
517 + * Update WCID information
518 + */
519 + rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
520 +
521 + return 0;
522 +}
523 +
524 +static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
525 + const unsigned int filter_flags)
526 +{
527 + u32 reg;
528 +
529 + /*
530 + * Start configuration steps.
531 + * Note that the version error will always be dropped
532 + * and broadcast frames will always be accepted since
533 + * there is no filter for it at this time.
534 + */
535 + rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
536 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
537 + !(filter_flags & FIF_FCSFAIL));
538 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
539 + !(filter_flags & FIF_PLCPFAIL));
540 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
541 + !(filter_flags & FIF_PROMISC_IN_BSS));
542 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
543 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
544 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
545 + !(filter_flags & FIF_ALLMULTI));
546 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
547 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
548 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
549 + !(filter_flags & FIF_CONTROL));
550 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
551 + !(filter_flags & FIF_CONTROL));
552 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
553 + !(filter_flags & FIF_CONTROL));
554 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
555 + !(filter_flags & FIF_CONTROL));
556 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
557 + !(filter_flags & FIF_CONTROL));
558 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
559 + !(filter_flags & FIF_CONTROL));
560 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
561 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
562 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
563 + !(filter_flags & FIF_CONTROL));
564 + rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
565 +}
566 +
567 +static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
568 + struct rt2x00_intf *intf,
569 + struct rt2x00intf_conf *conf,
570 + const unsigned int flags)
571 +{
572 + unsigned int beacon_base;
573 + u32 reg;
574 +
575 + if (flags & CONFIG_UPDATE_TYPE) {
576 + /*
577 + * Clear current synchronisation setup.
578 + * For the Beacon base registers we only need to clear
579 + * the first byte since that byte contains the VALID and OWNER
580 + * bits which (when set to 0) will invalidate the entire beacon.
581 + */
582 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
583 + rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
584 +
585 + /*
586 + * Enable synchronisation.
587 + */
588 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
589 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
590 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
591 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
592 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
593 + }
594 +
595 + if (flags & CONFIG_UPDATE_MAC) {
596 + reg = le32_to_cpu(conf->mac[1]);
597 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
598 + conf->mac[1] = cpu_to_le32(reg);
599 +
600 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
601 + conf->mac, sizeof(conf->mac));
602 + }
603 +
604 + if (flags & CONFIG_UPDATE_BSSID) {
605 + reg = le32_to_cpu(conf->bssid[1]);
606 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
607 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
608 + conf->bssid[1] = cpu_to_le32(reg);
609 +
610 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
611 + conf->bssid, sizeof(conf->bssid));
612 + }
613 +}
614 +
615 +static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
616 + struct rt2x00lib_erp *erp)
617 +{
618 + u32 reg;
619 +
620 + rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
621 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
622 + DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
623 + rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
624 +
625 + rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
626 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
627 + !!erp->short_preamble);
628 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
629 + !!erp->short_preamble);
630 + rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
631 +
632 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
633 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
634 + erp->cts_protection ? 2 : 0);
635 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
636 +
637 + rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
638 + erp->basic_rates);
639 + rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
640 +
641 + rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
642 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
643 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
644 + rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
645 +
646 + rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
647 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
648 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
649 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
650 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
651 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
652 + rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
653 +}
654 +
655 +static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
656 + struct antenna_setup *ant)
657 +{
658 + u16 eeprom;
659 + u8 r1;
660 + u8 r3;
661 +
662 + /*
663 + * FIXME: Use requested antenna configuration.
664 + */
665 +
666 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
667 +
668 + rt2800usb_bbp_read(rt2x00dev, 1, &r1);
669 + rt2800usb_bbp_read(rt2x00dev, 3, &r3);
670 +
671 + /*
672 + * Configure the TX antenna.
673 + */
674 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
675 + case 1:
676 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
677 + break;
678 + case 2:
679 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
680 + break;
681 + case 3:
682 + /* Do nothing */
683 + break;
684 + }
685 +
686 + /*
687 + * Configure the RX antenna.
688 + */
689 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
690 + case 1:
691 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
692 + break;
693 + case 2:
694 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
695 + break;
696 + case 3:
697 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
698 + break;
699 + }
700 +
701 + rt2800usb_bbp_write(rt2x00dev, 3, r3);
702 + rt2800usb_bbp_write(rt2x00dev, 1, r1);
703 +}
704 +
705 +static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
706 + struct rt2x00lib_conf *libconf)
707 +{
708 + u16 eeprom;
709 + short lna_gain;
710 +
711 + if (libconf->rf.channel <= 14) {
712 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
713 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
714 + } else if (libconf->rf.channel <= 64) {
715 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
716 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
717 + } else if (libconf->rf.channel <= 128) {
718 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
719 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
720 + } else {
721 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
722 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
723 + }
724 +
725 + rt2x00dev->lna_gain = lna_gain;
726 +}
727 +
728 +static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
729 + struct ieee80211_conf *conf,
730 + struct rf_channel *rf,
731 + struct channel_info *info)
732 +{
733 + u16 eeprom;
734 +
735 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
736 +
737 + /*
738 + * Determine antenna settings from EEPROM
739 + */
740 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
741 +
742 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
743 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
744 +
745 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
746 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
747 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
748 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
749 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
750 +
751 + if (rf->channel > 14) {
752 + /*
753 + * When TX power is below 0, we should increase it by 7 to
754 + * make it a positive value (Minumum value is -7).
755 + * However this means that values between 0 and 7 have
756 + * double meaning, and we should set a 7DBm boost flag.
757 + */
758 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
759 + (info->tx_power1 >= 0));
760 +
761 + if (info->tx_power1 < 0)
762 + info->tx_power1 += 7;
763 +
764 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
765 + TXPOWER_A_TO_DEV(info->tx_power1));
766 +
767 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
768 + (info->tx_power2 >= 0));
769 +
770 + if (info->tx_power2 < 0)
771 + info->tx_power2 += 7;
772 +
773 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
774 + TXPOWER_A_TO_DEV(info->tx_power2));
775 + } else {
776 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
777 + TXPOWER_G_TO_DEV(info->tx_power1));
778 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
779 + TXPOWER_G_TO_DEV(info->tx_power2));
780 + }
781 +
782 + rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
783 +
784 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
785 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
786 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
787 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
788 +
789 + udelay(200);
790 +
791 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
792 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
793 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
794 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
795 +
796 + udelay(200);
797 +
798 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
799 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
800 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
801 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
802 +}
803 +
804 +static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
805 + struct ieee80211_conf *conf,
806 + struct rf_channel *rf,
807 + struct channel_info *info)
808 +{
809 + u8 rfcsr;
810 +
811 + rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
812 + rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
813 +
814 + rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
815 + rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
816 + rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
817 +
818 + rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
819 + rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
820 + TXPOWER_G_TO_DEV(info->tx_power1));
821 + rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
822 +
823 + rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
824 + rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
825 + rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
826 +
827 + if (conf_is_ht40(conf))
828 + rt2800usb_rfcsr_write(rt2x00dev, 24,
829 + rt2x00dev->calibration_bw40);
830 + else
831 + rt2800usb_rfcsr_write(rt2x00dev, 24,
832 + rt2x00dev->calibration_bw20);
833 +
834 + rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
835 + rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
836 + rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
837 +}
838 +
839 +static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
840 + struct ieee80211_conf *conf,
841 + struct rf_channel *rf,
842 + struct channel_info *info)
843 +{
844 + u32 reg;
845 + unsigned int tx_pin;
846 + u16 eeprom;
847 + u8 bbp;
848 +
849 + /*
850 + * Determine antenna settings from EEPROM
851 + */
852 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
853 +
854 + if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
855 + rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
856 + else
857 + rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
858 +
859 + /*
860 + * Change BBP settings
861 + */
862 + rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
863 + rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
864 + rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
865 + rt2800usb_bbp_write(rt2x00dev, 86, 0);
866 +
867 + if (rf->channel <= 14) {
868 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
869 + rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
870 + rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
871 + } else {
872 + rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
873 + rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
874 + }
875 + } else {
876 + rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
877 +
878 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
879 + rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
880 + else
881 + rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
882 + }
883 +
884 + rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
885 + rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
886 + rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
887 + rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
888 + rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
889 +
890 + tx_pin = 0;
891 +
892 + /* Turn on unused PA or LNA when not using 1T or 1R */
893 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
894 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
895 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
896 + }
897 +
898 + /* Turn on unused PA or LNA when not using 1T or 1R */
899 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
900 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
901 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
902 + }
903 +
904 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
905 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
906 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
907 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
908 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
909 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
910 +
911 + rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
912 +
913 + rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
914 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
915 + rt2800usb_bbp_write(rt2x00dev, 4, bbp);
916 +
917 + rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
918 + rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
919 + rt2800usb_bbp_write(rt2x00dev, 3, bbp);
920 +
921 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
922 + if (conf_is_ht40(conf)) {
923 + rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
924 + rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
925 + rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
926 + } else {
927 + rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
928 + rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
929 + rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
930 + }
931 + }
932 +
933 + msleep(1);
934 +}
935 +
936 +static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
937 + const int txpower)
938 +{
939 + u32 reg;
940 + u32 value = TXPOWER_G_TO_DEV(txpower);
941 + u8 r1;
942 +
943 + rt2800usb_bbp_read(rt2x00dev, 1, &r1);
944 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
945 + rt2800usb_bbp_write(rt2x00dev, 1, r1);
946 +
947 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
948 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
949 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
950 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
951 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
952 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
953 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
954 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
955 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
956 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
957 +
958 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
959 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
960 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
961 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
962 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
963 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
964 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
965 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
966 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
967 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
968 +
969 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
970 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
971 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
972 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
973 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
974 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
975 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
976 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
977 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
978 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
979 +
980 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
981 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
982 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
983 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
984 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
985 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
986 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
987 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
988 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
989 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
990 +
991 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
992 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
993 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
994 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
995 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
996 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
997 +}
998 +
999 +static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1000 + struct rt2x00lib_conf *libconf)
1001 +{
1002 + u32 reg;
1003 +
1004 + rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1005 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1006 + libconf->conf->short_frame_max_tx_count);
1007 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1008 + libconf->conf->long_frame_max_tx_count);
1009 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1010 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1011 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1012 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1013 + rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
1014 +}
1015 +
1016 +static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
1017 + struct rt2x00lib_conf *libconf)
1018 +{
1019 + u32 reg;
1020 +
1021 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1022 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1023 + libconf->conf->beacon_int * 16);
1024 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1025 +}
1026 +
1027 +static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
1028 + struct rt2x00lib_conf *libconf)
1029 +{
1030 + enum dev_state state =
1031 + (libconf->conf->flags & IEEE80211_CONF_PS) ?
1032 + STATE_SLEEP : STATE_AWAKE;
1033 + u32 reg;
1034 +
1035 + if (state == STATE_SLEEP) {
1036 + rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1037 +
1038 + rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1039 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1040 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1041 + libconf->conf->listen_interval - 1);
1042 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1043 + rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1044 +
1045 + rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
1046 + } else {
1047 + rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1048 +
1049 + rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1050 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1051 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1052 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1053 + rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1054 + }
1055 +}
1056 +
1057 +static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1058 + struct rt2x00lib_conf *libconf,
1059 + const unsigned int flags)
1060 +{
1061 + /* Always recalculate LNA gain before changing configuration */
1062 + rt2800usb_config_lna_gain(rt2x00dev, libconf);
1063 +
1064 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1065 + rt2800usb_config_channel(rt2x00dev, libconf->conf,
1066 + &libconf->rf, &libconf->channel);
1067 + if (flags & IEEE80211_CONF_CHANGE_POWER)
1068 + rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1069 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1070 + rt2800usb_config_retry_limit(rt2x00dev, libconf);
1071 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1072 + rt2800usb_config_duration(rt2x00dev, libconf);
1073 + if (flags & IEEE80211_CONF_CHANGE_PS)
1074 + rt2800usb_config_ps(rt2x00dev, libconf);
1075 +}
1076 +
1077 +/*
1078 + * Link tuning
1079 + */
1080 +static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1081 + struct link_qual *qual)
1082 +{
1083 + u32 reg;
1084 +
1085 + /*
1086 + * Update FCS error count from register.
1087 + */
1088 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1089 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1090 +}
1091 +
1092 +static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1093 +{
1094 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1095 + if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1096 + return 0x1c + (2 * rt2x00dev->lna_gain);
1097 + else
1098 + return 0x2e + rt2x00dev->lna_gain;
1099 + }
1100 +
1101 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1102 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1103 + else
1104 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1105 +}
1106 +
1107 +static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1108 + struct link_qual *qual, u8 vgc_level)
1109 +{
1110 + if (qual->vgc_level != vgc_level) {
1111 + rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1112 + qual->vgc_level = vgc_level;
1113 + qual->vgc_level_reg = vgc_level;
1114 + }
1115 +}
1116 +
1117 +static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1118 + struct link_qual *qual)
1119 +{
1120 + rt2800usb_set_vgc(rt2x00dev, qual,
1121 + rt2800usb_get_default_vgc(rt2x00dev));
1122 +}
1123 +
1124 +static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1125 + struct link_qual *qual, const u32 count)
1126 +{
1127 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1128 + return;
1129 +
1130 + /*
1131 + * When RSSI is better then -80 increase VGC level with 0x10
1132 + */
1133 + rt2800usb_set_vgc(rt2x00dev, qual,
1134 + rt2800usb_get_default_vgc(rt2x00dev) +
1135 + ((qual->rssi > -80) * 0x10));
1136 +}
1137 +
1138 +/*
1139 + * Firmware functions
1140 + */
1141 +static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1142 +{
1143 + return FIRMWARE_RT2870;
1144 +}
1145 +
1146 +static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1147 +{
1148 + u16 fw_crc;
1149 + u16 crc;
1150 +
1151 + /*
1152 + * The last 2 bytes in the firmware array are the crc checksum itself,
1153 + * this means that we should never pass those 2 bytes to the crc
1154 + * algorithm.
1155 + */
1156 + fw_crc = (data[len - 2] << 8 | data[len - 1]);
1157 +
1158 + /*
1159 + * Use the crc ccitt algorithm.
1160 + * This will return the same value as the legacy driver which
1161 + * used bit ordering reversion on the both the firmware bytes
1162 + * before input input as well as on the final output.
1163 + * Obviously using crc ccitt directly is much more efficient.
1164 + */
1165 + crc = crc_ccitt(~0, data, len - 2);
1166 +
1167 + /*
1168 + * There is a small difference between the crc-itu-t + bitrev and
1169 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1170 + * will be swapped, use swab16 to convert the crc to the correct
1171 + * value.
1172 + */
1173 + crc = swab16(crc);
1174 +
1175 + return fw_crc == crc;
1176 +}
1177 +
1178 +static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1179 + const u8 *data, const size_t len)
1180 +{
1181 + u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1182 + size_t offset = 0;
1183 +
1184 + /*
1185 + * Firmware files:
1186 + * There are 2 variations of the rt2870 firmware.
1187 + * a) size: 4kb
1188 + * b) size: 8kb
1189 + * Note that (b) contains 2 seperate firmware blobs of 4k
1190 + * within the file. The first blob is the same firmware as (a),
1191 + * but the second blob is for the additional chipsets.
1192 + */
1193 + if (len != 4096 && len != 8192)
1194 + return FW_BAD_LENGTH;
1195 +
1196 + /*
1197 + * Check if we need the upper 4kb firmware data or not.
1198 + */
1199 + if ((len == 4096) &&
1200 + (chipset != 0x2860) &&
1201 + (chipset != 0x2872) &&
1202 + (chipset != 0x3070))
1203 + return FW_BAD_VERSION;
1204 +
1205 + /*
1206 + * 8kb firmware files must be checked as if it were
1207 + * 2 seperate firmware files.
1208 + */
1209 + while (offset < len) {
1210 + if (!rt2800usb_check_crc(data + offset, 4096))
1211 + return FW_BAD_CRC;
1212 +
1213 + offset += 4096;
1214 + }
1215 +
1216 + return FW_OK;
1217 +}
1218 +
1219 +static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1220 + const u8 *data, const size_t len)
1221 +{
1222 + unsigned int i;
1223 + int status;
1224 + u32 reg;
1225 + u32 offset;
1226 + u32 length;
1227 + u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1228 +
1229 + /*
1230 + * Check which section of the firmware we need.
1231 + */
1232 + if ((chipset == 0x2860) || (chipset == 0x2872) || (chipset == 0x3070)) {
1233 + offset = 0;
1234 + length = 4096;
1235 + } else {
1236 + offset = 4096;
1237 + length = 4096;
1238 + }
1239 +
1240 + /*
1241 + * Wait for stable hardware.
1242 + */
1243 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1244 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1245 + if (reg && reg != ~0)
1246 + break;
1247 + msleep(1);
1248 + }
1249 +
1250 + if (i == REGISTER_BUSY_COUNT) {
1251 + ERROR(rt2x00dev, "Unstable hardware.\n");
1252 + return -EBUSY;
1253 + }
1254 +
1255 + /*
1256 + * Write firmware to device.
1257 + */
1258 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1259 + USB_VENDOR_REQUEST_OUT,
1260 + FIRMWARE_IMAGE_BASE,
1261 + data + offset, length,
1262 + REGISTER_TIMEOUT32(length));
1263 +
1264 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1265 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1266 +
1267 + /*
1268 + * Send firmware request to device to load firmware,
1269 + * we need to specify a long timeout time.
1270 + */
1271 + status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1272 + 0, USB_MODE_FIRMWARE,
1273 + REGISTER_TIMEOUT_FIRMWARE);
1274 + if (status < 0) {
1275 + ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1276 + return status;
1277 + }
1278 +
1279 + /*
1280 + * Wait for device to stabilize.
1281 + */
1282 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1283 + rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1284 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1285 + break;
1286 + msleep(1);
1287 + }
1288 +
1289 + if (i == REGISTER_BUSY_COUNT) {
1290 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1291 + return -EBUSY;
1292 + }
1293 +
1294 + /*
1295 + * Initialize firmware.
1296 + */
1297 + rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1298 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1299 + msleep(1);
1300 +
1301 + return 0;
1302 +}
1303 +
1304 +/*
1305 + * Initialization functions.
1306 + */
1307 +static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1308 +{
1309 + u32 reg;
1310 + unsigned int i;
1311 +
1312 + /*
1313 + * Wait untill BBP and RF are ready.
1314 + */
1315 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1316 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1317 + if (reg && reg != ~0)
1318 + break;
1319 + msleep(1);
1320 + }
1321 +
1322 + if (i == REGISTER_BUSY_COUNT) {
1323 + ERROR(rt2x00dev, "Unstable hardware.\n");
1324 + return -EBUSY;
1325 + }
1326 +
1327 + rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1328 + rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1329 +
1330 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1331 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1332 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1333 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1334 +
1335 + rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1336 +
1337 + rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1338 + USB_MODE_RESET, REGISTER_TIMEOUT);
1339 +
1340 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1341 +
1342 + rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1343 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1344 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1345 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1346 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1347 + rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1348 +
1349 + rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1350 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1351 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1352 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1353 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1354 + rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1355 +
1356 + rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1357 + rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1358 +
1359 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1360 +
1361 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1362 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1363 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1364 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1365 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1366 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1367 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1368 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1369 +
1370 + if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1371 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1372 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1373 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1374 + } else {
1375 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1376 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1377 + }
1378 +
1379 + rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1380 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1381 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1382 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1383 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1384 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1385 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1386 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1387 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1388 + rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1389 +
1390 + rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1391 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1392 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1393 + rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1394 +
1395 + rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1396 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1397 + if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1398 + rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1399 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1400 + else
1401 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1402 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1403 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1404 + rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1405 +
1406 + rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1407 +
1408 + rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1409 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1410 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1411 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1412 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1413 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1414 + rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1415 +
1416 + rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1417 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1418 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1419 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1420 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1421 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1422 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1423 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1424 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1425 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1426 + rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1427 +
1428 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1429 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1430 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1431 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1432 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1433 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1434 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1435 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1436 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1437 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1438 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1439 +
1440 + rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1441 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1442 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1443 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1444 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1445 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1446 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1447 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1448 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1449 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1450 + rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1451 +
1452 + rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1453 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1454 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1455 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1456 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1457 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1458 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1459 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1460 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1461 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1462 + rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1463 +
1464 + rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1465 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1466 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1467 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1468 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1469 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1470 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1471 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1472 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1473 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1474 + rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1475 +
1476 + rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1477 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1478 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1479 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1480 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1481 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1482 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1483 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1484 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1485 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1486 + rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1487 +
1488 + rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1489 +
1490 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1491 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1492 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1493 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1494 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1495 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1496 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1497 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1498 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1499 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1500 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1501 +
1502 + rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1503 + rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1504 +
1505 + rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1506 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1507 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1508 + IEEE80211_MAX_RTS_THRESHOLD);
1509 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1510 + rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1511 +
1512 + rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1513 + rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1514 +
1515 + /*
1516 + * ASIC will keep garbage value after boot, clear encryption keys.
1517 + */
1518 + for (i = 0; i < 256; i++) {
1519 + u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1520 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1521 + wcid, sizeof(wcid));
1522 +
1523 + rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1524 + rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1525 + }
1526 +
1527 + for (i = 0; i < 16; i++)
1528 + rt2x00usb_register_write(rt2x00dev,
1529 + SHARED_KEY_MODE_ENTRY(i), 0);
1530 +
1531 + /*
1532 + * Clear all beacons
1533 + * For the Beacon base registers we only need to clear
1534 + * the first byte since that byte contains the VALID and OWNER
1535 + * bits which (when set to 0) will invalidate the entire beacon.
1536 + */
1537 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1538 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1539 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1540 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1541 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1542 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1543 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1544 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1545 +
1546 + rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1547 + rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1548 + rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1549 +
1550 + rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1551 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1552 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1553 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1554 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1555 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1556 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1557 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1558 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1559 + rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1560 +
1561 + rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1562 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1563 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1564 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1565 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1566 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1567 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1568 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1569 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1570 + rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1571 +
1572 + rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1573 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1574 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1575 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1576 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1577 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1578 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1579 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1580 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1581 + rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1582 +
1583 + rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1584 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1585 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1586 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1587 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1588 + rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1589 +
1590 + /*
1591 + * We must clear the error counters.
1592 + * These registers are cleared on read,
1593 + * so we may pass a useless variable to store the value.
1594 + */
1595 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1596 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1597 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1598 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1599 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1600 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1601 +
1602 + return 0;
1603 +}
1604 +
1605 +static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1606 +{
1607 + unsigned int i;
1608 + u32 reg;
1609 +
1610 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1611 + rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1612 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1613 + return 0;
1614 +
1615 + udelay(REGISTER_BUSY_DELAY);
1616 + }
1617 +
1618 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1619 + return -EACCES;
1620 +}
1621 +
1622 +static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1623 +{
1624 + unsigned int i;
1625 + u8 value;
1626 +
1627 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1628 + rt2800usb_bbp_read(rt2x00dev, 0, &value);
1629 + if ((value != 0xff) && (value != 0x00))
1630 + return 0;
1631 + udelay(REGISTER_BUSY_DELAY);
1632 + }
1633 +
1634 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1635 + return -EACCES;
1636 +}
1637 +
1638 +static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1639 +{
1640 + unsigned int i;
1641 + u16 eeprom;
1642 + u8 reg_id;
1643 + u8 value;
1644 +
1645 + if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1646 + rt2800usb_wait_bbp_ready(rt2x00dev)))
1647 + return -EACCES;
1648 +
1649 + rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1650 + rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1651 + rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1652 + rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1653 + rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1654 + rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1655 + rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1656 + rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1657 + rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1658 + rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1659 + rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1660 + rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1661 + rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1662 + rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1663 +
1664 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1665 + rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1666 + rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1667 + }
1668 +
1669 + if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1670 + rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1671 + }
1672 +
1673 + if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1674 + rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1675 + rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1676 + rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1677 + }
1678 +
1679 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1680 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1681 +
1682 + if (eeprom != 0xffff && eeprom != 0x0000) {
1683 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1684 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1685 + rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1686 + }
1687 + }
1688 +
1689 + return 0;
1690 +}
1691 +
1692 +static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1693 + bool bw40, u8 rfcsr24, u8 filter_target)
1694 +{
1695 + unsigned int i;
1696 + u8 bbp;
1697 + u8 rfcsr;
1698 + u8 passband;
1699 + u8 stopband;
1700 + u8 overtuned = 0;
1701 +
1702 + rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1703 +
1704 + rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1705 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1706 + rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1707 +
1708 + rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1709 + rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1710 + rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1711 +
1712 + /*
1713 + * Set power & frequency of passband test tone
1714 + */
1715 + rt2800usb_bbp_write(rt2x00dev, 24, 0);
1716 +
1717 + for (i = 0; i < 100; i++) {
1718 + rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1719 + msleep(1);
1720 +
1721 + rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1722 + if (passband)
1723 + break;
1724 + }
1725 +
1726 + /*
1727 + * Set power & frequency of stopband test tone
1728 + */
1729 + rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1730 +
1731 + for (i = 0; i < 100; i++) {
1732 + rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1733 + msleep(1);
1734 +
1735 + rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1736 +
1737 + if ((passband - stopband) <= filter_target) {
1738 + rfcsr24++;
1739 + overtuned += ((passband - stopband) == filter_target);
1740 + } else
1741 + break;
1742 +
1743 + rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1744 + }
1745 +
1746 + rfcsr24 -= !!overtuned;
1747 +
1748 + rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1749 + return rfcsr24;
1750 +}
1751 +
1752 +static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1753 +{
1754 + u8 rfcsr;
1755 + u8 bbp;
1756 +
1757 + if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1758 + return 0;
1759 +
1760 + /*
1761 + * Init RF calibration.
1762 + */
1763 + rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1764 + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1765 + rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1766 + msleep(1);
1767 + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1768 + rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1769 +
1770 + rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1771 + rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1772 + rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1773 + rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1774 + rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1775 + rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1776 + rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1777 + rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1778 + rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1779 + rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1780 + rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1781 + rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1782 + rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1783 + rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1784 + rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1785 + rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1786 + rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1787 + rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1788 + rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1789 + rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1790 +
1791 + /*
1792 + * Set RX Filter calibration for 20MHz and 40MHz
1793 + */
1794 + rt2x00dev->calibration_bw20 =
1795 + rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1796 + rt2x00dev->calibration_bw40 =
1797 + rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1798 +
1799 + /*
1800 + * Set back to initial state
1801 + */
1802 + rt2800usb_bbp_write(rt2x00dev, 24, 0);
1803 +
1804 + rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1805 + rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1806 + rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1807 +
1808 + /*
1809 + * set BBP back to BW20
1810 + */
1811 + rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1812 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1813 + rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1814 +
1815 + return 0;
1816 +}
1817 +
1818 +/*
1819 + * Device state switch handlers.
1820 + */
1821 +static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1822 + enum dev_state state)
1823 +{
1824 + u32 reg;
1825 +
1826 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1827 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1828 + (state == STATE_RADIO_RX_ON) ||
1829 + (state == STATE_RADIO_RX_ON_LINK));
1830 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1831 +}
1832 +
1833 +static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1834 +{
1835 + unsigned int i;
1836 + u32 reg;
1837 +
1838 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1839 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1840 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1841 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1842 + return 0;
1843 +
1844 + msleep(1);
1845 + }
1846 +
1847 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1848 + return -EACCES;
1849 +}
1850 +
1851 +static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1852 +{
1853 + u32 reg;
1854 + u16 word;
1855 +
1856 + /*
1857 + * Initialize all registers.
1858 + */
1859 + if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1860 + rt2800usb_init_registers(rt2x00dev) ||
1861 + rt2800usb_init_bbp(rt2x00dev) ||
1862 + rt2800usb_init_rfcsr(rt2x00dev)))
1863 + return -EIO;
1864 +
1865 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1866 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1867 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1868 +
1869 + udelay(50);
1870 +
1871 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1872 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1873 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1874 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1875 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1876 +
1877 +
1878 + rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1879 + rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1880 + /* Don't use bulk in aggregation when working with USB 1.1 */
1881 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1882 + (rt2x00dev->rx->usb_maxpacket == 512));
1883 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1884 + /* FIXME: Calculate this value based on Aggregation defines */
1885 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
1886 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1887 + rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1888 + rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1889 +
1890 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1891 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1892 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1893 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1894 +
1895 + /*
1896 + * Send signal to firmware during boot time.
1897 + */
1898 + rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1899 +
1900 + /*
1901 + * Initialize LED control
1902 + */
1903 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1904 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1905 + word & 0xff, (word >> 8) & 0xff);
1906 +
1907 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1908 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1909 + word & 0xff, (word >> 8) & 0xff);
1910 +
1911 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1912 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1913 + word & 0xff, (word >> 8) & 0xff);
1914 +
1915 + return 0;
1916 +}
1917 +
1918 +static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1919 +{
1920 + u32 reg;
1921 +
1922 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1923 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1924 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1925 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1926 +
1927 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1928 + rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1929 + rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1930 +
1931 + /* Wait for DMA, ignore error */
1932 + rt2800usb_wait_wpdma_ready(rt2x00dev);
1933 +
1934 + rt2x00usb_disable_radio(rt2x00dev);
1935 +}
1936 +
1937 +static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1938 + enum dev_state state)
1939 +{
1940 + rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1941 +
1942 + if (state == STATE_AWAKE)
1943 + rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1944 + else
1945 + rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1946 +
1947 + return 0;
1948 +}
1949 +
1950 +static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1951 + enum dev_state state)
1952 +{
1953 + int retval = 0;
1954 +
1955 + switch (state) {
1956 + case STATE_RADIO_ON:
1957 + /*
1958 + * Before the radio can be enabled, the device first has
1959 + * to be woken up. After that it needs a bit of time
1960 + * to be fully awake and the radio can be enabled.
1961 + */
1962 + rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1963 + msleep(1);
1964 + retval = rt2800usb_enable_radio(rt2x00dev);
1965 + break;
1966 + case STATE_RADIO_OFF:
1967 + /*
1968 + * After the radio has been disablee, the device should
1969 + * be put to sleep for powersaving.
1970 + */
1971 + rt2800usb_disable_radio(rt2x00dev);
1972 + rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1973 + break;
1974 + case STATE_RADIO_RX_ON:
1975 + case STATE_RADIO_RX_ON_LINK:
1976 + case STATE_RADIO_RX_OFF:
1977 + case STATE_RADIO_RX_OFF_LINK:
1978 + rt2800usb_toggle_rx(rt2x00dev, state);
1979 + break;
1980 + case STATE_RADIO_IRQ_ON:
1981 + case STATE_RADIO_IRQ_OFF:
1982 + /* No support, but no error either */
1983 + break;
1984 + case STATE_DEEP_SLEEP:
1985 + case STATE_SLEEP:
1986 + case STATE_STANDBY:
1987 + case STATE_AWAKE:
1988 + retval = rt2800usb_set_state(rt2x00dev, state);
1989 + break;
1990 + default:
1991 + retval = -ENOTSUPP;
1992 + break;
1993 + }
1994 +
1995 + if (unlikely(retval))
1996 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1997 + state, retval);
1998 +
1999 + return retval;
2000 +}
2001 +
2002 +/*
2003 + * TX descriptor initialization
2004 + */
2005 +static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2006 + struct sk_buff *skb,
2007 + struct txentry_desc *txdesc)
2008 +{
2009 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
2010 + __le32 *txi = skbdesc->desc;
2011 + __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
2012 + u32 word;
2013 +
2014 + /*
2015 + * Initialize TX Info descriptor
2016 + */
2017 + rt2x00_desc_read(txwi, 0, &word);
2018 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
2019 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2020 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2021 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2022 + rt2x00_set_field32(&word, TXWI_W0_TS,
2023 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2024 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2025 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2026 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2027 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2028 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2029 + rt2x00_set_field32(&word, TXWI_W0_BW,
2030 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2031 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2032 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2033 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2034 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2035 + rt2x00_desc_write(txwi, 0, word);
2036 +
2037 + rt2x00_desc_read(txwi, 1, &word);
2038 + rt2x00_set_field32(&word, TXWI_W1_ACK,
2039 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2040 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2041 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2042 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2043 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2044 + test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2045 + txdesc->key_idx : 0xff);
2046 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
2047 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2048 + skbdesc->entry->entry_idx);
2049 + rt2x00_desc_write(txwi, 1, word);
2050 +
2051 + /*
2052 + * Always write 0 to IV/EIV fields, hardware will insert the IV
2053 + * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2054 + * When TXINFO_W0_WIV is set to 1 it will use the IV data
2055 + * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2056 + * crypto entry in the registers should be used to encrypt the frame.
2057 + */
2058 + _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2059 + _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2060 +
2061 + /*
2062 + * Initialize TX descriptor
2063 + */
2064 + rt2x00_desc_read(txi, 0, &word);
2065 + rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2066 + skb->len + TXWI_DESC_SIZE);
2067 + rt2x00_set_field32(&word, TXINFO_W0_WIV,
2068 + !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2069 + rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2070 + rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2071 + rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2072 + rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2073 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2074 + rt2x00_desc_write(txi, 0, word);
2075 +}
2076 +
2077 +/*
2078 + * TX data initialization
2079 + */
2080 +static void rt2800usb_write_beacon(struct queue_entry *entry)
2081 +{
2082 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2083 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2084 + unsigned int beacon_base;
2085 + u32 reg;
2086 +
2087 + /*
2088 + * Add the descriptor in front of the skb.
2089 + */
2090 + skb_push(entry->skb, entry->queue->desc_size);
2091 + memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2092 + skbdesc->desc = entry->skb->data;
2093 +
2094 + /*
2095 + * Disable beaconing while we are reloading the beacon data,
2096 + * otherwise we might be sending out invalid data.
2097 + */
2098 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2099 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2100 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2101 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2102 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2103 +
2104 + /*
2105 + * Write entire beacon with descriptor to register.
2106 + */
2107 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2108 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2109 + USB_VENDOR_REQUEST_OUT, beacon_base,
2110 + entry->skb->data, entry->skb->len,
2111 + REGISTER_TIMEOUT32(entry->skb->len));
2112 +
2113 + /*
2114 + * Clean up the beacon skb.
2115 + */
2116 + dev_kfree_skb(entry->skb);
2117 + entry->skb = NULL;
2118 +}
2119 +
2120 +static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2121 +{
2122 + int length;
2123 +
2124 + /*
2125 + * The length _must_ include 4 bytes padding,
2126 + * it should always be multiple of 4,
2127 + * but it must _not_ be a multiple of the USB packet size.
2128 + */
2129 + length = roundup(entry->skb->len + 4, 4);
2130 + length += (4 * !(length % entry->queue->usb_maxpacket));
2131 +
2132 + return length;
2133 +}
2134 +
2135 +static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2136 + const enum data_queue_qid queue)
2137 +{
2138 + u32 reg;
2139 +
2140 + if (queue != QID_BEACON) {
2141 + rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2142 + return;
2143 + }
2144 +
2145 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2146 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2147 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2148 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2149 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2150 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2151 + }
2152 +}
2153 +
2154 +/*
2155 + * RX control handlers
2156 + */
2157 +static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2158 + struct rxdone_entry_desc *rxdesc)
2159 +{
2160 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2161 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2162 + __le32 *rxd = (__le32 *)entry->skb->data;
2163 + __le32 *rxwi;
2164 + u32 rxd0;
2165 + u32 rxwi0;
2166 + u32 rxwi1;
2167 + u32 rxwi2;
2168 + u32 rxwi3;
2169 +
2170 + /*
2171 + * Copy descriptor to the skbdesc->desc buffer, making it safe from
2172 + * moving of frame data in rt2x00usb.
2173 + */
2174 + memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2175 + rxd = (__le32 *)skbdesc->desc;
2176 + rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2177 +
2178 + /*
2179 + * It is now safe to read the descriptor on all architectures.
2180 + */
2181 + rt2x00_desc_read(rxd, 0, &rxd0);
2182 + rt2x00_desc_read(rxwi, 0, &rxwi0);
2183 + rt2x00_desc_read(rxwi, 1, &rxwi1);
2184 + rt2x00_desc_read(rxwi, 2, &rxwi2);
2185 + rt2x00_desc_read(rxwi, 3, &rxwi3);
2186 +
2187 + if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2188 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2189 +
2190 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2191 + rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2192 + rxdesc->cipher_status =
2193 + rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2194 + }
2195 +
2196 + if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2197 + /*
2198 + * Hardware has stripped IV/EIV data from 802.11 frame during
2199 + * decryption. Unfortunately the descriptor doesn't contain
2200 + * any fields with the EIV/IV data either, so they can't
2201 + * be restored by rt2x00lib.
2202 + */
2203 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2204 +
2205 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2206 + rxdesc->flags |= RX_FLAG_DECRYPTED;
2207 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2208 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2209 + }
2210 +
2211 + if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2212 + rxdesc->dev_flags |= RXDONE_MY_BSS;
2213 +
2214 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2215 + rxdesc->flags |= RX_FLAG_SHORT_GI;
2216 +
2217 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2218 + rxdesc->flags |= RX_FLAG_40MHZ;
2219 +
2220 + /*
2221 + * Detect RX rate, always use MCS as signal type.
2222 + */
2223 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2224 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2225 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2226 +
2227 + /*
2228 + * Mask of 0x8 bit to remove the short preamble flag.
2229 + */
2230 + if (rxdesc->rate_mode == RATE_MODE_CCK)
2231 + rxdesc->signal &= ~0x8;
2232 +
2233 + rxdesc->rssi =
2234 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2235 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2236 +
2237 + rxdesc->noise =
2238 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2239 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2240 +
2241 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2242 +
2243 + /*
2244 + * Remove RXWI descriptor from start of buffer.
2245 + */
2246 + skb_pull(entry->skb, skbdesc->desc_len);
2247 + skb_trim(entry->skb, rxdesc->size);
2248 +}
2249 +
2250 +/*
2251 + * Device probe functions.
2252 + */
2253 +static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2254 +{
2255 + u16 word;
2256 + u8 *mac;
2257 + u8 default_lna_gain;
2258 +
2259 + rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2260 +
2261 + /*
2262 + * Start validation of the data that has been read.
2263 + */
2264 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2265 + if (!is_valid_ether_addr(mac)) {
2266 + DECLARE_MAC_BUF(macbuf);
2267 +
2268 + random_ether_addr(mac);
2269 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2270 + }
2271 +
2272 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2273 + if (word == 0xffff) {
2274 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2275 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2276 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2277 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2278 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2279 + } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2280 + /*
2281 + * There is a max of 2 RX streams for RT2860 series
2282 + */
2283 + if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2284 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2285 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2286 + }
2287 +
2288 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2289 + if (word == 0xffff) {
2290 + rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2291 + rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2292 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2293 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2294 + rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2295 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2296 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2297 + rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2298 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2299 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2300 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2301 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2302 + }
2303 +
2304 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2305 + if ((word & 0x00ff) == 0x00ff) {
2306 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2307 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2308 + LED_MODE_TXRX_ACTIVITY);
2309 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2310 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2311 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2312 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2313 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2314 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2315 + }
2316 +
2317 + /*
2318 + * During the LNA validation we are going to use
2319 + * lna0 as correct value. Note that EEPROM_LNA
2320 + * is never validated.
2321 + */
2322 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2323 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2324 +
2325 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2326 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2327 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2328 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2329 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2330 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2331 +
2332 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2333 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2334 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2335 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2336 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2337 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2338 + default_lna_gain);
2339 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2340 +
2341 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2342 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2343 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2344 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2345 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2346 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2347 +
2348 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2349 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2350 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2351 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2352 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2353 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2354 + default_lna_gain);
2355 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2356 +
2357 + return 0;
2358 +}
2359 +
2360 +static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2361 +{
2362 + u32 reg;
2363 + u16 value;
2364 + u16 eeprom;
2365 +
2366 + /*
2367 + * Read EEPROM word for configuration.
2368 + */
2369 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2370 +
2371 + /*
2372 + * Identify RF chipset.
2373 + */
2374 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2375 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2376 + rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2377 +
2378 + /*
2379 + * The check for rt2860 is not a typo, some rt2870 hardware
2380 + * identifies itself as rt2860 in the CSR register.
2381 + */
2382 + if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
2383 + (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870) &&
2384 + (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x3070)) {
2385 + ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2386 + return -ENODEV;
2387 + }
2388 +
2389 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2390 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2391 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2392 + !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2393 + !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2394 + !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2395 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2396 + return -ENODEV;
2397 + }
2398 +
2399 + /*
2400 + * Read frequency offset and RF programming sequence.
2401 + */
2402 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2403 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2404 +
2405 + /*
2406 + * Read external LNA informations.
2407 + */
2408 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2409 +
2410 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2411 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2412 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2413 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2414 +
2415 + /*
2416 + * Detect if this device has an hardware controlled radio.
2417 + */
2418 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2419 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2420 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2421 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2422 +
2423 + /*
2424 + * Store led settings, for correct led behaviour.
2425 + */
2426 +#ifdef CONFIG_RT2X00_LIB_LEDS
2427 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2428 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2429 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2430 +
2431 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2432 + &rt2x00dev->led_mcu_reg);
2433 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2434 +
2435 + return 0;
2436 +}
2437 +
2438 +/*
2439 + * RF value list for rt2870
2440 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2441 + */
2442 +static const struct rf_channel rf_vals[] = {
2443 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2444 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2445 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2446 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2447 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2448 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2449 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2450 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2451 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2452 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2453 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2454 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2455 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2456 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2457 +
2458 + /* 802.11 UNI / HyperLan 2 */
2459 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2460 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2461 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2462 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2463 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2464 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2465 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2466 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2467 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2468 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2469 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2470 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2471 +
2472 + /* 802.11 HyperLan 2 */
2473 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2474 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2475 + { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2476 + { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2477 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2478 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2479 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2480 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2481 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2482 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2483 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2484 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2485 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2486 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2487 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2488 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2489 +
2490 + /* 802.11 UNII */
2491 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2492 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2493 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2494 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2495 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2496 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2497 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2498 +
2499 + /* 802.11 Japan */
2500 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2501 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2502 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2503 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2504 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2505 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2506 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2507 +};
2508 +
2509 +/*
2510 + * RF value list for rt3070
2511 + * Supports: 2.4 GHz
2512 + */
2513 +static const struct rf_channel rf_vals_3070[] = {
2514 + {1, 241, 2, 2 },
2515 + {2, 241, 2, 7 },
2516 + {3, 242, 2, 2 },
2517 + {4, 242, 2, 7 },
2518 + {5, 243, 2, 2 },
2519 + {6, 243, 2, 7 },
2520 + {7, 244, 2, 2 },
2521 + {8, 244, 2, 7 },
2522 + {9, 245, 2, 2 },
2523 + {10, 245, 2, 7 },
2524 + {11, 246, 2, 2 },
2525 + {12, 246, 2, 7 },
2526 + {13, 247, 2, 2 },
2527 + {14, 248, 2, 4 },
2528 +};
2529 +
2530 +static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2531 +{
2532 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2533 + struct channel_info *info;
2534 + char *tx_power1;
2535 + char *tx_power2;
2536 + unsigned int i;
2537 + u16 eeprom;
2538 +
2539 + /*
2540 + * Initialize all hw fields.
2541 + */
2542 + rt2x00dev->hw->flags =
2543 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2544 + IEEE80211_HW_SIGNAL_DBM |
2545 + IEEE80211_HW_SUPPORTS_PS |
2546 + IEEE80211_HW_PS_NULLFUNC_STACK;
2547 + rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2548 +
2549 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2550 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2551 + rt2x00_eeprom_addr(rt2x00dev,
2552 + EEPROM_MAC_ADDR_0));
2553 +
2554 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2555 +
2556 + /*
2557 + * Initialize HT information.
2558 + */
2559 + spec->ht.ht_supported = true;
2560 + spec->ht.cap =
2561 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2562 + IEEE80211_HT_CAP_GRN_FLD |
2563 + IEEE80211_HT_CAP_SGI_20 |
2564 + IEEE80211_HT_CAP_SGI_40 |
2565 + IEEE80211_HT_CAP_TX_STBC |
2566 + IEEE80211_HT_CAP_RX_STBC |
2567 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2568 + spec->ht.ampdu_factor = 3;
2569 + spec->ht.ampdu_density = 4;
2570 + spec->ht.mcs.tx_params =
2571 + IEEE80211_HT_MCS_TX_DEFINED |
2572 + IEEE80211_HT_MCS_TX_RX_DIFF |
2573 + ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2574 + IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2575 +
2576 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2577 + case 3:
2578 + spec->ht.mcs.rx_mask[2] = 0xff;
2579 + case 2:
2580 + spec->ht.mcs.rx_mask[1] = 0xff;
2581 + case 1:
2582 + spec->ht.mcs.rx_mask[0] = 0xff;
2583 + spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2584 + break;
2585 + }
2586 +
2587 + /*
2588 + * Initialize hw_mode information.
2589 + */
2590 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2591 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2592 +
2593 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2594 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2595 + spec->num_channels = 14;
2596 + spec->channels = rf_vals;
2597 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2598 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2599 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2600 + spec->num_channels = ARRAY_SIZE(rf_vals);
2601 + spec->channels = rf_vals;
2602 + } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2603 + rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2604 + spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2605 + spec->channels = rf_vals_3070;
2606 + }
2607 +
2608 + /*
2609 + * Create channel information array
2610 + */
2611 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2612 + if (!info)
2613 + return -ENOMEM;
2614 +
2615 + spec->channels_info = info;
2616 +
2617 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2618 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2619 +
2620 + for (i = 0; i < 14; i++) {
2621 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2622 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2623 + }
2624 +
2625 + if (spec->num_channels > 14) {
2626 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2627 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2628 +
2629 + for (i = 14; i < spec->num_channels; i++) {
2630 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2631 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2632 + }
2633 + }
2634 +
2635 + return 0;
2636 +}
2637 +
2638 +static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2639 +{
2640 + int retval;
2641 +
2642 + /*
2643 + * Allocate eeprom data.
2644 + */
2645 + retval = rt2800usb_validate_eeprom(rt2x00dev);
2646 + if (retval)
2647 + return retval;
2648 +
2649 + retval = rt2800usb_init_eeprom(rt2x00dev);
2650 + if (retval)
2651 + return retval;
2652 +
2653 + /*
2654 + * Initialize hw specifications.
2655 + */
2656 + retval = rt2800usb_probe_hw_mode(rt2x00dev);
2657 + if (retval)
2658 + return retval;
2659 +
2660 + /*
2661 + * This device requires firmware.
2662 + */
2663 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2664 + __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2665 + if (!modparam_nohwcrypt)
2666 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2667 +
2668 + /*
2669 + * Set the rssi offset.
2670 + */
2671 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2672 +
2673 + return 0;
2674 +}
2675 +
2676 +/*
2677 + * IEEE80211 stack callback functions.
2678 + */
2679 +static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2680 + u32 *iv32, u16 *iv16)
2681 +{
2682 + struct rt2x00_dev *rt2x00dev = hw->priv;
2683 + struct mac_iveiv_entry iveiv_entry;
2684 + u32 offset;
2685 +
2686 + offset = MAC_IVEIV_ENTRY(hw_key_idx);
2687 + rt2x00usb_register_multiread(rt2x00dev, offset,
2688 + &iveiv_entry, sizeof(iveiv_entry));
2689 +
2690 + memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2691 + memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2692 +}
2693 +
2694 +static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2695 +{
2696 + struct rt2x00_dev *rt2x00dev = hw->priv;
2697 + u32 reg;
2698 + bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2699 +
2700 + rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2701 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2702 + rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2703 +
2704 + rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2705 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2706 + rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2707 +
2708 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2709 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2710 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2711 +
2712 + rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2713 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2714 + rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2715 +
2716 + rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2717 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2718 + rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2719 +
2720 + rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2721 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2722 + rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2723 +
2724 + rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2725 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2726 + rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2727 +
2728 + return 0;
2729 +}
2730 +
2731 +static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2732 + const struct ieee80211_tx_queue_params *params)
2733 +{
2734 + struct rt2x00_dev *rt2x00dev = hw->priv;
2735 + struct data_queue *queue;
2736 + struct rt2x00_field32 field;
2737 + int retval;
2738 + u32 reg;
2739 + u32 offset;
2740 +
2741 + /*
2742 + * First pass the configuration through rt2x00lib, that will
2743 + * update the queue settings and validate the input. After that
2744 + * we are free to update the registers based on the value
2745 + * in the queue parameter.
2746 + */
2747 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2748 + if (retval)
2749 + return retval;
2750 +
2751 + /*
2752 + * We only need to perform additional register initialization
2753 + * for WMM queues/
2754 + */
2755 + if (queue_idx >= 4)
2756 + return 0;
2757 +
2758 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2759 +
2760 + /* Update WMM TXOP register */
2761 + offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2762 + field.bit_offset = (queue_idx & 1) * 16;
2763 + field.bit_mask = 0xffff << field.bit_offset;
2764 +
2765 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
2766 + rt2x00_set_field32(&reg, field, queue->txop);
2767 + rt2x00usb_register_write(rt2x00dev, offset, reg);
2768 +
2769 + /* Update WMM registers */
2770 + field.bit_offset = queue_idx * 4;
2771 + field.bit_mask = 0xf << field.bit_offset;
2772 +
2773 + rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2774 + rt2x00_set_field32(&reg, field, queue->aifs);
2775 + rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2776 +
2777 + rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2778 + rt2x00_set_field32(&reg, field, queue->cw_min);
2779 + rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2780 +
2781 + rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2782 + rt2x00_set_field32(&reg, field, queue->cw_max);
2783 + rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2784 +
2785 + /* Update EDCA registers */
2786 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2787 +
2788 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
2789 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2790 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2791 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2792 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2793 + rt2x00usb_register_write(rt2x00dev, offset, reg);
2794 +
2795 + return 0;
2796 +}
2797 +
2798 +static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2799 +{
2800 + struct rt2x00_dev *rt2x00dev = hw->priv;
2801 + u64 tsf;
2802 + u32 reg;
2803 +
2804 + rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2805 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2806 + rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2807 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2808 +
2809 + return tsf;
2810 +}
2811 +
2812 +static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2813 + .tx = rt2x00mac_tx,
2814 + .start = rt2x00mac_start,
2815 + .stop = rt2x00mac_stop,
2816 + .add_interface = rt2x00mac_add_interface,
2817 + .remove_interface = rt2x00mac_remove_interface,
2818 + .config = rt2x00mac_config,
2819 + .config_interface = rt2x00mac_config_interface,
2820 + .configure_filter = rt2x00mac_configure_filter,
2821 + .set_key = rt2x00mac_set_key,
2822 + .get_stats = rt2x00mac_get_stats,
2823 + .get_tkip_seq = rt2800usb_get_tkip_seq,
2824 + .set_rts_threshold = rt2800usb_set_rts_threshold,
2825 + .bss_info_changed = rt2x00mac_bss_info_changed,
2826 + .conf_tx = rt2800usb_conf_tx,
2827 + .get_tx_stats = rt2x00mac_get_tx_stats,
2828 + .get_tsf = rt2800usb_get_tsf,
2829 +};
2830 +
2831 +static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2832 + .probe_hw = rt2800usb_probe_hw,
2833 + .get_firmware_name = rt2800usb_get_firmware_name,
2834 + .check_firmware = rt2800usb_check_firmware,
2835 + .load_firmware = rt2800usb_load_firmware,
2836 + .initialize = rt2x00usb_initialize,
2837 + .uninitialize = rt2x00usb_uninitialize,
2838 + .clear_entry = rt2x00usb_clear_entry,
2839 + .set_device_state = rt2800usb_set_device_state,
2840 + .rfkill_poll = rt2800usb_rfkill_poll,
2841 + .link_stats = rt2800usb_link_stats,
2842 + .reset_tuner = rt2800usb_reset_tuner,
2843 + .link_tuner = rt2800usb_link_tuner,
2844 + .write_tx_desc = rt2800usb_write_tx_desc,
2845 + .write_tx_data = rt2x00usb_write_tx_data,
2846 + .write_beacon = rt2800usb_write_beacon,
2847 + .get_tx_data_len = rt2800usb_get_tx_data_len,
2848 + .kick_tx_queue = rt2800usb_kick_tx_queue,
2849 + .kill_tx_queue = rt2x00usb_kill_tx_queue,
2850 + .fill_rxdone = rt2800usb_fill_rxdone,
2851 + .config_shared_key = rt2800usb_config_shared_key,
2852 + .config_pairwise_key = rt2800usb_config_pairwise_key,
2853 + .config_filter = rt2800usb_config_filter,
2854 + .config_intf = rt2800usb_config_intf,
2855 + .config_erp = rt2800usb_config_erp,
2856 + .config_ant = rt2800usb_config_ant,
2857 + .config = rt2800usb_config,
2858 +};
2859 +
2860 +static const struct data_queue_desc rt2800usb_queue_rx = {
2861 + .entry_num = RX_ENTRIES,
2862 + .data_size = AGGREGATION_SIZE,
2863 + .desc_size = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2864 + .priv_size = sizeof(struct queue_entry_priv_usb),
2865 +};
2866 +
2867 +static const struct data_queue_desc rt2800usb_queue_tx = {
2868 + .entry_num = TX_ENTRIES,
2869 + .data_size = AGGREGATION_SIZE,
2870 + .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2871 + .priv_size = sizeof(struct queue_entry_priv_usb),
2872 +};
2873 +
2874 +static const struct data_queue_desc rt2800usb_queue_bcn = {
2875 + .entry_num = 8 * BEACON_ENTRIES,
2876 + .data_size = MGMT_FRAME_SIZE,
2877 + .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2878 + .priv_size = sizeof(struct queue_entry_priv_usb),
2879 +};
2880 +
2881 +static const struct rt2x00_ops rt2800usb_ops = {
2882 + .name = KBUILD_MODNAME,
2883 + .max_sta_intf = 1,
2884 + .max_ap_intf = 8,
2885 + .eeprom_size = EEPROM_SIZE,
2886 + .rf_size = RF_SIZE,
2887 + .tx_queues = NUM_TX_QUEUES,
2888 + .rx = &rt2800usb_queue_rx,
2889 + .tx = &rt2800usb_queue_tx,
2890 + .bcn = &rt2800usb_queue_bcn,
2891 + .lib = &rt2800usb_rt2x00_ops,
2892 + .hw = &rt2800usb_mac80211_ops,
2893 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2894 + .debugfs = &rt2800usb_rt2x00debug,
2895 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2896 +};
2897 +
2898 +/*
2899 + * rt2800usb module information.
2900 + */
2901 +static struct usb_device_id rt2800usb_device_table[] = {
2902 + /* Abocom */
2903 + { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2904 + { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2905 + { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2906 + { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2907 + { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2908 + { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2909 + /* AirTies */
2910 + { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2911 + /* Amigo */
2912 + { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2913 + { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2914 + /* Amit */
2915 + { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2916 + /* ASUS */
2917 + { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2918 + { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2919 + { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2920 + { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2921 + { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2922 + /* AzureWave */
2923 + { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2924 + { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2925 + { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2926 + /* Belkin */
2927 + { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2928 + { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2929 + { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2930 + /* Buffalo */
2931 + { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2932 + /* Conceptronic */
2933 + { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2934 + { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2935 + { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2936 + { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2937 + { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2938 + { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2939 + { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2940 + { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2941 + /* Corega */
2942 + { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2943 + { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2944 + { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2945 + { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2946 + { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2947 + /* D-Link */
2948 + { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2949 + { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2950 + { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2951 + { USB_DEVICE(0x2001, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2952 + { USB_DEVICE(0x2001, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2953 + /* Edimax */
2954 + { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2955 + { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2956 + { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2957 + /* EnGenius */
2958 + { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2959 + { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2960 + { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2961 + /* Gemtek */
2962 + { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2963 + /* Gigabyte */
2964 + { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2965 + { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2966 + { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2967 + /* Hawking */
2968 + { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2969 + { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2970 + { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2971 + { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2972 + /* LevelOne */
2973 + { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2974 + { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2975 + /* Linksys */
2976 + { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2977 + /* Logitec */
2978 + { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2979 + { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2980 + { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2981 + /* Pegatron */
2982 + { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2983 + /* Philips */
2984 + { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2985 + /* Planex */
2986 + { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2987 + { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2988 + { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2989 + /* Qcom */
2990 + { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2991 + /* Quanta */
2992 + { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2993 + /* Ralink */
2994 + { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2995 + { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2996 + { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2997 + { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2998 + { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2999 + { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3000 + /* Samsung */
3001 + { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3002 + /* Siemens */
3003 + { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
3004 + /* Sitecom */
3005 + { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
3006 + { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
3007 + { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3008 + { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3009 + { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3010 + { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3011 + { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3012 + { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3013 + { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3014 + { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3015 + /* SMC */
3016 + { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3017 + { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3018 + { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3019 + { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3020 + { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3021 + { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3022 + { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3023 + /* Sparklan */
3024 + { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3025 + /* U-Media*/
3026 + { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3027 + /* ZCOM */
3028 + { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3029 + { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3030 + /* Zinwell */
3031 + { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3032 + { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3033 + /* Zyxel */
3034 + { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3035 + { 0, }
3036 +};
3037 +
3038 +MODULE_AUTHOR(DRV_PROJECT);
3039 +MODULE_VERSION(DRV_VERSION);
3040 +MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3041 +MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3042 +MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3043 +MODULE_FIRMWARE(FIRMWARE_RT2870);
3044 +MODULE_LICENSE("GPL");
3045 +
3046 +static struct usb_driver rt2800usb_driver = {
3047 + .name = KBUILD_MODNAME,
3048 + .id_table = rt2800usb_device_table,
3049 + .probe = rt2x00usb_probe,
3050 + .disconnect = rt2x00usb_disconnect,
3051 + .suspend = rt2x00usb_suspend,
3052 + .resume = rt2x00usb_resume,
3053 +};
3054 +
3055 +static int __init rt2800usb_init(void)
3056 +{
3057 + return usb_register(&rt2800usb_driver);
3058 +}
3059 +
3060 +static void __exit rt2800usb_exit(void)
3061 +{
3062 + usb_deregister(&rt2800usb_driver);
3063 +}
3064 +
3065 +module_init(rt2800usb_init);
3066 +module_exit(rt2800usb_exit);
3067 --- /dev/null
3068 +++ b/drivers/net/wireless/rt2x00/rt2800usb.h
3069 @@ -0,0 +1,1934 @@
3070 +/*
3071 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3072 + <http://rt2x00.serialmonkey.com>
3073 +
3074 + This program is free software; you can redistribute it and/or modify
3075 + it under the terms of the GNU General Public License as published by
3076 + the Free Software Foundation; either version 2 of the License, or
3077 + (at your option) any later version.
3078 +
3079 + This program is distributed in the hope that it will be useful,
3080 + but WITHOUT ANY WARRANTY; without even the implied warranty of
3081 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3082 + GNU General Public License for more details.
3083 +
3084 + You should have received a copy of the GNU General Public License
3085 + along with this program; if not, write to the
3086 + Free Software Foundation, Inc.,
3087 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3088 + */
3089 +
3090 +/*
3091 + Module: rt2800usb
3092 + Abstract: Data structures and registers for the rt2800usb module.
3093 + Supported chipsets: RT2800U.
3094 + */
3095 +
3096 +#ifndef RT2800USB_H
3097 +#define RT2800USB_H
3098 +
3099 +/*
3100 + * RF chip defines.
3101 + *
3102 + * RF2820 2.4G 2T3R
3103 + * RF2850 2.4G/5G 2T3R
3104 + * RF2720 2.4G 1T2R
3105 + * RF2750 2.4G/5G 1T2R
3106 + * RF3020 2.4G 1T1R
3107 + * RF2020 2.4G B/G
3108 + */
3109 +#define RF2820 0x0001
3110 +#define RF2850 0x0002
3111 +#define RF2720 0x0003
3112 +#define RF2750 0x0004
3113 +#define RF3020 0x0005
3114 +#define RF2020 0x0006
3115 +
3116 +/*
3117 + * RT2870 version
3118 + */
3119 +#define RT2860C_VERSION 0x28600100
3120 +#define RT2860D_VERSION 0x28600101
3121 +#define RT2880E_VERSION 0x28720200
3122 +#define RT2883_VERSION 0x28830300
3123 +#define RT3070_VERSION 0x30700200
3124 +
3125 +/*
3126 + * Signal information.
3127 + * Defaul offset is required for RSSI <-> dBm conversion.
3128 + */
3129 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
3130 +
3131 +/*
3132 + * Register layout information.
3133 + */
3134 +#define CSR_REG_BASE 0x1000
3135 +#define CSR_REG_SIZE 0x0800
3136 +#define EEPROM_BASE 0x0000
3137 +#define EEPROM_SIZE 0x0110
3138 +#define BBP_BASE 0x0000
3139 +#define BBP_SIZE 0x0080
3140 +#define RF_BASE 0x0004
3141 +#define RF_SIZE 0x0010
3142 +
3143 +/*
3144 + * Number of TX queues.
3145 + */
3146 +#define NUM_TX_QUEUES 4
3147 +
3148 +/*
3149 + * USB registers.
3150 + */
3151 +
3152 +/*
3153 + * HOST-MCU shared memory
3154 + */
3155 +#define HOST_CMD_CSR 0x0404
3156 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
3157 +
3158 +/*
3159 + * INT_SOURCE_CSR: Interrupt source register.
3160 + * Write one to clear corresponding bit.
3161 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3162 + */
3163 +#define INT_SOURCE_CSR 0x0200
3164 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
3165 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
3166 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
3167 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3168 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3169 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3170 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3171 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3172 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3173 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
3174 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
3175 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
3176 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
3177 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3178 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3179 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
3180 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
3181 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
3182 +
3183 +/*
3184 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3185 + */
3186 +#define INT_MASK_CSR 0x0204
3187 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
3188 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
3189 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
3190 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3191 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3192 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3193 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3194 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3195 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3196 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
3197 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
3198 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
3199 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
3200 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3201 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3202 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
3203 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
3204 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
3205 +
3206 +/*
3207 + * WPDMA_GLO_CFG
3208 + */
3209 +#define WPDMA_GLO_CFG 0x0208
3210 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
3211 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
3212 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
3213 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
3214 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
3215 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
3216 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
3217 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
3218 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
3219 +
3220 +/*
3221 + * WPDMA_RST_IDX
3222 + */
3223 +#define WPDMA_RST_IDX 0x020c
3224 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
3225 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
3226 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
3227 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
3228 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
3229 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
3230 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
3231 +
3232 +/*
3233 + * DELAY_INT_CFG
3234 + */
3235 +#define DELAY_INT_CFG 0x0210
3236 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
3237 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
3238 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
3239 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
3240 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
3241 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
3242 +
3243 +/*
3244 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3245 + * AIFSN0: AC_BE
3246 + * AIFSN1: AC_BK
3247 + * AIFSN1: AC_VI
3248 + * AIFSN1: AC_VO
3249 + */
3250 +#define WMM_AIFSN_CFG 0x0214
3251 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
3252 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
3253 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
3254 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
3255 +
3256 +/*
3257 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3258 + * CWMIN0: AC_BE
3259 + * CWMIN1: AC_BK
3260 + * CWMIN1: AC_VI
3261 + * CWMIN1: AC_VO
3262 + */
3263 +#define WMM_CWMIN_CFG 0x0218
3264 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
3265 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
3266 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
3267 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
3268 +
3269 +/*
3270 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3271 + * CWMAX0: AC_BE
3272 + * CWMAX1: AC_BK
3273 + * CWMAX1: AC_VI
3274 + * CWMAX1: AC_VO
3275 + */
3276 +#define WMM_CWMAX_CFG 0x021c
3277 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
3278 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
3279 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
3280 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
3281 +
3282 +/*
3283 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3284 + * AC0TXOP: AC_BK in unit of 32us
3285 + * AC1TXOP: AC_BE in unit of 32us
3286 + */
3287 +#define WMM_TXOP0_CFG 0x0220
3288 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
3289 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
3290 +
3291 +/*
3292 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3293 + * AC2TXOP: AC_VI in unit of 32us
3294 + * AC3TXOP: AC_VO in unit of 32us
3295 + */
3296 +#define WMM_TXOP1_CFG 0x0224
3297 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
3298 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
3299 +
3300 +/*
3301 + * GPIO_CTRL_CFG:
3302 + */
3303 +#define GPIO_CTRL_CFG 0x0228
3304 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3305 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3306 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3307 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3308 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3309 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3310 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3311 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3312 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3313 +
3314 +/*
3315 + * MCU_CMD_CFG
3316 + */
3317 +#define MCU_CMD_CFG 0x022c
3318 +
3319 +/*
3320 + * AC_BK register offsets
3321 + */
3322 +#define TX_BASE_PTR0 0x0230
3323 +#define TX_MAX_CNT0 0x0234
3324 +#define TX_CTX_IDX0 0x0238
3325 +#define TX_DTX_IDX0 0x023c
3326 +
3327 +/*
3328 + * AC_BE register offsets
3329 + */
3330 +#define TX_BASE_PTR1 0x0240
3331 +#define TX_MAX_CNT1 0x0244
3332 +#define TX_CTX_IDX1 0x0248
3333 +#define TX_DTX_IDX1 0x024c
3334 +
3335 +/*
3336 + * AC_VI register offsets
3337 + */
3338 +#define TX_BASE_PTR2 0x0250
3339 +#define TX_MAX_CNT2 0x0254
3340 +#define TX_CTX_IDX2 0x0258
3341 +#define TX_DTX_IDX2 0x025c
3342 +
3343 +/*
3344 + * AC_VO register offsets
3345 + */
3346 +#define TX_BASE_PTR3 0x0260
3347 +#define TX_MAX_CNT3 0x0264
3348 +#define TX_CTX_IDX3 0x0268
3349 +#define TX_DTX_IDX3 0x026c
3350 +
3351 +/*
3352 + * HCCA register offsets
3353 + */
3354 +#define TX_BASE_PTR4 0x0270
3355 +#define TX_MAX_CNT4 0x0274
3356 +#define TX_CTX_IDX4 0x0278
3357 +#define TX_DTX_IDX4 0x027c
3358 +
3359 +/*
3360 + * MGMT register offsets
3361 + */
3362 +#define TX_BASE_PTR5 0x0280
3363 +#define TX_MAX_CNT5 0x0284
3364 +#define TX_CTX_IDX5 0x0288
3365 +#define TX_DTX_IDX5 0x028c
3366 +
3367 +/*
3368 + * RX register offsets
3369 + */
3370 +#define RX_BASE_PTR 0x0290
3371 +#define RX_MAX_CNT 0x0294
3372 +#define RX_CRX_IDX 0x0298
3373 +#define RX_DRX_IDX 0x029c
3374 +
3375 +/*
3376 + * USB_DMA_CFG
3377 + * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
3378 + * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
3379 + * PHY_CLEAR: phy watch dog enable.
3380 + * TX_CLEAR: Clear USB DMA TX path.
3381 + * TXOP_HALT: Halt TXOP count down when TX buffer is full.
3382 + * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
3383 + * RX_BULK_EN: Enable USB DMA Rx.
3384 + * TX_BULK_EN: Enable USB DMA Tx.
3385 + * EP_OUT_VALID: OUT endpoint data valid.
3386 + * RX_BUSY: USB DMA RX FSM busy.
3387 + * TX_BUSY: USB DMA TX FSM busy.
3388 + */
3389 +#define USB_DMA_CFG 0x02a0
3390 +#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
3391 +#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
3392 +#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
3393 +#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
3394 +#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
3395 +#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
3396 +#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
3397 +#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
3398 +#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
3399 +#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
3400 +#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
3401 +
3402 +/*
3403 + * USB_CYC_CFG
3404 + */
3405 +#define USB_CYC_CFG 0x02a4
3406 +#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
3407 +
3408 +/*
3409 + * PBF_SYS_CTRL
3410 + * HOST_RAM_WRITE: enable Host program ram write selection
3411 + */
3412 +#define PBF_SYS_CTRL 0x0400
3413 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3414 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3415 +
3416 +/*
3417 + * PBF registers
3418 + * Most are for debug. Driver doesn't touch PBF register.
3419 + */
3420 +#define PBF_CFG 0x0408
3421 +#define PBF_MAX_PCNT 0x040c
3422 +#define PBF_CTRL 0x0410
3423 +#define PBF_INT_STA 0x0414
3424 +#define PBF_INT_ENA 0x0418
3425 +
3426 +/*
3427 + * BCN_OFFSET0:
3428 + */
3429 +#define BCN_OFFSET0 0x042c
3430 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3431 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3432 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3433 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3434 +
3435 +/*
3436 + * BCN_OFFSET1:
3437 + */
3438 +#define BCN_OFFSET1 0x0430
3439 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3440 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3441 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3442 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3443 +
3444 +/*
3445 + * PBF registers
3446 + * Most are for debug. Driver doesn't touch PBF register.
3447 + */
3448 +#define TXRXQ_PCNT 0x0438
3449 +#define PBF_DBG 0x043c
3450 +
3451 +/*
3452 + * RF registers
3453 + */
3454 +#define RF_CSR_CFG 0x0500
3455 +#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
3456 +#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
3457 +#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
3458 +#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
3459 +
3460 +/*
3461 + * MAC Control/Status Registers(CSR).
3462 + * Some values are set in TU, whereas 1 TU == 1024 us.
3463 + */
3464 +
3465 +/*
3466 + * MAC_CSR0: ASIC revision number.
3467 + * ASIC_REV: 0
3468 + * ASIC_VER: 2870
3469 + */
3470 +#define MAC_CSR0 0x1000
3471 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3472 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3473 +
3474 +/*
3475 + * MAC_SYS_CTRL:
3476 + */
3477 +#define MAC_SYS_CTRL 0x1004
3478 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3479 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3480 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3481 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3482 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3483 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3484 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3485 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3486 +
3487 +/*
3488 + * MAC_ADDR_DW0: STA MAC register 0
3489 + */
3490 +#define MAC_ADDR_DW0 0x1008
3491 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3492 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3493 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3494 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3495 +
3496 +/*
3497 + * MAC_ADDR_DW1: STA MAC register 1
3498 + * UNICAST_TO_ME_MASK:
3499 + * Used to mask off bits from byte 5 of the MAC address
3500 + * to determine the UNICAST_TO_ME bit for RX frames.
3501 + * The full mask is complemented by BSS_ID_MASK:
3502 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3503 + */
3504 +#define MAC_ADDR_DW1 0x100c
3505 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3506 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3507 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3508 +
3509 +/*
3510 + * MAC_BSSID_DW0: BSSID register 0
3511 + */
3512 +#define MAC_BSSID_DW0 0x1010
3513 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3514 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3515 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3516 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3517 +
3518 +/*
3519 + * MAC_BSSID_DW1: BSSID register 1
3520 + * BSS_ID_MASK:
3521 + * 0: 1-BSSID mode (BSS index = 0)
3522 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3523 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3524 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3525 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3526 + * BSSID. This will make sure that those bits will be ignored
3527 + * when determining the MY_BSS of RX frames.
3528 + */
3529 +#define MAC_BSSID_DW1 0x1014
3530 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3531 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3532 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3533 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3534 +
3535 +/*
3536 + * MAX_LEN_CFG: Maximum frame length register.
3537 + * MAX_MPDU: rt2860b max 16k bytes
3538 + * MAX_PSDU: Maximum PSDU length
3539 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3540 + */
3541 +#define MAX_LEN_CFG 0x1018
3542 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3543 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3544 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3545 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3546 +
3547 +/*
3548 + * BBP_CSR_CFG: BBP serial control register
3549 + * VALUE: Register value to program into BBP
3550 + * REG_NUM: Selected BBP register
3551 + * READ_CONTROL: 0 write BBP, 1 read BBP
3552 + * BUSY: ASIC is busy executing BBP commands
3553 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3554 + * BBP_RW_MODE: 0 serial, 1 paralell
3555 + */
3556 +#define BBP_CSR_CFG 0x101c
3557 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3558 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3559 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3560 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3561 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3562 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3563 +
3564 +/*
3565 + * RF_CSR_CFG0: RF control register
3566 + * REGID_AND_VALUE: Register value to program into RF
3567 + * BITWIDTH: Selected RF register
3568 + * STANDBYMODE: 0 high when standby, 1 low when standby
3569 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3570 + * BUSY: ASIC is busy executing RF commands
3571 + */
3572 +#define RF_CSR_CFG0 0x1020
3573 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3574 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3575 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3576 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3577 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3578 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3579 +
3580 +/*
3581 + * RF_CSR_CFG1: RF control register
3582 + * REGID_AND_VALUE: Register value to program into RF
3583 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3584 + * 0: 3 system clock cycle (37.5usec)
3585 + * 1: 5 system clock cycle (62.5usec)
3586 + */
3587 +#define RF_CSR_CFG1 0x1024
3588 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3589 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3590 +
3591 +/*
3592 + * RF_CSR_CFG2: RF control register
3593 + * VALUE: Register value to program into RF
3594 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3595 + * 0: 3 system clock cycle (37.5usec)
3596 + * 1: 5 system clock cycle (62.5usec)
3597 + */
3598 +#define RF_CSR_CFG2 0x1028
3599 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3600 +
3601 +/*
3602 + * LED_CFG: LED control
3603 + * color LED's:
3604 + * 0: off
3605 + * 1: blinking upon TX2
3606 + * 2: periodic slow blinking
3607 + * 3: always on
3608 + * LED polarity:
3609 + * 0: active low
3610 + * 1: active high
3611 + */
3612 +#define LED_CFG 0x102c
3613 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3614 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3615 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3616 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3617 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3618 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3619 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3620 +
3621 +/*
3622 + * XIFS_TIME_CFG: MAC timing
3623 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3624 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3625 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3626 + * when MAC doesn't reference BBP signal BBRXEND
3627 + * EIFS: unit 1us
3628 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3629 + *
3630 + */
3631 +#define XIFS_TIME_CFG 0x1100
3632 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3633 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3634 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3635 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3636 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3637 +
3638 +/*
3639 + * BKOFF_SLOT_CFG:
3640 + */
3641 +#define BKOFF_SLOT_CFG 0x1104
3642 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3643 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3644 +
3645 +/*
3646 + * NAV_TIME_CFG:
3647 + */
3648 +#define NAV_TIME_CFG 0x1108
3649 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3650 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3651 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3652 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3653 +
3654 +/*
3655 + * CH_TIME_CFG: count as channel busy
3656 + */
3657 +#define CH_TIME_CFG 0x110c
3658 +
3659 +/*
3660 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3661 + */
3662 +#define PBF_LIFE_TIMER 0x1110
3663 +
3664 +/*
3665 + * BCN_TIME_CFG:
3666 + * BEACON_INTERVAL: in unit of 1/16 TU
3667 + * TSF_TICKING: Enable TSF auto counting
3668 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3669 + * BEACON_GEN: Enable beacon generator
3670 + */
3671 +#define BCN_TIME_CFG 0x1114
3672 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3673 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3674 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3675 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3676 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3677 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3678 +
3679 +/*
3680 + * TBTT_SYNC_CFG:
3681 + */
3682 +#define TBTT_SYNC_CFG 0x1118
3683 +
3684 +/*
3685 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3686 + */
3687 +#define TSF_TIMER_DW0 0x111c
3688 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3689 +
3690 +/*
3691 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3692 + */
3693 +#define TSF_TIMER_DW1 0x1120
3694 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3695 +
3696 +/*
3697 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3698 + */
3699 +#define TBTT_TIMER 0x1124
3700 +
3701 +/*
3702 + * INT_TIMER_CFG:
3703 + */
3704 +#define INT_TIMER_CFG 0x1128
3705 +
3706 +/*
3707 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3708 + */
3709 +#define INT_TIMER_EN 0x112c
3710 +
3711 +/*
3712 + * CH_IDLE_STA: channel idle time
3713 + */
3714 +#define CH_IDLE_STA 0x1130
3715 +
3716 +/*
3717 + * CH_BUSY_STA: channel busy time
3718 + */
3719 +#define CH_BUSY_STA 0x1134
3720 +
3721 +/*
3722 + * MAC_STATUS_CFG:
3723 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3724 + * if 1 or higher one of the 2 registers is busy.
3725 + */
3726 +#define MAC_STATUS_CFG 0x1200
3727 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3728 +
3729 +/*
3730 + * PWR_PIN_CFG:
3731 + */
3732 +#define PWR_PIN_CFG 0x1204
3733 +
3734 +/*
3735 + * AUTOWAKEUP_CFG: Manual power control / status register
3736 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3737 + * AUTOWAKE: 0:sleep, 1:awake
3738 + */
3739 +#define AUTOWAKEUP_CFG 0x1208
3740 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3741 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3742 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3743 +
3744 +/*
3745 + * EDCA_AC0_CFG:
3746 + */
3747 +#define EDCA_AC0_CFG 0x1300
3748 +#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
3749 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3750 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3751 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3752 +
3753 +/*
3754 + * EDCA_AC1_CFG:
3755 + */
3756 +#define EDCA_AC1_CFG 0x1304
3757 +#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
3758 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3759 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3760 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3761 +
3762 +/*
3763 + * EDCA_AC2_CFG:
3764 + */
3765 +#define EDCA_AC2_CFG 0x1308
3766 +#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
3767 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3768 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3769 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3770 +
3771 +/*
3772 + * EDCA_AC3_CFG:
3773 + */
3774 +#define EDCA_AC3_CFG 0x130c
3775 +#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
3776 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3777 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3778 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3779 +
3780 +/*
3781 + * EDCA_TID_AC_MAP:
3782 + */
3783 +#define EDCA_TID_AC_MAP 0x1310
3784 +
3785 +/*
3786 + * TX_PWR_CFG_0:
3787 + */
3788 +#define TX_PWR_CFG_0 0x1314
3789 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3790 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3791 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3792 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3793 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3794 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3795 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3796 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3797 +
3798 +/*
3799 + * TX_PWR_CFG_1:
3800 + */
3801 +#define TX_PWR_CFG_1 0x1318
3802 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3803 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3804 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3805 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3806 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3807 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3808 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3809 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3810 +
3811 +/*
3812 + * TX_PWR_CFG_2:
3813 + */
3814 +#define TX_PWR_CFG_2 0x131c
3815 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3816 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3817 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3818 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3819 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3820 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3821 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3822 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3823 +
3824 +/*
3825 + * TX_PWR_CFG_3:
3826 + */
3827 +#define TX_PWR_CFG_3 0x1320
3828 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3829 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3830 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3831 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3832 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3833 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3834 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3835 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3836 +
3837 +/*
3838 + * TX_PWR_CFG_4:
3839 + */
3840 +#define TX_PWR_CFG_4 0x1324
3841 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3842 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3843 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3844 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3845 +
3846 +/*
3847 + * TX_PIN_CFG:
3848 + */
3849 +#define TX_PIN_CFG 0x1328
3850 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3851 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3852 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3853 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3854 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3855 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3856 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3857 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3858 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3859 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3860 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3861 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3862 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3863 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3864 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3865 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3866 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3867 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3868 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3869 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3870 +
3871 +/*
3872 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3873 + */
3874 +#define TX_BAND_CFG 0x132c
3875 +#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
3876 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3877 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3878 +
3879 +/*
3880 + * TX_SW_CFG0:
3881 + */
3882 +#define TX_SW_CFG0 0x1330
3883 +
3884 +/*
3885 + * TX_SW_CFG1:
3886 + */
3887 +#define TX_SW_CFG1 0x1334
3888 +
3889 +/*
3890 + * TX_SW_CFG2:
3891 + */
3892 +#define TX_SW_CFG2 0x1338
3893 +
3894 +/*
3895 + * TXOP_THRES_CFG:
3896 + */
3897 +#define TXOP_THRES_CFG 0x133c
3898 +
3899 +/*
3900 + * TXOP_CTRL_CFG:
3901 + */
3902 +#define TXOP_CTRL_CFG 0x1340
3903 +
3904 +/*
3905 + * TX_RTS_CFG:
3906 + * RTS_THRES: unit:byte
3907 + * RTS_FBK_EN: enable rts rate fallback
3908 + */
3909 +#define TX_RTS_CFG 0x1344
3910 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3911 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3912 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3913 +
3914 +/*
3915 + * TX_TIMEOUT_CFG:
3916 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3917 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3918 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3919 + * it is recommended that:
3920 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3921 + */
3922 +#define TX_TIMEOUT_CFG 0x1348
3923 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3924 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3925 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3926 +
3927 +/*
3928 + * TX_RTY_CFG:
3929 + * SHORT_RTY_LIMIT: short retry limit
3930 + * LONG_RTY_LIMIT: long retry limit
3931 + * LONG_RTY_THRE: Long retry threshoold
3932 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3933 + * 0:expired by retry limit, 1: expired by mpdu life timer
3934 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3935 + * 0:expired by retry limit, 1: expired by mpdu life timer
3936 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3937 + */
3938 +#define TX_RTY_CFG 0x134c
3939 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3940 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3941 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3942 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3943 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3944 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3945 +
3946 +/*
3947 + * TX_LINK_CFG:
3948 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3949 + * MFB_ENABLE: TX apply remote MFB 1:enable
3950 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3951 + * 0: not apply remote remote unsolicit (MFS=7)
3952 + * TX_MRQ_EN: MCS request TX enable
3953 + * TX_RDG_EN: RDG TX enable
3954 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3955 + * REMOTE_MFB: remote MCS feedback
3956 + * REMOTE_MFS: remote MCS feedback sequence number
3957 + */
3958 +#define TX_LINK_CFG 0x1350
3959 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3960 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3961 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3962 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3963 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3964 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3965 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3966 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3967 +
3968 +/*
3969 + * HT_FBK_CFG0:
3970 + */
3971 +#define HT_FBK_CFG0 0x1354
3972 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3973 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3974 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3975 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3976 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3977 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3978 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3979 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3980 +
3981 +/*
3982 + * HT_FBK_CFG1:
3983 + */
3984 +#define HT_FBK_CFG1 0x1358
3985 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3986 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3987 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3988 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3989 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3990 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3991 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3992 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3993 +
3994 +/*
3995 + * LG_FBK_CFG0:
3996 + */
3997 +#define LG_FBK_CFG0 0x135c
3998 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3999 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
4000 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
4001 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
4002 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
4003 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
4004 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
4005 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
4006 +
4007 +/*
4008 + * LG_FBK_CFG1:
4009 + */
4010 +#define LG_FBK_CFG1 0x1360
4011 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
4012 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
4013 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
4014 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
4015 +
4016 +/*
4017 + * CCK_PROT_CFG: CCK Protection
4018 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
4019 + * PROTECT_CTRL: Protection control frame type for CCK TX
4020 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
4021 + * PROTECT_NAV: TXOP protection type for CCK TX
4022 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
4023 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
4024 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
4025 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
4026 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
4027 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
4028 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
4029 + * RTS_TH_EN: RTS threshold enable on CCK TX
4030 + */
4031 +#define CCK_PROT_CFG 0x1364
4032 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4033 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4034 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4035 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4036 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4037 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4038 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4039 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4040 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4041 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4042 +
4043 +/*
4044 + * OFDM_PROT_CFG: OFDM Protection
4045 + */
4046 +#define OFDM_PROT_CFG 0x1368
4047 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4048 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4049 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4050 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4051 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4052 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4053 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4054 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4055 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4056 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4057 +
4058 +/*
4059 + * MM20_PROT_CFG: MM20 Protection
4060 + */
4061 +#define MM20_PROT_CFG 0x136c
4062 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4063 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4064 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4065 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4066 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4067 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4068 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4069 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4070 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4071 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4072 +
4073 +/*
4074 + * MM40_PROT_CFG: MM40 Protection
4075 + */
4076 +#define MM40_PROT_CFG 0x1370
4077 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4078 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4079 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4080 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4081 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4082 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4083 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4084 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4085 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4086 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4087 +
4088 +/*
4089 + * GF20_PROT_CFG: GF20 Protection
4090 + */
4091 +#define GF20_PROT_CFG 0x1374
4092 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4093 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4094 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4095 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4096 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4097 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4098 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4099 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4100 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4101 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4102 +
4103 +/*
4104 + * GF40_PROT_CFG: GF40 Protection
4105 + */
4106 +#define GF40_PROT_CFG 0x1378
4107 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4108 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4109 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4110 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4111 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4112 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4113 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4114 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4115 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4116 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4117 +
4118 +/*
4119 + * EXP_CTS_TIME:
4120 + */
4121 +#define EXP_CTS_TIME 0x137c
4122 +
4123 +/*
4124 + * EXP_ACK_TIME:
4125 + */
4126 +#define EXP_ACK_TIME 0x1380
4127 +
4128 +/*
4129 + * RX_FILTER_CFG: RX configuration register.
4130 + */
4131 +#define RX_FILTER_CFG 0x1400
4132 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
4133 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
4134 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
4135 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4136 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
4137 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
4138 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
4139 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
4140 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
4141 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
4142 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
4143 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
4144 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
4145 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
4146 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
4147 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
4148 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
4149 +
4150 +/*
4151 + * AUTO_RSP_CFG:
4152 + * AUTORESPONDER: 0: disable, 1: enable
4153 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4154 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4155 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4156 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4157 + * DUAL_CTS_EN: Power bit value in control frame
4158 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4159 + */
4160 +#define AUTO_RSP_CFG 0x1404
4161 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
4162 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
4163 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
4164 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
4165 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
4166 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
4167 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
4168 +
4169 +/*
4170 + * LEGACY_BASIC_RATE:
4171 + */
4172 +#define LEGACY_BASIC_RATE 0x1408
4173 +
4174 +/*
4175 + * HT_BASIC_RATE:
4176 + */
4177 +#define HT_BASIC_RATE 0x140c
4178 +
4179 +/*
4180 + * HT_CTRL_CFG:
4181 + */
4182 +#define HT_CTRL_CFG 0x1410
4183 +
4184 +/*
4185 + * SIFS_COST_CFG:
4186 + */
4187 +#define SIFS_COST_CFG 0x1414
4188 +
4189 +/*
4190 + * RX_PARSER_CFG:
4191 + * Set NAV for all received frames
4192 + */
4193 +#define RX_PARSER_CFG 0x1418
4194 +
4195 +/*
4196 + * TX_SEC_CNT0:
4197 + */
4198 +#define TX_SEC_CNT0 0x1500
4199 +
4200 +/*
4201 + * RX_SEC_CNT0:
4202 + */
4203 +#define RX_SEC_CNT0 0x1504
4204 +
4205 +/*
4206 + * CCMP_FC_MUTE:
4207 + */
4208 +#define CCMP_FC_MUTE 0x1508
4209 +
4210 +/*
4211 + * TXOP_HLDR_ADDR0:
4212 + */
4213 +#define TXOP_HLDR_ADDR0 0x1600
4214 +
4215 +/*
4216 + * TXOP_HLDR_ADDR1:
4217 + */
4218 +#define TXOP_HLDR_ADDR1 0x1604
4219 +
4220 +/*
4221 + * TXOP_HLDR_ET:
4222 + */
4223 +#define TXOP_HLDR_ET 0x1608
4224 +
4225 +/*
4226 + * QOS_CFPOLL_RA_DW0:
4227 + */
4228 +#define QOS_CFPOLL_RA_DW0 0x160c
4229 +
4230 +/*
4231 + * QOS_CFPOLL_RA_DW1:
4232 + */
4233 +#define QOS_CFPOLL_RA_DW1 0x1610
4234 +
4235 +/*
4236 + * QOS_CFPOLL_QC:
4237 + */
4238 +#define QOS_CFPOLL_QC 0x1614
4239 +
4240 +/*
4241 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4242 + */
4243 +#define RX_STA_CNT0 0x1700
4244 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
4245 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
4246 +
4247 +/*
4248 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4249 + */
4250 +#define RX_STA_CNT1 0x1704
4251 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
4252 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
4253 +
4254 +/*
4255 + * RX_STA_CNT2:
4256 + */
4257 +#define RX_STA_CNT2 0x1708
4258 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
4259 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
4260 +
4261 +/*
4262 + * TX_STA_CNT0: TX Beacon count
4263 + */
4264 +#define TX_STA_CNT0 0x170c
4265 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
4266 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
4267 +
4268 +/*
4269 + * TX_STA_CNT1: TX tx count
4270 + */
4271 +#define TX_STA_CNT1 0x1710
4272 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
4273 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
4274 +
4275 +/*
4276 + * TX_STA_CNT2: TX tx count
4277 + */
4278 +#define TX_STA_CNT2 0x1714
4279 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
4280 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
4281 +
4282 +/*
4283 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4284 + */
4285 +#define TX_STA_FIFO 0x1718
4286 +#define TX_STA_FIFO_VALID FIELD32(0x00000001)
4287 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
4288 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
4289 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
4290 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
4291 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
4292 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
4293 +
4294 +/*
4295 + * TX_AGG_CNT: Debug counter
4296 + */
4297 +#define TX_AGG_CNT 0x171c
4298 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
4299 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
4300 +
4301 +/*
4302 + * TX_AGG_CNT0:
4303 + */
4304 +#define TX_AGG_CNT0 0x1720
4305 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
4306 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
4307 +
4308 +/*
4309 + * TX_AGG_CNT1:
4310 + */
4311 +#define TX_AGG_CNT1 0x1724
4312 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
4313 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
4314 +
4315 +/*
4316 + * TX_AGG_CNT2:
4317 + */
4318 +#define TX_AGG_CNT2 0x1728
4319 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
4320 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
4321 +
4322 +/*
4323 + * TX_AGG_CNT3:
4324 + */
4325 +#define TX_AGG_CNT3 0x172c
4326 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
4327 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
4328 +
4329 +/*
4330 + * TX_AGG_CNT4:
4331 + */
4332 +#define TX_AGG_CNT4 0x1730
4333 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
4334 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
4335 +
4336 +/*
4337 + * TX_AGG_CNT5:
4338 + */
4339 +#define TX_AGG_CNT5 0x1734
4340 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
4341 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
4342 +
4343 +/*
4344 + * TX_AGG_CNT6:
4345 + */
4346 +#define TX_AGG_CNT6 0x1738
4347 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
4348 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
4349 +
4350 +/*
4351 + * TX_AGG_CNT7:
4352 + */
4353 +#define TX_AGG_CNT7 0x173c
4354 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
4355 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
4356 +
4357 +/*
4358 + * MPDU_DENSITY_CNT:
4359 + * TX_ZERO_DEL: TX zero length delimiter count
4360 + * RX_ZERO_DEL: RX zero length delimiter count
4361 + */
4362 +#define MPDU_DENSITY_CNT 0x1740
4363 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4364 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4365 +
4366 +/*
4367 + * Security key table memory.
4368 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4369 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4370 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4371 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4372 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4373 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4374 + */
4375 +#define MAC_WCID_BASE 0x1800
4376 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
4377 +#define MAC_IVEIV_TABLE_BASE 0x6000
4378 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
4379 +#define SHARED_KEY_TABLE_BASE 0x6c00
4380 +#define SHARED_KEY_MODE_BASE 0x7000
4381 +
4382 +#define MAC_WCID_ENTRY(__idx) \
4383 + ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4384 +#define PAIRWISE_KEY_ENTRY(__idx) \
4385 + ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4386 +#define MAC_IVEIV_ENTRY(__idx) \
4387 + ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4388 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4389 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4390 +#define SHARED_KEY_ENTRY(__idx) \
4391 + ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4392 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4393 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4394 +
4395 +struct mac_wcid_entry {
4396 + u8 mac[6];
4397 + u8 reserved[2];
4398 +} __attribute__ ((packed));
4399 +
4400 +struct hw_key_entry {
4401 + u8 key[16];
4402 + u8 tx_mic[8];
4403 + u8 rx_mic[8];
4404 +} __attribute__ ((packed));
4405 +
4406 +struct mac_iveiv_entry {
4407 + u8 iv[8];
4408 +} __attribute__ ((packed));
4409 +
4410 +/*
4411 + * MAC_WCID_ATTRIBUTE:
4412 + */
4413 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
4414 +#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
4415 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
4416 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
4417 +
4418 +/*
4419 + * SHARED_KEY_MODE:
4420 + */
4421 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
4422 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
4423 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
4424 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
4425 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
4426 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
4427 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
4428 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
4429 +
4430 +/*
4431 + * HOST-MCU communication
4432 + */
4433 +
4434 +/*
4435 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4436 + */
4437 +#define H2M_MAILBOX_CSR 0x7010
4438 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
4439 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
4440 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
4441 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
4442 +
4443 +/*
4444 + * H2M_MAILBOX_CID:
4445 + */
4446 +#define H2M_MAILBOX_CID 0x7014
4447 +
4448 +/*
4449 + * H2M_MAILBOX_STATUS:
4450 + */
4451 +#define H2M_MAILBOX_STATUS 0x701c
4452 +
4453 +/*
4454 + * H2M_INT_SRC:
4455 + */
4456 +#define H2M_INT_SRC 0x7024
4457 +
4458 +/*
4459 + * H2M_BBP_AGENT:
4460 + */
4461 +#define H2M_BBP_AGENT 0x7028
4462 +
4463 +/*
4464 + * MCU_LEDCS: LED control for MCU Mailbox.
4465 + */
4466 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
4467 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
4468 +
4469 +/*
4470 + * HW_CS_CTS_BASE:
4471 + * Carrier-sense CTS frame base address.
4472 + * It's where mac stores carrier-sense frame for carrier-sense function.
4473 + */
4474 +#define HW_CS_CTS_BASE 0x7700
4475 +
4476 +/*
4477 + * HW_DFS_CTS_BASE:
4478 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4479 + */
4480 +#define HW_DFS_CTS_BASE 0x7780
4481 +
4482 +/*
4483 + * TXRX control registers - base address 0x3000
4484 + */
4485 +
4486 +/*
4487 + * TXRX_CSR1:
4488 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4489 + */
4490 +#define TXRX_CSR1 0x77d0
4491 +
4492 +/*
4493 + * HW_DEBUG_SETTING_BASE:
4494 + * since NULL frame won't be that long (256 byte)
4495 + * We steal 16 tail bytes to save debugging settings
4496 + */
4497 +#define HW_DEBUG_SETTING_BASE 0x77f0
4498 +#define HW_DEBUG_SETTING_BASE2 0x7770
4499 +
4500 +/*
4501 + * HW_BEACON_BASE
4502 + * In order to support maximum 8 MBSS and its maximum length
4503 + * is 512 bytes for each beacon
4504 + * Three section discontinue memory segments will be used.
4505 + * 1. The original region for BCN 0~3
4506 + * 2. Extract memory from FCE table for BCN 4~5
4507 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4508 + * It occupied those memory of wcid 238~253 for BCN 6
4509 + * and wcid 222~237 for BCN 7
4510 + *
4511 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4512 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4513 + */
4514 +#define HW_BEACON_BASE0 0x7800
4515 +#define HW_BEACON_BASE1 0x7a00
4516 +#define HW_BEACON_BASE2 0x7c00
4517 +#define HW_BEACON_BASE3 0x7e00
4518 +#define HW_BEACON_BASE4 0x7200
4519 +#define HW_BEACON_BASE5 0x7400
4520 +#define HW_BEACON_BASE6 0x5dc0
4521 +#define HW_BEACON_BASE7 0x5bc0
4522 +
4523 +#define HW_BEACON_OFFSET(__index) \
4524 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4525 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4526 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4527 +
4528 +/*
4529 + * 8051 firmware image.
4530 + */
4531 +#define FIRMWARE_RT2870 "rt2870.bin"
4532 +#define FIRMWARE_IMAGE_BASE 0x3000
4533 +
4534 +/*
4535 + * BBP registers.
4536 + * The wordsize of the BBP is 8 bits.
4537 + */
4538 +
4539 +/*
4540 + * BBP 1: TX Antenna
4541 + */
4542 +#define BBP1_TX_POWER FIELD8(0x07)
4543 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4544 +
4545 +/*
4546 + * BBP 3: RX Antenna
4547 + */
4548 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4549 +#define BBP3_HT40_PLUS FIELD8(0x20)
4550 +
4551 +/*
4552 + * BBP 4: Bandwidth
4553 + */
4554 +#define BBP4_TX_BF FIELD8(0x01)
4555 +#define BBP4_BANDWIDTH FIELD8(0x18)
4556 +
4557 +/*
4558 + * RFCSR registers
4559 + * The wordsize of the RFCSR is 8 bits.
4560 + */
4561 +
4562 +/*
4563 + * RFCSR 6:
4564 + */
4565 +#define RFCSR6_R FIELD8(0x03)
4566 +
4567 +/*
4568 + * RFCSR 7:
4569 + */
4570 +#define RFCSR7_RF_TUNING FIELD8(0x01)
4571 +
4572 +/*
4573 + * RFCSR 12:
4574 + */
4575 +#define RFCSR12_TX_POWER FIELD8(0x1f)
4576 +
4577 +/*
4578 + * RFCSR 22:
4579 + */
4580 +#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
4581 +
4582 +/*
4583 + * RFCSR 23:
4584 + */
4585 +#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
4586 +
4587 +/*
4588 + * RFCSR 30:
4589 + */
4590 +#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
4591 +
4592 +/*
4593 + * RF registers
4594 + */
4595 +
4596 +/*
4597 + * RF 2
4598 + */
4599 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4600 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4601 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4602 +
4603 +/*
4604 + * RF 3
4605 + */
4606 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4607 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4608 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4609 +
4610 +/*
4611 + * RF 4
4612 + */
4613 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4614 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4615 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4616 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4617 +#define RF4_HT40 FIELD32(0x00200000)
4618 +
4619 +/*
4620 + * EEPROM content.
4621 + * The wordsize of the EEPROM is 16 bits.
4622 + */
4623 +
4624 +/*
4625 + * EEPROM Version
4626 + */
4627 +#define EEPROM_VERSION 0x0001
4628 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4629 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4630 +
4631 +/*
4632 + * HW MAC address.
4633 + */
4634 +#define EEPROM_MAC_ADDR_0 0x0002
4635 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4636 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4637 +#define EEPROM_MAC_ADDR_1 0x0003
4638 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4639 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4640 +#define EEPROM_MAC_ADDR_2 0x0004
4641 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4642 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4643 +
4644 +/*
4645 + * EEPROM ANTENNA config
4646 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4647 + * TXPATH: 1: 1T, 2: 2T
4648 + */
4649 +#define EEPROM_ANTENNA 0x001a
4650 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4651 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4652 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4653 +
4654 +/*
4655 + * EEPROM NIC config
4656 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4657 + */
4658 +#define EEPROM_NIC 0x001b
4659 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4660 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4661 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4662 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4663 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4664 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4665 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4666 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4667 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4668 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4669 +
4670 +/*
4671 + * EEPROM frequency
4672 + */
4673 +#define EEPROM_FREQ 0x001d
4674 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4675 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4676 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4677 +
4678 +/*
4679 + * EEPROM LED
4680 + * POLARITY_RDY_G: Polarity RDY_G setting.
4681 + * POLARITY_RDY_A: Polarity RDY_A setting.
4682 + * POLARITY_ACT: Polarity ACT setting.
4683 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4684 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4685 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4686 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4687 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4688 + * LED_MODE: Led mode.
4689 + */
4690 +#define EEPROM_LED1 0x001e
4691 +#define EEPROM_LED2 0x001f
4692 +#define EEPROM_LED3 0x0020
4693 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4694 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4695 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4696 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4697 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4698 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4699 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4700 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4701 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4702 +
4703 +/*
4704 + * EEPROM LNA
4705 + */
4706 +#define EEPROM_LNA 0x0022
4707 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4708 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4709 +
4710 +/*
4711 + * EEPROM RSSI BG offset
4712 + */
4713 +#define EEPROM_RSSI_BG 0x0023
4714 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4715 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4716 +
4717 +/*
4718 + * EEPROM RSSI BG2 offset
4719 + */
4720 +#define EEPROM_RSSI_BG2 0x0024
4721 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4722 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4723 +
4724 +/*
4725 + * EEPROM RSSI A offset
4726 + */
4727 +#define EEPROM_RSSI_A 0x0025
4728 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4729 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4730 +
4731 +/*
4732 + * EEPROM RSSI A2 offset
4733 + */
4734 +#define EEPROM_RSSI_A2 0x0026
4735 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4736 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4737 +
4738 +/*
4739 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4740 + * This is delta in 40MHZ.
4741 + * VALUE: Tx Power dalta value (MAX=4)
4742 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4743 + * TXPOWER: Enable:
4744 + */
4745 +#define EEPROM_TXPOWER_DELTA 0x0028
4746 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4747 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4748 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4749 +
4750 +/*
4751 + * EEPROM TXPOWER 802.11BG
4752 + */
4753 +#define EEPROM_TXPOWER_BG1 0x0029
4754 +#define EEPROM_TXPOWER_BG2 0x0030
4755 +#define EEPROM_TXPOWER_BG_SIZE 7
4756 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4757 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4758 +
4759 +/*
4760 + * EEPROM TXPOWER 802.11A
4761 + */
4762 +#define EEPROM_TXPOWER_A1 0x003c
4763 +#define EEPROM_TXPOWER_A2 0x0053
4764 +#define EEPROM_TXPOWER_A_SIZE 6
4765 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4766 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4767 +
4768 +/*
4769 + * EEPROM TXpower byrate: 20MHZ power
4770 + */
4771 +#define EEPROM_TXPOWER_BYRATE 0x006f
4772 +
4773 +/*
4774 + * EEPROM BBP.
4775 + */
4776 +#define EEPROM_BBP_START 0x0078
4777 +#define EEPROM_BBP_SIZE 16
4778 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4779 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4780 +
4781 +/*
4782 + * MCU mailbox commands.
4783 + */
4784 +#define MCU_SLEEP 0x30
4785 +#define MCU_WAKEUP 0x31
4786 +#define MCU_RADIO_OFF 0x35
4787 +#define MCU_LED 0x50
4788 +#define MCU_LED_STRENGTH 0x51
4789 +#define MCU_LED_1 0x52
4790 +#define MCU_LED_2 0x53
4791 +#define MCU_LED_3 0x54
4792 +#define MCU_RADAR 0x60
4793 +#define MCU_BOOT_SIGNAL 0x72
4794 +#define MCU_BBP_SIGNAL 0x80
4795 +
4796 +/*
4797 + * DMA descriptor defines.
4798 + */
4799 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
4800 +#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
4801 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4802 +#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
4803 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4804 +
4805 +/*
4806 + * TX descriptor format for TX, PRIO and Beacon Ring.
4807 + */
4808 +
4809 +/*
4810 + * Word0
4811 + */
4812 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
4813 +
4814 +/*
4815 + * Word1
4816 + */
4817 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
4818 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
4819 +#define TXD_W1_BURST FIELD32(0x00008000)
4820 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
4821 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
4822 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
4823 +
4824 +/*
4825 + * Word2
4826 + */
4827 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
4828 +
4829 +/*
4830 + * Word3
4831 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4832 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4833 + * 0:MGMT, 1:HCCA 2:EDCA
4834 + */
4835 +#define TXD_W3_WIV FIELD32(0x01000000)
4836 +#define TXD_W3_QSEL FIELD32(0x06000000)
4837 +#define TXD_W3_TCO FIELD32(0x20000000)
4838 +#define TXD_W3_UCO FIELD32(0x40000000)
4839 +#define TXD_W3_ICO FIELD32(0x80000000)
4840 +
4841 +/*
4842 + * TX Info structure
4843 + */
4844 +
4845 +/*
4846 + * Word0
4847 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4848 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4849 + * 0:MGMT, 1:HCCA 2:EDCA
4850 + * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
4851 + * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
4852 + * Force USB DMA transmit frame from current selected endpoint
4853 + */
4854 +#define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff)
4855 +#define TXINFO_W0_WIV FIELD32(0x01000000)
4856 +#define TXINFO_W0_QSEL FIELD32(0x06000000)
4857 +#define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000)
4858 +#define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000)
4859 +#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
4860 +
4861 +/*
4862 + * TX WI structure
4863 + */
4864 +
4865 +/*
4866 + * Word0
4867 + * FRAG: 1 To inform TKIP engine this is a fragment.
4868 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4869 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4870 + * BW: Channel bandwidth 20MHz or 40 MHz
4871 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4872 + */
4873 +#define TXWI_W0_FRAG FIELD32(0x00000001)
4874 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
4875 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
4876 +#define TXWI_W0_TS FIELD32(0x00000008)
4877 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
4878 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
4879 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
4880 +#define TXWI_W0_MCS FIELD32(0x007f0000)
4881 +#define TXWI_W0_BW FIELD32(0x00800000)
4882 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
4883 +#define TXWI_W0_STBC FIELD32(0x06000000)
4884 +#define TXWI_W0_IFS FIELD32(0x08000000)
4885 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
4886 +
4887 +/*
4888 + * Word1
4889 + */
4890 +#define TXWI_W1_ACK FIELD32(0x00000001)
4891 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
4892 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
4893 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
4894 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4895 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
4896 +
4897 +/*
4898 + * Word2
4899 + */
4900 +#define TXWI_W2_IV FIELD32(0xffffffff)
4901 +
4902 +/*
4903 + * Word3
4904 + */
4905 +#define TXWI_W3_EIV FIELD32(0xffffffff)
4906 +
4907 +/*
4908 + * RX descriptor format for RX Ring.
4909 + */
4910 +
4911 +/*
4912 + * Word0
4913 + * UNICAST_TO_ME: This RX frame is unicast to me.
4914 + * MULTICAST: This is a multicast frame.
4915 + * BROADCAST: This is a broadcast frame.
4916 + * MY_BSS: this frame belongs to the same BSSID.
4917 + * CRC_ERROR: CRC error.
4918 + * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
4919 + * AMSDU: rx with 802.3 header, not 802.11 header.
4920 + */
4921 +
4922 +#define RXD_W0_BA FIELD32(0x00000001)
4923 +#define RXD_W0_DATA FIELD32(0x00000002)
4924 +#define RXD_W0_NULLDATA FIELD32(0x00000004)
4925 +#define RXD_W0_FRAG FIELD32(0x00000008)
4926 +#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000010)
4927 +#define RXD_W0_MULTICAST FIELD32(0x00000020)
4928 +#define RXD_W0_BROADCAST FIELD32(0x00000040)
4929 +#define RXD_W0_MY_BSS FIELD32(0x00000080)
4930 +#define RXD_W0_CRC_ERROR FIELD32(0x00000100)
4931 +#define RXD_W0_CIPHER_ERROR FIELD32(0x00000600)
4932 +#define RXD_W0_AMSDU FIELD32(0x00000800)
4933 +#define RXD_W0_HTC FIELD32(0x00001000)
4934 +#define RXD_W0_RSSI FIELD32(0x00002000)
4935 +#define RXD_W0_L2PAD FIELD32(0x00004000)
4936 +#define RXD_W0_AMPDU FIELD32(0x00008000)
4937 +#define RXD_W0_DECRYPTED FIELD32(0x00010000)
4938 +#define RXD_W0_PLCP_RSSI FIELD32(0x00020000)
4939 +#define RXD_W0_CIPHER_ALG FIELD32(0x00040000)
4940 +#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
4941 +#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
4942 +
4943 +/*
4944 + * RX WI structure
4945 + */
4946 +
4947 +/*
4948 + * Word0
4949 + */
4950 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
4951 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
4952 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
4953 +#define RXWI_W0_UDF FIELD32(0x0000e000)
4954 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4955 +#define RXWI_W0_TID FIELD32(0xf0000000)
4956 +
4957 +/*
4958 + * Word1
4959 + */
4960 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
4961 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
4962 +#define RXWI_W1_MCS FIELD32(0x007f0000)
4963 +#define RXWI_W1_BW FIELD32(0x00800000)
4964 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
4965 +#define RXWI_W1_STBC FIELD32(0x06000000)
4966 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
4967 +
4968 +/*
4969 + * Word2
4970 + */
4971 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
4972 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
4973 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
4974 +
4975 +/*
4976 + * Word3
4977 + */
4978 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
4979 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
4980 +
4981 +/*
4982 + * Macro's for converting txpower from EEPROM to mac80211 value
4983 + * and from mac80211 value to register value.
4984 + */
4985 +#define MIN_G_TXPOWER 0
4986 +#define MIN_A_TXPOWER -7
4987 +#define MAX_G_TXPOWER 31
4988 +#define MAX_A_TXPOWER 15
4989 +#define DEFAULT_TXPOWER 5
4990 +
4991 +#define TXPOWER_G_FROM_DEV(__txpower) \
4992 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4993 +
4994 +#define TXPOWER_G_TO_DEV(__txpower) \
4995 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4996 +
4997 +#define TXPOWER_A_FROM_DEV(__txpower) \
4998 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4999 +
5000 +#define TXPOWER_A_TO_DEV(__txpower) \
5001 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
5002 +
5003 +#endif /* RT2800USB_H */
5004 --- a/drivers/net/wireless/rt2x00/rt2x00.h
5005 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
5006 @@ -144,6 +144,7 @@ struct rt2x00_chip {
5007 #define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
5008 #define RT2880 0x2880 /* WSOC */
5009 #define RT3052 0x3052 /* WSOC */
5010 +#define RT2870 0x1600
5011
5012 u16 rf;
5013 u32 rev;
5014 @@ -788,6 +789,12 @@ struct rt2x00_dev {
5015 u8 freq_offset;
5016
5017 /*
5018 + * Calibration information (for rt2800usb).
5019 + */
5020 + u8 calibration_bw20;
5021 + u8 calibration_bw40;
5022 +
5023 + /*
5024 * Low level statistics which will have
5025 * to be kept up to date while device is running.
5026 */
Staging tree of florian