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Fixup the hcd driver, add a start/stop/reset/sw_reset functions, should allow it...
[openwrt/staging/florian.git] / target / linux / adm5120-2.6 / files / drivers / usb / host / adm5120-hcd.c
1 /*
2 * HCD driver for ADM5120 SoC
3 *
4 * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
5 *
6 * Based on the ADMtek 2.4 driver
7 * (C) Copyright 2003 Junius Chen <juniusc@admtek.com.tw>
8 * Which again was based on the ohci and uhci drivers.
9 */
10
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/debugfs.h>
14 #include <linux/seq_file.h>
15 #include <linux/errno.h>
16 #include <linux/init.h>
17 #include <linux/list.h>
18 #include <linux/usb.h>
19 #include <linux/platform_device.h>
20
21 #include <asm/bootinfo.h>
22 #include <asm/io.h>
23 #include <asm/irq.h>
24 #include <asm/system.h>
25 #include <asm/byteorder.h>
26 #include <asm/mach-adm5120/adm5120_info.h>
27
28 #include "../core/hcd.h"
29
30 MODULE_DESCRIPTION("ADM5120 USB Host Controller Driver");
31 MODULE_LICENSE("GPL");
32 MODULE_AUTHOR("Jeroen Vreeken (pe1rxq@amsat.org)");
33
34 #define PFX "adm5120-hcd: "
35
36 #define ADMHCD_REG_CONTROL 0x00
37 #define ADMHCD_REG_INTSTATUS 0x04
38 #define ADMHCD_REG_INTENABLE 0x08
39 #define ADMHCD_REG_HOSTCONTROL 0x10
40 #define ADMHCD_REG_FMINTERVAL 0x18
41 #define ADMHCD_REG_FMNUMBER 0x1c
42 #define ADMHCD_REG_LSTHRESH 0x70
43 #define ADMHCD_REG_RHDESCR 0x74
44 #define ADMHCD_REG_PORTSTATUS0 0x78
45 #define ADMHCD_REG_PORTSTATUS1 0x7c
46 #define ADMHCD_REG_HOSTHEAD 0x80
47
48
49 #define ADMHCD_NUMPORTS 2
50
51 #define ADMHCD_HOST_EN 0x00000001 /* Host enable */
52 #define ADMHCD_SW_INTREQ 0x00000002 /* request software int */
53 #define ADMHCD_SW_RESET 0x00000008 /* Reset */
54
55 #define ADMHCD_INT_TD 0x00100000 /* TD completed */
56 #define ADMHCD_INT_SW 0x20000000 /* software interrupt */
57 #define ADMHCD_INT_FATAL 0x40000000 /* Fatal interrupt */
58 #define ADMHCD_INT_ACT 0x80000000 /* Interrupt active */
59
60 #define ADMHCD_STATE_RST 0x00000000 /* bus state reset */
61 #define ADMHCD_STATE_RES 0x00000001 /* bus state resume */
62 #define ADMHCD_STATE_OP 0x00000002 /* bus state operational */
63 #define ADMHCD_STATE_SUS 0x00000003 /* bus state suspended */
64 #define ADMHCD_DMA_EN 0x00000004 /* enable dma engine */
65
66 #define ADMHCD_RST_ST 0x00 /* USB reset state */
67 #define ADMHCD_RSM_ST 0x01 /* USB resume state */
68 #define ADMHCD_OPR_ST 0x10 /* USB operational state */
69 #define ADMHCD_SUS_ST 0x11 /* USB suspend state */
70
71 #define ADMHCD_NPS 0x00000200 /* No Power Switch */
72 #define ADMHCD_PSM 0x00000100 /* Power switch mode */
73 #define ADMHCD_OPCM 0x00000400 /* Over current protect mode */
74 #define ADMHCD_NOCP 0x00000800 /* No over current protect mode */
75 #define ADMHCD_LPSC 0x04000000 /* Local power switch change */
76 #define ADMHCD_LPS 0x01000000 /* Local power switch/global power switch */
77
78 #define ADMHCD_CCS 0x00000001 /* current connect status */
79 #define ADMHCD_PES 0x00000002 /* port enable status */
80 #define ADMHCD_PSS 0x00000004 /* port suspend status */
81 #define ADMHCD_POCI 0x00000008 /* port overcurrent indicator */
82 #define ADMHCD_PRS 0x00000010 /* port reset status */
83 #define ADMHCD_PPS 0x00000100 /* port power status */
84 #define ADMHCD_LSDA 0x00000200 /* low speed device attached */
85 #define ADMHCD_CSC 0x00010000 /* connect status change */
86 #define ADMHCD_PESC 0x00020000 /* enable status change */
87 #define ADMHCD_PSSC 0x00040000 /* suspend status change */
88 #define ADMHCD_OCIC 0x00080000 /* overcurrent change*/
89 #define ADMHCD_PRSC 0x00100000 /* reset status change */
90
91
92 struct admhcd_ed {
93 /* Don't change first four, they used for DMA */
94 u32 control;
95 struct admhcd_td *tail;
96 struct admhcd_td *head;
97 struct admhcd_ed *next;
98 /* the rest is for the driver only: */
99 struct admhcd_td *cur;
100 struct usb_host_endpoint *ep;
101 struct urb *urb;
102 struct admhcd_ed *real;
103 } __attribute__ ((packed));
104
105 #define ADMHCD_ED_EPSHIFT 7 /* Shift for endpoint number */
106 #define ADMHCD_ED_INT 0x00000800 /* Is this an int endpoint */
107 #define ADMHCD_ED_SPEED 0x00002000 /* Is it a high speed dev? */
108 #define ADMHCD_ED_SKIP 0x00004000 /* Skip this ED */
109 #define ADMHCD_ED_FORMAT 0x00008000 /* Is this an isoc endpoint */
110 #define ADMHCD_ED_MAXSHIFT 16 /* Shift for max packet size */
111
112 struct admhcd_td {
113 /* Don't change first four, they are used for DMA */
114 u32 control;
115 u32 buffer;
116 u32 buflen;
117 struct admhcd_td *next;
118 /* the rest is for the driver only: */
119 struct urb *urb;
120 struct admhcd_td *real;
121 } __attribute__ ((packed));
122
123 #define ADMHCD_TD_OWN 0x80000000
124 #define ADMHCD_TD_TOGGLE 0x00000000
125 #define ADMHCD_TD_DATA0 0x01000000
126 #define ADMHCD_TD_DATA1 0x01800000
127 #define ADMHCD_TD_OUT 0x00200000
128 #define ADMHCD_TD_IN 0x00400000
129 #define ADMHCD_TD_SETUP 0x00000000
130 #define ADMHCD_TD_ISO 0x00010000
131 #define ADMHCD_TD_R 0x00040000
132 #define ADMHCD_TD_INTEN 0x00010000
133
134 static int admhcd_td_err[16] = {
135 0, /* No */
136 -EREMOTEIO, /* CRC */
137 -EREMOTEIO, /* bit stuff */
138 -EREMOTEIO, /* data toggle */
139 -EPIPE, /* stall */
140 -ETIMEDOUT, /* timeout */
141 -EPROTO, /* pid err */
142 -EPROTO, /* unexpected pid */
143 -EREMOTEIO, /* data overrun */
144 -EREMOTEIO, /* data underrun */
145 -ETIMEDOUT, /* 1010 */
146 -ETIMEDOUT, /* 1011 */
147 -EREMOTEIO, /* buffer overrun */
148 -EREMOTEIO, /* buffer underrun */
149 -ETIMEDOUT, /* 1110 */
150 -ETIMEDOUT, /* 1111 */
151 };
152
153 #define ADMHCD_TD_ERRMASK 0x38000000
154 #define ADMHCD_TD_ERRSHIFT 27
155
156 #define TD(td) ((struct admhcd_td *)(((u32)(td)) & ~0xf))
157 #define ED(ed) ((struct admhcd_ed *)(((u32)(ed)) & ~0xf))
158
159 struct admhcd {
160 spinlock_t lock;
161
162 void __iomem *data_reg;
163 /* Root hub registers */
164 u32 rhdesca;
165 u32 rhdescb;
166 u32 rhstatus;
167 u32 rhport[2];
168
169 /* async schedule: control, bulk */
170 struct list_head async;
171 u32 base;
172 u32 dma_en;
173 unsigned long flags;
174
175 };
176
177 static inline struct admhcd *hcd_to_admhcd(struct usb_hcd *hcd)
178 {
179 return (struct admhcd *)(hcd->hcd_priv);
180 }
181
182 static inline struct usb_hcd *admhcd_to_hcd(struct admhcd *admhcd)
183 {
184 return container_of((void *)admhcd, struct usb_hcd, hcd_priv);
185 }
186
187 static char hcd_name[] = "adm5120-hcd";
188
189 static u32 admhcd_reg_get(struct admhcd *ahcd, int reg)
190 {
191 return *(volatile u32 *)KSEG1ADDR(ahcd->base+reg);
192 }
193
194 static void admhcd_reg_set(struct admhcd *ahcd, int reg, u32 val)
195 {
196 *(volatile u32 *)KSEG1ADDR(ahcd->base+reg) = val;
197 }
198
199 static void admhcd_lock(struct admhcd *ahcd)
200 {
201 spin_lock_irqsave(&ahcd->lock, ahcd->flags);
202 ahcd->dma_en = admhcd_reg_get(ahcd, ADMHCD_REG_HOSTCONTROL) &
203 ADMHCD_DMA_EN;
204 admhcd_reg_set(ahcd, ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP);
205 }
206
207 static void admhcd_unlock(struct admhcd *ahcd)
208 {
209 admhcd_reg_set(ahcd, ADMHCD_REG_HOSTCONTROL,
210 ADMHCD_STATE_OP | ahcd->dma_en);
211 spin_unlock_irqrestore(&ahcd->lock, ahcd->flags);
212 }
213
214 static struct admhcd_td *admhcd_td_alloc(struct admhcd_ed *ed, struct urb *urb)
215 {
216 struct admhcd_td *tdn, *td;
217
218 tdn = kmalloc(sizeof(struct admhcd_td), GFP_ATOMIC);
219 if (!tdn)
220 return NULL;
221 tdn->real = tdn;
222 tdn = (struct admhcd_td *)KSEG1ADDR(tdn);
223 memset(tdn, 0, sizeof(struct admhcd_td));
224 if (ed->cur == NULL) {
225 ed->cur = tdn;
226 ed->head = tdn;
227 ed->tail = tdn;
228 td = tdn;
229 } else {
230 /* Supply back the old tail and link in new td as tail */
231 td = TD(ed->tail);
232 TD(ed->tail)->next = tdn;
233 ed->tail = tdn;
234 }
235 td->urb = urb;
236
237 return td;
238 }
239
240 static void admhcd_td_free(struct admhcd_ed *ed, struct urb *urb)
241 {
242 struct admhcd_td *td, **tdp;
243
244 if (urb == NULL)
245 ed->control |= ADMHCD_ED_SKIP;
246 tdp = &ed->cur;
247 td = ed->cur;
248 do {
249 if (td->urb == urb)
250 break;
251 tdp = &td->next;
252 td = TD(td->next);
253 } while (td);
254 while (td && td->urb == urb) {
255 *tdp = TD(td->next);
256 kfree(td->real);
257 td = *tdp;
258 }
259 }
260
261 /* Find an endpoint's descriptor, if needed allocate a new one and link it
262 in the DMA chain
263 */
264 static struct admhcd_ed *admhcd_get_ed(struct admhcd *ahcd,
265 struct usb_host_endpoint *ep, struct urb *urb)
266 {
267 struct admhcd_ed *hosthead;
268 struct admhcd_ed *found = NULL, *ed = NULL;
269 unsigned int pipe = urb->pipe;
270
271 admhcd_lock(ahcd);
272 hosthead = (struct admhcd_ed *)admhcd_reg_get(ahcd, ADMHCD_REG_HOSTHEAD);
273 if (hosthead) {
274 for (ed = hosthead;; ed = ED(ed->next)) {
275 if (ed->ep == ep) {
276 found = ed;
277 break;
278 }
279 if (ED(ed->next) == hosthead)
280 break;
281 }
282 }
283 if (!found) {
284 found = kmalloc(sizeof(struct admhcd_ed), GFP_ATOMIC);
285 if (!found)
286 goto out;
287 memset(found, 0, sizeof(struct admhcd_ed));
288 found->real = found;
289 found->ep = ep;
290 found = (struct admhcd_ed *)KSEG1ADDR(found);
291 found->control = usb_pipedevice(pipe) |
292 (usb_pipeendpoint(pipe) << ADMHCD_ED_EPSHIFT) |
293 (usb_pipeint(pipe) ? ADMHCD_ED_INT : 0) |
294 (urb->dev->speed == USB_SPEED_FULL ? ADMHCD_ED_SPEED : 0) |
295 (usb_pipeisoc(pipe) ? ADMHCD_ED_FORMAT : 0) |
296 (usb_maxpacket(urb->dev, pipe, usb_pipeout(pipe)) << ADMHCD_ED_MAXSHIFT);
297 /* Alloc first dummy td */
298 admhcd_td_alloc(found, NULL);
299 if (hosthead) {
300 found->next = hosthead;
301 ed->next = found;
302 } else {
303 found->next = found;
304 admhcd_reg_set(ahcd, ADMHCD_REG_HOSTHEAD, (u32)found);
305 }
306 }
307 out:
308 admhcd_unlock(ahcd);
309 return found;
310 }
311
312 static struct admhcd_td *admhcd_td_fill(u32 control, struct admhcd_td *td,
313 dma_addr_t data, int len)
314 {
315 td->buffer = data;
316 td->buflen = len;
317 td->control = control;
318 return TD(td->next);
319 }
320
321 static void admhcd_ed_start(struct admhcd *ahcd, struct admhcd_ed *ed)
322 {
323 struct admhcd_td *td = ed->cur;
324
325 if (ed->urb)
326 return;
327 if (td->urb) {
328 ed->urb = td->urb;
329 while (1) {
330 td->control |= ADMHCD_TD_OWN;
331 if (TD(td->next)->urb != td->urb) {
332 td->buflen |= ADMHCD_TD_INTEN;
333 break;
334 }
335 td = TD(td->next);
336 }
337 }
338 ed->head = TD(ed->head);
339 ahcd->dma_en |= ADMHCD_DMA_EN;
340 }
341
342 static irqreturn_t adm5120hcd_irq(struct usb_hcd *hcd)
343 {
344 struct admhcd *ahcd = hcd_to_admhcd(hcd);
345 u32 intstatus;
346
347 intstatus = admhcd_reg_get(ahcd, ADMHCD_REG_INTSTATUS);
348 if (intstatus & ADMHCD_INT_FATAL) {
349 admhcd_reg_set(ahcd, ADMHCD_REG_INTSTATUS, ADMHCD_INT_FATAL);
350 //
351 }
352 if (intstatus & ADMHCD_INT_SW) {
353 admhcd_reg_set(ahcd, ADMHCD_REG_INTSTATUS, ADMHCD_INT_SW);
354 //
355 }
356 if (intstatus & ADMHCD_INT_TD) {
357 struct admhcd_ed *ed, *head;
358
359 admhcd_reg_set(ahcd, ADMHCD_REG_INTSTATUS, ADMHCD_INT_TD);
360
361 head = (struct admhcd_ed *)admhcd_reg_get(ahcd, ADMHCD_REG_HOSTHEAD);
362 ed = head;
363 if (ed) do {
364 /* Is it a finished TD? */
365 if (ed->urb && !(ed->cur->control & ADMHCD_TD_OWN)) {
366 struct admhcd_td *td;
367 int error;
368
369 td = ed->cur;
370 error = (td->control & ADMHCD_TD_ERRMASK) >>
371 ADMHCD_TD_ERRSHIFT;
372 ed->urb->status = admhcd_td_err[error];
373 admhcd_td_free(ed, ed->urb);
374 // Calculate real length!!!
375 ed->urb->actual_length = ed->urb->transfer_buffer_length;
376 ed->urb->hcpriv = NULL;
377 usb_hcd_giveback_urb(hcd, ed->urb);
378 ed->urb = NULL;
379 }
380 admhcd_ed_start(ahcd, ed);
381 ed = ED(ed->next);
382 } while (ed != head);
383 }
384
385 return IRQ_HANDLED;
386 }
387
388 static int admhcd_urb_enqueue(struct usb_hcd *hcd, struct usb_host_endpoint *ep,
389 struct urb *urb, gfp_t mem_flags)
390 {
391 struct admhcd *ahcd = hcd_to_admhcd(hcd);
392 struct admhcd_ed *ed;
393 struct admhcd_td *td;
394 int size = 0, i, zero = 0, ret = 0;
395 unsigned int pipe = urb->pipe, toggle = 0;
396 dma_addr_t data = (dma_addr_t)urb->transfer_buffer;
397 int data_len = urb->transfer_buffer_length;
398
399 ed = admhcd_get_ed(ahcd, ep, urb);
400 if (!ed)
401 return -ENOMEM;
402
403 switch(usb_pipetype(pipe)) {
404 case PIPE_CONTROL:
405 size = 2;
406 case PIPE_INTERRUPT:
407 case PIPE_BULK:
408 default:
409 size += urb->transfer_buffer_length / 4096;
410 if (urb->transfer_buffer_length % 4096)
411 size++;
412 if (size == 0)
413 size++;
414 else if (urb->transfer_flags & URB_ZERO_PACKET &&
415 !(urb->transfer_buffer_length %
416 usb_maxpacket(urb->dev, pipe, usb_pipeout(pipe)))) {
417 size++;
418 zero = 1;
419 }
420 break;
421 case PIPE_ISOCHRONOUS:
422 size = urb->number_of_packets;
423 break;
424 }
425
426 admhcd_lock(ahcd);
427 /* Remember the first td */
428 td = admhcd_td_alloc(ed, urb);
429 if (!td) {
430 ret = -ENOMEM;
431 goto out;
432 }
433 /* Allocate additionall tds first */
434 for (i = 1; i < size; i++) {
435 if (admhcd_td_alloc(ed, urb) == NULL) {
436 admhcd_td_free(ed, urb);
437 ret = -ENOMEM;
438 goto out;
439 }
440 }
441
442 if (usb_gettoggle(urb->dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)))
443 toggle = ADMHCD_TD_TOGGLE;
444 else {
445 toggle = ADMHCD_TD_DATA0;
446 usb_settoggle(urb->dev, usb_pipeendpoint(pipe),
447 usb_pipeout(pipe), 1);
448 }
449
450 switch(usb_pipetype(pipe)) {
451 case PIPE_CONTROL:
452 td = admhcd_td_fill(ADMHCD_TD_SETUP | ADMHCD_TD_DATA0,
453 td, (dma_addr_t)urb->setup_packet, 8);
454 while (data_len > 0) {
455 td = admhcd_td_fill(ADMHCD_TD_DATA1
456 | ADMHCD_TD_R |
457 (usb_pipeout(pipe) ?
458 ADMHCD_TD_OUT : ADMHCD_TD_IN), td,
459 data, data_len % 4097);
460 data_len -= 4096;
461 }
462 admhcd_td_fill(ADMHCD_TD_DATA1 | (usb_pipeout(pipe) ?
463 ADMHCD_TD_IN : ADMHCD_TD_OUT), td,
464 data, 0);
465 break;
466 case PIPE_INTERRUPT:
467 case PIPE_BULK:
468 //info ok for interrupt?
469 i = 0;
470 while(data_len > 4096) {
471 td = admhcd_td_fill((usb_pipeout(pipe) ?
472 ADMHCD_TD_OUT :
473 ADMHCD_TD_IN | ADMHCD_TD_R) |
474 (i ? ADMHCD_TD_TOGGLE : toggle), td,
475 data, 4096);
476 data += 4096;
477 data_len -= 4096;
478 i++;
479 }
480 td = admhcd_td_fill((usb_pipeout(pipe) ?
481 ADMHCD_TD_OUT : ADMHCD_TD_IN) |
482 (i ? ADMHCD_TD_TOGGLE : toggle), td, data, data_len);
483 i++;
484 if (zero)
485 admhcd_td_fill((usb_pipeout(pipe) ?
486 ADMHCD_TD_OUT : ADMHCD_TD_IN) |
487 (i ? ADMHCD_TD_TOGGLE : toggle), td, 0, 0);
488 break;
489 case PIPE_ISOCHRONOUS:
490 for (i = 0; i < urb->number_of_packets; i++) {
491 td = admhcd_td_fill(ADMHCD_TD_ISO |
492 ((urb->start_frame + i) & 0xffff), td,
493 data + urb->iso_frame_desc[i].offset,
494 urb->iso_frame_desc[i].length);
495 }
496 break;
497 }
498 urb->hcpriv = ed;
499 admhcd_ed_start(ahcd, ed);
500 out:
501 admhcd_unlock(ahcd);
502 return ret;
503 }
504
505 static int admhcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
506 {
507 struct admhcd *ahcd = hcd_to_admhcd(hcd);
508 struct admhcd_ed *ed;
509
510 admhcd_lock(ahcd);
511
512 ed = urb->hcpriv;
513 if (ed && ed->urb != urb)
514 admhcd_td_free(ed, urb);
515
516 admhcd_unlock(ahcd);
517 return 0;
518 }
519
520 static void admhcd_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
521 {
522 struct admhcd *ahcd = hcd_to_admhcd(hcd);
523 struct admhcd_ed *ed, *edt, *head;
524
525 admhcd_lock(ahcd);
526
527 head = (struct admhcd_ed *)admhcd_reg_get(ahcd, ADMHCD_REG_HOSTHEAD);
528 if (!head)
529 goto out;
530 for (ed = head; ED(ed->next) != head; ed = ED(ed->next))
531 if (ed->ep == ep)
532 break;
533 if (ed->ep != ep)
534 goto out;
535 while (ed->cur)
536 admhcd_td_free(ed, ed->cur->urb);
537 if (head == ed) {
538 if (ED(ed->next) == ed) {
539 admhcd_reg_set(ahcd, ADMHCD_REG_HOSTHEAD, 0);
540 ahcd->dma_en = 0;
541 goto out_free;
542 }
543 head = ED(ed->next);
544 for (edt = head; ED(edt->next) != head; edt = ED(edt->next));
545 edt->next = ED(ed->next);
546 admhcd_reg_set(ahcd, ADMHCD_REG_HOSTHEAD, (u32)ed->next);
547 goto out_free;
548 }
549 for (edt = head; edt->next != ed; edt = edt->next);
550 edt->next = ed->next;
551 out_free:
552 kfree(ed->real);
553 out:
554 admhcd_unlock(ahcd);
555 }
556
557 static int admhcd_get_frame_number(struct usb_hcd *hcd)
558 {
559 struct admhcd *ahcd = hcd_to_admhcd(hcd);
560
561 return admhcd_reg_get(ahcd, ADMHCD_REG_FMNUMBER) & 0x0000ffff;
562 }
563
564 static int admhcd_hub_status_data(struct usb_hcd *hcd, char *buf)
565 {
566 struct admhcd *ahcd = hcd_to_admhcd(hcd);
567 int port;
568
569 *buf = 0;
570 for (port = 0; port < ADMHCD_NUMPORTS; port++) {
571 if (admhcd_reg_get(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4) &
572 (ADMHCD_CSC | ADMHCD_PESC | ADMHCD_PSSC | ADMHCD_OCIC |
573 ADMHCD_PRSC))
574 *buf |= (1 << (port + 1));
575 }
576 return !!*buf;
577 }
578
579 static __u8 root_hub_hub_des[] = {
580 0x09, /* __u8 bLength; */
581 0x29, /* __u8 bDescriptorType; Hub-descriptor */
582 0x02, /* __u8 bNbrPorts; */
583 0x0a, 0x00, /* __u16 wHubCharacteristics; */
584 0x01, /* __u8 bPwrOn2pwrGood; 2ms */
585 0x00, /* __u8 bHubContrCurrent; 0mA */
586 0x00, /* __u8 DeviceRemovable; */
587 0xff, /* __u8 PortPwrCtrlMask; */
588 };
589
590 static int admhcd_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
591 u16 wIndex, char *buf, u16 wLength)
592 {
593 struct admhcd *ahcd = hcd_to_admhcd(hcd);
594 int retval = 0, len;
595 unsigned int port = wIndex -1;
596
597 switch (typeReq) {
598
599 case GetHubStatus:
600 *(__le32 *)buf = cpu_to_le32(0);
601 break;
602 case GetPortStatus:
603 if (port >= ADMHCD_NUMPORTS)
604 goto err;
605 *(__le32 *)buf = cpu_to_le32(
606 admhcd_reg_get(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4));
607 break;
608 case SetHubFeature: /* We don't implement these */
609 case ClearHubFeature:
610 switch (wValue) {
611 case C_HUB_OVER_CURRENT:
612 case C_HUB_LOCAL_POWER:
613 break;
614 default:
615 goto err;
616 }
617 case SetPortFeature:
618 if (port >= ADMHCD_NUMPORTS)
619 goto err;
620
621 switch (wValue) {
622 case USB_PORT_FEAT_SUSPEND:
623 admhcd_reg_set(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4,
624 ADMHCD_PSS);
625 break;
626 case USB_PORT_FEAT_RESET:
627 if (admhcd_reg_get(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4)
628 & ADMHCD_CCS) {
629 admhcd_reg_set(ahcd,
630 ADMHCD_REG_PORTSTATUS0 + port*4,
631 ADMHCD_PRS | ADMHCD_CSC);
632 mdelay(50);
633 admhcd_reg_set(ahcd,
634 ADMHCD_REG_PORTSTATUS0 + port*4,
635 ADMHCD_PES | ADMHCD_CSC);
636 }
637 break;
638 case USB_PORT_FEAT_POWER:
639 admhcd_reg_set(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4,
640 ADMHCD_PPS);
641 break;
642 default:
643 goto err;
644 }
645 break;
646 case ClearPortFeature:
647 if (port >= ADMHCD_NUMPORTS)
648 goto err;
649
650 switch (wValue) {
651 case USB_PORT_FEAT_ENABLE:
652 admhcd_reg_set(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4,
653 ADMHCD_CCS);
654 break;
655 case USB_PORT_FEAT_C_ENABLE:
656 admhcd_reg_set(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4,
657 ADMHCD_PESC);
658 break;
659 case USB_PORT_FEAT_SUSPEND:
660 admhcd_reg_set(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4,
661 ADMHCD_POCI);
662 break;
663 case USB_PORT_FEAT_C_SUSPEND:
664 admhcd_reg_set(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4,
665 ADMHCD_PSSC);
666 case USB_PORT_FEAT_POWER:
667 admhcd_reg_set(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4,
668 ADMHCD_LSDA);
669 break;
670 case USB_PORT_FEAT_C_CONNECTION:
671 admhcd_reg_set(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4,
672 ADMHCD_CSC);
673 break;
674 case USB_PORT_FEAT_C_OVER_CURRENT:
675 admhcd_reg_set(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4,
676 ADMHCD_OCIC);
677 break;
678 case USB_PORT_FEAT_C_RESET:
679 admhcd_reg_set(ahcd, ADMHCD_REG_PORTSTATUS0 + port*4,
680 ADMHCD_PRSC);
681 break;
682 default:
683 goto err;
684 }
685 break;
686 case GetHubDescriptor:
687 len = min_t(unsigned int, sizeof(root_hub_hub_des), wLength);
688 memcpy(buf, root_hub_hub_des, len);
689 break;
690 default:
691 err:
692 retval = -EPIPE;
693 }
694
695 return retval;
696 }
697
698 static int admhcd_start(struct usb_hcd *hcd)
699 {
700 struct admhcd *ahcd = hcd_to_admhcd(hcd);
701 unsigned long flags;
702
703 spin_lock_irqsave(&ahcd->lock, flags);
704
705 /* Initialise the HCD registers */
706 admhcd_reg_set(ahcd, ADMHCD_REG_INTENABLE, 0);
707 mdelay(10);
708
709 admhcd_reg_set(ahcd, ADMHCD_REG_CONTROL, ADMHCD_SW_RESET);
710
711 while (admhcd_reg_get(ahcd, ADMHCD_REG_CONTROL) & ADMHCD_SW_RESET)
712 mdelay(1);
713
714 /* Enable USB host mode */
715 admhcd_reg_set(ahcd, ADMHCD_REG_CONTROL, ADMHCD_HOST_EN);
716
717 /* Set host specific settings */
718 admhcd_reg_set(ahcd, ADMHCD_REG_HOSTHEAD, 0x00000000);
719 admhcd_reg_set(ahcd, ADMHCD_REG_FMINTERVAL, 0x20002edf);
720 admhcd_reg_set(ahcd, ADMHCD_REG_LSTHRESH, 0x628);
721
722 /* Set interrupts */
723 admhcd_reg_set(ahcd, ADMHCD_REG_INTENABLE,
724 ADMHCD_INT_ACT | ADMHCD_INT_FATAL | ADMHCD_INT_SW | ADMHCD_INT_TD);
725 admhcd_reg_set(ahcd, ADMHCD_REG_INTSTATUS,
726 ADMHCD_INT_ACT | ADMHCD_INT_FATAL | ADMHCD_INT_SW | ADMHCD_INT_TD);
727
728 admhcd_reg_set(ahcd, ADMHCD_REG_RHDESCR, ADMHCD_NPS | ADMHCD_LPSC);
729 admhcd_reg_set(ahcd, ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP);
730
731
732 hcd->state = HC_STATE_RUNNING;
733
734 spin_unlock_irqrestore(&ahcd->lock, flags);
735 return 0;
736 }
737
738 static int admhcd_sw_reset(struct admhcd *ahcd)
739 {
740 int retries = 15;
741 unsigned long flags;
742 int ret = 0;
743
744 spin_lock_irqsave(&ahcd->lock, flags);
745
746 admhcd_reg_set(ahcd, ADMHCD_REG_INTENABLE, 0);
747 mdelay(10);
748
749 admhcd_reg_set(ahcd, ADMHCD_REG_CONTROL, ADMHCD_SW_RESET);
750
751 while (--retries) {
752 mdelay(1);
753 if (!(admhcd_reg_get(ahcd, ADMHCD_REG_CONTROL) & ADMHCD_SW_RESET))
754 break;
755 }
756 if (!retries) {
757 printk(KERN_WARNING "%s Software reset timeout\n", hcd_name);
758 ret = -ETIME;
759 }
760 spin_unlock_irqrestore(&ahcd->lock, flags);
761 return ret;
762 }
763
764 static int admhcd_reset(struct usb_hcd *hcd)
765 {
766 struct admhcd *ahcd = hcd_to_admhcd(hcd);
767 u32 val = 0;
768 int ret, timeout = 15; /* ms */
769 unsigned long t;
770
771 ret = admhcd_sw_reset(ahcd);
772 if (ret)
773 return ret;
774
775 t = jiffies + msecs_to_jiffies(timeout);
776 while (time_before_eq(jiffies, t)) {
777 msleep(4);
778 spin_lock_irq(&ahcd->lock);
779 val = admhcd_reg_get(ahcd, ADMHCD_REG_HOSTCONTROL) & ADMHCD_OPR_ST;
780 spin_unlock_irq(&ahcd->lock);
781 if (val)
782 break;
783 }
784 if (!val) {
785 printk(KERN_WARNING "Device not ready after %dms\n", timeout);
786 ret = -ENODEV;
787 }
788 return ret;
789 }
790
791 static void admhcd_stop(struct usb_hcd *hcd)
792 {
793 struct admhcd *ahcd = hcd_to_admhcd(hcd);
794 unsigned long flags;
795 u32 val;
796
797 spin_lock_irqsave(&ahcd->lock, flags);
798 admhcd_reg_set(ahcd, ADMHCD_REG_INTENABLE, 0);
799
800 /* Set global control of power for ports */
801 val = admhcd_reg_get(ahcd, ADMHCD_REG_RHDESCR);
802 val &= (~ADMHCD_PSM | ADMHCD_LPS);
803 admhcd_reg_set(ahcd, ADMHCD_REG_RHDESCR, val);
804
805 spin_unlock_irqrestore(&ahcd->lock, flags);
806
807 /* Ask for software reset */
808 admhcd_sw_reset(ahcd);
809 }
810
811
812 static struct hc_driver adm5120_hc_driver = {
813 .description = hcd_name,
814 .product_desc = "ADM5120 HCD",
815 .hcd_priv_size = sizeof(struct admhcd),
816 .irq = adm5120hcd_irq,
817 .flags = HCD_MEMORY|HCD_USB11,
818 .urb_enqueue = admhcd_urb_enqueue,
819 .urb_dequeue = admhcd_urb_dequeue,
820 .endpoint_disable = admhcd_endpoint_disable,
821 .get_frame_number = admhcd_get_frame_number,
822 .hub_status_data = admhcd_hub_status_data,
823 .hub_control = admhcd_hub_control,
824 .start = admhcd_start,
825 .stop = admhcd_stop,
826 .reset = admhcd_reset,
827 };
828
829 #define resource_len(r) (((r)->end - (r)->start) + 1)
830
831 static int __init adm5120hcd_probe(struct platform_device *pdev)
832 {
833 struct usb_hcd *hcd;
834 struct admhcd *ahcd;
835 struct resource *data;
836 void __iomem *data_reg;
837
838 int err = 0, irq;
839
840 if (pdev->num_resources < 2) {
841 err = -ENODEV;
842 goto out;
843 }
844
845 if (pdev->dev.dma_mask) {
846 printk(KERN_DEBUG "no we won't dma\n");
847 return -EINVAL;
848 }
849
850 irq = platform_get_irq(pdev, 0);
851 data = platform_get_resource(pdev, IORESOURCE_MEM, 0);
852
853 if (!data || irq < 0) {
854 err = -ENODEV;
855 goto out;
856 }
857
858 if (!request_mem_region(data->start, 2, hcd_name)) {
859 err = -EBUSY;
860 goto out_unmap;
861 }
862
863 data_reg = ioremap(data->start, resource_len(data));
864 if (data_reg == NULL) {
865 err = -ENOMEM;
866 goto out_mem;
867 }
868
869 hcd = usb_create_hcd(&adm5120_hc_driver, &pdev->dev, pdev->dev.bus_id);
870 if (!hcd)
871 goto out_mem;
872
873 hcd->rsrc_start = data->start;
874 hcd->rsrc_len = resource_len(data);
875 hcd->regs = (u32)data_reg;
876 ahcd = hcd_to_admhcd(hcd);
877
878 spin_lock_init(&ahcd->lock);
879 INIT_LIST_HEAD(&ahcd->async);
880
881 ahcd->data_reg = data_reg;
882 ahcd->base = (u32)data_reg;
883
884 hcd->product_desc = "ADM5120 HCD";
885
886 err = usb_add_hcd(hcd, irq, IRQF_DISABLED);
887 if (err)
888 goto out_dev;
889
890 return 0;
891
892 out_dev:
893 usb_put_hcd(hcd);
894 out_unmap:
895 iounmap(data_reg);
896 out_mem:
897 release_mem_region(pdev->resource[0].start, pdev->resource[0].end - pdev->resource[0].start +1);
898 out:
899 return err;
900 }
901
902 static int __init_or_module adm5120hcd_remove(struct platform_device *pdev)
903 {
904 struct usb_hcd *hcd = platform_get_drvdata(pdev);
905 struct admhcd *ahcd;
906
907 if (!hcd)
908 return 0;
909 ahcd = hcd_to_admhcd(hcd);
910 usb_remove_hcd(hcd);
911
912 usb_put_hcd(hcd);
913 return 0;
914 }
915
916 static struct platform_driver adm5120hcd_driver = {
917 .probe = adm5120hcd_probe,
918 .remove = adm5120hcd_remove,
919 .driver = {
920 .name = "adm5120-usbc",
921 .owner = THIS_MODULE,
922 },
923 };
924
925 static int __init adm5120hcd_init(void)
926 {
927 int ret;
928
929 if (usb_disabled()) {
930 printk(KERN_DEBUG PFX "USB support is disabled\n");
931 return -ENODEV;
932 }
933
934 if (mips_machgroup != MACH_GROUP_ADM5120) {
935 printk(KERN_DEBUG PFX "unsupported machine group\n");
936 return -ENODEV;
937 }
938
939 ret = platform_driver_register(&adm5120hcd_driver);
940 if (ret == 0)
941 printk(KERN_INFO PFX "registered\n");
942
943 return ret;
944 }
945
946 static void __exit adm5120hcd_exit(void)
947 {
948 platform_driver_unregister(&adm5120hcd_driver);
949 }
950
951 module_init(adm5120hcd_init);
952 module_exit(adm5120hcd_exit);
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