target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-eth.c

   1 /*
   2  *  Atheros AP91 reference board ethernet initialization
   3  *
   4  *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #include "devices.h"
  12 #include "dev-dsa.h"
  13 #include "dev-ap91-eth.h"
  14
  15 static struct dsa_chip_data ap91_dsa_chip = {
  16         .port_names[0]  = "cpu",
  17         .port_names[1]  = "lan1",
  18         .port_names[2]  = "lan2",
  19         .port_names[3]  = "lan3",
  20         .port_names[4]  = "lan4",
  21 };
  22
  23 static struct dsa_platform_data ap91_dsa_data = {
  24         .nr_chips       = 1,
  25         .chip           = &ap91_dsa_chip,
  26 };
  27
  28 static void ap91_eth_set_port_name(unsigned port, const char *name)
  29 {
  30         if (port < 1 || port > 5)
  31                 return;
  32
  33         if (name)
  34                 ap91_dsa_chip.port_names[port] = (char *) name;
  35 }
  36
  37 void __init ap91_eth_init(u8 *mac_addr, const char *port_names[])
  38 {
  39         if (mac_addr)
  40                 ar71xx_set_mac_base(mac_addr);
  41
  42         if (port_names) {
  43                 int i;
  44
  45                 for (i = 0; i < AP91_ETH_NUM_PORT_NAMES; i++)
  46                         ap91_eth_set_port_name(i + 1, port_names[i]);
  47         }
  48
  49         /* WAN port */
  50         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  51         ar71xx_eth0_data.phy_mask = 0x0;
  52         ar71xx_eth0_data.speed = SPEED_100;
  53         ar71xx_eth0_data.duplex = DUPLEX_FULL;
  54         ar71xx_eth0_data.fifo_cfg1 = 0x0fff0000;
  55         ar71xx_eth0_data.fifo_cfg2 = 0x00001fff;
  56         ar71xx_eth0_data.fifo_cfg3 = 0x008001ff;
  57
  58         /* LAN ports */
  59         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  60         ar71xx_eth1_data.phy_mask = 0x0;
  61         ar71xx_eth1_data.speed = SPEED_1000;
  62         ar71xx_eth1_data.duplex = DUPLEX_FULL;
  63         ar71xx_eth1_data.fifo_cfg1 = 0x0fff0000;
  64         ar71xx_eth1_data.fifo_cfg2 = 0x00001fff;
  65         ar71xx_eth1_data.fifo_cfg3 = 0x008001ff;
  66
  67         ar71xx_add_device_mdio(0x0);
  68         ar71xx_add_device_eth(1);
  69         ar71xx_add_device_eth(0);
  70
  71         ar71xx_add_device_dsa(1, &ap91_dsa_data);
  72 }