target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/bootmem.h>
  21
  22 #include <asm/bootinfo.h>
  23 #include <asm/traps.h>
  24 #include <asm/time.h>           /* for mips_hpt_frequency */
  25 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  26 #include <asm/mips_machine.h>
  27
  28 #include <asm/mach-ar71xx/ar71xx.h>
  29 #include <asm/mach-ar71xx/pci.h>
  30 #include <asm/mach-ar71xx/platform.h>
  31
  32 #define AR71XX_SYS_TYPE_LEN     64
  33 #define AR71XX_BASE_FREQ        40000000
  34 #define AR91XX_BASE_FREQ        5000000
  35
  36 #define AR71XX_MEM_SIZE_MIN     0x0200000
  37 #define AR71XX_MEM_SIZE_MAX     0x8000000
  38
  39 unsigned long ar71xx_mach_type;
  40
  41 u32 ar71xx_cpu_freq;
  42 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  43
  44 u32 ar71xx_ahb_freq;
  45 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  46
  47 u32 ar71xx_ddr_freq;
  48 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  49
  50 enum ar71xx_soc_type ar71xx_soc;
  51 EXPORT_SYMBOL_GPL(ar71xx_soc);
  52
  53 int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
  54                              struct ar71xx_pci_irq *map) __initdata;
  55
  56 int (*ar71xx_pci_be_handler)(int is_fixup);
  57
  58 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  59
  60 static void ar71xx_restart(char *command)
  61 {
  62         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  63         for (;;)
  64                 if (cpu_wait)
  65                         cpu_wait();
  66 }
  67
  68 static void ar71xx_halt(void)
  69 {
  70         while (1)
  71                 cpu_wait();
  72 }
  73
  74 static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
  75 {
  76         int err = 0;
  77
  78         if (ar71xx_pci_be_handler)
  79                 err = ar71xx_pci_be_handler(is_fixup);
  80
  81         return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
  82 }
  83
  84 int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
  85 {
  86         if (!ar71xx_pci_bios_init)
  87                 return 0;
  88
  89         return ar71xx_pci_bios_init(nr_irqs, map);
  90 }
  91
  92 static void __init ar71xx_detect_mem_size(void)
  93 {
  94         unsigned long size;
  95
  96         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  97              size <<= 1 ) {
  98                 if (!memcmp(ar71xx_detect_mem_size,
  99                             ar71xx_detect_mem_size + size, 1024))
 100                         break;
 101         }
 102
 103         add_memory_region(0, size, BOOT_MEM_RAM);
 104 }
 105
 106 static void __init ar71xx_detect_sys_type(void)
 107 {
 108         char *chip;
 109         u32 id;
 110         u32 rev;
 111
 112         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & REV_ID_MASK;
 113         rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
 114
 115         switch (id & REV_ID_CHIP_MASK) {
 116         case REV_ID_CHIP_AR7130:
 117                 ar71xx_soc = AR71XX_SOC_AR7130;
 118                 chip = "7130";
 119                 break;
 120
 121         case REV_ID_CHIP_AR7141:
 122                 ar71xx_soc = AR71XX_SOC_AR7141;
 123                 chip = "7141";
 124                 break;
 125
 126         case REV_ID_CHIP_AR7161:
 127                 ar71xx_soc = AR71XX_SOC_AR7161;
 128                 chip = "7161";
 129                 break;
 130
 131         case REV_ID_CHIP_AR9130:
 132                 ar71xx_soc = AR71XX_SOC_AR9130;
 133                 chip = "9130";
 134                 break;
 135
 136         case REV_ID_CHIP_AR9132:
 137                 ar71xx_soc = AR71XX_SOC_AR9132;
 138                 chip = "9132";
 139                 break;
 140
 141         default:
 142                 panic("ar71xx: unknown chip id:0x%02x\n", id);
 143         }
 144
 145         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
 146                 chip, rev, id);
 147 }
 148
 149 static void __init ar91xx_detect_sys_frequency(void)
 150 {
 151         u32 pll;
 152         u32 freq;
 153         u32 div;
 154
 155         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 156
 157         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 158         freq = div * AR91XX_BASE_FREQ;
 159
 160         ar71xx_cpu_freq = freq;
 161
 162         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 163         ar71xx_ddr_freq = freq / div;
 164
 165         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 166         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 167 }
 168
 169 static void __init ar71xx_detect_sys_frequency(void)
 170 {
 171         u32 pll;
 172         u32 freq;
 173         u32 div;
 174
 175         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 176
 177         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 178         freq = div * AR71XX_BASE_FREQ;
 179
 180         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 181         ar71xx_cpu_freq = freq / div;
 182
 183         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 184         ar71xx_ddr_freq = freq / div;
 185
 186         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 187         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 188 }
 189
 190 static void __init detect_sys_frequency(void)
 191 {
 192         switch (ar71xx_soc) {
 193         case AR71XX_SOC_AR7130:
 194         case AR71XX_SOC_AR7141:
 195         case AR71XX_SOC_AR7161:
 196                 ar71xx_detect_sys_frequency();
 197                 break;
 198
 199         case AR71XX_SOC_AR9130:
 200         case AR71XX_SOC_AR9132:
 201                 ar91xx_detect_sys_frequency();
 202                 break;
 203
 204         default:
 205                 BUG();
 206         }
 207 }
 208
 209 #ifdef CONFIG_AR71XX_EARLY_SERIAL
 210 static void __init ar71xx_early_serial_setup(void)
 211 {
 212         struct uart_port p;
 213
 214         memset(&p, 0, sizeof(p));
 215
 216         p.flags         = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
 217         p.iotype        = UPIO_MEM32;
 218         p.uartclk       = ar71xx_ahb_freq;
 219         p.irq           = AR71XX_MISC_IRQ_UART;
 220         p.regshift      = 2;
 221         p.mapbase       = AR71XX_UART_BASE;
 222
 223         early_serial_setup(&p);
 224 }
 225 #else
 226 static inline void ar71xx_early_serial_setup(void) {};
 227 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
 228
 229 const char *get_system_type(void)
 230 {
 231         return ar71xx_sys_type;
 232 }
 233
 234 unsigned int __cpuinit get_c0_compare_irq(void)
 235 {
 236         return CP0_LEGACY_COMPARE_IRQ;
 237 }
 238
 239 void __init plat_mem_setup(void)
 240 {
 241         set_io_port_base(KSEG1);
 242
 243         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 244                                                 AR71XX_DDR_CTRL_SIZE);
 245
 246         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 247                                                 AR71XX_PLL_SIZE);
 248
 249         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 250                                                 AR71XX_RESET_SIZE);
 251
 252         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 253
 254         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 255                                                 AR71XX_USB_CTRL_SIZE);
 256
 257         ar71xx_detect_mem_size();
 258         ar71xx_detect_sys_type();
 259         detect_sys_frequency();
 260
 261         printk(KERN_INFO
 262                 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
 263                 ar71xx_sys_type,
 264                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 265                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 266                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
 267
 268         _machine_restart = ar71xx_restart;
 269         _machine_halt = ar71xx_halt;
 270         pm_power_off = ar71xx_halt;
 271
 272         board_be_handler = ar71xx_be_handler;
 273
 274         ar71xx_early_serial_setup();
 275 }
 276
 277 void __init plat_time_init(void)
 278 {
 279         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 280 }
 281
 282 static int __init ar71xx_machine_setup(void)
 283 {
 284         ar71xx_gpio_init();
 285
 286         ar71xx_add_device_uart();
 287         ar71xx_add_device_wdt();
 288
 289         mips_machine_setup(ar71xx_mach_type);
 290         return 0;
 291 }
 292
 293 arch_initcall(ar71xx_machine_setup);