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[openwrt/staging/florian.git] / target / linux / atheros / patches-3.10 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -138,6 +138,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -838,6 +851,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR5312/AR2312 WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,261 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <linux/io.h>
110 +#include <asm/irq_cpu.h>
111 +#include <asm/reboot.h>
112 +
113 +#include <ar231x_platform.h>
114 +#include "devices.h"
115 +#include "ar5312.h"
116 +#include "ar2315.h"
117 +
118 +void (*ar231x_irq_dispatch)(void);
119 +
120 +static inline bool
121 +check_radio_magic(u8 *addr)
122 +{
123 + addr += 0x7a; /* offset for flash magic */
124 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
125 + return 1;
126 +
127 + return 0;
128 +}
129 +
130 +static inline bool
131 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
132 +{
133 + /* config magic found */
134 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
135 + return 1;
136 +
137 + if (!broken)
138 + return 0;
139 +
140 + if (check_radio_magic(addr + 0xf8))
141 + ar231x_board.radio = addr + 0xf8;
142 + if ((addr < flash_limit + 0x10000) &&
143 + check_radio_magic(addr + 0x10000))
144 + ar231x_board.radio = addr + 0x10000;
145 +
146 + if (ar231x_board.radio) {
147 + /* broken board data detected, use radio data to find the
148 + * offset, user will fix this */
149 + return 1;
150 + }
151 + return 0;
152 +}
153 +
154 +static u8 *
155 +find_board_config(u8 *flash_limit, bool broken)
156 +{
157 + u8 *addr;
158 + int found = 0;
159 +
160 + for (addr = flash_limit - 0x1000;
161 + addr >= flash_limit - 0x30000;
162 + addr -= 0x1000) {
163 +
164 + if (check_board_data(flash_limit, addr, broken)) {
165 + found = 1;
166 + break;
167 + }
168 + }
169 +
170 + if (!found)
171 + addr = NULL;
172 +
173 + return addr;
174 +}
175 +
176 +static u8 *
177 +find_radio_config(u8 *flash_limit, u8 *board_config)
178 +{
179 + int found;
180 + u8 *radio_config;
181 +
182 + /*
183 + * Now find the start of Radio Configuration data, using heuristics:
184 + * Search forward from Board Configuration data by 0x1000 bytes
185 + * at a time until we find non-0xffffffff.
186 + */
187 + found = 0;
188 + for (radio_config = board_config + 0x1000;
189 + (radio_config < flash_limit);
190 + radio_config += 0x1000) {
191 + if ((*(u32 *)radio_config != 0xffffffff) &&
192 + check_radio_magic(radio_config)) {
193 + found = 1;
194 + break;
195 + }
196 + }
197 +
198 + /* AR2316 relocates radio config to new location */
199 + if (!found) {
200 + for (radio_config = board_config + 0xf8;
201 + (radio_config < flash_limit - 0x1000 + 0xf8);
202 + radio_config += 0x1000) {
203 + if ((*(u32 *)radio_config != 0xffffffff) &&
204 + check_radio_magic(radio_config)) {
205 + found = 1;
206 + break;
207 + }
208 + }
209 + }
210 +
211 + if (!found) {
212 + pr_warn("WARNING: Could not find Radio Configuration data\n");
213 + radio_config = 0;
214 + }
215 +
216 + return radio_config;
217 +}
218 +
219 +int __init
220 +ar231x_find_config(u8 *flash_limit)
221 +{
222 + struct ar231x_boarddata *config;
223 + unsigned int rcfg_size;
224 + int broken_boarddata = 0;
225 + u8 *bcfg, *rcfg;
226 + u8 *board_data;
227 + u8 *radio_data;
228 + u8 *mac_addr;
229 + u32 offset;
230 +
231 + ar231x_board.config = NULL;
232 + ar231x_board.radio = NULL;
233 + /* Copy the board and radio data to RAM, because accessing the mapped
234 + * memory of the flash directly after booting is not safe */
235 +
236 + /* Try to find valid board and radio data */
237 + bcfg = find_board_config(flash_limit, false);
238 +
239 + /* If that fails, try to at least find valid radio data */
240 + if (!bcfg) {
241 + bcfg = find_board_config(flash_limit, true);
242 + broken_boarddata = 1;
243 + }
244 +
245 + if (!bcfg) {
246 + pr_warn("WARNING: No board configuration data found!\n");
247 + return -ENODEV;
248 + }
249 +
250 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
251 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
252 + memcpy(board_data, bcfg, 0x100);
253 + if (broken_boarddata) {
254 + pr_warn("WARNING: broken board data detected\n");
255 + config = ar231x_board.config;
256 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
257 + pr_info("Fixing up empty mac addresses\n");
258 + config->reset_config_gpio = 0xffff;
259 + config->sys_led_gpio = 0xffff;
260 + random_ether_addr(config->wlan0_mac);
261 + config->wlan0_mac[0] &= ~0x06;
262 + random_ether_addr(config->enet0_mac);
263 + random_ether_addr(config->enet1_mac);
264 + }
265 + }
266 +
267 +
268 + /* Radio config starts 0x100 bytes after board config, regardless
269 + * of what the physical layout on the flash chip looks like */
270 +
271 + if (ar231x_board.radio)
272 + rcfg = (u8 *)ar231x_board.radio;
273 + else
274 + rcfg = find_radio_config(flash_limit, bcfg);
275 +
276 + if (!rcfg)
277 + return -ENODEV;
278 +
279 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
280 + ar231x_board.radio = radio_data;
281 + offset = radio_data - board_data;
282 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
283 + offset);
284 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
285 + memcpy(radio_data, rcfg, rcfg_size);
286 +
287 + mac_addr = &radio_data[0x1d * 2];
288 + if (is_broadcast_ether_addr(mac_addr)) {
289 + pr_info("Radio MAC is blank; using board-data\n");
290 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
291 + }
292 +
293 + return 0;
294 +}
295 +
296 +static void
297 +ar231x_halt(void)
298 +{
299 + local_irq_disable();
300 + while (1)
301 + ;
302 +}
303 +
304 +void __init
305 +plat_mem_setup(void)
306 +{
307 + _machine_halt = ar231x_halt;
308 + pm_power_off = ar231x_halt;
309 +
310 + ar5312_plat_setup();
311 + ar2315_plat_setup();
312 +
313 + /* Disable data watchpoints */
314 + write_c0_watchlo0(0);
315 +}
316 +
317 +
318 +asmlinkage void
319 +plat_irq_dispatch(void)
320 +{
321 + ar231x_irq_dispatch();
322 +}
323 +
324 +void __init
325 +plat_time_init(void)
326 +{
327 + ar5312_time_init();
328 + ar2315_time_init();
329 +}
330 +
331 +unsigned int __cpuinit
332 +get_c0_compare_int(void)
333 +{
334 + return CP0_LEGACY_COMPARE_IRQ;
335 +}
336 +
337 +void __init
338 +arch_init_irq(void)
339 +{
340 + clear_c0_status(ST0_IM);
341 + mips_cpu_irq_init();
342 +
343 + /* Initialize interrupt controllers */
344 + ar5312_irq_init();
345 + ar2315_irq_init();
346 +}
347 +
348 +
349 --- /dev/null
350 +++ b/arch/mips/ar231x/prom.c
351 @@ -0,0 +1,37 @@
352 +/*
353 + * This file is subject to the terms and conditions of the GNU General Public
354 + * License. See the file "COPYING" in the main directory of this archive
355 + * for more details.
356 + *
357 + * Copyright MontaVista Software Inc
358 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
359 + * Copyright (C) 2006 FON Technology, SL.
360 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
361 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
362 + */
363 +
364 +/*
365 + * Prom setup file for ar531x
366 + */
367 +
368 +#include <linux/init.h>
369 +#include <generated/autoconf.h>
370 +#include <linux/kernel.h>
371 +#include <linux/string.h>
372 +#include <linux/mm.h>
373 +#include <linux/bootmem.h>
374 +
375 +#include <asm/bootinfo.h>
376 +#include <asm/addrspace.h>
377 +#include "ar5312.h"
378 +#include "ar2315.h"
379 +
380 +void __init prom_init(void)
381 +{
382 + ar5312_prom_init();
383 + ar2315_prom_init();
384 +}
385 +
386 +void __init prom_free_prom_memory(void)
387 +{
388 +}
389 --- /dev/null
390 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
391 @@ -0,0 +1,84 @@
392 +#ifndef __AR531X_PLATFORM_H
393 +#define __AR531X_PLATFORM_H
394 +
395 +/*
396 + * This is board-specific data that is stored in a "fixed" location in flash.
397 + * It is shared across operating systems, so it should not be changed lightly.
398 + * The main reason we need it is in order to extract the ethernet MAC
399 + * address(es).
400 + */
401 +struct ar231x_boarddata {
402 + u32 magic; /* board data is valid */
403 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
404 + u16 cksum; /* checksum (starting with BD_REV 2) */
405 + u16 rev; /* revision of this struct */
406 +#define BD_REV 4
407 + char board_name[64]; /* Name of board */
408 + u16 major; /* Board major number */
409 + u16 minor; /* Board minor number */
410 + u32 flags; /* Board configuration */
411 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
412 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
413 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
414 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
415 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
416 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
417 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
418 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
419 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
420 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
421 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
422 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
423 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
424 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
425 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
426 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
427 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
428 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
429 + u16 reset_config_gpio; /* Reset factory GPIO pin */
430 + u16 sys_led_gpio; /* System LED GPIO pin */
431 +
432 + u32 cpu_freq; /* CPU core frequency in Hz */
433 + u32 sys_freq; /* System frequency in Hz */
434 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
435 +
436 + u8 wlan0_mac[6];
437 + u8 enet0_mac[6];
438 + u8 enet1_mac[6];
439 +
440 + u16 pci_id; /* Pseudo PCIID for common code */
441 + u16 mem_cap; /* cap bank1 in MB */
442 +
443 + /* version 3 */
444 + u8 wlan1_mac[6]; /* (ar5212) */
445 +};
446 +
447 +#define BOARD_CONFIG_BUFSZ 0x1000
448 +
449 +/*
450 + * Platform device information for the Wireless MAC
451 + */
452 +struct ar231x_board_config {
453 + u16 devid;
454 +
455 + /* board config data */
456 + struct ar231x_boarddata *config;
457 +
458 + /* radio calibration data */
459 + const char *radio;
460 +};
461 +
462 +/*
463 + * Platform device information for the Ethernet MAC
464 + */
465 +struct ar231x_eth {
466 + void (*reset_set)(u32);
467 + void (*reset_clear)(u32);
468 + u32 reset_mac;
469 + u32 reset_phy;
470 + u32 phy_base;
471 + struct ar231x_board_config *config;
472 + char *macaddr;
473 +};
474 +
475 +#endif /* __AR531X_PLATFORM_H */
476 --- /dev/null
477 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
478 @@ -0,0 +1,84 @@
479 +/*
480 + * Atheros SoC specific CPU feature overrides
481 + *
482 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
483 + *
484 + * This file was derived from: include/asm-mips/cpu-features.h
485 + * Copyright (C) 2003, 2004 Ralf Baechle
486 + * Copyright (C) 2004 Maciej W. Rozycki
487 + *
488 + * This program is free software; you can redistribute it and/or modify it
489 + * under the terms of the GNU General Public License version 2 as published
490 + * by the Free Software Foundation.
491 + *
492 + */
493 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
494 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
495 +
496 +/*
497 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
498 + */
499 +#define cpu_has_tlb 1
500 +#define cpu_has_4kex 1
501 +#define cpu_has_3k_cache 0
502 +#define cpu_has_4k_cache 1
503 +#define cpu_has_tx39_cache 0
504 +#define cpu_has_sb1_cache 0
505 +#define cpu_has_fpu 0
506 +#define cpu_has_32fpr 0
507 +#define cpu_has_counter 1
508 +/* #define cpu_has_watch ? */
509 +/* #define cpu_has_divec ? */
510 +/* #define cpu_has_vce ? */
511 +/* #define cpu_has_cache_cdex_p ? */
512 +/* #define cpu_has_cache_cdex_s ? */
513 +/* #define cpu_has_prefetch ? */
514 +/* #define cpu_has_mcheck ? */
515 +#define cpu_has_ejtag 1
516 +
517 +#if !defined(CONFIG_ATHEROS_AR5312)
518 +# define cpu_has_llsc 1
519 +#else
520 +/*
521 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
522 + * ll/sc instructions.
523 + */
524 +# define cpu_has_llsc 0
525 +#endif
526 +
527 +#define cpu_has_mips16 0
528 +#define cpu_has_mdmx 0
529 +#define cpu_has_mips3d 0
530 +#define cpu_has_smartmips 0
531 +
532 +/* #define cpu_has_vtag_icache ? */
533 +/* #define cpu_has_dc_aliases ? */
534 +/* #define cpu_has_ic_fills_f_dc ? */
535 +/* #define cpu_has_pindexed_dcache ? */
536 +
537 +/* #define cpu_icache_snoops_remote_store ? */
538 +
539 +#define cpu_has_mips32r1 1
540 +
541 +#if !defined(CONFIG_ATHEROS_AR5312)
542 +# define cpu_has_mips32r2 1
543 +#endif
544 +
545 +#define cpu_has_mips64r1 0
546 +#define cpu_has_mips64r2 0
547 +
548 +#define cpu_has_dsp 0
549 +#define cpu_has_mipsmt 0
550 +
551 +/* #define cpu_has_nofpuex ? */
552 +#define cpu_has_64bits 0
553 +#define cpu_has_64bit_zero_reg 0
554 +#define cpu_has_64bit_gp_regs 0
555 +#define cpu_has_64bit_addresses 0
556 +
557 +/* #define cpu_has_inclusive_pcaches ? */
558 +
559 +/* #define cpu_dcache_line_size() ? */
560 +/* #define cpu_icache_line_size() ? */
561 +
562 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
563 --- /dev/null
564 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
565 @@ -0,0 +1,79 @@
566 +/*
567 + * This file is subject to the terms and conditions of the GNU General Public
568 + * License. See the file "COPYING" in the main directory of this archive
569 + * for more details.
570 + *
571 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
572 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
573 + *
574 + */
575 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
576 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
577 +
578 +#define PCI_DMA_OFFSET 0x20000000
579 +
580 +#include <linux/device.h>
581 +
582 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
583 +{
584 +#ifdef CONFIG_PCI
585 + extern struct bus_type pci_bus_type;
586 +
587 + if (dev && dev->bus == &pci_bus_type)
588 + return PCI_DMA_OFFSET;
589 + else
590 +#endif
591 + return 0;
592 +}
593 +
594 +static inline dma_addr_t
595 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
596 +{
597 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
598 +}
599 +
600 +static inline dma_addr_t
601 +plat_map_dma_mem_page(struct device *dev, struct page *page)
602 +{
603 + return page_to_phys(page) + ar231x_dev_offset(dev);
604 +}
605 +
606 +static inline unsigned long
607 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
608 +{
609 + return dma_addr - ar231x_dev_offset(dev);
610 +}
611 +
612 +static inline void
613 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
614 + enum dma_data_direction direction)
615 +{
616 +}
617 +
618 +static inline int plat_dma_supported(struct device *dev, u64 mask)
619 +{
620 + return 1;
621 +}
622 +
623 +static inline void plat_extra_sync_for_device(struct device *dev)
624 +{
625 + return;
626 +}
627 +
628 +static inline int plat_dma_mapping_error(struct device *dev,
629 + dma_addr_t dma_addr)
630 +{
631 + return 0;
632 +}
633 +
634 +static inline int plat_device_is_coherent(struct device *dev)
635 +{
636 +#ifdef CONFIG_DMA_COHERENT
637 + return 1;
638 +#endif
639 +#ifdef CONFIG_DMA_NONCOHERENT
640 + return 0;
641 +#endif
642 +}
643 +
644 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
645 --- /dev/null
646 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
647 @@ -0,0 +1,30 @@
648 +#ifndef _ATHEROS_GPIO_H_
649 +#define _ATHEROS_GPIO_H_
650 +
651 +#include <ar231x.h>
652 +
653 +#define gpio_get_value __gpio_get_value
654 +#define gpio_set_value __gpio_set_value
655 +#define gpio_cansleep __gpio_cansleep
656 +
657 +/*
658 + * Wrappers for the generic GPIO layer
659 + */
660 +
661 +/* not sure if these are used? */
662 +
663 +/* Returns IRQ to attach for gpio. Unchecked function */
664 +static inline int gpio_to_irq(unsigned gpio)
665 +{
666 + return AR531X_GPIO_IRQ(gpio);
667 +}
668 +
669 +/* Returns gpio for IRQ attached. Unchecked function */
670 +static inline int irq_to_gpio(unsigned irq)
671 +{
672 + return irq - AR531X_GPIO_IRQ(0);
673 +}
674 +
675 +#include <asm-generic/gpio.h> /* cansleep wrappers */
676 +
677 +#endif
678 --- /dev/null
679 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
680 @@ -0,0 +1,6 @@
681 +#ifndef __AR531X_RESET_H
682 +#define __AR531X_RESET_H
683 +
684 +void ar531x_disable_reset_button(void);
685 +
686 +#endif /* __AR531X_RESET_H */
687 --- /dev/null
688 +++ b/arch/mips/include/asm/mach-ar231x/war.h
689 @@ -0,0 +1,25 @@
690 +/*
691 + * This file is subject to the terms and conditions of the GNU General Public
692 + * License. See the file "COPYING" in the main directory of this archive
693 + * for more details.
694 + *
695 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
696 + */
697 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
698 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
699 +
700 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
701 +#define R4600_V1_HIT_CACHEOP_WAR 0
702 +#define R4600_V2_HIT_CACHEOP_WAR 0
703 +#define R5432_CP0_INTERRUPT_WAR 0
704 +#define BCM1250_M3_WAR 0
705 +#define SIBYTE_1956_WAR 0
706 +#define MIPS4K_ICACHE_REFILL_WAR 0
707 +#define MIPS_CACHE_SYNC_WAR 0
708 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
709 +#define RM9000_CDEX_SMP_WAR 0
710 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
711 +#define R10000_LLSC_WAR 0
712 +#define MIPS34K_MISSED_ITLB_WAR 0
713 +
714 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
715 --- /dev/null
716 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
717 @@ -0,0 +1,614 @@
718 +/*
719 + * Register definitions for AR2315+
720 + *
721 + * This file is subject to the terms and conditions of the GNU General Public
722 + * License. See the file "COPYING" in the main directory of this archive
723 + * for more details.
724 + *
725 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
726 + * Copyright (C) 2006 FON Technology, SL.
727 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
728 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
729 + */
730 +
731 +#ifndef __AR2315_REG_H
732 +#define __AR2315_REG_H
733 +
734 +/*
735 + * IRQs
736 + */
737 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
738 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
739 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
740 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
741 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
742 +
743 +
744 +/*
745 + * Miscellaneous interrupts, which share IP2.
746 + */
747 +#define AR2315_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
748 +#define AR2315_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+1)
749 +#define AR2315_MISC_IRQ_I2C_RSVD (AR531X_MISC_IRQ_BASE+2)
750 +#define AR2315_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+3)
751 +#define AR2315_MISC_IRQ_AHB (AR531X_MISC_IRQ_BASE+4)
752 +#define AR2315_MISC_IRQ_APB (AR531X_MISC_IRQ_BASE+5)
753 +#define AR2315_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+6)
754 +#define AR2315_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+7)
755 +#define AR2315_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+8)
756 +#define AR2315_MISC_IRQ_IR_RSVD (AR531X_MISC_IRQ_BASE+9)
757 +#define AR2315_MISC_IRQ_COUNT 10
758 +
759 +
760 +/*
761 + * Address map
762 + */
763 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
764 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
765 +#define AR2315_PCI 0x10100000 /* PCI MMR */
766 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
767 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
768 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
769 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
770 +#define AR2315_UART0 0x11100003 /* UART MMR */
771 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
772 +#define AR2315_PCIEXT 0x80000000 /* pci external */
773 +
774 +/*
775 + * Reset Register
776 + */
777 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
778 +
779 +#define AR2315_RESET_COLD_AHB 0x00000001
780 +#define AR2315_RESET_COLD_APB 0x00000002
781 +#define AR2315_RESET_COLD_CPU 0x00000004
782 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
783 +#define AR2315_RESET_SYSTEM \
784 + (RESET_COLD_CPU |\
785 + RESET_COLD_APB |\
786 + RESET_COLD_AHB) /* full system */
787 +#define AR2317_RESET_SYSTEM 0x00000010
788 +
789 +
790 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
791 +
792 +/* warm reset WLAN0 MAC */
793 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
794 +/* warm reset WLAN0 BaseBand */
795 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
796 +/* warm reset MPEG-TS */
797 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
798 +/* warm reset PCI ahb/dma */
799 +#define AR2315_RESET_PCIDMA 0x00000008
800 +/* warm reset memory controller */
801 +#define AR2315_RESET_MEMCTL 0x00000010
802 +/* warm reset local bus */
803 +#define AR2315_RESET_LOCAL 0x00000020
804 +/* warm reset I2C bus */
805 +#define AR2315_RESET_I2C_RSVD 0x00000040
806 +/* warm reset SPI interface */
807 +#define AR2315_RESET_SPI 0x00000080
808 +/* warm reset UART0 */
809 +#define AR2315_RESET_UART0 0x00000100
810 +/* warm reset IR interface */
811 +#define AR2315_RESET_IR_RSVD 0x00000200
812 +/* cold reset ENET0 phy */
813 +#define AR2315_RESET_EPHY0 0x00000400
814 +/* cold reset ENET0 mac */
815 +#define AR2315_RESET_ENET0 0x00000800
816 +
817 +/*
818 + * AHB master arbitration control
819 + */
820 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
821 +
822 +/* CPU, default */
823 +#define AR2315_ARB_CPU 0x00000001
824 +/* WLAN */
825 +#define AR2315_ARB_WLAN 0x00000002
826 +/* MPEG-TS */
827 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
828 +/* LOCAL */
829 +#define AR2315_ARB_LOCAL 0x00000008
830 +/* PCI */
831 +#define AR2315_ARB_PCI 0x00000010
832 +/* Ethernet */
833 +#define AR2315_ARB_ETHERNET 0x00000020
834 +/* retry policy, debug only */
835 +#define AR2315_ARB_RETRY 0x00000100
836 +
837 +/*
838 + * Config Register
839 + */
840 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
841 +
842 +/* EC - AHB bridge endianess */
843 +#define AR2315_CONFIG_AHB 0x00000001
844 +/* WLAN byteswap */
845 +#define AR2315_CONFIG_WLAN 0x00000002
846 +/* MPEG-TS byteswap */
847 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
848 +/* PCI byteswap */
849 +#define AR2315_CONFIG_PCI 0x00000008
850 +/* Memory controller endianess */
851 +#define AR2315_CONFIG_MEMCTL 0x00000010
852 +/* Local bus byteswap */
853 +#define AR2315_CONFIG_LOCAL 0x00000020
854 +/* Ethernet byteswap */
855 +#define AR2315_CONFIG_ETHERNET 0x00000040
856 +
857 +/* CPU write buffer merge */
858 +#define AR2315_CONFIG_MERGE 0x00000200
859 +/* CPU big endian */
860 +#define AR2315_CONFIG_CPU 0x00000400
861 +#define AR2315_CONFIG_PCIAHB 0x00000800
862 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
863 +/* SPI byteswap */
864 +#define AR2315_CONFIG_SPI 0x00008000
865 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
866 +#define AR2315_CONFIG_CPU_PCI 0x00020000
867 +#define AR2315_CONFIG_CPU_MMR 0x00040000
868 +#define AR2315_CONFIG_BIG 0x00000400
869 +
870 +
871 +/*
872 + * NMI control
873 + */
874 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
875 +
876 +#define AR2315_NMI_EN 1
877 +
878 +/*
879 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
880 + */
881 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
882 +
883 +#define AR2315_REV_MAJ 0x00f0
884 +#define AR2315_REV_MAJ_S 4
885 +#define AR2315_REV_MIN 0x000f
886 +#define AR2315_REV_MIN_S 0
887 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
888 +
889 +/*
890 + * Interface Enable
891 + */
892 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
893 +
894 +#define AR2315_IF_MASK 0x00000007
895 +#define AR2315_IF_DISABLED 0
896 +#define AR2315_IF_PCI 1
897 +#define AR2315_IF_TS_LOCAL 2
898 +/* only for emulation with separate pins */
899 +#define AR2315_IF_ALL 3
900 +#define AR2315_IF_LOCAL_HOST 0x00000008
901 +#define AR2315_IF_PCI_HOST 0x00000010
902 +#define AR2315_IF_PCI_INTR 0x00000020
903 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
904 +#define AR2315_IF_PCI_CLK_INPUT 0
905 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
906 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
907 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
908 +#define AR2315_IF_PCI_CLK_SHIFT 16
909 +
910 +/*
911 + * APB Interrupt control
912 + */
913 +
914 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
915 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
916 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
917 +
918 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
919 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
920 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
921 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
922 +#define AR2315_ISR_APB 0x0010 /* APB error */
923 +#define AR2315_ISR_TIMER 0x0020 /* timer */
924 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
925 +#define AR2315_ISR_WD 0x0080 /* watchdog */
926 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
927 +
928 +#define AR2315_GISR_MISC 0x0001
929 +#define AR2315_GISR_WLAN0 0x0002
930 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
931 +#define AR2315_GISR_LOCALPCI 0x0008
932 +#define AR2315_GISR_WMACPOLL 0x0010
933 +#define AR2315_GISR_TIMER 0x0020
934 +#define AR2315_GISR_ETHERNET 0x0040
935 +
936 +/*
937 + * Interrupt routing from IO to the processor IP bits
938 + * Define our inter mask and level
939 + */
940 +#define AR2315_INTR_MISCIO SR_IBIT3
941 +#define AR2315_INTR_WLAN0 SR_IBIT4
942 +#define AR2315_INTR_ENET0 SR_IBIT5
943 +#define AR2315_INTR_LOCALPCI SR_IBIT6
944 +#define AR2315_INTR_WMACPOLL SR_IBIT7
945 +#define AR2315_INTR_COMPARE SR_IBIT8
946 +
947 +/*
948 + * Timers
949 + */
950 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
951 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
952 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
953 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
954 +
955 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
956 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
957 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
958 +
959 +/*
960 + * CPU Performance Counters
961 + */
962 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
963 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
964 +
965 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
966 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
967 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
968 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
969 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
970 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
971 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
972 +
973 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
974 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
975 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
976 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
977 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
978 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
979 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
980 +
981 +/*
982 + * AHB Error Reporting.
983 + */
984 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
985 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
986 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
987 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
988 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
989 +
990 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
991 + /* write 1 to clear all bits in ERR0 */
992 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
993 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
994 +
995 +#define AR2315_PROCERR_HMAST 0x0000000f
996 +#define AR2315_PROCERR_HMAST_DFLT 0
997 +#define AR2315_PROCERR_HMAST_WMAC 1
998 +#define AR2315_PROCERR_HMAST_ENET 2
999 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
1000 +#define AR2315_PROCERR_HMAST_LOCAL 4
1001 +#define AR2315_PROCERR_HMAST_CPU 5
1002 +#define AR2315_PROCERR_HMAST_PCITGT 6
1003 +
1004 +#define AR2315_PROCERR_HMAST_S 0
1005 +#define AR2315_PROCERR_HWRITE 0x00000010
1006 +#define AR2315_PROCERR_HSIZE 0x00000060
1007 +#define AR2315_PROCERR_HSIZE_S 5
1008 +#define AR2315_PROCERR_HTRANS 0x00000180
1009 +#define AR2315_PROCERR_HTRANS_S 7
1010 +#define AR2315_PROCERR_HBURST 0x00000e00
1011 +#define AR2315_PROCERR_HBURST_S 9
1012 +
1013 +/*
1014 + * Clock Control
1015 + */
1016 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
1017 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1018 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1019 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1020 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1021 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1022 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1023 +
1024 +/* PLLc Control fields */
1025 +#define PLLC_REF_DIV_M 0x00000003
1026 +#define PLLC_REF_DIV_S 0
1027 +#define PLLC_FDBACK_DIV_M 0x0000007C
1028 +#define PLLC_FDBACK_DIV_S 2
1029 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1030 +#define PLLC_ADD_FDBACK_DIV_S 7
1031 +#define PLLC_CLKC_DIV_M 0x0001c000
1032 +#define PLLC_CLKC_DIV_S 14
1033 +#define PLLC_CLKM_DIV_M 0x00700000
1034 +#define PLLC_CLKM_DIV_S 20
1035 +
1036 +/* CPU CLK Control fields */
1037 +#define CPUCLK_CLK_SEL_M 0x00000003
1038 +#define CPUCLK_CLK_SEL_S 0
1039 +#define CPUCLK_CLK_DIV_M 0x0000000c
1040 +#define CPUCLK_CLK_DIV_S 2
1041 +
1042 +/* AMBA CLK Control fields */
1043 +#define AMBACLK_CLK_SEL_M 0x00000003
1044 +#define AMBACLK_CLK_SEL_S 0
1045 +#define AMBACLK_CLK_DIV_M 0x0000000c
1046 +#define AMBACLK_CLK_DIV_S 2
1047 +
1048 +/*
1049 + * GPIO
1050 + */
1051 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1052 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1053 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1054 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1055 +
1056 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1057 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1058 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1059 +
1060 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1061 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1062 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1063 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1064 +
1065 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1066 + * AR5313_GPIO_INT_* macros */
1067 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1068 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1069 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1070 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1071 +
1072 +#define AR2315_RESET_GPIO 5
1073 +#define AR2315_NUM_GPIO 22
1074 +
1075 +/*
1076 + * PCI Clock Control
1077 + */
1078 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1079 +
1080 +#define AR2315_PCICLK_INPUT_M 0x3
1081 +#define AR2315_PCICLK_INPUT_S 0
1082 +
1083 +#define AR2315_PCICLK_PLLC_CLKM 0
1084 +#define AR2315_PCICLK_PLLC_CLKM1 1
1085 +#define AR2315_PCICLK_PLLC_CLKC 2
1086 +#define AR2315_PCICLK_REF_CLK 3
1087 +
1088 +#define AR2315_PCICLK_DIV_M 0xc
1089 +#define AR2315_PCICLK_DIV_S 2
1090 +
1091 +#define AR2315_PCICLK_IN_FREQ 0
1092 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1093 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1094 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1095 +
1096 +/*
1097 + * Observation Control Register
1098 + */
1099 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1100 +#define OCR_GPIO0_IRIN 0x0040
1101 +#define OCR_GPIO1_IROUT 0x0080
1102 +#define OCR_GPIO3_RXCLR 0x0200
1103 +
1104 +/*
1105 + * General Clock Control
1106 + */
1107 +
1108 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1109 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1110 +#define MISCCLK_PROCREFCLK 0x00000002
1111 +
1112 +/*
1113 + * SDRAM Controller
1114 + * - No read or write buffers are included.
1115 + */
1116 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1117 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1118 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1119 +
1120 +#define SDRAM_DATA_WIDTH_M 0x00006000
1121 +#define SDRAM_DATA_WIDTH_S 13
1122 +
1123 +#define SDRAM_COL_WIDTH_M 0x00001E00
1124 +#define SDRAM_COL_WIDTH_S 9
1125 +
1126 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1127 +#define SDRAM_ROW_WIDTH_S 5
1128 +
1129 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1130 +#define SDRAM_BANKADDR_BITS_S 3
1131 +
1132 +/*
1133 + * PCI Bus Interface Registers
1134 + */
1135 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1136 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1137 +
1138 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1139 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1140 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1141 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1142 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1143 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1144 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1145 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1146 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1147 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1148 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1149 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1150 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1151 + * disable */
1152 +
1153 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1154 +
1155 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1156 +
1157 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1158 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1159 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1160 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1161 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1162 +
1163 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1164 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1165 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1166 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1167 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1168 +
1169 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1170 +
1171 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1172 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1173 +
1174 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1175 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1176 +
1177 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1178 +
1179 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1180 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1181 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1182 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1183 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1184 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1185 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1186 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1187 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1188 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1189 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1190 +#define AR2315_PCI_EXT_INT 0x02000000
1191 +#define AR2315_PCI_ABORT_INT 0x04000000
1192 +
1193 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1194 +
1195 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1196 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1197 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1198 +
1199 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1200 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1201 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1202 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1203 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1204 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1205 +
1206 +
1207 +/*
1208 + * Local Bus Interface Registers
1209 + */
1210 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1211 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1212 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1213 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1214 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1215 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1216 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1217 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1218 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1219 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1220 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1221 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1222 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1223 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1224 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1225 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1226 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1227 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1228 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1229 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1230 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1231 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1232 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1233 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1234 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1235 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1236 +
1237 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1238 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1239 +
1240 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1241 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1242 +
1243 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1244 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1245 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1246 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1247 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1248 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1249 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1250 +#define AR2315_LBM_TIMEOUT_SHFT 7
1251 +#define AR2315_LBM_PORTMUX 0x07000000
1252 +
1253 +
1254 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1255 +
1256 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1257 +#define AR2315_LB_TXEN_0 0x01
1258 +#define AR2315_LB_TXEN_1 0x02
1259 +#define AR2315_LB_TXEN_2 0x04
1260 +#define AR2315_LB_TXEN_3 0x08
1261 +
1262 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1263 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1264 +
1265 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1266 +#define AR2315_LB_RXEN 0x01
1267 +
1268 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1269 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1270 +
1271 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1272 +#define AR2315_INT_TX_DESC 0x0001
1273 +#define AR2315_INT_TX_OK 0x0002
1274 +#define AR2315_INT_TX_ERR 0x0004
1275 +#define AR2315_INT_TX_EOF 0x0008
1276 +#define AR2315_INT_RX_DESC 0x0010
1277 +#define AR2315_INT_RX_OK 0x0020
1278 +#define AR2315_INT_RX_ERR 0x0040
1279 +#define AR2315_INT_RX_EOF 0x0080
1280 +#define AR2315_INT_TX_TRUNC 0x0100
1281 +#define AR2315_INT_TX_STARVE 0x0200
1282 +#define AR2315_INT_LB_TIMEOUT 0x0400
1283 +#define AR2315_INT_LB_ERR 0x0800
1284 +#define AR2315_INT_MBOX_WR 0x1000
1285 +#define AR2315_INT_MBOX_RD 0x2000
1286 +
1287 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1288 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1289 +
1290 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1291 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1292 +
1293 +/*
1294 + * IR Interface Registers
1295 + */
1296 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1297 +
1298 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1299 +
1300 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1301 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1302 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1303 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1304 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1305 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1306 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1307 +
1308 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1309 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1310 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1311 +
1312 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1313 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1314 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1315 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1316 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1317 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1318 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1319 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1320 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1321 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1322 +
1323 +#define HOST_PCI_DEV_ID 3
1324 +#define HOST_PCI_MBAR0 0x10000000
1325 +#define HOST_PCI_MBAR1 0x20000000
1326 +#define HOST_PCI_MBAR2 0x30000000
1327 +
1328 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1329 +#define PCI_DEVICE_MEM_SPACE 0x800000
1330 +
1331 +#endif /* __AR2315_REG_H */
1332 --- /dev/null
1333 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1334 @@ -0,0 +1,249 @@
1335 +/*
1336 + * This file is subject to the terms and conditions of the GNU General Public
1337 + * License. See the file "COPYING" in the main directory of this archive
1338 + * for more details.
1339 + *
1340 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1341 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1342 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1343 + */
1344 +
1345 +#ifndef AR5312_H
1346 +#define AR5312_H
1347 +
1348 +#include <asm/addrspace.h>
1349 +
1350 +/*
1351 + * IRQs
1352 + */
1353 +
1354 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1355 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1356 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1357 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1358 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1359 +
1360 +
1361 +/*
1362 + * Miscellaneous interrupts, which share IP6.
1363 + */
1364 +#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
1365 +#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
1366 +#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
1367 +#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
1368 +#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
1369 +#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
1370 +#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
1371 +#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
1372 +#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
1373 +#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
1374 +#define AR531X_MISC_IRQ_COUNT 10
1375 +
1376 +
1377 +/* Address Map */
1378 +#define AR531X_WLAN0 0x18000000
1379 +#define AR531X_WLAN1 0x18500000
1380 +#define AR531X_ENET0 0x18100000
1381 +#define AR531X_ENET1 0x18200000
1382 +#define AR531X_SDRAMCTL 0x18300000
1383 +#define AR531X_FLASHCTL 0x18400000
1384 +#define AR531X_APBBASE 0x1c000000
1385 +#define AR531X_FLASH 0x1e000000
1386 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1387 +
1388 +/*
1389 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1390 + * should be considered available. The AR5312 supports 2 enet MACS,
1391 + * even though many reference boards only actually use 1 of them
1392 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1393 + * The AR2312 supports 1 enet MAC.
1394 + */
1395 +#define AR531X_NUM_ENET_MAC 2
1396 +
1397 +/*
1398 + * Need these defines to determine true number of ethernet MACs
1399 + */
1400 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1401 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1402 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1403 +
1404 +/*
1405 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1406 + * should be considered available.
1407 + */
1408 +#define AR531X_NUM_WMAC 2
1409 +
1410 +/* Reset/Timer Block Address Map */
1411 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1412 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1413 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1414 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1415 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1416 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1417 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1418 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1419 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1420 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1421 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1422 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1423 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1424 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1425 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1426 +
1427 +/* AR531X_WD_CTRL register bit field definitions */
1428 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1429 +#define AR531X_WD_CTRL_NMI 0x0001
1430 +#define AR531X_WD_CTRL_RESET 0x0002
1431 +
1432 +/* AR531X_ISR register bit field definitions */
1433 +#define AR531X_ISR_NONE 0x0000
1434 +#define AR531X_ISR_TIMER 0x0001
1435 +#define AR531X_ISR_AHBPROC 0x0002
1436 +#define AR531X_ISR_AHBDMA 0x0004
1437 +#define AR531X_ISR_GPIO 0x0008
1438 +#define AR531X_ISR_UART0 0x0010
1439 +#define AR531X_ISR_UART0DMA 0x0020
1440 +#define AR531X_ISR_WD 0x0040
1441 +#define AR531X_ISR_LOCAL 0x0080
1442 +
1443 +/* AR531X_RESET register bit field definitions */
1444 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1445 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1446 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1447 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1448 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1449 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1450 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1451 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1452 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1453 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1454 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1455 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1456 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1457 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1458 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1459 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1460 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1461 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1462 +
1463 +#define AR531X_RESET_WMAC0_BITS \
1464 + (AR531X_RESET_WLAN0 |\
1465 + AR531X_RESET_WARM_WLAN0_MAC |\
1466 + AR531X_RESET_WARM_WLAN0_BB)
1467 +
1468 +#define AR531X_RESERT_WMAC1_BITS \
1469 + (AR531X_RESET_WLAN1 |\
1470 + AR531X_RESET_WARM_WLAN1_MAC |\
1471 + AR531X_RESET_WARM_WLAN1_BB)
1472 +
1473 +/* AR5312_CLOCKCTL1 register bit field definitions */
1474 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1475 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1476 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1477 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1478 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1479 +
1480 +/* Valid for AR5312 and AR2312 */
1481 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1482 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1483 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1484 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1485 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1486 +
1487 +/* Valid for AR2313 */
1488 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1489 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1490 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1491 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1492 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1493 +
1494 +
1495 +/* AR531X_ENABLE register bit field definitions */
1496 +#define AR531X_ENABLE_WLAN0 0x0001
1497 +#define AR531X_ENABLE_ENET0 0x0002
1498 +#define AR531X_ENABLE_ENET1 0x0004
1499 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1500 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1501 +#define AR531X_ENABLE_WLAN1 \
1502 + (AR531X_ENABLE_UART_AND_WLAN1_PIO |\
1503 + AR531X_ENABLE_WLAN1_DMA)
1504 +
1505 +/* AR531X_REV register bit field definitions */
1506 +#define AR531X_REV_WMAC_MAJ 0xf000
1507 +#define AR531X_REV_WMAC_MAJ_S 12
1508 +#define AR531X_REV_WMAC_MIN 0x0f00
1509 +#define AR531X_REV_WMAC_MIN_S 8
1510 +#define AR531X_REV_MAJ 0x00f0
1511 +#define AR531X_REV_MAJ_S 4
1512 +#define AR531X_REV_MIN 0x000f
1513 +#define AR531X_REV_MIN_S 0
1514 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1515 +
1516 +/* Major revision numbers, bits 7..4 of Revision ID register */
1517 +#define AR531X_REV_MAJ_AR5312 0x4
1518 +#define AR531X_REV_MAJ_AR2313 0x5
1519 +
1520 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1521 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1522 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1523 +
1524 +/* AR531X_FLASHCTL register bit field definitions */
1525 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1526 +#define FLASHCTL_IDCY_S 0
1527 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1528 +#define FLASHCTL_WST1_S 5
1529 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1530 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1531 +#define FLASHCTL_WST2_S 11
1532 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1533 +#define FLASHCTL_AC_S 16
1534 +#define FLASHCTL_AC_128K 0x00000000
1535 +#define FLASHCTL_AC_256K 0x00010000
1536 +#define FLASHCTL_AC_512K 0x00020000
1537 +#define FLASHCTL_AC_1M 0x00030000
1538 +#define FLASHCTL_AC_2M 0x00040000
1539 +#define FLASHCTL_AC_4M 0x00050000
1540 +#define FLASHCTL_AC_8M 0x00060000
1541 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1542 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1543 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1544 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1545 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1546 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1547 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1548 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1549 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1550 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1551 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1552 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1553 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1554 +
1555 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1556 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1557 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1558 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1559 +
1560 +/* ARM SDRAM Controller -- just enough to determine memory size */
1561 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1562 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1563 +#define MEM_CFG1_AC0_S 8
1564 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1565 +#define MEM_CFG1_AC1_S 12
1566 +
1567 +/* GPIO Address Map */
1568 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1569 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1570 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1571 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1572 +
1573 +/* GPIO Control Register bit field definitions */
1574 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1575 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1576 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1577 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1578 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1579 +#define AR531X_NUM_GPIO 8
1580 +
1581 +
1582 +#endif
1583 +
1584 --- /dev/null
1585 +++ b/arch/mips/ar231x/ar5312.c
1586 @@ -0,0 +1,596 @@
1587 +/*
1588 + * This file is subject to the terms and conditions of the GNU General Public
1589 + * License. See the file "COPYING" in the main directory of this archive
1590 + * for more details.
1591 + *
1592 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1593 + * Copyright (C) 2006 FON Technology, SL.
1594 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1595 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1596 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1597 + */
1598 +
1599 +/*
1600 + * Platform devices for Atheros SoCs
1601 + */
1602 +
1603 +#include <generated/autoconf.h>
1604 +#include <linux/init.h>
1605 +#include <linux/module.h>
1606 +#include <linux/types.h>
1607 +#include <linux/string.h>
1608 +#include <linux/mtd/physmap.h>
1609 +#include <linux/platform_device.h>
1610 +#include <linux/kernel.h>
1611 +#include <linux/reboot.h>
1612 +#include <linux/leds.h>
1613 +#include <linux/gpio.h>
1614 +#include <asm/bootinfo.h>
1615 +#include <asm/reboot.h>
1616 +#include <asm/time.h>
1617 +#include <linux/irq.h>
1618 +#include <linux/io.h>
1619 +
1620 +#include <ar231x_platform.h>
1621 +#include <ar5312_regs.h>
1622 +#include <ar231x.h>
1623 +#include "devices.h"
1624 +#include "ar5312.h"
1625 +
1626 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1627 +{
1628 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) &
1629 + ar231x_read_reg(AR531X_IMR);
1630 +
1631 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1632 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1633 + (void)ar231x_read_reg(AR531X_TIMER);
1634 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1635 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1636 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1637 + do_IRQ(AR531X_MISC_IRQ_UART0);
1638 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1639 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1640 + else
1641 + do_IRQ(AR531X_MISC_IRQ_NONE);
1642 +}
1643 +
1644 +static asmlinkage void
1645 +ar5312_irq_dispatch(void)
1646 +{
1647 + int pending = read_c0_status() & read_c0_cause();
1648 +
1649 + if (pending & CAUSEF_IP2)
1650 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1651 + else if (pending & CAUSEF_IP3)
1652 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1653 + else if (pending & CAUSEF_IP4)
1654 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1655 + else if (pending & CAUSEF_IP5)
1656 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1657 + else if (pending & CAUSEF_IP6)
1658 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1659 + else if (pending & CAUSEF_IP7)
1660 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1661 +}
1662 +
1663 +
1664 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1665 +static void
1666 +ar5312_misc_irq_unmask(struct irq_data *d)
1667 +{
1668 + unsigned int imr;
1669 +
1670 + imr = ar231x_read_reg(AR531X_IMR);
1671 + imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1672 + ar231x_write_reg(AR531X_IMR, imr);
1673 +}
1674 +
1675 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1676 +static void
1677 +ar5312_misc_irq_mask(struct irq_data *d)
1678 +{
1679 + unsigned int imr;
1680 +
1681 + imr = ar231x_read_reg(AR531X_IMR);
1682 + imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1683 + ar231x_write_reg(AR531X_IMR, imr);
1684 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1685 +}
1686 +
1687 +static struct irq_chip ar5312_misc_irq_chip = {
1688 + .name = "AR5312-MISC",
1689 + .irq_unmask = ar5312_misc_irq_unmask,
1690 + .irq_mask = ar5312_misc_irq_mask,
1691 +};
1692 +
1693 +
1694 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1695 +{
1696 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1697 + u32 proc_addr = ar231x_read_reg(AR531X_PROCADDR); /* clears error */
1698 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1699 + u32 dma_addr = ar231x_read_reg(AR531X_DMAADDR); /* clears error */
1700 +
1701 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
1702 + "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
1703 + dma1);
1704 +
1705 + machine_restart("AHB error"); /* Catastrophic failure */
1706 + return IRQ_HANDLED;
1707 +}
1708 +
1709 +
1710 +static struct irqaction ar5312_ahb_proc_interrupt = {
1711 + .handler = ar5312_ahb_proc_handler,
1712 + .name = "ar5312_ahb_proc_interrupt",
1713 +};
1714 +
1715 +
1716 +void __init ar5312_irq_init(void)
1717 +{
1718 + int i;
1719 +
1720 + if (!is_5312())
1721 + return;
1722 +
1723 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1724 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1725 + int irq = AR531X_MISC_IRQ_BASE + i;
1726 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1727 + handle_level_irq);
1728 + }
1729 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1730 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1731 +}
1732 +
1733 +static u32
1734 +ar5312_gpio_set_output(u32 mask, u32 val)
1735 +{
1736 + u32 reg;
1737 +
1738 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1739 + reg |= mask;
1740 + reg &= ~val;
1741 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1742 + return reg;
1743 +}
1744 +
1745 +static u32
1746 +ar5312_gpio_get(u32 valid_mask)
1747 +{
1748 + u32 reg;
1749 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1750 + reg &= valid_mask;
1751 + return reg;
1752 +}
1753 +
1754 +static u32
1755 +ar5312_gpio_set(u32 mask, u32 value)
1756 +{
1757 + u32 reg;
1758 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1759 + reg &= ~mask;
1760 + reg |= value;
1761 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1762 + return reg;
1763 +}
1764 +
1765 +/*
1766 + * gpiolib implementations. Original mask based methods preserved
1767 + */
1768 +static int
1769 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1770 +{
1771 + struct ar231x_gpio_chip *gpch =
1772 + container_of(chip, struct ar231x_gpio_chip, chip);
1773 + u32 mask = 1 << gpio;
1774 + u32 rett;
1775 + if (!(gpch->valid_mask & mask))
1776 + return 0;
1777 + rett = ar5312_gpio_get(gpch->valid_mask);
1778 + return !!(rett & mask);
1779 +}
1780 +
1781 +static void
1782 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1783 +{
1784 + struct ar231x_gpio_chip *gpch =
1785 + container_of(chip, struct ar231x_gpio_chip, chip);
1786 + u32 mask = 1 << gpio;
1787 + if (!(gpch->valid_mask & mask))
1788 + return;
1789 + ar5312_gpio_set(mask, (!!value) * mask);
1790 +}
1791 +
1792 +static int
1793 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1794 +{
1795 + struct ar231x_gpio_chip *gpch =
1796 + container_of(chip, struct ar231x_gpio_chip, chip);
1797 + u32 mask = 1 << gpio;
1798 + if (!(gpch->valid_mask & mask))
1799 + return -ENXIO;
1800 + ar5312_gpio_set_output(mask, 0);
1801 + return 0;
1802 +}
1803 +static int
1804 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1805 +{
1806 + struct ar231x_gpio_chip *gpch =
1807 + container_of(chip, struct ar231x_gpio_chip, chip);
1808 + u32 mask = 1 << gpio;
1809 + if (!(gpch->valid_mask & mask))
1810 + return -ENXIO;
1811 + ar5312_gpio_set_output(mask, mask);
1812 + ar5312_gpio_set(mask, (!!value) * mask);
1813 + return 0;
1814 +}
1815 +
1816 +static struct ar231x_gpio_chip ar5312_gpio_chip = {
1817 + .valid_mask = (1 << 22) - 1,
1818 + .chip = {
1819 + .label = "ar5312-gpio",
1820 + .direction_input = ar5312_gpio_direction_input,
1821 + .direction_output = ar5312_gpio_direction_output,
1822 + .set = ar5312_gpio_set_value,
1823 + .get = ar5312_gpio_get_value,
1824 + .base = 0,
1825 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
1826 + }
1827 +};
1828 +
1829 +/* end of gpiolib */
1830 +
1831 +static void ar5312_device_reset_set(u32 mask)
1832 +{
1833 + u32 val;
1834 +
1835 + val = ar231x_read_reg(AR531X_RESET);
1836 + ar231x_write_reg(AR531X_RESET, val | mask);
1837 +}
1838 +
1839 +static void ar5312_device_reset_clear(u32 mask)
1840 +{
1841 + u32 val;
1842 +
1843 + val = ar231x_read_reg(AR531X_RESET);
1844 + ar231x_write_reg(AR531X_RESET, val & ~mask);
1845 +}
1846 +
1847 +static struct physmap_flash_data ar5312_flash_data = {
1848 + .width = 2,
1849 +};
1850 +
1851 +static struct resource ar5312_flash_resource = {
1852 + .start = AR531X_FLASH,
1853 + .end = AR531X_FLASH + 0x800000 - 1,
1854 + .flags = IORESOURCE_MEM,
1855 +};
1856 +
1857 +static struct ar231x_eth ar5312_eth0_data = {
1858 + .reset_set = ar5312_device_reset_set,
1859 + .reset_clear = ar5312_device_reset_clear,
1860 + .reset_mac = AR531X_RESET_ENET0,
1861 + .reset_phy = AR531X_RESET_EPHY0,
1862 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1863 + .config = &ar231x_board,
1864 +};
1865 +
1866 +static struct ar231x_eth ar5312_eth1_data = {
1867 + .reset_set = ar5312_device_reset_set,
1868 + .reset_clear = ar5312_device_reset_clear,
1869 + .reset_mac = AR531X_RESET_ENET1,
1870 + .reset_phy = AR531X_RESET_EPHY1,
1871 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1872 + .config = &ar231x_board,
1873 +};
1874 +
1875 +static struct platform_device ar5312_physmap_flash = {
1876 + .name = "physmap-flash",
1877 + .id = 0,
1878 + .dev.platform_data = &ar5312_flash_data,
1879 + .resource = &ar5312_flash_resource,
1880 + .num_resources = 1,
1881 +};
1882 +
1883 +#ifdef CONFIG_LEDS_GPIO
1884 +static struct gpio_led ar5312_leds[] = {
1885 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1886 +};
1887 +
1888 +static const struct gpio_led_platform_data ar5312_led_data = {
1889 + .num_leds = ARRAY_SIZE(ar5312_leds),
1890 + .leds = (void *)ar5312_leds,
1891 +};
1892 +
1893 +static struct platform_device ar5312_gpio_leds = {
1894 + .name = "leds-gpio",
1895 + .id = -1,
1896 + .dev.platform_data = (void *)&ar5312_led_data,
1897 +};
1898 +#endif
1899 +
1900 +/*
1901 + * NB: This mapping size is larger than the actual flash size,
1902 + * but this shouldn't be a problem here, because the flash
1903 + * will simply be mapped multiple times.
1904 + */
1905 +static char __init *ar5312_flash_limit(void)
1906 +{
1907 + u32 ctl;
1908 + /*
1909 + * Configure flash bank 0.
1910 + * Assume 8M window size. Flash will be aliased if it's smaller
1911 + */
1912 + ctl = FLASHCTL_E |
1913 + FLASHCTL_AC_8M |
1914 + FLASHCTL_RBLE |
1915 + (0x01 << FLASHCTL_IDCY_S) |
1916 + (0x07 << FLASHCTL_WST1_S) |
1917 + (0x07 << FLASHCTL_WST2_S) |
1918 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1919 +
1920 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1921 +
1922 + /* Disable other flash banks */
1923 + ar231x_write_reg(AR531X_FLASHCTL1,
1924 + ar231x_read_reg(AR531X_FLASHCTL1) &
1925 + ~(FLASHCTL_E | FLASHCTL_AC));
1926 +
1927 + ar231x_write_reg(AR531X_FLASHCTL2,
1928 + ar231x_read_reg(AR531X_FLASHCTL2) &
1929 + ~(FLASHCTL_E | FLASHCTL_AC));
1930 +
1931 + return (char *)KSEG1ADDR(AR531X_FLASH + 0x800000);
1932 +}
1933 +
1934 +int __init ar5312_init_devices(void)
1935 +{
1936 + struct ar231x_boarddata *config;
1937 + u32 fctl = 0;
1938 + u8 *c;
1939 +
1940 + if (!is_5312())
1941 + return 0;
1942 +
1943 + /* Locate board/radio config data */
1944 + ar231x_find_config(ar5312_flash_limit());
1945 + config = ar231x_board.config;
1946 +
1947 + /* AR2313 has CPU minor rev. 10 */
1948 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1949 + ar231x_devtype = DEV_TYPE_AR2313;
1950 +
1951 + /* AR2312 shares the same Silicon ID as AR5312 */
1952 + else if (config->flags & BD_ISCASPER)
1953 + ar231x_devtype = DEV_TYPE_AR2312;
1954 +
1955 + /* Everything else is probably AR5312 or compatible */
1956 + else
1957 + ar231x_devtype = DEV_TYPE_AR5312;
1958 +
1959 + /* fixup flash width */
1960 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1961 + switch (fctl) {
1962 + case FLASHCTL_MWx16:
1963 + ar5312_flash_data.width = 2;
1964 + break;
1965 + case FLASHCTL_MWx8:
1966 + default:
1967 + ar5312_flash_data.width = 1;
1968 + break;
1969 + }
1970 +
1971 + platform_device_register(&ar5312_physmap_flash);
1972 +
1973 +#ifdef CONFIG_LEDS_GPIO
1974 + ar5312_leds[0].gpio = config->sys_led_gpio;
1975 + platform_device_register(&ar5312_gpio_leds);
1976 +#endif
1977 +
1978 + /* Fix up MAC addresses if necessary */
1979 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1980 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1981 +
1982 + /* If ENET0 and ENET1 have the same mac address,
1983 + * increment the one from ENET1 */
1984 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1985 + c = config->enet1_mac + 5;
1986 + while ((c >= config->enet1_mac) && !(++(*c)))
1987 + c--;
1988 + }
1989 +
1990 + switch (ar231x_devtype) {
1991 + case DEV_TYPE_AR5312:
1992 + ar5312_eth0_data.macaddr = config->enet0_mac;
1993 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1994 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1995 +
1996 + ar5312_eth1_data.macaddr = config->enet1_mac;
1997 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1998 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1999 +
2000 + if (!ar231x_board.radio)
2001 + return 0;
2002 +
2003 + if (!(config->flags & BD_WLAN0))
2004 + break;
2005 +
2006 + ar231x_add_wmac(0, AR531X_WLAN0, AR5312_IRQ_WLAN0_INTRS);
2007 + break;
2008 + /*
2009 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
2010 + * of ENET1. Atheros calls it 'twisted' for a reason :)
2011 + */
2012 + case DEV_TYPE_AR2312:
2013 + case DEV_TYPE_AR2313:
2014 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
2015 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
2016 + ar5312_eth1_data.macaddr = config->enet0_mac;
2017 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
2018 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
2019 +
2020 + if (!ar231x_board.radio)
2021 + return 0;
2022 + break;
2023 + default:
2024 + break;
2025 + }
2026 +
2027 + if (config->flags & BD_WLAN1)
2028 + ar231x_add_wmac(1, AR531X_WLAN1, AR5312_IRQ_WLAN1_INTRS);
2029 +
2030 + return 0;
2031 +}
2032 +
2033 +
2034 +static void ar5312_restart(char *command)
2035 +{
2036 + /* reset the system */
2037 + local_irq_disable();
2038 + while (1)
2039 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
2040 +}
2041 +
2042 +
2043 +/*
2044 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2045 + * to determine the predevisor value.
2046 + */
2047 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2048 +
2049 +
2050 +static int __init
2051 +ar5312_cpu_frequency(void)
2052 +{
2053 + unsigned int scratch;
2054 + unsigned int predivide_mask, predivide_shift;
2055 + unsigned int multiplier_mask, multiplier_shift;
2056 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
2057 + unsigned int doubler_mask;
2058 + u16 devid;
2059 +
2060 + /* Trust the bootrom's idea of cpu frequency. */
2061 + scratch = ar231x_read_reg(AR5312_SCRATCH);
2062 + if (scratch)
2063 + return scratch;
2064 +
2065 + devid = ar231x_read_reg(AR531X_REV);
2066 + devid &= AR531X_REV_MAJ;
2067 + devid >>= AR531X_REV_MAJ_S;
2068 + if (devid == AR531X_REV_MAJ_AR2313) {
2069 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2070 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2071 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2072 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2073 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2074 + } else { /* AR5312 and AR2312 */
2075 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2076 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2077 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2078 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2079 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2080 + }
2081 +
2082 + /*
2083 + * Clocking is derived from a fixed 40MHz input clock.
2084 + *
2085 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2086 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2087 + * flash, Timer, Watchdog Timer)
2088 + *
2089 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2090 + *
2091 + * So, for example, with a PLL multiplier of 5, we have
2092 + *
2093 + * cpu_freq = 200MHz
2094 + * sys_freq = 50MHz
2095 + * cnt_freq = 100MHz
2096 + *
2097 + * We compute the CPU frequency, based on PLL settings.
2098 + */
2099 +
2100 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2101 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2102 + predivisor = clockctl1_predivide_table[predivide_select];
2103 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2104 +
2105 + if (clock_ctl1 & doubler_mask)
2106 + multiplier = multiplier << 1;
2107 +
2108 + return (40000000 / predivisor) * multiplier;
2109 +}
2110 +
2111 +static inline int
2112 +ar5312_sys_frequency(void)
2113 +{
2114 + return ar5312_cpu_frequency() / 4;
2115 +}
2116 +
2117 +void __init
2118 +ar5312_time_init(void)
2119 +{
2120 + if (!is_5312())
2121 + return;
2122 +
2123 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2124 +}
2125 +
2126 +int __init
2127 +ar5312_gpio_init(void)
2128 +{
2129 + int ret;
2130 + struct ar231x_gpio_chip *gpch;
2131 + gpch = &ar5312_gpio_chip;
2132 + ret = gpiochip_add(&gpch->chip);
2133 + if (ret) {
2134 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2135 + return ret;
2136 + }
2137 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2138 + gpch->chip.ngpio);
2139 + return ret;
2140 +}
2141 +
2142 +void __init
2143 +ar5312_prom_init(void)
2144 +{
2145 + u32 memsize, memcfg, bank0AC, bank1AC;
2146 + u32 devid;
2147 +
2148 + if (!is_5312())
2149 + return;
2150 +
2151 + /* Detect memory size */
2152 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2153 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2154 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2155 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2156 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2157 + memsize <<= 20;
2158 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2159 +
2160 + devid = ar231x_read_reg(AR531X_REV);
2161 + devid >>= AR531X_REV_WMAC_MIN_S;
2162 + devid &= AR531X_REV_CHIP;
2163 + ar231x_board.devid = (u16) devid;
2164 + ar5312_gpio_init();
2165 +}
2166 +
2167 +void __init
2168 +ar5312_plat_setup(void)
2169 +{
2170 + if (!is_5312())
2171 + return;
2172 +
2173 + /* Clear any lingering AHB errors */
2174 + ar231x_read_reg(AR531X_PROCADDR);
2175 + ar231x_read_reg(AR531X_DMAADDR);
2176 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2177 +
2178 + _machine_restart = ar5312_restart;
2179 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), AR531X_MISC_IRQ_UART0,
2180 + ar5312_sys_frequency());
2181 +}
2182 +
2183 --- /dev/null
2184 +++ b/arch/mips/ar231x/ar2315.c
2185 @@ -0,0 +1,615 @@
2186 +/*
2187 + * This file is subject to the terms and conditions of the GNU General Public
2188 + * License. See the file "COPYING" in the main directory of this archive
2189 + * for more details.
2190 + *
2191 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2192 + * Copyright (C) 2006 FON Technology, SL.
2193 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2194 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2195 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2196 + */
2197 +
2198 +/*
2199 + * Platform devices for Atheros SoCs
2200 + */
2201 +
2202 +#include <generated/autoconf.h>
2203 +#include <linux/init.h>
2204 +#include <linux/module.h>
2205 +#include <linux/types.h>
2206 +#include <linux/string.h>
2207 +#include <linux/platform_device.h>
2208 +#include <linux/kernel.h>
2209 +#include <linux/reboot.h>
2210 +#include <linux/delay.h>
2211 +#include <linux/leds.h>
2212 +#include <linux/gpio.h>
2213 +#include <asm/bootinfo.h>
2214 +#include <asm/reboot.h>
2215 +#include <asm/time.h>
2216 +#include <linux/irq.h>
2217 +#include <linux/io.h>
2218 +
2219 +#include <ar231x_platform.h>
2220 +#include <ar2315_regs.h>
2221 +#include <ar231x.h>
2222 +#include "devices.h"
2223 +#include "ar2315.h"
2224 +
2225 +static u32 gpiointmask, gpiointval;
2226 +
2227 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
2228 +{
2229 + u32 pend;
2230 + int bit = -1;
2231 +
2232 + /* only do one gpio interrupt at a time */
2233 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2234 +
2235 + if (pend) {
2236 + bit = fls(pend) - 1;
2237 + pend &= ~(1 << bit);
2238 + gpiointval ^= (1 << bit);
2239 + }
2240 +
2241 + if (!pend)
2242 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2243 +
2244 + /* Enable interrupt with edge detection */
2245 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) !=
2246 + AR2315_GPIO_CR_I(bit))
2247 + return;
2248 +
2249 + if (bit >= 0)
2250 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2251 +}
2252 +
2253 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2254 +{
2255 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2256 + ar231x_read_reg(AR2315_IMR);
2257 +
2258 + if (misc_intr & AR2315_ISR_SPI)
2259 + do_IRQ(AR2315_MISC_IRQ_SPI);
2260 + else if (misc_intr & AR2315_ISR_TIMER)
2261 + do_IRQ(AR2315_MISC_IRQ_TIMER);
2262 + else if (misc_intr & AR2315_ISR_AHB)
2263 + do_IRQ(AR2315_MISC_IRQ_AHB);
2264 + else if (misc_intr & AR2315_ISR_GPIO)
2265 + do_IRQ(AR2315_MISC_IRQ_GPIO);
2266 + else if (misc_intr & AR2315_ISR_UART0)
2267 + do_IRQ(AR2315_MISC_IRQ_UART0);
2268 + else if (misc_intr & AR2315_ISR_WD) {
2269 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2270 + do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
2271 + } else
2272 + do_IRQ(AR2315_MISC_IRQ_NONE);
2273 +}
2274 +
2275 +/*
2276 + * Called when an interrupt is received, this function
2277 + * determines exactly which interrupt it was, and it
2278 + * invokes the appropriate handler.
2279 + *
2280 + * Implicitly, we also define interrupt priority by
2281 + * choosing which to dispatch first.
2282 + */
2283 +static asmlinkage void
2284 +ar2315_irq_dispatch(void)
2285 +{
2286 + int pending = read_c0_status() & read_c0_cause();
2287 +
2288 + if (pending & CAUSEF_IP3)
2289 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2290 + else if (pending & CAUSEF_IP4)
2291 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2292 + else if (pending & CAUSEF_IP2)
2293 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2294 + else if (pending & CAUSEF_IP7)
2295 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2296 +}
2297 +
2298 +static void ar2315_set_gpiointmask(int gpio, int level)
2299 +{
2300 + u32 reg;
2301 +
2302 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2303 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2304 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2305 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2306 +}
2307 +
2308 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2309 +{
2310 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2311 +
2312 + /* Enable interrupt with edge detection */
2313 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) !=
2314 + AR2315_GPIO_CR_I(gpio))
2315 + return;
2316 +
2317 + gpiointmask |= (1 << gpio);
2318 + ar2315_set_gpiointmask(gpio, 3);
2319 +}
2320 +
2321 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2322 +{
2323 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2324 +
2325 + /* Disable interrupt */
2326 + gpiointmask &= ~(1 << gpio);
2327 + ar2315_set_gpiointmask(gpio, 0);
2328 +}
2329 +
2330 +static struct irq_chip ar2315_gpio_irq_chip = {
2331 + .name = "AR2315-GPIO",
2332 + .irq_unmask = ar2315_gpio_irq_unmask,
2333 + .irq_mask = ar2315_gpio_irq_mask,
2334 +};
2335 +
2336 +static void
2337 +ar2315_misc_irq_unmask(struct irq_data *d)
2338 +{
2339 + unsigned int imr;
2340 +
2341 + imr = ar231x_read_reg(AR2315_IMR);
2342 + imr |= 1 << (d->irq - AR531X_MISC_IRQ_BASE - 1);
2343 + ar231x_write_reg(AR2315_IMR, imr);
2344 +}
2345 +
2346 +static void
2347 +ar2315_misc_irq_mask(struct irq_data *d)
2348 +{
2349 + unsigned int imr;
2350 +
2351 + imr = ar231x_read_reg(AR2315_IMR);
2352 + imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
2353 + ar231x_write_reg(AR2315_IMR, imr);
2354 +}
2355 +
2356 +static struct irq_chip ar2315_misc_irq_chip = {
2357 + .name = "AR2315-MISC",
2358 + .irq_unmask = ar2315_misc_irq_unmask,
2359 + .irq_mask = ar2315_misc_irq_mask,
2360 +};
2361 +
2362 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2363 +{
2364 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2365 + ar231x_read_reg(AR2315_AHB_ERR1);
2366 +
2367 + pr_emerg("AHB fatal error\n");
2368 + machine_restart("AHB error"); /* Catastrophic failure */
2369 +
2370 + return IRQ_HANDLED;
2371 +}
2372 +
2373 +static struct irqaction ar2315_ahb_proc_interrupt = {
2374 + .handler = ar2315_ahb_proc_handler,
2375 + .name = "ar2315_ahb_proc_interrupt",
2376 +};
2377 +
2378 +void
2379 +ar2315_irq_init(void)
2380 +{
2381 + int i;
2382 +
2383 + if (!is_2315())
2384 + return;
2385 +
2386 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2387 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2388 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2389 + int irq = AR531X_MISC_IRQ_BASE + i;
2390 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2391 + handle_level_irq);
2392 + }
2393 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2394 + int irq = AR531X_GPIO_IRQ_BASE + i;
2395 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2396 + handle_level_irq);
2397 + }
2398 + irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
2399 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2400 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2401 +}
2402 +
2403 +static u32
2404 +ar2315_gpio_set_output(u32 mask, u32 val)
2405 +{
2406 + u32 reg;
2407 +
2408 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2409 + reg &= ~mask;
2410 + reg |= val;
2411 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2412 + return reg;
2413 +}
2414 +
2415 +static u32
2416 +ar2315_gpio_get(u32 valid_mask)
2417 +{
2418 + u32 reg;
2419 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2420 + reg &= valid_mask;
2421 + return reg;
2422 +}
2423 +
2424 +static u32
2425 +ar2315_gpio_set(u32 mask, u32 value)
2426 +{
2427 + u32 reg;
2428 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2429 + reg &= ~mask;
2430 + reg |= value;
2431 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2432 + return reg;
2433 +}
2434 +
2435 +/*
2436 + * gpiolib implementation. Original legacy mask based methods
2437 + * preserved for now.
2438 + */
2439 +static int
2440 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2441 +{
2442 + struct ar231x_gpio_chip *gpch =
2443 + container_of(chip, struct ar231x_gpio_chip, chip);
2444 + u32 mask = 1 << gpio;
2445 + u32 rett;
2446 + if (!(gpch->valid_mask & mask))
2447 + return 0;
2448 + rett = ar2315_gpio_get(gpch->valid_mask); /* legacy code */
2449 + return !!(rett & mask);
2450 +}
2451 +
2452 +static void
2453 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2454 +{
2455 + struct ar231x_gpio_chip *gpch =
2456 + container_of(chip, struct ar231x_gpio_chip, chip);
2457 + u32 mask = 1 << gpio;
2458 + if (!(gpch->valid_mask & mask))
2459 + return;
2460 + ar2315_gpio_set(mask, (!!value) * mask); /* legacy */
2461 +}
2462 +
2463 +static int
2464 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2465 +{
2466 + struct ar231x_gpio_chip *gpch =
2467 + container_of(chip, struct ar231x_gpio_chip, chip);
2468 + u32 mask = 1 << gpio;
2469 + if (!(gpch->valid_mask & mask))
2470 + return -ENXIO;
2471 + ar2315_gpio_set_output(mask, 0); /* legacy */
2472 + return 0;
2473 +}
2474 +
2475 +static int
2476 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2477 +{
2478 + struct ar231x_gpio_chip *gpch =
2479 + container_of(chip, struct ar231x_gpio_chip, chip);
2480 + u32 mask = 1 << gpio;
2481 + if (!(gpch->valid_mask & mask))
2482 + return -ENXIO;
2483 + ar2315_gpio_set_output(mask, mask); /* both legacy */
2484 + ar2315_gpio_set(mask, (!!value) * mask);
2485 + return 0;
2486 +}
2487 +
2488 +static struct ar231x_gpio_chip ar2315_gpio_chip = {
2489 + .valid_mask = (1 << 22) - 1,
2490 + .chip = {
2491 + .label = "ar2315-gpio",
2492 + .direction_input = ar2315_gpio_direction_input,
2493 + .direction_output = ar2315_gpio_direction_output,
2494 + .set = ar2315_gpio_set_value,
2495 + .get = ar2315_gpio_get_value,
2496 + .base = 0,
2497 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
2498 + }
2499 +};
2500 +
2501 +/* end of gpiolib */
2502 +
2503 +static void ar2315_device_reset_set(u32 mask)
2504 +{
2505 + u32 val;
2506 +
2507 + val = ar231x_read_reg(AR2315_RESET);
2508 + ar231x_write_reg(AR2315_RESET, val | mask);
2509 +}
2510 +
2511 +static void ar2315_device_reset_clear(u32 mask)
2512 +{
2513 + u32 val;
2514 +
2515 + val = ar231x_read_reg(AR2315_RESET);
2516 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2517 +}
2518 +
2519 +static struct ar231x_eth ar2315_eth_data = {
2520 + .reset_set = ar2315_device_reset_set,
2521 + .reset_clear = ar2315_device_reset_clear,
2522 + .reset_mac = AR2315_RESET_ENET0,
2523 + .reset_phy = AR2315_RESET_EPHY0,
2524 + .phy_base = KSEG1ADDR(AR2315_ENET0),
2525 + .config = &ar231x_board,
2526 +};
2527 +
2528 +static struct resource ar2315_spiflash_res[] = {
2529 + {
2530 + .name = "spiflash_read",
2531 + .flags = IORESOURCE_MEM,
2532 + .start = AR2315_SPI_READ,
2533 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2534 + },
2535 + {
2536 + .name = "spiflash_mmr",
2537 + .flags = IORESOURCE_MEM,
2538 + .start = AR2315_SPI_MMR,
2539 + .end = AR2315_SPI_MMR + 12 - 1,
2540 + },
2541 +};
2542 +
2543 +static struct platform_device ar2315_spiflash = {
2544 + .id = 0,
2545 + .name = "ar2315-spiflash",
2546 + .resource = ar2315_spiflash_res,
2547 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2548 +};
2549 +
2550 +static struct resource ar2315_wdt_res[] = {
2551 + {
2552 + .flags = IORESOURCE_MEM,
2553 + .start = AR2315_WD,
2554 + .end = AR2315_WD + 8 - 1,
2555 + },
2556 + {
2557 + .flags = IORESOURCE_IRQ,
2558 + .start = AR2315_MISC_IRQ_WATCHDOG,
2559 + .end = AR2315_MISC_IRQ_WATCHDOG,
2560 + }
2561 +};
2562 +
2563 +static struct platform_device ar2315_wdt = {
2564 + .id = 0,
2565 + .name = "ar2315-wdt",
2566 + .resource = ar2315_wdt_res,
2567 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2568 +};
2569 +
2570 +/*
2571 + * NB: We use mapping size that is larger than the actual flash size,
2572 + * but this shouldn't be a problem here, because the flash will simply
2573 + * be mapped multiple times.
2574 + */
2575 +static u8 __init *ar2315_flash_limit(void)
2576 +{
2577 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2578 +}
2579 +
2580 +#ifdef CONFIG_LEDS_GPIO
2581 +static struct gpio_led ar2315_leds[6];
2582 +static struct gpio_led_platform_data ar2315_led_data = {
2583 + .leds = (void *)ar2315_leds,
2584 +};
2585 +
2586 +static struct platform_device ar2315_gpio_leds = {
2587 + .name = "leds-gpio",
2588 + .id = -1,
2589 + .dev = {
2590 + .platform_data = (void *)&ar2315_led_data,
2591 + }
2592 +};
2593 +
2594 +static void __init
2595 +ar2315_init_gpio_leds(void)
2596 +{
2597 + static char led_names[6][6];
2598 + int i, led = 0;
2599 +
2600 + ar2315_led_data.num_leds = 0;
2601 + for (i = 1; i < 8; i++) {
2602 + if ((i == AR2315_RESET_GPIO) ||
2603 + (i == ar231x_board.config->reset_config_gpio))
2604 + continue;
2605 +
2606 + if (i == ar231x_board.config->sys_led_gpio)
2607 + strcpy(led_names[led], "wlan");
2608 + else
2609 + sprintf(led_names[led], "gpio%d", i);
2610 +
2611 + ar2315_leds[led].name = led_names[led];
2612 + ar2315_leds[led].gpio = i;
2613 + ar2315_leds[led].active_low = 0;
2614 + led++;
2615 + }
2616 + ar2315_led_data.num_leds = led;
2617 + platform_device_register(&ar2315_gpio_leds);
2618 +}
2619 +#else
2620 +static inline void ar2315_init_gpio_leds(void)
2621 +{
2622 +}
2623 +#endif
2624 +
2625 +int __init
2626 +ar2315_init_devices(void)
2627 +{
2628 + if (!is_2315())
2629 + return 0;
2630 +
2631 + /* Find board configuration */
2632 + ar231x_find_config(ar2315_flash_limit());
2633 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2634 +
2635 + ar2315_init_gpio_leds();
2636 + platform_device_register(&ar2315_wdt);
2637 + platform_device_register(&ar2315_spiflash);
2638 + ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS,
2639 + &ar2315_eth_data);
2640 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2641 +
2642 + return 0;
2643 +}
2644 +
2645 +static void
2646 +ar2315_restart(char *command)
2647 +{
2648 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2649 +
2650 + local_irq_disable();
2651 +
2652 + /* try reset the system via reset control */
2653 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2654 +
2655 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2656 + * a workaround. Give it some time to attempt a gpio based hardware
2657 + * reset (atheros reference design workaround) */
2658 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2659 + mdelay(100);
2660 +
2661 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2662 + * workaround. Attempt to jump to the mips reset location -
2663 + * the boot loader itself might be able to recover the system */
2664 + mips_reset_vec();
2665 +}
2666 +
2667 +
2668 +/*
2669 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2670 + * to determine the predevisor value.
2671 + */
2672 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2673 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2674 +
2675 +static unsigned int __init
2676 +ar2315_sys_clk(unsigned int clock_ctl)
2677 +{
2678 + unsigned int pllc_ctrl, cpu_div;
2679 + unsigned int pllc_out, refdiv, fdiv, divby2;
2680 + unsigned int clk_div;
2681 +
2682 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2683 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2684 + refdiv = clockctl1_predivide_table[refdiv];
2685 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2686 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2687 + divby2 += 1;
2688 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2689 +
2690 + /* clkm input selected */
2691 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2692 + case 0:
2693 + case 1:
2694 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2695 + PLLC_CLKM_DIV_S];
2696 + break;
2697 + case 2:
2698 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2699 + PLLC_CLKC_DIV_S];
2700 + break;
2701 + default:
2702 + pllc_out = 40000000;
2703 + clk_div = 1;
2704 + break;
2705 + }
2706 +
2707 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2708 + cpu_div = cpu_div * 2 ?: 1;
2709 +
2710 + return pllc_out / (clk_div * cpu_div);
2711 +}
2712 +
2713 +static inline unsigned int
2714 +ar2315_cpu_frequency(void)
2715 +{
2716 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2717 +}
2718 +
2719 +static inline unsigned int
2720 +ar2315_apb_frequency(void)
2721 +{
2722 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2723 +}
2724 +
2725 +void __init
2726 +ar2315_time_init(void)
2727 +{
2728 + if (!is_2315())
2729 + return;
2730 +
2731 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2732 +}
2733 +
2734 +int __init
2735 +ar2315_gpio_init(void)
2736 +{
2737 + int ret;
2738 + struct ar231x_gpio_chip *gpch;
2739 + gpch = &ar2315_gpio_chip;
2740 + ret = gpiochip_add(&gpch->chip);
2741 + if (ret) {
2742 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2743 + return ret;
2744 + }
2745 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2746 + gpch->chip.ngpio);
2747 + return ret;
2748 +}
2749 +
2750 +
2751 +
2752 +void __init
2753 +ar2315_prom_init(void)
2754 +{
2755 + u32 memsize, memcfg, devid;
2756 +
2757 + if (!is_2315())
2758 + return;
2759 +
2760 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2761 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2762 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2763 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2764 + memsize <<= 3;
2765 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2766 +
2767 + /* Detect the hardware based on the device ID */
2768 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2769 + switch (devid) {
2770 + case 0x90:
2771 + case 0x91:
2772 + ar231x_devtype = DEV_TYPE_AR2317;
2773 + break;
2774 + default:
2775 + ar231x_devtype = DEV_TYPE_AR2315;
2776 + break;
2777 + }
2778 + ar2315_gpio_init();
2779 + ar231x_board.devid = devid;
2780 +}
2781 +
2782 +void __init
2783 +ar2315_plat_setup(void)
2784 +{
2785 + u32 config;
2786 +
2787 + if (!is_2315())
2788 + return;
2789 +
2790 + /* Clear any lingering AHB errors */
2791 + config = read_c0_config();
2792 + write_c0_config(config & ~0x3);
2793 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2794 + ar231x_read_reg(AR2315_AHB_ERR1);
2795 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2796 +
2797 + _machine_restart = ar2315_restart;
2798 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), AR2315_MISC_IRQ_UART0,
2799 + ar2315_apb_frequency());
2800 +}
2801 --- /dev/null
2802 +++ b/arch/mips/ar231x/ar2315.h
2803 @@ -0,0 +1,37 @@
2804 +#ifndef __AR2315_H
2805 +#define __AR2315_H
2806 +
2807 +#ifdef CONFIG_ATHEROS_AR2315
2808 +
2809 +extern void ar2315_irq_init(void);
2810 +extern int ar2315_init_devices(void);
2811 +extern void ar2315_prom_init(void);
2812 +extern void ar2315_plat_setup(void);
2813 +extern void ar2315_time_init(void);
2814 +
2815 +#else
2816 +
2817 +static inline void ar2315_irq_init(void)
2818 +{
2819 +}
2820 +
2821 +static inline int ar2315_init_devices(void)
2822 +{
2823 + return 0;
2824 +}
2825 +
2826 +static inline void ar2315_prom_init(void)
2827 +{
2828 +}
2829 +
2830 +static inline void ar2315_plat_setup(void)
2831 +{
2832 +}
2833 +
2834 +static inline void ar2315_time_init(void)
2835 +{
2836 +}
2837 +
2838 +#endif
2839 +
2840 +#endif
2841 --- /dev/null
2842 +++ b/arch/mips/ar231x/ar5312.h
2843 @@ -0,0 +1,38 @@
2844 +#ifndef __AR5312_H
2845 +#define __AR5312_H
2846 +
2847 +#ifdef CONFIG_ATHEROS_AR5312
2848 +
2849 +extern void ar5312_irq_init(void);
2850 +extern int ar5312_init_devices(void);
2851 +extern void ar5312_prom_init(void);
2852 +extern void ar5312_plat_setup(void);
2853 +extern void ar5312_time_init(void);
2854 +extern void ar5312_time_init(void);
2855 +
2856 +#else
2857 +
2858 +static inline void ar5312_irq_init(void)
2859 +{
2860 +}
2861 +
2862 +static inline int ar5312_init_devices(void)
2863 +{
2864 + return 0;
2865 +}
2866 +
2867 +static inline void ar5312_prom_init(void)
2868 +{
2869 +}
2870 +
2871 +static inline void ar5312_plat_setup(void)
2872 +{
2873 +}
2874 +
2875 +static inline void ar5312_time_init(void)
2876 +{
2877 +}
2878 +
2879 +#endif
2880 +
2881 +#endif
2882 --- /dev/null
2883 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2884 @@ -0,0 +1,44 @@
2885 +#ifndef __AR531X_H
2886 +#define __AR531X_H
2887 +
2888 +#include <linux/types.h>
2889 +#include <linux/io.h>
2890 +
2891 +#define AR531X_MISC_IRQ_BASE 0x20
2892 +#define AR531X_GPIO_IRQ_BASE 0x30
2893 +
2894 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2895 +#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2896 +#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2897 +
2898 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2899 +#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
2900 +#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
2901 +#define AR531X_GPIO_IRQ_COUNT 22
2902 +
2903 +static inline u32
2904 +ar231x_read_reg(u32 reg)
2905 +{
2906 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2907 +}
2908 +
2909 +static inline void
2910 +ar231x_write_reg(u32 reg, u32 val)
2911 +{
2912 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2913 +}
2914 +
2915 +static inline u32
2916 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2917 +{
2918 + u32 ret;
2919 +
2920 + ret = ar231x_read_reg(reg);
2921 + ret &= ~mask;
2922 + ret |= val;
2923 + ar231x_write_reg(reg, ret);
2924 +
2925 + return ret;
2926 +}
2927 +
2928 +#endif
2929 --- /dev/null
2930 +++ b/arch/mips/ar231x/devices.h
2931 @@ -0,0 +1,42 @@
2932 +#ifndef __AR231X_DEVICES_H
2933 +#define __AR231X_DEVICES_H
2934 +#include <linux/gpio.h>
2935 +
2936 +enum {
2937 + /* handled by ar5312.c */
2938 + DEV_TYPE_AR2312,
2939 + DEV_TYPE_AR2313,
2940 + DEV_TYPE_AR5312,
2941 +
2942 + /* handled by ar2315.c */
2943 + DEV_TYPE_AR2315,
2944 + DEV_TYPE_AR2316,
2945 + DEV_TYPE_AR2317,
2946 +
2947 + DEV_TYPE_UNKNOWN
2948 +};
2949 +
2950 +extern int ar231x_devtype;
2951 +extern struct ar231x_board_config ar231x_board;
2952 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2953 +
2954 +extern int ar231x_find_config(u8 *flash_limit);
2955 +extern void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2956 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2957 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2958 +
2959 +static inline bool is_2315(void)
2960 +{
2961 + return (current_cpu_data.cputype == CPU_4KEC);
2962 +}
2963 +
2964 +static inline bool is_5312(void)
2965 +{
2966 + return !is_2315();
2967 +}
2968 +
2969 +struct ar231x_gpio_chip {
2970 + u32 valid_mask;
2971 + struct gpio_chip chip;
2972 +};
2973 +#endif
2974 --- /dev/null
2975 +++ b/arch/mips/ar231x/devices.c
2976 @@ -0,0 +1,168 @@
2977 +#include <linux/kernel.h>
2978 +#include <linux/init.h>
2979 +#include <linux/serial.h>
2980 +#include <linux/serial_core.h>
2981 +#include <linux/serial_8250.h>
2982 +#include <linux/platform_device.h>
2983 +#include <ar231x_platform.h>
2984 +#include <ar231x.h>
2985 +#include "devices.h"
2986 +#include "ar5312.h"
2987 +#include "ar2315.h"
2988 +
2989 +struct ar231x_board_config ar231x_board;
2990 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2991 +
2992 +static struct resource ar231x_eth0_res[] = {
2993 + {
2994 + .name = "eth0_membase",
2995 + .flags = IORESOURCE_MEM,
2996 + },
2997 + {
2998 + .name = "eth0_irq",
2999 + .flags = IORESOURCE_IRQ,
3000 + }
3001 +};
3002 +
3003 +static struct resource ar231x_eth1_res[] = {
3004 + {
3005 + .name = "eth1_membase",
3006 + .flags = IORESOURCE_MEM,
3007 + },
3008 + {
3009 + .name = "eth1_irq",
3010 + .flags = IORESOURCE_IRQ,
3011 + }
3012 +};
3013 +
3014 +static struct platform_device ar231x_eth[] = {
3015 + {
3016 + .id = 0,
3017 + .name = "ar231x-eth",
3018 + .resource = ar231x_eth0_res,
3019 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3020 + },
3021 + {
3022 + .id = 1,
3023 + .name = "ar231x-eth",
3024 + .resource = ar231x_eth1_res,
3025 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3026 + }
3027 +};
3028 +
3029 +static struct resource ar231x_wmac0_res[] = {
3030 + {
3031 + .name = "wmac0_membase",
3032 + .flags = IORESOURCE_MEM,
3033 + },
3034 + {
3035 + .name = "wmac0_irq",
3036 + .flags = IORESOURCE_IRQ,
3037 + }
3038 +};
3039 +
3040 +static struct resource ar231x_wmac1_res[] = {
3041 + {
3042 + .name = "wmac1_membase",
3043 + .flags = IORESOURCE_MEM,
3044 + },
3045 + {
3046 + .name = "wmac1_irq",
3047 + .flags = IORESOURCE_IRQ,
3048 + }
3049 +};
3050 +
3051 +
3052 +static struct platform_device ar231x_wmac[] = {
3053 + {
3054 + .id = 0,
3055 + .name = "ar231x-wmac",
3056 + .resource = ar231x_wmac0_res,
3057 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3058 + .dev.platform_data = &ar231x_board,
3059 + },
3060 + {
3061 + .id = 1,
3062 + .name = "ar231x-wmac",
3063 + .resource = ar231x_wmac1_res,
3064 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3065 + .dev.platform_data = &ar231x_board,
3066 + },
3067 +};
3068 +
3069 +static const char * const devtype_strings[] = {
3070 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3071 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3072 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3073 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3074 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3075 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3076 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3077 +};
3078 +
3079 +const char *get_system_type(void)
3080 +{
3081 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3082 + !devtype_strings[ar231x_devtype])
3083 + return devtype_strings[DEV_TYPE_UNKNOWN];
3084 + return devtype_strings[ar231x_devtype];
3085 +}
3086 +
3087 +
3088 +int __init
3089 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3090 +{
3091 + struct resource *res;
3092 +
3093 + ar231x_eth[nr].dev.platform_data = pdata;
3094 + res = &ar231x_eth[nr].resource[0];
3095 + res->start = base;
3096 + res->end = base + 0x2000 - 1;
3097 + res++;
3098 + res->start = irq;
3099 + res->end = irq;
3100 + return platform_device_register(&ar231x_eth[nr]);
3101 +}
3102 +
3103 +void __init
3104 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
3105 +{
3106 + struct uart_port s;
3107 +
3108 + memset(&s, 0, sizeof(s));
3109 +
3110 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3111 + s.iotype = UPIO_MEM;
3112 + s.irq = irq;
3113 + s.regshift = 2;
3114 + s.mapbase = mapbase;
3115 + s.uartclk = uartclk;
3116 + s.membase = (void __iomem *)s.mapbase;
3117 +
3118 + early_serial_setup(&s);
3119 +}
3120 +
3121 +int __init
3122 +ar231x_add_wmac(int nr, u32 base, int irq)
3123 +{
3124 + struct resource *res;
3125 +
3126 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3127 + res = &ar231x_wmac[nr].resource[0];
3128 + res->start = base;
3129 + res->end = base + 0x10000 - 1;
3130 + res++;
3131 + res->start = irq;
3132 + res->end = irq;
3133 + return platform_device_register(&ar231x_wmac[nr]);
3134 +}
3135 +
3136 +static int __init ar231x_register_devices(void)
3137 +{
3138 + ar5312_init_devices();
3139 + ar2315_init_devices();
3140 +
3141 + return 0;
3142 +}
3143 +
3144 +device_initcall(ar231x_register_devices);
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