projects / openwrt / staging / florian.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
atheros: v3.18: change calls logic
[openwrt/staging/florian.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,234 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ath25_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ath25_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == ATH25_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ath25_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ath25_board.radio = addr + 0x10000;
140 +
141 + if (ath25_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ath25_find_config(u8 *flash_limit)
191 +{
192 + struct ath25_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ath25_board.config = NULL;
202 + ath25_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ath25_board.config = (struct ath25_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ath25_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ath25_board.radio)
241 + rcfg = (u8 *)ath25_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ath25_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ath25_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ath25_halt;
275 + pm_power_off = ath25_halt;
276 +
277 + if (is_ar5312())
278 + ar5312_plat_mem_setup();
279 + else
280 + ar2315_plat_mem_setup();
281 +
282 + /* Disable data watchpoints */
283 + write_c0_watchlo0(0);
284 +}
285 +
286 +asmlinkage void plat_irq_dispatch(void)
287 +{
288 + ath25_irq_dispatch();
289 +}
290 +
291 +void __init plat_time_init(void)
292 +{
293 + if (is_ar5312())
294 + ar5312_plat_time_init();
295 + else
296 + ar2315_plat_time_init();
297 +}
298 +
299 +unsigned int __cpuinit get_c0_compare_int(void)
300 +{
301 + return CP0_LEGACY_COMPARE_IRQ;
302 +}
303 +
304 +void __init arch_init_irq(void)
305 +{
306 + clear_c0_status(ST0_IM);
307 + mips_cpu_irq_init();
308 +
309 + /* Initialize interrupt controllers */
310 + if (is_ar5312())
311 + ar5312_arch_init_irq();
312 + else
313 + ar2315_arch_init_irq();
314 +}
315 --- /dev/null
316 +++ b/arch/mips/ath25/prom.c
317 @@ -0,0 +1,40 @@
318 +/*
319 + * This file is subject to the terms and conditions of the GNU General Public
320 + * License. See the file "COPYING" in the main directory of this archive
321 + * for more details.
322 + *
323 + * Copyright MontaVista Software Inc
324 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
325 + * Copyright (C) 2006 FON Technology, SL.
326 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
327 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
328 + */
329 +
330 +/*
331 + * Prom setup file for ar231x
332 + */
333 +
334 +#include <linux/init.h>
335 +#include <generated/autoconf.h>
336 +#include <linux/kernel.h>
337 +#include <linux/string.h>
338 +#include <linux/mm.h>
339 +#include <linux/bootmem.h>
340 +
341 +#include <asm/bootinfo.h>
342 +#include <asm/addrspace.h>
343 +#include "ar5312.h"
344 +#include "ar2315.h"
345 +#include "devices.h"
346 +
347 +void __init prom_init(void)
348 +{
349 + if (is_ar5312())
350 + ar5312_prom_init();
351 + else
352 + ar2315_prom_init();
353 +}
354 +
355 +void __init prom_free_prom_memory(void)
356 +{
357 +}
358 --- /dev/null
359 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
360 @@ -0,0 +1,84 @@
361 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
362 +#define __ASM_MACH_ATH25_PLATFORM_H
363 +
364 +#include <linux/etherdevice.h>
365 +
366 +/*
367 + * This is board-specific data that is stored in a "fixed" location in flash.
368 + * It is shared across operating systems, so it should not be changed lightly.
369 + * The main reason we need it is in order to extract the ethernet MAC
370 + * address(es).
371 + */
372 +struct ath25_boarddata {
373 + u32 magic; /* board data is valid */
374 +#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
375 + u16 cksum; /* checksum (starting with BD_REV 2) */
376 + u16 rev; /* revision of this struct */
377 +#define BD_REV 4
378 + char board_name[64]; /* Name of board */
379 + u16 major; /* Board major number */
380 + u16 minor; /* Board minor number */
381 + u32 flags; /* Board configuration */
382 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
383 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
384 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
385 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
386 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
387 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
388 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
389 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
390 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
391 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
392 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
393 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
394 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
395 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
396 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
397 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
398 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
399 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
400 + u16 reset_config_gpio; /* Reset factory GPIO pin */
401 + u16 sys_led_gpio; /* System LED GPIO pin */
402 +
403 + u32 cpu_freq; /* CPU core frequency in Hz */
404 + u32 sys_freq; /* System frequency in Hz */
405 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
406 +
407 + u8 wlan0_mac[ETH_ALEN];
408 + u8 enet0_mac[ETH_ALEN];
409 + u8 enet1_mac[ETH_ALEN];
410 +
411 + u16 pci_id; /* Pseudo PCIID for common code */
412 + u16 mem_cap; /* cap bank1 in MB */
413 +
414 + /* version 3 */
415 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
416 +};
417 +
418 +#define BOARD_CONFIG_BUFSZ 0x1000
419 +
420 +/*
421 + * Platform device information for the Wireless MAC
422 + */
423 +struct ar231x_board_config {
424 + u16 devid;
425 +
426 + /* board config data */
427 + struct ath25_boarddata *config;
428 +
429 + /* radio calibration data */
430 + const char *radio;
431 +};
432 +
433 +/*
434 + * Platform device information for the Ethernet MAC
435 + */
436 +struct ar231x_eth {
437 + void (*reset_set)(u32);
438 + void (*reset_clear)(u32);
439 + u32 reset_mac;
440 + u32 reset_phy;
441 + char *macaddr;
442 +};
443 +
444 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
445 --- /dev/null
446 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
447 @@ -0,0 +1,64 @@
448 +/*
449 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
450 + *
451 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
452 + *
453 + * This file was derived from: include/asm-mips/cpu-features.h
454 + * Copyright (C) 2003, 2004 Ralf Baechle
455 + * Copyright (C) 2004 Maciej W. Rozycki
456 + *
457 + * This program is free software; you can redistribute it and/or modify it
458 + * under the terms of the GNU General Public License version 2 as published
459 + * by the Free Software Foundation.
460 + *
461 + */
462 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
463 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
464 +
465 +/*
466 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
467 + */
468 +#define cpu_has_tlb 1
469 +#define cpu_has_4kex 1
470 +#define cpu_has_3k_cache 0
471 +#define cpu_has_4k_cache 1
472 +#define cpu_has_tx39_cache 0
473 +#define cpu_has_sb1_cache 0
474 +#define cpu_has_fpu 0
475 +#define cpu_has_32fpr 0
476 +#define cpu_has_counter 1
477 +#define cpu_has_ejtag 1
478 +
479 +#if !defined(CONFIG_SOC_AR5312)
480 +# define cpu_has_llsc 1
481 +#else
482 +/*
483 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
484 + * ll/sc instructions.
485 + */
486 +# define cpu_has_llsc 0
487 +#endif
488 +
489 +#define cpu_has_mips16 0
490 +#define cpu_has_mdmx 0
491 +#define cpu_has_mips3d 0
492 +#define cpu_has_smartmips 0
493 +
494 +#define cpu_has_mips32r1 1
495 +
496 +#if !defined(CONFIG_SOC_AR5312)
497 +# define cpu_has_mips32r2 1
498 +#endif
499 +
500 +#define cpu_has_mips64r1 0
501 +#define cpu_has_mips64r2 0
502 +
503 +#define cpu_has_dsp 0
504 +#define cpu_has_mipsmt 0
505 +
506 +#define cpu_has_64bits 0
507 +#define cpu_has_64bit_zero_reg 0
508 +#define cpu_has_64bit_gp_regs 0
509 +#define cpu_has_64bit_addresses 0
510 +
511 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
512 --- /dev/null
513 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
514 @@ -0,0 +1,76 @@
515 +/*
516 + * This file is subject to the terms and conditions of the GNU General Public
517 + * License. See the file "COPYING" in the main directory of this archive
518 + * for more details.
519 + *
520 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
521 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
522 + *
523 + */
524 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
525 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
526 +
527 +#include <linux/device.h>
528 +#include <ar2315_regs.h>
529 +
530 +static inline dma_addr_t ath25_dev_offset(struct device *dev)
531 +{
532 +#ifdef CONFIG_PCI
533 + extern struct bus_type pci_bus_type;
534 +
535 + if (dev && dev->bus == &pci_bus_type)
536 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
537 +#endif
538 + return 0;
539 +}
540 +
541 +static inline dma_addr_t
542 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
543 +{
544 + return virt_to_phys(addr) + ath25_dev_offset(dev);
545 +}
546 +
547 +static inline dma_addr_t
548 +plat_map_dma_mem_page(struct device *dev, struct page *page)
549 +{
550 + return page_to_phys(page) + ath25_dev_offset(dev);
551 +}
552 +
553 +static inline unsigned long
554 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
555 +{
556 + return dma_addr - ath25_dev_offset(dev);
557 +}
558 +
559 +static inline void
560 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
561 + enum dma_data_direction direction)
562 +{
563 +}
564 +
565 +static inline int plat_dma_supported(struct device *dev, u64 mask)
566 +{
567 + return 1;
568 +}
569 +
570 +static inline void plat_extra_sync_for_device(struct device *dev)
571 +{
572 +}
573 +
574 +static inline int plat_dma_mapping_error(struct device *dev,
575 + dma_addr_t dma_addr)
576 +{
577 + return 0;
578 +}
579 +
580 +static inline int plat_device_is_coherent(struct device *dev)
581 +{
582 +#ifdef CONFIG_DMA_COHERENT
583 + return 1;
584 +#endif
585 +#ifdef CONFIG_DMA_NONCOHERENT
586 + return 0;
587 +#endif
588 +}
589 +
590 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
591 --- /dev/null
592 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
593 @@ -0,0 +1,16 @@
594 +#ifndef __ASM_MACH_ATH25_GPIO_H
595 +#define __ASM_MACH_ATH25_GPIO_H
596 +
597 +#include <asm-generic/gpio.h>
598 +
599 +#define gpio_get_value __gpio_get_value
600 +#define gpio_set_value __gpio_set_value
601 +#define gpio_cansleep __gpio_cansleep
602 +#define gpio_to_irq __gpio_to_irq
603 +
604 +static inline int irq_to_gpio(unsigned irq)
605 +{
606 + return -EINVAL;
607 +}
608 +
609 +#endif /* __ASM_MACH_ATH25_GPIO_H */
610 --- /dev/null
611 +++ b/arch/mips/include/asm/mach-ath25/war.h
612 @@ -0,0 +1,25 @@
613 +/*
614 + * This file is subject to the terms and conditions of the GNU General Public
615 + * License. See the file "COPYING" in the main directory of this archive
616 + * for more details.
617 + *
618 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
619 + */
620 +#ifndef __ASM_MACH_ATH25_WAR_H
621 +#define __ASM_MACH_ATH25_WAR_H
622 +
623 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
624 +#define R4600_V1_HIT_CACHEOP_WAR 0
625 +#define R4600_V2_HIT_CACHEOP_WAR 0
626 +#define R5432_CP0_INTERRUPT_WAR 0
627 +#define BCM1250_M3_WAR 0
628 +#define SIBYTE_1956_WAR 0
629 +#define MIPS4K_ICACHE_REFILL_WAR 0
630 +#define MIPS_CACHE_SYNC_WAR 0
631 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
632 +#define RM9000_CDEX_SMP_WAR 0
633 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
634 +#define R10000_LLSC_WAR 0
635 +#define MIPS34K_MISSED_ITLB_WAR 0
636 +
637 +#endif /* __ASM_MACH_ATH25_WAR_H */
638 --- /dev/null
639 +++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
640 @@ -0,0 +1,608 @@
641 +/*
642 + * Register definitions for AR2315+
643 + *
644 + * This file is subject to the terms and conditions of the GNU General Public
645 + * License. See the file "COPYING" in the main directory of this archive
646 + * for more details.
647 + *
648 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
649 + * Copyright (C) 2006 FON Technology, SL.
650 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
651 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
652 + */
653 +
654 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
655 +#define __ASM_MACH_ATH25_AR2315_REGS_H
656 +
657 +/*
658 + * IRQs
659 + */
660 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
661 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
662 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
663 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
664 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
665 +
666 +/*
667 + * Miscellaneous interrupts, which share IP2.
668 + */
669 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
670 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
671 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
672 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
673 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
674 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
675 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
676 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
677 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
678 +#define AR2315_MISC_IRQ_COUNT 9
679 +
680 +/*
681 + * PCI interrupts, which share IP5
682 + * Keep ordered according to AR2315_PCI_INT_XXX bits
683 + */
684 +#define AR2315_PCI_IRQ_BASE 0x50
685 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
686 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
687 +#define AR2315_PCI_IRQ_COUNT 2
688 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
689 +
690 +/*
691 + * Address map
692 + */
693 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
694 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
695 +#define AR2315_PCI 0x10100000 /* PCI MMR */
696 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
697 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
698 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
699 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
700 +#define AR2315_UART0 0x11100000 /* UART MMR */
701 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
702 +#define AR2315_PCIEXT 0x80000000 /* pci external */
703 +#define AR2315_PCIEXT_SZ 0x40000000
704 +
705 +/* MII registers offset inside Ethernet MMR region */
706 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
707 +
708 +/*
709 + * Cold reset register
710 + */
711 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
712 +
713 +#define AR2315_RESET_COLD_AHB 0x00000001
714 +#define AR2315_RESET_COLD_APB 0x00000002
715 +#define AR2315_RESET_COLD_CPU 0x00000004
716 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
717 +#define AR2315_RESET_SYSTEM \
718 + (RESET_COLD_CPU |\
719 + RESET_COLD_APB |\
720 + RESET_COLD_AHB) /* full system */
721 +#define AR2317_RESET_SYSTEM 0x00000010
722 +
723 +/*
724 + * Reset register
725 + */
726 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
727 +
728 +/* warm reset WLAN0 MAC */
729 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
730 +/* warm reset WLAN0 BaseBand */
731 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
732 +/* warm reset MPEG-TS */
733 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
734 +/* warm reset PCI ahb/dma */
735 +#define AR2315_RESET_PCIDMA 0x00000008
736 +/* warm reset memory controller */
737 +#define AR2315_RESET_MEMCTL 0x00000010
738 +/* warm reset local bus */
739 +#define AR2315_RESET_LOCAL 0x00000020
740 +/* warm reset I2C bus */
741 +#define AR2315_RESET_I2C_RSVD 0x00000040
742 +/* warm reset SPI interface */
743 +#define AR2315_RESET_SPI 0x00000080
744 +/* warm reset UART0 */
745 +#define AR2315_RESET_UART0 0x00000100
746 +/* warm reset IR interface */
747 +#define AR2315_RESET_IR_RSVD 0x00000200
748 +/* cold reset ENET0 phy */
749 +#define AR2315_RESET_EPHY0 0x00000400
750 +/* cold reset ENET0 mac */
751 +#define AR2315_RESET_ENET0 0x00000800
752 +
753 +/*
754 + * AHB master arbitration control
755 + */
756 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
757 +
758 +/* CPU, default */
759 +#define AR2315_ARB_CPU 0x00000001
760 +/* WLAN */
761 +#define AR2315_ARB_WLAN 0x00000002
762 +/* MPEG-TS */
763 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
764 +/* LOCAL */
765 +#define AR2315_ARB_LOCAL 0x00000008
766 +/* PCI */
767 +#define AR2315_ARB_PCI 0x00000010
768 +/* Ethernet */
769 +#define AR2315_ARB_ETHERNET 0x00000020
770 +/* retry policy, debug only */
771 +#define AR2315_ARB_RETRY 0x00000100
772 +
773 +/*
774 + * Config Register
775 + */
776 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
777 +
778 +/* EC - AHB bridge endianess */
779 +#define AR2315_CONFIG_AHB 0x00000001
780 +/* WLAN byteswap */
781 +#define AR2315_CONFIG_WLAN 0x00000002
782 +/* MPEG-TS byteswap */
783 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
784 +/* PCI byteswap */
785 +#define AR2315_CONFIG_PCI 0x00000008
786 +/* Memory controller endianess */
787 +#define AR2315_CONFIG_MEMCTL 0x00000010
788 +/* Local bus byteswap */
789 +#define AR2315_CONFIG_LOCAL 0x00000020
790 +/* Ethernet byteswap */
791 +#define AR2315_CONFIG_ETHERNET 0x00000040
792 +
793 +/* CPU write buffer merge */
794 +#define AR2315_CONFIG_MERGE 0x00000200
795 +/* CPU big endian */
796 +#define AR2315_CONFIG_CPU 0x00000400
797 +#define AR2315_CONFIG_PCIAHB 0x00000800
798 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
799 +/* SPI byteswap */
800 +#define AR2315_CONFIG_SPI 0x00008000
801 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
802 +#define AR2315_CONFIG_CPU_PCI 0x00020000
803 +#define AR2315_CONFIG_CPU_MMR 0x00040000
804 +#define AR2315_CONFIG_BIG 0x00000400
805 +
806 +/*
807 + * NMI control
808 + */
809 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
810 +
811 +#define AR2315_NMI_EN 1
812 +
813 +/*
814 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
815 + */
816 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
817 +
818 +#define AR2315_REV_MAJ 0x00f0
819 +#define AR2315_REV_MAJ_S 4
820 +#define AR2315_REV_MIN 0x000f
821 +#define AR2315_REV_MIN_S 0
822 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
823 +
824 +/*
825 + * Interface Enable
826 + */
827 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
828 +
829 +#define AR2315_IF_MASK 0x00000007
830 +#define AR2315_IF_DISABLED 0
831 +#define AR2315_IF_PCI 1
832 +#define AR2315_IF_TS_LOCAL 2
833 +/* only for emulation with separate pins */
834 +#define AR2315_IF_ALL 3
835 +#define AR2315_IF_LOCAL_HOST 0x00000008
836 +#define AR2315_IF_PCI_HOST 0x00000010
837 +#define AR2315_IF_PCI_INTR 0x00000020
838 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
839 +#define AR2315_IF_PCI_CLK_INPUT 0
840 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
841 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
842 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
843 +#define AR2315_IF_PCI_CLK_SHIFT 16
844 +
845 +/*
846 + * APB Interrupt control
847 + */
848 +
849 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
850 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
851 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
852 +
853 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
854 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
855 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
856 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
857 +#define AR2315_ISR_APB 0x0010 /* APB error */
858 +#define AR2315_ISR_TIMER 0x0020 /* timer */
859 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
860 +#define AR2315_ISR_WD 0x0080 /* watchdog */
861 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
862 +
863 +#define AR2315_GISR_MISC 0x0001
864 +#define AR2315_GISR_WLAN0 0x0002
865 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
866 +#define AR2315_GISR_LOCALPCI 0x0008
867 +#define AR2315_GISR_WMACPOLL 0x0010
868 +#define AR2315_GISR_TIMER 0x0020
869 +#define AR2315_GISR_ETHERNET 0x0040
870 +
871 +/*
872 + * Interrupt routing from IO to the processor IP bits
873 + * Define our inter mask and level
874 + */
875 +#define AR2315_INTR_MISCIO SR_IBIT3
876 +#define AR2315_INTR_WLAN0 SR_IBIT4
877 +#define AR2315_INTR_ENET0 SR_IBIT5
878 +#define AR2315_INTR_LOCALPCI SR_IBIT6
879 +#define AR2315_INTR_WMACPOLL SR_IBIT7
880 +#define AR2315_INTR_COMPARE SR_IBIT8
881 +
882 +/*
883 + * Timers
884 + */
885 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
886 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
887 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
888 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
889 +
890 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
891 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
892 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
893 +
894 +/*
895 + * CPU Performance Counters
896 + */
897 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
898 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
899 +
900 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
901 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
902 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
903 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
904 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
905 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
906 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
907 +
908 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
909 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
910 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
911 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
912 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
913 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
914 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
915 +
916 +/*
917 + * AHB Error Reporting.
918 + */
919 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
920 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
921 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
922 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
923 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
924 +
925 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
926 + /* write 1 to clear all bits in ERR0 */
927 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
928 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
929 +
930 +#define AR2315_PROCERR_HMAST 0x0000000f
931 +#define AR2315_PROCERR_HMAST_DFLT 0
932 +#define AR2315_PROCERR_HMAST_WMAC 1
933 +#define AR2315_PROCERR_HMAST_ENET 2
934 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
935 +#define AR2315_PROCERR_HMAST_LOCAL 4
936 +#define AR2315_PROCERR_HMAST_CPU 5
937 +#define AR2315_PROCERR_HMAST_PCITGT 6
938 +
939 +#define AR2315_PROCERR_HMAST_S 0
940 +#define AR2315_PROCERR_HWRITE 0x00000010
941 +#define AR2315_PROCERR_HSIZE 0x00000060
942 +#define AR2315_PROCERR_HSIZE_S 5
943 +#define AR2315_PROCERR_HTRANS 0x00000180
944 +#define AR2315_PROCERR_HTRANS_S 7
945 +#define AR2315_PROCERR_HBURST 0x00000e00
946 +#define AR2315_PROCERR_HBURST_S 9
947 +
948 +/*
949 + * Clock Control
950 + */
951 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
952 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
953 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
954 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
955 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
956 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
957 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
958 +
959 +/* PLLc Control fields */
960 +#define PLLC_REF_DIV_M 0x00000003
961 +#define PLLC_REF_DIV_S 0
962 +#define PLLC_FDBACK_DIV_M 0x0000007C
963 +#define PLLC_FDBACK_DIV_S 2
964 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
965 +#define PLLC_ADD_FDBACK_DIV_S 7
966 +#define PLLC_CLKC_DIV_M 0x0001c000
967 +#define PLLC_CLKC_DIV_S 14
968 +#define PLLC_CLKM_DIV_M 0x00700000
969 +#define PLLC_CLKM_DIV_S 20
970 +
971 +/* CPU CLK Control fields */
972 +#define CPUCLK_CLK_SEL_M 0x00000003
973 +#define CPUCLK_CLK_SEL_S 0
974 +#define CPUCLK_CLK_DIV_M 0x0000000c
975 +#define CPUCLK_CLK_DIV_S 2
976 +
977 +/* AMBA CLK Control fields */
978 +#define AMBACLK_CLK_SEL_M 0x00000003
979 +#define AMBACLK_CLK_SEL_S 0
980 +#define AMBACLK_CLK_DIV_M 0x0000000c
981 +#define AMBACLK_CLK_DIV_S 2
982 +
983 +/* GPIO MMR base address */
984 +#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
985 +
986 +#define AR2315_RESET_GPIO 5
987 +
988 +/*
989 + * PCI Clock Control
990 + */
991 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
992 +
993 +#define AR2315_PCICLK_INPUT_M 0x3
994 +#define AR2315_PCICLK_INPUT_S 0
995 +
996 +#define AR2315_PCICLK_PLLC_CLKM 0
997 +#define AR2315_PCICLK_PLLC_CLKM1 1
998 +#define AR2315_PCICLK_PLLC_CLKC 2
999 +#define AR2315_PCICLK_REF_CLK 3
1000 +
1001 +#define AR2315_PCICLK_DIV_M 0xc
1002 +#define AR2315_PCICLK_DIV_S 2
1003 +
1004 +#define AR2315_PCICLK_IN_FREQ 0
1005 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1006 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1007 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1008 +
1009 +/*
1010 + * Observation Control Register
1011 + */
1012 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1013 +#define OCR_GPIO0_IRIN 0x0040
1014 +#define OCR_GPIO1_IROUT 0x0080
1015 +#define OCR_GPIO3_RXCLR 0x0200
1016 +
1017 +/*
1018 + * General Clock Control
1019 + */
1020 +
1021 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1022 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1023 +#define MISCCLK_PROCREFCLK 0x00000002
1024 +
1025 +/*
1026 + * SDRAM Controller
1027 + * - No read or write buffers are included.
1028 + */
1029 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1030 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1031 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1032 +
1033 +#define SDRAM_DATA_WIDTH_M 0x00006000
1034 +#define SDRAM_DATA_WIDTH_S 13
1035 +
1036 +#define SDRAM_COL_WIDTH_M 0x00001E00
1037 +#define SDRAM_COL_WIDTH_S 9
1038 +
1039 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1040 +#define SDRAM_ROW_WIDTH_S 5
1041 +
1042 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1043 +#define SDRAM_BANKADDR_BITS_S 3
1044 +
1045 +/*
1046 + * PCI Bus Interface Registers
1047 + */
1048 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1049 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1050 +
1051 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1052 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1053 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1054 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1055 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1056 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1057 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1058 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1059 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1060 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1061 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1062 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1063 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1064 + * disable */
1065 +
1066 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1067 +
1068 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1069 +
1070 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1071 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1072 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1073 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1074 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1075 +
1076 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1077 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1078 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1079 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1080 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1081 +
1082 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1083 +
1084 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1085 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1086 +
1087 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1088 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1089 +
1090 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1091 +
1092 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
1093 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
1094 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
1095 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
1096 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
1097 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
1098 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
1099 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
1100 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
1101 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1102 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
1103 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
1104 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
1105 +
1106 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
1107 +
1108 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
1109 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
1110 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
1111 +
1112 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1113 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1114 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1115 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1116 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1117 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1118 +
1119 +/*
1120 + * Local Bus Interface Registers
1121 + */
1122 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1123 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1124 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1125 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1126 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1127 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1128 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1129 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1130 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1131 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1132 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1133 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1134 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1135 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1136 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1137 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1138 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1139 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1140 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1141 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1142 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1143 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1144 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1145 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1146 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1147 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1148 +
1149 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1150 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1151 +
1152 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1153 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1154 +
1155 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1156 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1157 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1158 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1159 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1160 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1161 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1162 +#define AR2315_LBM_TIMEOUT_SHFT 7
1163 +#define AR2315_LBM_PORTMUX 0x07000000
1164 +
1165 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1166 +
1167 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1168 +#define AR2315_LB_TXEN_0 0x01
1169 +#define AR2315_LB_TXEN_1 0x02
1170 +#define AR2315_LB_TXEN_2 0x04
1171 +#define AR2315_LB_TXEN_3 0x08
1172 +
1173 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1174 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1175 +
1176 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1177 +#define AR2315_LB_RXEN 0x01
1178 +
1179 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1180 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1181 +
1182 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1183 +#define AR2315_INT_TX_DESC 0x0001
1184 +#define AR2315_INT_TX_OK 0x0002
1185 +#define AR2315_INT_TX_ERR 0x0004
1186 +#define AR2315_INT_TX_EOF 0x0008
1187 +#define AR2315_INT_RX_DESC 0x0010
1188 +#define AR2315_INT_RX_OK 0x0020
1189 +#define AR2315_INT_RX_ERR 0x0040
1190 +#define AR2315_INT_RX_EOF 0x0080
1191 +#define AR2315_INT_TX_TRUNC 0x0100
1192 +#define AR2315_INT_TX_STARVE 0x0200
1193 +#define AR2315_INT_LB_TIMEOUT 0x0400
1194 +#define AR2315_INT_LB_ERR 0x0800
1195 +#define AR2315_INT_MBOX_WR 0x1000
1196 +#define AR2315_INT_MBOX_RD 0x2000
1197 +
1198 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1199 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1200 +
1201 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1202 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1203 +
1204 +/*
1205 + * IR Interface Registers
1206 + */
1207 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1208 +
1209 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1210 +
1211 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1212 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1213 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1214 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1215 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1216 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1217 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1218 +
1219 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1220 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1221 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1222 +
1223 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1224 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1225 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1226 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1227 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1228 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1229 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1230 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1231 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1232 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1233 +
1234 +/*
1235 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
1236 + * of PCI host controller to enable DMA. The same value should be used as the
1237 + * offset to calculate the physical address of DMA buffer for PCI devices.
1238 + */
1239 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
1240 +
1241 +/* ??? access BAR */
1242 +#define AR2315_PCI_HOST_MBAR0 0x10000000
1243 +/* RAM access BAR */
1244 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
1245 +/* ??? access BAR */
1246 +#define AR2315_PCI_HOST_MBAR2 0x30000000
1247 +
1248 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1249 --- /dev/null
1250 +++ b/arch/mips/include/asm/mach-ath25/ar5312_regs.h
1251 @@ -0,0 +1,235 @@
1252 +/*
1253 + * This file is subject to the terms and conditions of the GNU General Public
1254 + * License. See the file "COPYING" in the main directory of this archive
1255 + * for more details.
1256 + *
1257 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1258 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1259 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1260 + */
1261 +
1262 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1263 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1264 +
1265 +#include <asm/addrspace.h>
1266 +
1267 +/*
1268 + * IRQs
1269 + */
1270 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1271 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1272 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1273 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1274 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1275 +
1276 +/*
1277 + * Miscellaneous interrupts, which share IP6.
1278 + */
1279 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1280 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1281 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1282 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1283 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1284 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1285 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1286 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1287 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1288 +#define AR5312_MISC_IRQ_COUNT 9
1289 +
1290 +/*
1291 + * Address Map
1292 + */
1293 +#define AR5312_WLAN0 0x18000000
1294 +#define AR5312_WLAN1 0x18500000
1295 +#define AR5312_ENET0 0x18100000
1296 +#define AR5312_ENET1 0x18200000
1297 +#define AR5312_SDRAMCTL 0x18300000
1298 +#define AR5312_FLASHCTL 0x18400000
1299 +#define AR5312_APBBASE 0x1c000000
1300 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1301 +#define AR5312_FLASH 0x1e000000
1302 +
1303 +/*
1304 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1305 + * should be considered available. The AR5312 supports 2 enet MACS,
1306 + * even though many reference boards only actually use 1 of them
1307 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1308 + * The AR2312 supports 1 enet MAC.
1309 + */
1310 +#define AR5312_NUM_ENET_MAC 2
1311 +
1312 +/*
1313 + * Need these defines to determine true number of ethernet MACs
1314 + */
1315 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1316 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1317 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1318 +
1319 +/* MII registers offset inside Ethernet MMR region */
1320 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1321 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1322 +
1323 +/*
1324 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1325 + * should be considered available.
1326 + */
1327 +#define AR5312_NUM_WMAC 2
1328 +
1329 +/* Reset/Timer Block Address Map */
1330 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1331 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1332 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1333 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1334 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1335 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1336 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1337 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1338 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1339 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1340 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1341 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1342 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1343 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1344 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1345 +
1346 +/* AR5312_WD_CTRL register bit field definitions */
1347 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1348 +#define AR5312_WD_CTRL_NMI 0x0001
1349 +#define AR5312_WD_CTRL_RESET 0x0002
1350 +
1351 +/* AR5312_ISR register bit field definitions */
1352 +#define AR5312_ISR_TIMER 0x0001
1353 +#define AR5312_ISR_AHBPROC 0x0002
1354 +#define AR5312_ISR_AHBDMA 0x0004
1355 +#define AR5312_ISR_GPIO 0x0008
1356 +#define AR5312_ISR_UART0 0x0010
1357 +#define AR5312_ISR_UART0DMA 0x0020
1358 +#define AR5312_ISR_WD 0x0040
1359 +#define AR5312_ISR_LOCAL 0x0080
1360 +
1361 +/* AR5312_RESET register bit field definitions */
1362 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1363 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1364 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1365 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1366 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1367 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1368 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1369 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1370 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1371 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1372 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1373 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1374 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1375 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1376 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1377 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1378 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1379 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1380 +
1381 +#define AR5312_RESET_WMAC0_BITS \
1382 + (AR5312_RESET_WLAN0 |\
1383 + AR5312_RESET_WARM_WLAN0_MAC |\
1384 + AR5312_RESET_WARM_WLAN0_BB)
1385 +
1386 +#define AR5312_RESET_WMAC1_BITS \
1387 + (AR5312_RESET_WLAN1 |\
1388 + AR5312_RESET_WARM_WLAN1_MAC |\
1389 + AR5312_RESET_WARM_WLAN1_BB)
1390 +
1391 +/* AR5312_CLOCKCTL1 register bit field definitions */
1392 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1393 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1394 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1395 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1396 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1397 +
1398 +/* Valid for AR5312 and AR2312 */
1399 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1400 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1401 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1402 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1403 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1404 +
1405 +/* Valid for AR2313 */
1406 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1407 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1408 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1409 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1410 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1411 +
1412 +/* AR5312_ENABLE register bit field definitions */
1413 +#define AR5312_ENABLE_WLAN0 0x0001
1414 +#define AR5312_ENABLE_ENET0 0x0002
1415 +#define AR5312_ENABLE_ENET1 0x0004
1416 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1417 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1418 +#define AR5312_ENABLE_WLAN1 \
1419 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1420 + AR5312_ENABLE_WLAN1_DMA)
1421 +
1422 +/* AR5312_REV register bit field definitions */
1423 +#define AR5312_REV_WMAC_MAJ 0xf000
1424 +#define AR5312_REV_WMAC_MAJ_S 12
1425 +#define AR5312_REV_WMAC_MIN 0x0f00
1426 +#define AR5312_REV_WMAC_MIN_S 8
1427 +#define AR5312_REV_MAJ 0x00f0
1428 +#define AR5312_REV_MAJ_S 4
1429 +#define AR5312_REV_MIN 0x000f
1430 +#define AR5312_REV_MIN_S 0
1431 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1432 +
1433 +/* Major revision numbers, bits 7..4 of Revision ID register */
1434 +#define AR5312_REV_MAJ_AR5312 0x4
1435 +#define AR5312_REV_MAJ_AR2313 0x5
1436 +
1437 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1438 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1439 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1440 +
1441 +/* AR5312_FLASHCTL register bit field definitions */
1442 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1443 +#define FLASHCTL_IDCY_S 0
1444 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1445 +#define FLASHCTL_WST1_S 5
1446 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1447 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1448 +#define FLASHCTL_WST2_S 11
1449 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1450 +#define FLASHCTL_AC_S 16
1451 +#define FLASHCTL_AC_128K 0x00000000
1452 +#define FLASHCTL_AC_256K 0x00010000
1453 +#define FLASHCTL_AC_512K 0x00020000
1454 +#define FLASHCTL_AC_1M 0x00030000
1455 +#define FLASHCTL_AC_2M 0x00040000
1456 +#define FLASHCTL_AC_4M 0x00050000
1457 +#define FLASHCTL_AC_8M 0x00060000
1458 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1459 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1460 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1461 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1462 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1463 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1464 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1465 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1466 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1467 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1468 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1469 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1470 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1471 +
1472 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1473 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1474 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1475 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1476 +
1477 +/* ARM SDRAM Controller -- just enough to determine memory size */
1478 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1479 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1480 +#define MEM_CFG1_AC0_S 8
1481 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1482 +#define MEM_CFG1_AC1_S 12
1483 +
1484 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1485 +
1486 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1487 --- /dev/null
1488 +++ b/arch/mips/ath25/ar5312.c
1489 @@ -0,0 +1,450 @@
1490 +/*
1491 + * This file is subject to the terms and conditions of the GNU General Public
1492 + * License. See the file "COPYING" in the main directory of this archive
1493 + * for more details.
1494 + *
1495 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1496 + * Copyright (C) 2006 FON Technology, SL.
1497 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1498 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1499 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1500 + */
1501 +
1502 +/*
1503 + * Platform devices for Atheros SoCs
1504 + */
1505 +
1506 +#include <generated/autoconf.h>
1507 +#include <linux/init.h>
1508 +#include <linux/module.h>
1509 +#include <linux/types.h>
1510 +#include <linux/string.h>
1511 +#include <linux/mtd/physmap.h>
1512 +#include <linux/platform_device.h>
1513 +#include <linux/kernel.h>
1514 +#include <linux/reboot.h>
1515 +#include <linux/leds.h>
1516 +#include <linux/gpio.h>
1517 +#include <asm/bootinfo.h>
1518 +#include <asm/reboot.h>
1519 +#include <asm/time.h>
1520 +#include <linux/irq.h>
1521 +#include <linux/io.h>
1522 +
1523 +#include <ath25_platform.h>
1524 +#include <ar5312_regs.h>
1525 +#include <ar231x.h>
1526 +#include "devices.h"
1527 +#include "ar5312.h"
1528 +
1529 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1530 +{
1531 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1532 + ar231x_read_reg(AR5312_IMR);
1533 +
1534 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1535 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1536 + (void)ar231x_read_reg(AR5312_TIMER);
1537 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1538 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1539 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1540 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1541 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1542 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1543 + else
1544 + spurious_interrupt();
1545 +}
1546 +
1547 +static void ar5312_irq_dispatch(void)
1548 +{
1549 + int pending = read_c0_status() & read_c0_cause();
1550 +
1551 + if (pending & CAUSEF_IP2)
1552 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1553 + else if (pending & CAUSEF_IP3)
1554 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1555 + else if (pending & CAUSEF_IP4)
1556 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1557 + else if (pending & CAUSEF_IP5)
1558 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1559 + else if (pending & CAUSEF_IP6)
1560 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1561 + else if (pending & CAUSEF_IP7)
1562 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1563 + else
1564 + spurious_interrupt();
1565 +}
1566 +
1567 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1568 +static void ar5312_misc_irq_unmask(struct irq_data *d)
1569 +{
1570 + unsigned int imr;
1571 +
1572 + imr = ar231x_read_reg(AR5312_IMR);
1573 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1574 + ar231x_write_reg(AR5312_IMR, imr);
1575 +}
1576 +
1577 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1578 +static void ar5312_misc_irq_mask(struct irq_data *d)
1579 +{
1580 + unsigned int imr;
1581 +
1582 + imr = ar231x_read_reg(AR5312_IMR);
1583 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1584 + ar231x_write_reg(AR5312_IMR, imr);
1585 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1586 +}
1587 +
1588 +static struct irq_chip ar5312_misc_irq_chip = {
1589 + .name = "ar5312-misc",
1590 + .irq_unmask = ar5312_misc_irq_unmask,
1591 + .irq_mask = ar5312_misc_irq_mask,
1592 +};
1593 +
1594 +static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
1595 +{
1596 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1597 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1598 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1599 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1600 +
1601 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1602 + proc_addr, proc1, dma_addr, dma1);
1603 +
1604 + machine_restart("AHB error"); /* Catastrophic failure */
1605 + return IRQ_HANDLED;
1606 +}
1607 +
1608 +static struct irqaction ar5312_ahb_err_interrupt = {
1609 + .handler = ar5312_ahb_err_handler,
1610 + .name = "ar5312-ahb-error",
1611 +};
1612 +
1613 +void __init ar5312_arch_init_irq(void)
1614 +{
1615 + int i;
1616 +
1617 + ath25_irq_dispatch = ar5312_irq_dispatch;
1618 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1619 + int irq = AR231X_MISC_IRQ_BASE + i;
1620 +
1621 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1622 + handle_level_irq);
1623 + }
1624 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_err_interrupt);
1625 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1626 +}
1627 +
1628 +static void ar5312_device_reset_set(u32 mask)
1629 +{
1630 + u32 val;
1631 +
1632 + val = ar231x_read_reg(AR5312_RESET);
1633 + ar231x_write_reg(AR5312_RESET, val | mask);
1634 +}
1635 +
1636 +static void ar5312_device_reset_clear(u32 mask)
1637 +{
1638 + u32 val;
1639 +
1640 + val = ar231x_read_reg(AR5312_RESET);
1641 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1642 +}
1643 +
1644 +static struct physmap_flash_data ar5312_flash_data = {
1645 + .width = 2,
1646 +};
1647 +
1648 +static struct resource ar5312_flash_resource = {
1649 + .start = AR5312_FLASH,
1650 + .end = AR5312_FLASH + 0x800000 - 1,
1651 + .flags = IORESOURCE_MEM,
1652 +};
1653 +
1654 +static struct ar231x_eth ar5312_eth0_data = {
1655 + .reset_set = ar5312_device_reset_set,
1656 + .reset_clear = ar5312_device_reset_clear,
1657 + .reset_mac = AR5312_RESET_ENET0,
1658 + .reset_phy = AR5312_RESET_EPHY0,
1659 +};
1660 +
1661 +static struct ar231x_eth ar5312_eth1_data = {
1662 + .reset_set = ar5312_device_reset_set,
1663 + .reset_clear = ar5312_device_reset_clear,
1664 + .reset_mac = AR5312_RESET_ENET1,
1665 + .reset_phy = AR5312_RESET_EPHY1,
1666 +};
1667 +
1668 +static struct platform_device ar5312_physmap_flash = {
1669 + .name = "physmap-flash",
1670 + .id = 0,
1671 + .dev.platform_data = &ar5312_flash_data,
1672 + .resource = &ar5312_flash_resource,
1673 + .num_resources = 1,
1674 +};
1675 +
1676 +#ifdef CONFIG_LEDS_GPIO
1677 +static struct gpio_led ar5312_leds[] = {
1678 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1679 +};
1680 +
1681 +static const struct gpio_led_platform_data ar5312_led_data = {
1682 + .num_leds = ARRAY_SIZE(ar5312_leds),
1683 + .leds = (void *)ar5312_leds,
1684 +};
1685 +
1686 +static struct platform_device ar5312_gpio_leds = {
1687 + .name = "leds-gpio",
1688 + .id = -1,
1689 + .dev.platform_data = (void *)&ar5312_led_data,
1690 +};
1691 +#endif
1692 +
1693 +/*
1694 + * NB: This mapping size is larger than the actual flash size,
1695 + * but this shouldn't be a problem here, because the flash
1696 + * will simply be mapped multiple times.
1697 + */
1698 +static char __init *ar5312_flash_limit(void)
1699 +{
1700 + u32 ctl;
1701 + /*
1702 + * Configure flash bank 0.
1703 + * Assume 8M window size. Flash will be aliased if it's smaller
1704 + */
1705 + ctl = FLASHCTL_E |
1706 + FLASHCTL_AC_8M |
1707 + FLASHCTL_RBLE |
1708 + (0x01 << FLASHCTL_IDCY_S) |
1709 + (0x07 << FLASHCTL_WST1_S) |
1710 + (0x07 << FLASHCTL_WST2_S) |
1711 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1712 +
1713 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1714 +
1715 + /* Disable other flash banks */
1716 + ar231x_write_reg(AR5312_FLASHCTL1,
1717 + ar231x_read_reg(AR5312_FLASHCTL1) &
1718 + ~(FLASHCTL_E | FLASHCTL_AC));
1719 +
1720 + ar231x_write_reg(AR5312_FLASHCTL2,
1721 + ar231x_read_reg(AR5312_FLASHCTL2) &
1722 + ~(FLASHCTL_E | FLASHCTL_AC));
1723 +
1724 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1725 +}
1726 +
1727 +void __init ar5312_init_devices(void)
1728 +{
1729 + struct ath25_boarddata *config;
1730 + u32 fctl = 0;
1731 + u8 *c;
1732 +
1733 + /* Locate board/radio config data */
1734 + ath25_find_config(ar5312_flash_limit());
1735 + config = ath25_board.config;
1736 +
1737 + /* AR2313 has CPU minor rev. 10 */
1738 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1739 + ath25_soc = ATH25_SOC_AR2313;
1740 +
1741 + /* AR2312 shares the same Silicon ID as AR5312 */
1742 + else if (config->flags & BD_ISCASPER)
1743 + ath25_soc = ATH25_SOC_AR2312;
1744 +
1745 + /* Everything else is probably AR5312 or compatible */
1746 + else
1747 + ath25_soc = ATH25_SOC_AR5312;
1748 +
1749 + /* fixup flash width */
1750 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1751 + switch (fctl) {
1752 + case FLASHCTL_MW16:
1753 + ar5312_flash_data.width = 2;
1754 + break;
1755 + case FLASHCTL_MW8:
1756 + default:
1757 + ar5312_flash_data.width = 1;
1758 + break;
1759 + }
1760 +
1761 + platform_device_register(&ar5312_physmap_flash);
1762 +
1763 +#ifdef CONFIG_LEDS_GPIO
1764 + ar5312_leds[0].gpio = config->sys_led_gpio;
1765 + platform_device_register(&ar5312_gpio_leds);
1766 +#endif
1767 +
1768 + /* Fix up MAC addresses if necessary */
1769 + if (is_broadcast_ether_addr(config->enet0_mac))
1770 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1771 +
1772 + /* If ENET0 and ENET1 have the same mac address,
1773 + * increment the one from ENET1 */
1774 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1775 + c = config->enet1_mac + 5;
1776 + while ((c >= config->enet1_mac) && !(++(*c)))
1777 + c--;
1778 + }
1779 +
1780 + switch (ath25_soc) {
1781 + case ATH25_SOC_AR5312:
1782 + ar5312_eth0_data.macaddr = config->enet0_mac;
1783 + ath25_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1784 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1785 + &ar5312_eth0_data);
1786 +
1787 + ar5312_eth1_data.macaddr = config->enet1_mac;
1788 + ath25_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1789 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1790 + &ar5312_eth1_data);
1791 +
1792 + if (!ath25_board.radio)
1793 + return;
1794 +
1795 + if (!(config->flags & BD_WLAN0))
1796 + break;
1797 +
1798 + ath25_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1799 + break;
1800 + /*
1801 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1802 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1803 + */
1804 + case ATH25_SOC_AR2312:
1805 + case ATH25_SOC_AR2313:
1806 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1807 + ar5312_eth1_data.macaddr = config->enet0_mac;
1808 + ath25_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1809 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1810 + &ar5312_eth1_data);
1811 +
1812 + if (!ath25_board.radio)
1813 + return;
1814 + break;
1815 + default:
1816 + break;
1817 + }
1818 +
1819 + if (config->flags & BD_WLAN1)
1820 + ath25_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1821 +}
1822 +
1823 +static void ar5312_restart(char *command)
1824 +{
1825 + /* reset the system */
1826 + local_irq_disable();
1827 + while (1)
1828 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1829 +}
1830 +
1831 +/*
1832 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1833 + * to determine the predevisor value.
1834 + */
1835 +static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1836 +
1837 +static unsigned __init ar5312_cpu_frequency(void)
1838 +{
1839 + unsigned int scratch;
1840 + unsigned int predivide_mask, predivide_shift;
1841 + unsigned int multiplier_mask, multiplier_shift;
1842 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1843 + unsigned int doubler_mask;
1844 + u16 devid;
1845 +
1846 + /* Trust the bootrom's idea of cpu frequency. */
1847 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1848 + if (scratch)
1849 + return scratch;
1850 +
1851 + devid = ar231x_read_reg(AR5312_REV);
1852 + devid &= AR5312_REV_MAJ;
1853 + devid >>= AR5312_REV_MAJ_S;
1854 + if (devid == AR5312_REV_MAJ_AR2313) {
1855 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1856 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1857 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1858 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1859 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1860 + } else { /* AR5312 and AR2312 */
1861 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1862 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1863 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1864 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1865 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1866 + }
1867 +
1868 + /*
1869 + * Clocking is derived from a fixed 40MHz input clock.
1870 + *
1871 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1872 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1873 + * flash, Timer, Watchdog Timer)
1874 + *
1875 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1876 + *
1877 + * So, for example, with a PLL multiplier of 5, we have
1878 + *
1879 + * cpu_freq = 200MHz
1880 + * sys_freq = 50MHz
1881 + * cnt_freq = 100MHz
1882 + *
1883 + * We compute the CPU frequency, based on PLL settings.
1884 + */
1885 +
1886 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
1887 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1888 + predivisor = clockctl1_predivide_table[predivide_select];
1889 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1890 +
1891 + if (clock_ctl1 & doubler_mask)
1892 + multiplier = multiplier << 1;
1893 +
1894 + return (40000000 / predivisor) * multiplier;
1895 +}
1896 +
1897 +static inline unsigned ar5312_sys_frequency(void)
1898 +{
1899 + return ar5312_cpu_frequency() / 4;
1900 +}
1901 +
1902 +void __init ar5312_plat_time_init(void)
1903 +{
1904 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1905 +}
1906 +
1907 +void __init
1908 +ar5312_prom_init(void)
1909 +{
1910 + u32 memsize, memcfg, bank0AC, bank1AC;
1911 + u32 devid;
1912 +
1913 + /* Detect memory size */
1914 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
1915 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1916 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1917 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1918 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1919 + memsize <<= 20;
1920 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1921 +
1922 + devid = ar231x_read_reg(AR5312_REV);
1923 + devid >>= AR5312_REV_WMAC_MIN_S;
1924 + devid &= AR5312_REV_CHIP;
1925 + ath25_board.devid = (u16)devid;
1926 +}
1927 +
1928 +void __init ar5312_plat_mem_setup(void)
1929 +{
1930 + /* Clear any lingering AHB errors */
1931 + ar231x_read_reg(AR5312_PROCADDR);
1932 + ar231x_read_reg(AR5312_DMAADDR);
1933 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
1934 +
1935 + _machine_restart = ar5312_restart;
1936 + ath25_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
1937 + ar5312_sys_frequency());
1938 +}
1939 +
1940 --- /dev/null
1941 +++ b/arch/mips/ath25/ar2315.c
1942 @@ -0,0 +1,401 @@
1943 +/*
1944 + * This file is subject to the terms and conditions of the GNU General Public
1945 + * License. See the file "COPYING" in the main directory of this archive
1946 + * for more details.
1947 + *
1948 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1949 + * Copyright (C) 2006 FON Technology, SL.
1950 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1951 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1952 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1953 + */
1954 +
1955 +/*
1956 + * Platform devices for Atheros SoCs
1957 + */
1958 +
1959 +#include <generated/autoconf.h>
1960 +#include <linux/init.h>
1961 +#include <linux/module.h>
1962 +#include <linux/types.h>
1963 +#include <linux/string.h>
1964 +#include <linux/platform_device.h>
1965 +#include <linux/kernel.h>
1966 +#include <linux/reboot.h>
1967 +#include <linux/delay.h>
1968 +#include <linux/leds.h>
1969 +#include <linux/gpio.h>
1970 +#include <asm/bootinfo.h>
1971 +#include <asm/reboot.h>
1972 +#include <asm/time.h>
1973 +#include <linux/irq.h>
1974 +#include <linux/io.h>
1975 +
1976 +#include <ath25_platform.h>
1977 +#include <ar2315_regs.h>
1978 +#include <ar231x.h>
1979 +#include "devices.h"
1980 +#include "ar2315.h"
1981 +
1982 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1983 +{
1984 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
1985 + ar231x_read_reg(AR2315_IMR);
1986 +
1987 + if (misc_intr & AR2315_ISR_SPI)
1988 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
1989 + else if (misc_intr & AR2315_ISR_TIMER)
1990 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
1991 + else if (misc_intr & AR2315_ISR_AHB)
1992 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
1993 + else if (misc_intr & AR2315_ISR_GPIO) {
1994 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
1995 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
1996 + } else if (misc_intr & AR2315_ISR_UART0)
1997 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
1998 + else if (misc_intr & AR2315_ISR_WD) {
1999 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2000 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
2001 + } else
2002 + spurious_interrupt();
2003 +}
2004 +
2005 +/*
2006 + * Called when an interrupt is received, this function
2007 + * determines exactly which interrupt it was, and it
2008 + * invokes the appropriate handler.
2009 + *
2010 + * Implicitly, we also define interrupt priority by
2011 + * choosing which to dispatch first.
2012 + */
2013 +static void ar2315_irq_dispatch(void)
2014 +{
2015 + int pending = read_c0_status() & read_c0_cause();
2016 +
2017 + if (pending & CAUSEF_IP3)
2018 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2019 + else if (pending & CAUSEF_IP4)
2020 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2021 + else if (pending & CAUSEF_IP2)
2022 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2023 + else if (pending & CAUSEF_IP7)
2024 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2025 + else
2026 + spurious_interrupt();
2027 +}
2028 +
2029 +static void ar2315_misc_irq_unmask(struct irq_data *d)
2030 +{
2031 + unsigned int imr;
2032 +
2033 + imr = ar231x_read_reg(AR2315_IMR);
2034 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
2035 + ar231x_write_reg(AR2315_IMR, imr);
2036 +}
2037 +
2038 +static void ar2315_misc_irq_mask(struct irq_data *d)
2039 +{
2040 + unsigned int imr;
2041 +
2042 + imr = ar231x_read_reg(AR2315_IMR);
2043 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
2044 + ar231x_write_reg(AR2315_IMR, imr);
2045 +}
2046 +
2047 +static struct irq_chip ar2315_misc_irq_chip = {
2048 + .name = "ar2315-misc",
2049 + .irq_unmask = ar2315_misc_irq_unmask,
2050 + .irq_mask = ar2315_misc_irq_mask,
2051 +};
2052 +
2053 +static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
2054 +{
2055 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2056 + ar231x_read_reg(AR2315_AHB_ERR1);
2057 +
2058 + pr_emerg("AHB fatal error\n");
2059 + machine_restart("AHB error"); /* Catastrophic failure */
2060 +
2061 + return IRQ_HANDLED;
2062 +}
2063 +
2064 +static struct irqaction ar2315_ahb_err_interrupt = {
2065 + .handler = ar2315_ahb_err_handler,
2066 + .name = "ar2315-ahb-error",
2067 +};
2068 +
2069 +void __init ar2315_arch_init_irq(void)
2070 +{
2071 + int i;
2072 +
2073 + ath25_irq_dispatch = ar2315_irq_dispatch;
2074 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2075 + int irq = AR231X_MISC_IRQ_BASE + i;
2076 +
2077 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2078 + handle_level_irq);
2079 + }
2080 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_err_interrupt);
2081 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2082 +}
2083 +
2084 +static void ar2315_device_reset_set(u32 mask)
2085 +{
2086 + u32 val;
2087 +
2088 + val = ar231x_read_reg(AR2315_RESET);
2089 + ar231x_write_reg(AR2315_RESET, val | mask);
2090 +}
2091 +
2092 +static void ar2315_device_reset_clear(u32 mask)
2093 +{
2094 + u32 val;
2095 +
2096 + val = ar231x_read_reg(AR2315_RESET);
2097 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2098 +}
2099 +
2100 +static struct ar231x_eth ar2315_eth_data = {
2101 + .reset_set = ar2315_device_reset_set,
2102 + .reset_clear = ar2315_device_reset_clear,
2103 + .reset_mac = AR2315_RESET_ENET0,
2104 + .reset_phy = AR2315_RESET_EPHY0,
2105 +};
2106 +
2107 +static struct resource ar2315_spiflash_res[] = {
2108 + {
2109 + .name = "spiflash_read",
2110 + .flags = IORESOURCE_MEM,
2111 + .start = AR2315_SPI_READ,
2112 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2113 + },
2114 + {
2115 + .name = "spiflash_mmr",
2116 + .flags = IORESOURCE_MEM,
2117 + .start = AR2315_SPI_MMR,
2118 + .end = AR2315_SPI_MMR + 12 - 1,
2119 + },
2120 +};
2121 +
2122 +static struct platform_device ar2315_spiflash = {
2123 + .id = 0,
2124 + .name = "ar2315-spiflash",
2125 + .resource = ar2315_spiflash_res,
2126 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2127 +};
2128 +
2129 +static struct resource ar2315_wdt_res[] = {
2130 + {
2131 + .flags = IORESOURCE_MEM,
2132 + .start = AR2315_WD,
2133 + .end = AR2315_WD + 8 - 1,
2134 + },
2135 + {
2136 + .flags = IORESOURCE_IRQ,
2137 + .start = AR2315_MISC_IRQ_WATCHDOG,
2138 + .end = AR2315_MISC_IRQ_WATCHDOG,
2139 + }
2140 +};
2141 +
2142 +static struct platform_device ar2315_wdt = {
2143 + .id = 0,
2144 + .name = "ar2315-wdt",
2145 + .resource = ar2315_wdt_res,
2146 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2147 +};
2148 +
2149 +/*
2150 + * NB: We use mapping size that is larger than the actual flash size,
2151 + * but this shouldn't be a problem here, because the flash will simply
2152 + * be mapped multiple times.
2153 + */
2154 +static u8 __init *ar2315_flash_limit(void)
2155 +{
2156 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2157 +}
2158 +
2159 +#ifdef CONFIG_LEDS_GPIO
2160 +static struct gpio_led ar2315_leds[6];
2161 +static struct gpio_led_platform_data ar2315_led_data = {
2162 + .leds = (void *)ar2315_leds,
2163 +};
2164 +
2165 +static struct platform_device ar2315_gpio_leds = {
2166 + .name = "leds-gpio",
2167 + .id = -1,
2168 + .dev = {
2169 + .platform_data = (void *)&ar2315_led_data,
2170 + }
2171 +};
2172 +
2173 +static void __init ar2315_init_gpio_leds(void)
2174 +{
2175 + static char led_names[6][6];
2176 + int i, led = 0;
2177 +
2178 + ar2315_led_data.num_leds = 0;
2179 + for (i = 1; i < 8; i++) {
2180 + if ((i == AR2315_RESET_GPIO) ||
2181 + (i == ath25_board.config->reset_config_gpio))
2182 + continue;
2183 +
2184 + if (i == ath25_board.config->sys_led_gpio)
2185 + strcpy(led_names[led], "wlan");
2186 + else
2187 + sprintf(led_names[led], "gpio%d", i);
2188 +
2189 + ar2315_leds[led].name = led_names[led];
2190 + ar2315_leds[led].gpio = i;
2191 + ar2315_leds[led].active_low = 0;
2192 + led++;
2193 + }
2194 + ar2315_led_data.num_leds = led;
2195 + platform_device_register(&ar2315_gpio_leds);
2196 +}
2197 +#else
2198 +static inline void ar2315_init_gpio_leds(void)
2199 +{
2200 +}
2201 +#endif
2202 +
2203 +void __init ar2315_init_devices(void)
2204 +{
2205 + /* Find board configuration */
2206 + ath25_find_config(ar2315_flash_limit());
2207 + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
2208 +
2209 + ar2315_init_gpio_leds();
2210 + platform_device_register(&ar2315_wdt);
2211 + platform_device_register(&ar2315_spiflash);
2212 + ath25_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2213 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2214 + ath25_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2215 +}
2216 +
2217 +static void ar2315_restart(char *command)
2218 +{
2219 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2220 +
2221 + local_irq_disable();
2222 +
2223 + /* try reset the system via reset control */
2224 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2225 +
2226 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2227 + * a workaround. Give it some time to attempt a gpio based hardware
2228 + * reset (atheros reference design workaround) */
2229 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2230 + mdelay(100);
2231 +
2232 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2233 + * workaround. Attempt to jump to the mips reset location -
2234 + * the boot loader itself might be able to recover the system */
2235 + mips_reset_vec();
2236 +}
2237 +
2238 +/*
2239 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2240 + * to determine the predevisor value.
2241 + */
2242 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2243 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2244 +
2245 +static unsigned __init ar2315_sys_clk(u32 clock_ctl)
2246 +{
2247 + unsigned int pllc_ctrl, cpu_div;
2248 + unsigned int pllc_out, refdiv, fdiv, divby2;
2249 + unsigned int clk_div;
2250 +
2251 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2252 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2253 + refdiv = clockctl1_predivide_table[refdiv];
2254 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2255 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2256 + divby2 += 1;
2257 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2258 +
2259 + /* clkm input selected */
2260 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2261 + case 0:
2262 + case 1:
2263 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2264 + PLLC_CLKM_DIV_S];
2265 + break;
2266 + case 2:
2267 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2268 + PLLC_CLKC_DIV_S];
2269 + break;
2270 + default:
2271 + pllc_out = 40000000;
2272 + clk_div = 1;
2273 + break;
2274 + }
2275 +
2276 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2277 + cpu_div = cpu_div * 2 ?: 1;
2278 +
2279 + return pllc_out / (clk_div * cpu_div);
2280 +}
2281 +
2282 +static inline unsigned ar2315_cpu_frequency(void)
2283 +{
2284 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2285 +}
2286 +
2287 +static inline unsigned ar2315_apb_frequency(void)
2288 +{
2289 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2290 +}
2291 +
2292 +void __init ar2315_plat_time_init(void)
2293 +{
2294 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2295 +}
2296 +
2297 +void __init
2298 +ar2315_prom_init(void)
2299 +{
2300 + u32 memsize, memcfg, devid;
2301 +
2302 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2303 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2304 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2305 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2306 + memsize <<= 3;
2307 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2308 +
2309 + /* Detect the hardware based on the device ID */
2310 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2311 + switch (devid) {
2312 + case 0x91: /* Need to check */
2313 + ath25_soc = ATH25_SOC_AR2318;
2314 + break;
2315 + case 0x90:
2316 + ath25_soc = ATH25_SOC_AR2317;
2317 + break;
2318 + case 0x87:
2319 + ath25_soc = ATH25_SOC_AR2316;
2320 + break;
2321 + case 0x86:
2322 + default:
2323 + ath25_soc = ATH25_SOC_AR2315;
2324 + break;
2325 + }
2326 + ath25_board.devid = devid;
2327 +}
2328 +
2329 +void __init ar2315_plat_mem_setup(void)
2330 +{
2331 + u32 config;
2332 +
2333 + /* Clear any lingering AHB errors */
2334 + config = read_c0_config();
2335 + write_c0_config(config & ~0x3);
2336 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2337 + ar231x_read_reg(AR2315_AHB_ERR1);
2338 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2339 +
2340 + _machine_restart = ar2315_restart;
2341 + ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2342 + ar2315_apb_frequency());
2343 +}
2344 --- /dev/null
2345 +++ b/arch/mips/ath25/ar2315.h
2346 @@ -0,0 +1,36 @@
2347 +#ifndef __AR2315_H
2348 +#define __AR2315_H
2349 +
2350 +#ifdef CONFIG_SOC_AR2315
2351 +
2352 +void ar2315_arch_init_irq(void);
2353 +void ar2315_init_devices(void);
2354 +void ar2315_plat_time_init(void);
2355 +void ar2315_prom_init(void);
2356 +void ar2315_plat_mem_setup(void);
2357 +
2358 +#else
2359 +
2360 +static inline void ar2315_arch_init_irq(void)
2361 +{
2362 +}
2363 +
2364 +static inline void ar2315_init_devices(void)
2365 +{
2366 +}
2367 +
2368 +static inline void ar2315_plat_time_init(void)
2369 +{
2370 +}
2371 +
2372 +static inline void ar2315_prom_init(void)
2373 +{
2374 +}
2375 +
2376 +static inline void ar2315_plat_mem_setup(void)
2377 +{
2378 +}
2379 +
2380 +#endif
2381 +
2382 +#endif
2383 --- /dev/null
2384 +++ b/arch/mips/ath25/ar5312.h
2385 @@ -0,0 +1,36 @@
2386 +#ifndef __AR5312_H
2387 +#define __AR5312_H
2388 +
2389 +#ifdef CONFIG_SOC_AR5312
2390 +
2391 +void ar5312_arch_init_irq(void);
2392 +void ar5312_init_devices(void);
2393 +void ar5312_plat_time_init(void);
2394 +void ar5312_prom_init(void);
2395 +void ar5312_plat_mem_setup(void);
2396 +
2397 +#else
2398 +
2399 +static inline void ar5312_arch_init_irq(void)
2400 +{
2401 +}
2402 +
2403 +static inline void ar5312_init_devices(void)
2404 +{
2405 +}
2406 +
2407 +static inline void ar5312_plat_time_init(void)
2408 +{
2409 +}
2410 +
2411 +static inline void ar5312_prom_init(void)
2412 +{
2413 +}
2414 +
2415 +static inline void ar5312_plat_mem_setup(void)
2416 +{
2417 +}
2418 +
2419 +#endif
2420 +
2421 +#endif
2422 --- /dev/null
2423 +++ b/arch/mips/include/asm/mach-ath25/ar231x.h
2424 @@ -0,0 +1,38 @@
2425 +#ifndef __ASM_MACH_ATH25_AR231X_H
2426 +#define __ASM_MACH_ATH25_AR231X_H
2427 +
2428 +#include <linux/types.h>
2429 +#include <linux/io.h>
2430 +
2431 +#define AR231X_MISC_IRQ_BASE 0x20
2432 +#define AR231X_GPIO_IRQ_BASE 0x30
2433 +
2434 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2435 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2436 +
2437 +static inline u32
2438 +ar231x_read_reg(u32 reg)
2439 +{
2440 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2441 +}
2442 +
2443 +static inline void
2444 +ar231x_write_reg(u32 reg, u32 val)
2445 +{
2446 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2447 +}
2448 +
2449 +static inline u32
2450 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2451 +{
2452 + u32 ret;
2453 +
2454 + ret = ar231x_read_reg(reg);
2455 + ret &= ~mask;
2456 + ret |= val;
2457 + ar231x_write_reg(reg, ret);
2458 +
2459 + return ret;
2460 +}
2461 +
2462 +#endif /* __ASM_MACH_ATH25_AR231X_H */
2463 --- /dev/null
2464 +++ b/arch/mips/ath25/devices.h
2465 @@ -0,0 +1,39 @@
2466 +#ifndef __ATH25_DEVICES_H
2467 +#define __ATH25_DEVICES_H
2468 +
2469 +enum ath25_soc_type {
2470 + /* handled by ar5312.c */
2471 + ATH25_SOC_AR2312,
2472 + ATH25_SOC_AR2313,
2473 + ATH25_SOC_AR5312,
2474 +
2475 + /* handled by ar2315.c */
2476 + ATH25_SOC_AR2315,
2477 + ATH25_SOC_AR2316,
2478 + ATH25_SOC_AR2317,
2479 + ATH25_SOC_AR2318,
2480 +
2481 + ATH25_SOC_UNKNOWN
2482 +};
2483 +
2484 +extern enum ath25_soc_type ath25_soc;
2485 +extern struct ar231x_board_config ath25_board;
2486 +extern void (*ath25_irq_dispatch)(void);
2487 +
2488 +int ath25_find_config(u8 *flash_limit);
2489 +int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2490 + int irq, void *pdata);
2491 +void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2492 +int ath25_add_wmac(int nr, u32 base, int irq);
2493 +
2494 +static inline bool is_ar2315(void)
2495 +{
2496 + return (current_cpu_data.cputype == CPU_4KEC);
2497 +}
2498 +
2499 +static inline bool is_ar5312(void)
2500 +{
2501 + return !is_ar2315();
2502 +}
2503 +
2504 +#endif
2505 --- /dev/null
2506 +++ b/arch/mips/ath25/devices.c
2507 @@ -0,0 +1,180 @@
2508 +#include <linux/kernel.h>
2509 +#include <linux/init.h>
2510 +#include <linux/serial.h>
2511 +#include <linux/serial_core.h>
2512 +#include <linux/serial_8250.h>
2513 +#include <linux/platform_device.h>
2514 +#include <asm/bootinfo.h>
2515 +
2516 +#include <ath25_platform.h>
2517 +#include <ar231x.h>
2518 +#include "devices.h"
2519 +#include "ar5312.h"
2520 +#include "ar2315.h"
2521 +
2522 +struct ar231x_board_config ath25_board;
2523 +enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
2524 +
2525 +static struct resource ath25_eth0_res[] = {
2526 + {
2527 + .name = "eth0_membase",
2528 + .flags = IORESOURCE_MEM,
2529 + },
2530 + {
2531 + .name = "eth0_mii",
2532 + .flags = IORESOURCE_MEM,
2533 + },
2534 + {
2535 + .name = "eth0_irq",
2536 + .flags = IORESOURCE_IRQ,
2537 + }
2538 +};
2539 +
2540 +static struct resource ath25_eth1_res[] = {
2541 + {
2542 + .name = "eth1_membase",
2543 + .flags = IORESOURCE_MEM,
2544 + },
2545 + {
2546 + .name = "eth1_mii",
2547 + .flags = IORESOURCE_MEM,
2548 + },
2549 + {
2550 + .name = "eth1_irq",
2551 + .flags = IORESOURCE_IRQ,
2552 + }
2553 +};
2554 +
2555 +static struct platform_device ath25_eth[] = {
2556 + {
2557 + .id = 0,
2558 + .name = "ar231x-eth",
2559 + .resource = ath25_eth0_res,
2560 + .num_resources = ARRAY_SIZE(ath25_eth0_res)
2561 + },
2562 + {
2563 + .id = 1,
2564 + .name = "ar231x-eth",
2565 + .resource = ath25_eth1_res,
2566 + .num_resources = ARRAY_SIZE(ath25_eth1_res)
2567 + }
2568 +};
2569 +
2570 +static struct resource ath25_wmac0_res[] = {
2571 + {
2572 + .name = "wmac0_membase",
2573 + .flags = IORESOURCE_MEM,
2574 + },
2575 + {
2576 + .name = "wmac0_irq",
2577 + .flags = IORESOURCE_IRQ,
2578 + }
2579 +};
2580 +
2581 +static struct resource ath25_wmac1_res[] = {
2582 + {
2583 + .name = "wmac1_membase",
2584 + .flags = IORESOURCE_MEM,
2585 + },
2586 + {
2587 + .name = "wmac1_irq",
2588 + .flags = IORESOURCE_IRQ,
2589 + }
2590 +};
2591 +
2592 +static struct platform_device ath25_wmac[] = {
2593 + {
2594 + .id = 0,
2595 + .name = "ar231x-wmac",
2596 + .resource = ath25_wmac0_res,
2597 + .num_resources = ARRAY_SIZE(ath25_wmac0_res),
2598 + .dev.platform_data = &ath25_board,
2599 + },
2600 + {
2601 + .id = 1,
2602 + .name = "ar231x-wmac",
2603 + .resource = ath25_wmac1_res,
2604 + .num_resources = ARRAY_SIZE(ath25_wmac1_res),
2605 + .dev.platform_data = &ath25_board,
2606 + },
2607 +};
2608 +
2609 +static const char * const soc_type_strings[] = {
2610 + [ATH25_SOC_AR5312] = "Atheros AR5312",
2611 + [ATH25_SOC_AR2312] = "Atheros AR2312",
2612 + [ATH25_SOC_AR2313] = "Atheros AR2313",
2613 + [ATH25_SOC_AR2315] = "Atheros AR2315",
2614 + [ATH25_SOC_AR2316] = "Atheros AR2316",
2615 + [ATH25_SOC_AR2317] = "Atheros AR2317",
2616 + [ATH25_SOC_AR2318] = "Atheros AR2318",
2617 + [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
2618 +};
2619 +
2620 +const char *get_system_type(void)
2621 +{
2622 + if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
2623 + !soc_type_strings[ath25_soc])
2624 + return soc_type_strings[ATH25_SOC_UNKNOWN];
2625 + return soc_type_strings[ath25_soc];
2626 +}
2627 +
2628 +int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
2629 + u32 mii_base, int irq, void *pdata)
2630 +{
2631 + struct resource *res;
2632 +
2633 + ath25_eth[nr].dev.platform_data = pdata;
2634 + res = &ath25_eth[nr].resource[0];
2635 + res->start = base;
2636 + res->end = base + 0x2000 - 1;
2637 + res++;
2638 + res->name = mii_name;
2639 + res->start = mii_base;
2640 + res->end = mii_base + 8 - 1;
2641 + res++;
2642 + res->start = irq;
2643 + res->end = irq;
2644 + return platform_device_register(&ath25_eth[nr]);
2645 +}
2646 +
2647 +void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2648 +{
2649 + struct uart_port s;
2650 +
2651 + memset(&s, 0, sizeof(s));
2652 +
2653 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2654 + s.iotype = UPIO_MEM32;
2655 + s.irq = irq;
2656 + s.regshift = 2;
2657 + s.mapbase = mapbase;
2658 + s.uartclk = uartclk;
2659 +
2660 + early_serial_setup(&s);
2661 +}
2662 +
2663 +int __init ath25_add_wmac(int nr, u32 base, int irq)
2664 +{
2665 + struct resource *res;
2666 +
2667 + ath25_wmac[nr].dev.platform_data = &ath25_board;
2668 + res = &ath25_wmac[nr].resource[0];
2669 + res->start = base;
2670 + res->end = base + 0x10000 - 1;
2671 + res++;
2672 + res->start = irq;
2673 + res->end = irq;
2674 + return platform_device_register(&ath25_wmac[nr]);
2675 +}
2676 +
2677 +static int __init ath25_register_devices(void)
2678 +{
2679 + if (is_ar5312())
2680 + ar5312_init_devices();
2681 + else
2682 + ar2315_init_devices();
2683 +
2684 + return 0;
2685 +}
2686 +
2687 +device_initcall(ath25_register_devices);
Staging tree of florian