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[openwrt/staging/florian.git] / target / linux / coldfire / patches / 023-Replace-readl-and-writel-for-FEC-driver.patch
1 From f7df9a8f3ce3a600ceeb7302bf0de899f321c818 Mon Sep 17 00:00:00 2001
2 From: Alison Wang <b18965@freescale.com>
3 Date: Thu, 4 Aug 2011 09:59:45 +0800
4 Subject: [PATCH 23/52] Replace readl and writel for FEC driver
5
6 Replace readl and writel by fec_readl and fec_writel
7 for FEC driver.
8
9 Signed-off-by: Alison Wang <b18965@freescale.com>
10 ---
11 drivers/net/fec.c | 129 ++++++++++++++++++++++++++++-------------------------
12 1 files changed, 68 insertions(+), 61 deletions(-)
13
14 --- a/drivers/net/fec.c
15 +++ b/drivers/net/fec.c
16 @@ -244,6 +244,11 @@ static void fec_stop(struct net_device *
17 /* Transmitter timeout */
18 #define TX_TIMEOUT (2 * HZ)
19
20 +#define fec_readl(addr) \
21 + ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
22 +#define fec_writel(b, addr) \
23 + (void)((*(volatile unsigned int *) (addr)) = (b))
24 +
25 static void *swap_buffer(void *bufaddr, int len)
26 {
27 int i;
28 @@ -347,7 +352,7 @@ fec_enet_start_xmit(struct sk_buff *skb,
29 bdp->cbd_sc = status;
30
31 /* Trigger transmission start */
32 - writel(0, fep->hwp + FEC_X_DES_ACTIVE);
33 + fec_writel(0, fep->hwp + FEC_X_DES_ACTIVE);
34
35 /* If this was the last BD in the ring, start at the beginning again. */
36 if (status & BD_ENET_TX_WRAP)
37 @@ -390,8 +395,8 @@ fec_enet_interrupt(int irq, void * dev_i
38 irqreturn_t ret = IRQ_NONE;
39
40 do {
41 - int_events = readl(fep->hwp + FEC_IEVENT);
42 - writel(int_events, fep->hwp + FEC_IEVENT);
43 + int_events = fec_readl(fep->hwp + FEC_IEVENT);
44 + fec_writel(int_events, fep->hwp + FEC_IEVENT);
45
46 #ifdef CONFIG_FEC_1588
47 if (__raw_readb(MCF_DTIM1_DTER) & MCF_DTIM_DTER_REF)
48 @@ -646,7 +651,7 @@ rx_processing_done:
49 * incoming frames. On a heavily loaded network, we should be
50 * able to keep up at the expense of system resources.
51 */
52 - writel(0, fep->hwp + FEC_R_DES_ACTIVE);
53 + fec_writel(0, fep->hwp + FEC_R_DES_ACTIVE);
54 }
55 fep->cur_rx = bdp;
56
57 @@ -686,9 +691,9 @@ static void __inline__ fec_get_mac(struc
58 */
59 if (!is_valid_ether_addr(iap)) {
60 *((unsigned long *) &tmpaddr[0]) =
61 - be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
62 + be32_to_cpu(fec_readl(fep->hwp + FEC_ADDR_LOW));
63 *((unsigned short *) &tmpaddr[4]) =
64 - be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
65 + be16_to_cpu(fec_readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
66 iap = &tmpaddr[0];
67 }
68
69 @@ -740,9 +745,9 @@ static void fec_enet_adjust_link(struct
70
71 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
72 #ifdef CONFIG_FEC_1588
73 - writel(0x00000012, fep->hwp + FEC_ECNTRL);
74 + fec_writel(0x00000012, fep->hwp + FEC_ECNTRL);
75 #else
76 - writel(0x00000002, fep->hwp + FEC_ECNTRL);
77 + fec_writel(0x00000002, fep->hwp + FEC_ECNTRL);
78 #endif
79 status_change = 1;
80 }
81 @@ -763,7 +768,7 @@ static int fec_enet_mdio_read(struct mii
82 init_completion(&fep->mdio_done);
83
84 /* start a read op */
85 - writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
86 + fec_writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
87 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
88 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
89
90 @@ -777,7 +782,7 @@ static int fec_enet_mdio_read(struct mii
91 }
92
93 /* return value */
94 - return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
95 + return FEC_MMFR_DATA(fec_readl(fep->hwp + FEC_MII_DATA));
96 }
97
98 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
99 @@ -790,7 +795,7 @@ static int fec_enet_mdio_write(struct mi
100 init_completion(&fep->mdio_done);
101
102 /* start a write op */
103 - writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
104 + fec_writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
105 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
106 FEC_MMFR_TA | FEC_MMFR_DATA(value),
107 fep->hwp + FEC_MII_DATA);
108 @@ -905,7 +910,7 @@ static int fec_enet_mii_init(struct plat
109 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
110 */
111 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
112 - writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
113 + fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
114
115 fep->mii_bus = mdiobus_alloc();
116 if (fep->mii_bus == NULL) {
117 @@ -1151,30 +1156,30 @@ static void set_multicast_list(struct ne
118 unsigned char hash;
119
120 if (dev->flags & IFF_PROMISC) {
121 - tmp = readl(fep->hwp + FEC_R_CNTRL);
122 + tmp = fec_readl(fep->hwp + FEC_R_CNTRL);
123 tmp |= 0x8;
124 - writel(tmp, fep->hwp + FEC_R_CNTRL);
125 + fec_writel(tmp, fep->hwp + FEC_R_CNTRL);
126 return;
127 }
128
129 - tmp = readl(fep->hwp + FEC_R_CNTRL);
130 + tmp = fec_readl(fep->hwp + FEC_R_CNTRL);
131 tmp &= ~0x8;
132 - writel(tmp, fep->hwp + FEC_R_CNTRL);
133 + fec_writel(tmp, fep->hwp + FEC_R_CNTRL);
134
135 if (dev->flags & IFF_ALLMULTI) {
136 /* Catch all multicast addresses, so set the
137 * filter to all 1's
138 */
139 - writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
140 - writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
141 + fec_writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
142 + fec_writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
143
144 return;
145 }
146
147 /* Clear filter and add the addresses in hash register
148 */
149 - writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
150 - writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
151 + fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
152 + fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
153
154 netdev_for_each_mc_addr(ha, dev) {
155 /* Only support group multicast for now */
156 @@ -1198,13 +1203,13 @@ static void set_multicast_list(struct ne
157 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
158
159 if (hash > 31) {
160 - tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
161 + tmp = fec_readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
162 tmp |= 1 << (hash - 32);
163 - writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
164 + fec_writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
165 } else {
166 - tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
167 + tmp = fec_readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
168 tmp |= 1 << hash;
169 - writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
170 + fec_writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
171 }
172 }
173 }
174 @@ -1221,10 +1226,10 @@ fec_set_mac_address(struct net_device *d
175
176 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
177
178 - writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
179 + fec_writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
180 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
181 fep->hwp + FEC_ADDR_LOW);
182 - writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
183 + fec_writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
184 fep->hwp + FEC_ADDR_HIGH);
185 return 0;
186 }
187 @@ -1323,7 +1328,7 @@ fec_restart(struct net_device *dev, int
188 u32 val, temp_mac[2];
189
190 /* Whack a reset. We should wait for this. */
191 - writel(1, fep->hwp + FEC_ECNTRL);
192 + fec_writel(1, fep->hwp + FEC_ECNTRL);
193 udelay(10);
194
195 /*
196 @@ -1332,31 +1337,32 @@ fec_restart(struct net_device *dev, int
197 */
198 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
199 memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
200 - writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
201 - writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
202 + fec_writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
203 + fec_writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
204 }
205
206 #ifdef CONFIG_FEC_1588
207 - writel(0x7fff8000, fep->hwp + FEC_IEVENT);
208 + fec_writel(0x7fff8000, fep->hwp + FEC_IEVENT);
209 #else
210 /* Clear any outstanding interrupt. */
211 - writel(0xffc00000, fep->hwp + FEC_IEVENT);
212 + fec_writel(0xffc00000, fep->hwp + FEC_IEVENT);
213 #endif
214
215 /* Reset all multicast. */
216 - writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
217 - writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
218 + fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
219 + fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
220 #ifndef CONFIG_M5272
221 - writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
222 - writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
223 + fec_writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
224 + fec_writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
225 #endif
226
227 /* Set maximum receive buffer size. */
228 - writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
229 + fec_writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
230
231 /* Set receive and transmit descriptor base. */
232 - writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
233 - writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
234 + fec_writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
235 + fec_writel((unsigned long)fep->bd_dma +
236 + sizeof(struct bufdesc) * RX_RING_SIZE,
237 fep->hwp + FEC_X_DES_START);
238
239 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
240 @@ -1374,24 +1380,24 @@ fec_restart(struct net_device *dev, int
241 /* Enable MII mode */
242 if (duplex) {
243 /* MII enable / FD enable */
244 - writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
245 - writel(0x04, fep->hwp + FEC_X_CNTRL);
246 + fec_writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
247 + fec_writel(0x04, fep->hwp + FEC_X_CNTRL);
248 } else {
249 /* MII enable / No Rcv on Xmit */
250 - writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
251 - writel(0x0, fep->hwp + FEC_X_CNTRL);
252 + fec_writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
253 + fec_writel(0x0, fep->hwp + FEC_X_CNTRL);
254 }
255 fep->full_duplex = duplex;
256
257 /* Set MII speed */
258 - writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
259 + fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
260
261 /*
262 * The phy interface and speed need to get configured
263 * differently on enet-mac.
264 */
265 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
266 - val = readl(fep->hwp + FEC_R_CNTRL);
267 + val = fec_readl(fep->hwp + FEC_R_CNTRL);
268
269 /* MII or RMII */
270 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
271 @@ -1405,23 +1411,23 @@ fec_restart(struct net_device *dev, int
272 else
273 val |= (1 << 9);
274
275 - writel(val, fep->hwp + FEC_R_CNTRL);
276 + fec_writel(val, fep->hwp + FEC_R_CNTRL);
277 } else {
278 #ifdef FEC_MIIGSK_ENR
279 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
280 /* disable the gasket and wait */
281 - writel(0, fep->hwp + FEC_MIIGSK_ENR);
282 - while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
283 + fec_writel(0, fep->hwp + FEC_MIIGSK_ENR);
284 + while (fec_readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
285 udelay(1);
286
287 /*
288 * configure the gasket:
289 * RMII, 50 MHz, no loopback, no echo
290 */
291 - writel(1, fep->hwp + FEC_MIIGSK_CFGR);
292 + fec_writel(1, fep->hwp + FEC_MIIGSK_CFGR);
293
294 /* re-enable the gasket */
295 - writel(2, fep->hwp + FEC_MIIGSK_ENR);
296 + fec_writel(2, fep->hwp + FEC_MIIGSK_ENR);
297 }
298 #endif
299 }
300 @@ -1433,22 +1439,22 @@ fec_restart(struct net_device *dev, int
301 ret = fec_ptp_start(fep->ptp_priv);
302 if (ret) {
303 fep->ptimer_present = 0;
304 - writel(2, fep->hwp + FEC_ECNTRL);
305 + fec_writel(2, fep->hwp + FEC_ECNTRL);
306 } else {
307 - val = readl(fep->hwp + FEC_ECNTRL);
308 + val = fec_readl(fep->hwp + FEC_ECNTRL);
309 val |= 0x00000012;
310 - writel(val, fep->hwp + FEC_ECNTRL);
311 + fec_writel(val, fep->hwp + FEC_ECNTRL);
312 }
313 } else
314 - writel(2, fep->hwp + FEC_ECNTRL);
315 + fec_writel(2, fep->hwp + FEC_ECNTRL);
316 #else
317 /* And last, enable the transmit and receive processing */
318 - writel(2, fep->hwp + FEC_ECNTRL);
319 + fec_writel(2, fep->hwp + FEC_ECNTRL);
320 #endif
321 - writel(0, fep->hwp + FEC_R_DES_ACTIVE);
322 + fec_writel(0, fep->hwp + FEC_R_DES_ACTIVE);
323
324 /* Enable interrupts we wish to service */
325 - writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
326 + fec_writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
327 }
328
329 static void
330 @@ -1458,21 +1464,22 @@ fec_stop(struct net_device *dev)
331
332 /* We cannot expect a graceful transmit stop without link !!! */
333 if (fep->link) {
334 - writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
335 + /* Graceful transmit stop */
336 + fec_writel(1, fep->hwp + FEC_X_CNTRL);
337 udelay(10);
338 - if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
339 + if (!(fec_readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
340 printk("fec_stop : Graceful transmit stop did not complete !\n");
341 }
342
343 /* Whack a reset. We should wait for this. */
344 - writel(1, fep->hwp + FEC_ECNTRL);
345 + fec_writel(1, fep->hwp + FEC_ECNTRL);
346 udelay(10);
347 - writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
348 + fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
349 #ifdef CONFIG_FEC_1588
350 if (fep->ptimer_present)
351 fec_ptp_stop(fep->ptp_priv);
352 #endif
353 - writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
354 + fec_writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
355 }
356
357 static int __devinit