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kernel: update bcma and ssb to version master-2012-04-12 from wireless-testing
[openwrt/staging/florian.git] / target / linux / generic / patches-2.6.36 / 941-ssb_update.patch
1 --- a/drivers/ssb/main.c
2 +++ b/drivers/ssb/main.c
3 @@ -3,7 +3,7 @@
4 * Subsystem core
5 *
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12 @@ -12,6 +12,7 @@
13
14 #include <linux/delay.h>
15 #include <linux/io.h>
16 +#include <linux/module.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 @@ -140,19 +141,6 @@ static void ssb_device_put(struct ssb_de
21 put_device(dev->dev);
22 }
23
24 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
25 -{
26 - if (drv)
27 - get_driver(&drv->drv);
28 - return drv;
29 -}
30 -
31 -static inline void ssb_driver_put(struct ssb_driver *drv)
32 -{
33 - if (drv)
34 - put_driver(&drv->drv);
35 -}
36 -
37 static int ssb_device_resume(struct device *dev)
38 {
39 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
40 @@ -250,11 +238,9 @@ int ssb_devices_freeze(struct ssb_bus *b
41 ssb_device_put(sdev);
42 continue;
43 }
44 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
45 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
46 - ssb_device_put(sdev);
47 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
48 + if (SSB_WARN_ON(!sdrv->remove))
49 continue;
50 - }
51 sdrv->remove(sdev);
52 ctx->device_frozen[i] = 1;
53 }
54 @@ -293,7 +279,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
55 dev_name(sdev->dev));
56 result = err;
57 }
58 - ssb_driver_put(sdrv);
59 ssb_device_put(sdev);
60 }
61
62 @@ -384,6 +369,35 @@ static int ssb_device_uevent(struct devi
63 ssb_dev->id.revision);
64 }
65
66 +#define ssb_config_attr(attrib, field, format_string) \
67 +static ssize_t \
68 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
69 +{ \
70 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
71 +}
72 +
73 +ssb_config_attr(core_num, core_index, "%u\n")
74 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
75 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
76 +ssb_config_attr(revision, id.revision, "%u\n")
77 +ssb_config_attr(irq, irq, "%u\n")
78 +static ssize_t
79 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
80 +{
81 + return sprintf(buf, "%s\n",
82 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
83 +}
84 +
85 +static struct device_attribute ssb_device_attrs[] = {
86 + __ATTR_RO(name),
87 + __ATTR_RO(core_num),
88 + __ATTR_RO(coreid),
89 + __ATTR_RO(vendor),
90 + __ATTR_RO(revision),
91 + __ATTR_RO(irq),
92 + __ATTR_NULL,
93 +};
94 +
95 static struct bus_type ssb_bustype = {
96 .name = "ssb",
97 .match = ssb_bus_match,
98 @@ -393,6 +407,7 @@ static struct bus_type ssb_bustype = {
99 .suspend = ssb_device_suspend,
100 .resume = ssb_device_resume,
101 .uevent = ssb_device_uevent,
102 + .dev_attrs = ssb_device_attrs,
103 };
104
105 static void ssb_buses_lock(void)
106 @@ -528,7 +543,7 @@ error:
107 }
108
109 /* Needs ssb_buses_lock() */
110 -static int ssb_attach_queued_buses(void)
111 +static int __devinit ssb_attach_queued_buses(void)
112 {
113 struct ssb_bus *bus, *n;
114 int err = 0;
115 @@ -739,9 +754,9 @@ out:
116 return err;
117 }
118
119 -static int ssb_bus_register(struct ssb_bus *bus,
120 - ssb_invariants_func_t get_invariants,
121 - unsigned long baseaddr)
122 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
123 + ssb_invariants_func_t get_invariants,
124 + unsigned long baseaddr)
125 {
126 int err;
127
128 @@ -822,8 +837,8 @@ err_disable_xtal:
129 }
130
131 #ifdef CONFIG_SSB_PCIHOST
132 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
133 - struct pci_dev *host_pci)
134 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
135 + struct pci_dev *host_pci)
136 {
137 int err;
138
139 @@ -846,9 +861,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
140 #endif /* CONFIG_SSB_PCIHOST */
141
142 #ifdef CONFIG_SSB_PCMCIAHOST
143 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
144 - struct pcmcia_device *pcmcia_dev,
145 - unsigned long baseaddr)
146 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
147 + struct pcmcia_device *pcmcia_dev,
148 + unsigned long baseaddr)
149 {
150 int err;
151
152 @@ -868,8 +883,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
153 #endif /* CONFIG_SSB_PCMCIAHOST */
154
155 #ifdef CONFIG_SSB_SDIOHOST
156 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
157 - unsigned int quirks)
158 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
159 + struct sdio_func *func,
160 + unsigned int quirks)
161 {
162 int err;
163
164 @@ -889,9 +905,9 @@ int ssb_bus_sdiobus_register(struct ssb_
165 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
166 #endif /* CONFIG_SSB_PCMCIAHOST */
167
168 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
169 - unsigned long baseaddr,
170 - ssb_invariants_func_t get_invariants)
171 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
172 + unsigned long baseaddr,
173 + ssb_invariants_func_t get_invariants)
174 {
175 int err;
176
177 @@ -972,8 +988,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
178 switch (plltype) {
179 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
180 if (m & SSB_CHIPCO_CLK_T6_MMASK)
181 - return SSB_CHIPCO_CLK_T6_M0;
182 - return SSB_CHIPCO_CLK_T6_M1;
183 + return SSB_CHIPCO_CLK_T6_M1;
184 + return SSB_CHIPCO_CLK_T6_M0;
185 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
186 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
187 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
188 @@ -1063,6 +1079,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
189 u32 plltype;
190 u32 clkctl_n, clkctl_m;
191
192 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
193 + return ssb_pmu_get_controlclock(&bus->chipco);
194 +
195 if (ssb_extif_available(&bus->extif))
196 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
197 &clkctl_n, &clkctl_m);
198 @@ -1088,23 +1107,22 @@ static u32 ssb_tmslow_reject_bitmask(str
199 {
200 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
201
202 - /* The REJECT bit changed position in TMSLOW between
203 - * Backplane revisions. */
204 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
205 switch (rev) {
206 case SSB_IDLOW_SSBREV_22:
207 - return SSB_TMSLOW_REJECT_22;
208 + case SSB_IDLOW_SSBREV_24:
209 + case SSB_IDLOW_SSBREV_26:
210 + return SSB_TMSLOW_REJECT;
211 case SSB_IDLOW_SSBREV_23:
212 return SSB_TMSLOW_REJECT_23;
213 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
214 - case SSB_IDLOW_SSBREV_25: /* same here */
215 - case SSB_IDLOW_SSBREV_26: /* same here */
216 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
217 case SSB_IDLOW_SSBREV_27: /* same here */
218 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
219 + return SSB_TMSLOW_REJECT; /* this is a guess */
220 default:
221 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
222 WARN_ON(1);
223 }
224 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
225 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
226 }
227
228 int ssb_device_is_enabled(struct ssb_device *dev)
229 @@ -1163,10 +1181,10 @@ void ssb_device_enable(struct ssb_device
230 }
231 EXPORT_SYMBOL(ssb_device_enable);
232
233 -/* Wait for a bit in a register to get set or unset.
234 +/* Wait for bitmask in a register to get set or cleared.
235 * timeout is in units of ten-microseconds */
236 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
237 - int timeout, int set)
238 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
239 + int timeout, int set)
240 {
241 int i;
242 u32 val;
243 @@ -1174,7 +1192,7 @@ static int ssb_wait_bit(struct ssb_devic
244 for (i = 0; i < timeout; i++) {
245 val = ssb_read32(dev, reg);
246 if (set) {
247 - if (val & bitmask)
248 + if ((val & bitmask) == bitmask)
249 return 0;
250 } else {
251 if (!(val & bitmask))
252 @@ -1191,20 +1209,38 @@ static int ssb_wait_bit(struct ssb_devic
253
254 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
255 {
256 - u32 reject;
257 + u32 reject, val;
258
259 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
260 return;
261
262 reject = ssb_tmslow_reject_bitmask(dev);
263 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
264 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
265 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
266 - ssb_write32(dev, SSB_TMSLOW,
267 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
268 - reject | SSB_TMSLOW_RESET |
269 - core_specific_flags);
270 - ssb_flush_tmslow(dev);
271 +
272 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
273 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
274 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
275 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
276 +
277 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
278 + val = ssb_read32(dev, SSB_IMSTATE);
279 + val |= SSB_IMSTATE_REJECT;
280 + ssb_write32(dev, SSB_IMSTATE, val);
281 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
282 + 0);
283 + }
284 +
285 + ssb_write32(dev, SSB_TMSLOW,
286 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
287 + reject | SSB_TMSLOW_RESET |
288 + core_specific_flags);
289 + ssb_flush_tmslow(dev);
290 +
291 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
292 + val = ssb_read32(dev, SSB_IMSTATE);
293 + val &= ~SSB_IMSTATE_REJECT;
294 + ssb_write32(dev, SSB_IMSTATE, val);
295 + }
296 + }
297
298 ssb_write32(dev, SSB_TMSLOW,
299 reject | SSB_TMSLOW_RESET |
300 @@ -1213,13 +1249,34 @@ void ssb_device_disable(struct ssb_devic
301 }
302 EXPORT_SYMBOL(ssb_device_disable);
303
304 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
305 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
306 +{
307 + u16 chip_id = dev->bus->chip_id;
308 +
309 + if (dev->id.coreid == SSB_DEV_80211) {
310 + return (chip_id == 0x4322 || chip_id == 43221 ||
311 + chip_id == 43231 || chip_id == 43222);
312 + }
313 +
314 + return 0;
315 +}
316 +
317 u32 ssb_dma_translation(struct ssb_device *dev)
318 {
319 switch (dev->bus->bustype) {
320 case SSB_BUSTYPE_SSB:
321 return 0;
322 case SSB_BUSTYPE_PCI:
323 - return SSB_PCI_DMA;
324 + if (pci_is_pcie(dev->bus->host_pci) &&
325 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
326 + return SSB_PCIE_DMA_H32;
327 + } else {
328 + if (ssb_dma_translation_special_bit(dev))
329 + return SSB_PCIE_DMA_H32;
330 + else
331 + return SSB_PCI_DMA;
332 + }
333 default:
334 __ssb_dma_not_implemented(dev);
335 }
336 @@ -1262,20 +1319,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
337
338 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
339 {
340 - struct ssb_chipcommon *cc;
341 int err;
342 enum ssb_clkmode mode;
343
344 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
345 if (err)
346 goto error;
347 - cc = &bus->chipco;
348 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
349 - ssb_chipco_set_clockmode(cc, mode);
350
351 #ifdef CONFIG_SSB_DEBUG
352 bus->powered_up = 1;
353 #endif
354 +
355 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
356 + ssb_chipco_set_clockmode(&bus->chipco, mode);
357 +
358 return 0;
359 error:
360 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
361 @@ -1283,6 +1340,37 @@ error:
362 }
363 EXPORT_SYMBOL(ssb_bus_powerup);
364
365 +static void ssb_broadcast_value(struct ssb_device *dev,
366 + u32 address, u32 data)
367 +{
368 +#ifdef CONFIG_SSB_DRIVER_PCICORE
369 + /* This is used for both, PCI and ChipCommon core, so be careful. */
370 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
371 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
372 +#endif
373 +
374 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
375 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
376 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
377 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
378 +}
379 +
380 +void ssb_commit_settings(struct ssb_bus *bus)
381 +{
382 + struct ssb_device *dev;
383 +
384 +#ifdef CONFIG_SSB_DRIVER_PCICORE
385 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
386 +#else
387 + dev = bus->chipco.dev;
388 +#endif
389 + if (WARN_ON(!dev))
390 + return;
391 + /* This forces an update of the cached registers. */
392 + ssb_broadcast_value(dev, 0xFD8, 0);
393 +}
394 +EXPORT_SYMBOL(ssb_commit_settings);
395 +
396 u32 ssb_admatch_base(u32 adm)
397 {
398 u32 base = 0;
399 --- a/drivers/ssb/pci.c
400 +++ b/drivers/ssb/pci.c
401 @@ -1,7 +1,7 @@
402 /*
403 * Sonics Silicon Backplane PCI-Hostbus related functions.
404 *
405 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
406 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
407 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
408 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
409 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
410 @@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ss
411 {
412 int i;
413 u16 v;
414 - s8 gain;
415 u16 loc[3];
416
417 if (out->revision == 3) /* rev 3 moved MAC */
418 @@ -390,20 +389,52 @@ static void sprom_extract_r123(struct ss
419 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
420
421 /* Extract the antenna gain values. */
422 - gain = r123_extract_antgain(out->revision, in,
423 - SSB_SPROM1_AGAIN_BG,
424 - SSB_SPROM1_AGAIN_BG_SHIFT);
425 - out->antenna_gain.ghz24.a0 = gain;
426 - out->antenna_gain.ghz24.a1 = gain;
427 - out->antenna_gain.ghz24.a2 = gain;
428 - out->antenna_gain.ghz24.a3 = gain;
429 - gain = r123_extract_antgain(out->revision, in,
430 - SSB_SPROM1_AGAIN_A,
431 - SSB_SPROM1_AGAIN_A_SHIFT);
432 - out->antenna_gain.ghz5.a0 = gain;
433 - out->antenna_gain.ghz5.a1 = gain;
434 - out->antenna_gain.ghz5.a2 = gain;
435 - out->antenna_gain.ghz5.a3 = gain;
436 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
437 + SSB_SPROM1_AGAIN_BG,
438 + SSB_SPROM1_AGAIN_BG_SHIFT);
439 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
440 + SSB_SPROM1_AGAIN_A,
441 + SSB_SPROM1_AGAIN_A_SHIFT);
442 +}
443 +
444 +/* Revs 4 5 and 8 have partially shared layout */
445 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
446 +{
447 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
448 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
449 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
450 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
451 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
452 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
453 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
454 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
455 +
456 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
457 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
458 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
459 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
460 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
461 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
462 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
463 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
464 +
465 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
466 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
467 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
468 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
469 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
470 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
471 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
472 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
473 +
474 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
475 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
476 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
477 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
478 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
479 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
480 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
481 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
482 }
483
484 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
485 @@ -428,10 +459,14 @@ static void sprom_extract_r45(struct ssb
486 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
487 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
488 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
489 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
490 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
491 } else {
492 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
493 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
494 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
495 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
496 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
497 }
498 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
499 SSB_SPROM4_ANTAVAIL_A_SHIFT);
500 @@ -460,16 +495,16 @@ static void sprom_extract_r45(struct ssb
501 }
502
503 /* Extract the antenna gain values. */
504 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
505 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
506 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
507 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
508 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
509 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
510 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
511 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
512 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
513 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
514 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
515 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
516 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
517 - sizeof(out->antenna_gain.ghz5));
518 +
519 + sprom_extract_r458(out, in);
520
521 /* TODO - get remaining rev 4 stuff needed */
522 }
523 @@ -477,7 +512,13 @@ static void sprom_extract_r45(struct ssb
524 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
525 {
526 int i;
527 - u16 v;
528 + u16 v, o;
529 + u16 pwr_info_offset[] = {
530 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
531 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
532 + };
533 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
534 + ARRAY_SIZE(out->core_pwr_info));
535
536 /* extract the MAC address */
537 for (i = 0; i < 3; i++) {
538 @@ -550,16 +591,71 @@ static void sprom_extract_r8(struct ssb_
539 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
540
541 /* Extract the antenna gain values. */
542 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
543 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
544 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
545 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
546 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
547 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
548 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
549 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
550 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
551 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
552 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
553 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
554 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
555 - sizeof(out->antenna_gain.ghz5));
556 +
557 + /* Extract cores power info info */
558 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
559 + o = pwr_info_offset[i];
560 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
561 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
562 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
563 + SSB_SPROM8_2G_MAXP, 0);
564 +
565 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
566 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
567 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
568 +
569 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
570 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
571 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
572 + SSB_SPROM8_5G_MAXP, 0);
573 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
574 + SSB_SPROM8_5GH_MAXP, 0);
575 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
576 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
577 +
578 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
579 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
580 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
581 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
582 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
583 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
584 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
585 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
586 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
587 + }
588 +
589 + /* Extract FEM info */
590 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
591 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
592 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
593 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
594 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
595 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
596 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
597 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
598 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
599 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
600 +
601 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
602 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
603 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
604 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
605 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
606 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
607 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
608 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
609 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
610 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
611 +
612 + sprom_extract_r458(out, in);
613
614 /* TODO - get remaining rev 8 stuff needed */
615 }
616 @@ -573,37 +669,34 @@ static int sprom_extract(struct ssb_bus
617 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
618 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
619 memset(out->et1mac, 0xFF, 6);
620 +
621 if ((bus->chip_id & 0xFF00) == 0x4400) {
622 /* Workaround: The BCM44XX chip has a stupid revision
623 * number stored in the SPROM.
624 * Always extract r1. */
625 out->revision = 1;
626 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
627 + }
628 +
629 + switch (out->revision) {
630 + case 1:
631 + case 2:
632 + case 3:
633 sprom_extract_r123(out, in);
634 - } else if (bus->chip_id == 0x4321) {
635 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
636 - out->revision = 4;
637 + break;
638 + case 4:
639 + case 5:
640 sprom_extract_r45(out, in);
641 - } else {
642 - switch (out->revision) {
643 - case 1:
644 - case 2:
645 - case 3:
646 - sprom_extract_r123(out, in);
647 - break;
648 - case 4:
649 - case 5:
650 - sprom_extract_r45(out, in);
651 - break;
652 - case 8:
653 - sprom_extract_r8(out, in);
654 - break;
655 - default:
656 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
657 - " revision %d detected. Will extract"
658 - " v1\n", out->revision);
659 - out->revision = 1;
660 - sprom_extract_r123(out, in);
661 - }
662 + break;
663 + case 8:
664 + sprom_extract_r8(out, in);
665 + break;
666 + default:
667 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
668 + " revision %d detected. Will extract"
669 + " v1\n", out->revision);
670 + out->revision = 1;
671 + sprom_extract_r123(out, in);
672 }
673
674 if (out->boardflags_lo == 0xFFFF)
675 @@ -617,15 +710,14 @@ static int sprom_extract(struct ssb_bus
676 static int ssb_pci_sprom_get(struct ssb_bus *bus,
677 struct ssb_sprom *sprom)
678 {
679 - const struct ssb_sprom *fallback;
680 - int err = -ENOMEM;
681 + int err;
682 u16 *buf;
683
684 if (!ssb_is_sprom_available(bus)) {
685 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
686 return -ENODEV;
687 }
688 - if (bus->chipco.dev) { /* can be unavailible! */
689 + if (bus->chipco.dev) { /* can be unavailable! */
690 /*
691 * get SPROM offset: SSB_SPROM_BASE1 except for
692 * chipcommon rev >= 31 or chip ID is 0x4312 and
693 @@ -645,7 +737,7 @@ static int ssb_pci_sprom_get(struct ssb_
694
695 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
696 if (!buf)
697 - goto out;
698 + return -ENOMEM;
699 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
700 sprom_do_read(bus, buf);
701 err = sprom_check_crc(buf, bus->sprom_size);
702 @@ -655,17 +747,24 @@ static int ssb_pci_sprom_get(struct ssb_
703 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
704 GFP_KERNEL);
705 if (!buf)
706 - goto out;
707 + return -ENOMEM;
708 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
709 sprom_do_read(bus, buf);
710 err = sprom_check_crc(buf, bus->sprom_size);
711 if (err) {
712 /* All CRC attempts failed.
713 * Maybe there is no SPROM on the device?
714 - * If we have a fallback, use that. */
715 - fallback = ssb_get_fallback_sprom();
716 - if (fallback) {
717 - memcpy(sprom, fallback, sizeof(*sprom));
718 + * Now we ask the arch code if there is some sprom
719 + * available for this device in some other storage */
720 + err = ssb_fill_sprom_with_fallback(bus, sprom);
721 + if (err) {
722 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
723 + " fallback SPROM failed (err %d)\n",
724 + err);
725 + } else {
726 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
727 + " revision %d provided by"
728 + " platform.\n", sprom->revision);
729 err = 0;
730 goto out_free;
731 }
732 @@ -677,19 +776,15 @@ static int ssb_pci_sprom_get(struct ssb_
733
734 out_free:
735 kfree(buf);
736 -out:
737 return err;
738 }
739
740 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
741 struct ssb_boardinfo *bi)
742 {
743 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
744 - &bi->vendor);
745 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
746 - &bi->type);
747 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
748 - &bi->rev);
749 + bi->vendor = bus->host_pci->subsystem_vendor;
750 + bi->type = bus->host_pci->subsystem_device;
751 + bi->rev = bus->host_pci->revision;
752 }
753
754 int ssb_pci_get_invariants(struct ssb_bus *bus,
755 --- a/drivers/ssb/pcihost_wrapper.c
756 +++ b/drivers/ssb/pcihost_wrapper.c
757 @@ -6,7 +6,7 @@
758 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
759 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
760 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
761 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
762 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
763 *
764 * Licensed under the GNU/GPL. See COPYING for details.
765 */
766 @@ -53,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
767 # define ssb_pcihost_resume NULL
768 #endif /* CONFIG_PM */
769
770 -static int ssb_pcihost_probe(struct pci_dev *dev,
771 - const struct pci_device_id *id)
772 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
773 + const struct pci_device_id *id)
774 {
775 struct ssb_bus *ssb;
776 int err = -ENOMEM;
777 const char *name;
778 + u32 val;
779
780 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
781 if (!ssb)
782 @@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
783 goto err_pci_disable;
784 pci_set_master(dev);
785
786 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
787 + * PCI Tx retries from interfering with C3 CPU state */
788 + pci_read_config_dword(dev, 0x40, &val);
789 + if ((val & 0x0000ff00) != 0)
790 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
791 +
792 err = ssb_bus_pcibus_register(ssb, dev);
793 if (err)
794 goto err_pci_release_regions;
795 @@ -103,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
796 pci_set_drvdata(dev, NULL);
797 }
798
799 -int ssb_pcihost_register(struct pci_driver *driver)
800 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
801 {
802 driver->probe = ssb_pcihost_probe;
803 driver->remove = ssb_pcihost_remove;
804 --- a/drivers/ssb/scan.c
805 +++ b/drivers/ssb/scan.c
806 @@ -2,7 +2,7 @@
807 * Sonics Silicon Backplane
808 * Bus scanning
809 *
810 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
811 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
812 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
813 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
814 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
815 @@ -259,7 +259,10 @@ static int we_support_multiple_80211_cor
816 #ifdef CONFIG_SSB_PCIHOST
817 if (bus->bustype == SSB_BUSTYPE_PCI) {
818 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
819 - bus->host_pci->device == 0x4324)
820 + ((bus->host_pci->device == 0x4313) ||
821 + (bus->host_pci->device == 0x431A) ||
822 + (bus->host_pci->device == 0x4321) ||
823 + (bus->host_pci->device == 0x4324)))
824 return 1;
825 }
826 #endif /* CONFIG_SSB_PCIHOST */
827 @@ -308,8 +311,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
828 } else {
829 if (bus->bustype == SSB_BUSTYPE_PCI) {
830 bus->chip_id = pcidev_to_chipid(bus->host_pci);
831 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
832 - &bus->chip_rev);
833 + bus->chip_rev = bus->host_pci->revision;
834 bus->chip_package = 0;
835 } else {
836 bus->chip_id = 0x4710;
837 @@ -317,6 +319,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
838 bus->chip_package = 0;
839 }
840 }
841 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
842 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
843 + bus->chip_package);
844 if (!bus->nr_devices)
845 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
846 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
847 @@ -406,10 +411,10 @@ int ssb_bus_scan(struct ssb_bus *bus,
848 /* Ignore PCI cores on PCI-E cards.
849 * Ignore PCI-E cores on PCI cards. */
850 if (dev->id.coreid == SSB_DEV_PCI) {
851 - if (bus->host_pci->is_pcie)
852 + if (pci_is_pcie(bus->host_pci))
853 continue;
854 } else {
855 - if (!bus->host_pci->is_pcie)
856 + if (!pci_is_pcie(bus->host_pci))
857 continue;
858 }
859 }
860 @@ -421,6 +426,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
861 bus->pcicore.dev = dev;
862 #endif /* CONFIG_SSB_DRIVER_PCICORE */
863 break;
864 + case SSB_DEV_ETHERNET:
865 + if (bus->bustype == SSB_BUSTYPE_PCI) {
866 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
867 + (bus->host_pci->device & 0xFF00) == 0x4300) {
868 + /* This is a dangling ethernet core on a
869 + * wireless device. Ignore it. */
870 + continue;
871 + }
872 + }
873 + break;
874 default:
875 break;
876 }
877 --- a/include/linux/ssb/ssb.h
878 +++ b/include/linux/ssb/ssb.h
879 @@ -16,6 +16,12 @@ struct pcmcia_device;
880 struct ssb_bus;
881 struct ssb_driver;
882
883 +struct ssb_sprom_core_pwr_info {
884 + u8 itssi_2g, itssi_5g;
885 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
886 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
887 +};
888 +
889 struct ssb_sprom {
890 u8 revision;
891 u8 il0mac[6]; /* MAC address for 802.11b/g */
892 @@ -25,8 +31,13 @@ struct ssb_sprom {
893 u8 et1phyaddr; /* MII address for enet1 */
894 u8 et0mdcport; /* MDIO for enet0 */
895 u8 et1mdcport; /* MDIO for enet1 */
896 - u8 board_rev; /* Board revision number from SPROM. */
897 + u16 board_rev; /* Board revision number from SPROM. */
898 + u16 board_num; /* Board number from SPROM. */
899 + u16 board_type; /* Board type from SPROM. */
900 u8 country_code; /* Country Code */
901 + char alpha2[2]; /* Country Code as two chars like EU or US */
902 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
903 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
904 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
905 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
906 u16 pa0b0;
907 @@ -45,18 +56,22 @@ struct ssb_sprom {
908 u8 gpio1; /* GPIO pin 1 */
909 u8 gpio2; /* GPIO pin 2 */
910 u8 gpio3; /* GPIO pin 3 */
911 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
912 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
913 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
914 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
915 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
916 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
917 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
918 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
919 u8 itssi_a; /* Idle TSSI Target for A-PHY */
920 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
921 u8 tri2g; /* 2.4GHz TX isolation */
922 u8 tri5gl; /* 5.2GHz TX isolation */
923 u8 tri5g; /* 5.3GHz TX isolation */
924 u8 tri5gh; /* 5.8GHz TX isolation */
925 - u8 rxpo2g; /* 2GHz RX power offset */
926 - u8 rxpo5g; /* 5GHz RX power offset */
927 + u8 txpid2g[4]; /* 2GHz TX power index */
928 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
929 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
930 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
931 + s8 rxpo2g; /* 2GHz RX power offset */
932 + s8 rxpo5g; /* 5GHz RX power offset */
933 u8 rssisav2g; /* 2GHz RSSI params */
934 u8 rssismc2g;
935 u8 rssismf2g;
936 @@ -76,26 +91,104 @@ struct ssb_sprom {
937 u16 boardflags2_hi; /* Board flags (bits 48-63) */
938 /* TODO store board flags in a single u64 */
939
940 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
941 +
942 /* Antenna gain values for up to 4 antennas
943 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
944 * loss in the connectors is bigger than the gain. */
945 struct {
946 - struct {
947 - s8 a0, a1, a2, a3;
948 - } ghz24; /* 2.4GHz band */
949 - struct {
950 - s8 a0, a1, a2, a3;
951 - } ghz5; /* 5GHz band */
952 + s8 a0, a1, a2, a3;
953 } antenna_gain;
954
955 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
956 + struct {
957 + struct {
958 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
959 + } ghz2;
960 + struct {
961 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
962 + } ghz5;
963 + } fem;
964 +
965 + u16 mcs2gpo[8];
966 + u16 mcs5gpo[8];
967 + u16 mcs5glpo[8];
968 + u16 mcs5ghpo[8];
969 + u8 opo;
970 +
971 + u8 rxgainerr2ga[3];
972 + u8 rxgainerr5gla[3];
973 + u8 rxgainerr5gma[3];
974 + u8 rxgainerr5gha[3];
975 + u8 rxgainerr5gua[3];
976 +
977 + u8 noiselvl2ga[3];
978 + u8 noiselvl5gla[3];
979 + u8 noiselvl5gma[3];
980 + u8 noiselvl5gha[3];
981 + u8 noiselvl5gua[3];
982 +
983 + u8 regrev;
984 + u8 txchain;
985 + u8 rxchain;
986 + u8 antswitch;
987 + u16 cddpo;
988 + u16 stbcpo;
989 + u16 bw40po;
990 + u16 bwduppo;
991 +
992 + u8 tempthresh;
993 + u8 tempoffset;
994 + u16 rawtempsense;
995 + u8 measpower;
996 + u8 tempsense_slope;
997 + u8 tempcorrx;
998 + u8 tempsense_option;
999 + u8 freqoffset_corr;
1000 + u8 iqcal_swp_dis;
1001 + u8 hw_iqcal_en;
1002 + u8 elna2g;
1003 + u8 elna5g;
1004 + u8 phycal_tempdelta;
1005 + u8 temps_period;
1006 + u8 temps_hysteresis;
1007 + u8 measpower1;
1008 + u8 measpower2;
1009 + u8 pcieingress_war;
1010 +
1011 + /* power per rate from sromrev 9 */
1012 + u16 cckbw202gpo;
1013 + u16 cckbw20ul2gpo;
1014 + u32 legofdmbw202gpo;
1015 + u32 legofdmbw20ul2gpo;
1016 + u32 legofdmbw205glpo;
1017 + u32 legofdmbw20ul5glpo;
1018 + u32 legofdmbw205gmpo;
1019 + u32 legofdmbw20ul5gmpo;
1020 + u32 legofdmbw205ghpo;
1021 + u32 legofdmbw20ul5ghpo;
1022 + u32 mcsbw202gpo;
1023 + u32 mcsbw20ul2gpo;
1024 + u32 mcsbw402gpo;
1025 + u32 mcsbw205glpo;
1026 + u32 mcsbw20ul5glpo;
1027 + u32 mcsbw405glpo;
1028 + u32 mcsbw205gmpo;
1029 + u32 mcsbw20ul5gmpo;
1030 + u32 mcsbw405gmpo;
1031 + u32 mcsbw205ghpo;
1032 + u32 mcsbw20ul5ghpo;
1033 + u32 mcsbw405ghpo;
1034 + u16 mcs32po;
1035 + u16 legofdm40duppo;
1036 + u8 sar2g;
1037 + u8 sar5g;
1038 };
1039
1040 /* Information about the PCB the circuitry is soldered on. */
1041 struct ssb_boardinfo {
1042 u16 vendor;
1043 u16 type;
1044 - u16 rev;
1045 + u8 rev;
1046 };
1047
1048
1049 @@ -225,10 +318,9 @@ struct ssb_driver {
1050 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
1051
1052 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
1053 -static inline int ssb_driver_register(struct ssb_driver *drv)
1054 -{
1055 - return __ssb_driver_register(drv, THIS_MODULE);
1056 -}
1057 +#define ssb_driver_register(drv) \
1058 + __ssb_driver_register(drv, THIS_MODULE)
1059 +
1060 extern void ssb_driver_unregister(struct ssb_driver *drv);
1061
1062
1063 @@ -304,7 +396,7 @@ struct ssb_bus {
1064
1065 /* ID information about the Chip. */
1066 u16 chip_id;
1067 - u16 chip_rev;
1068 + u8 chip_rev;
1069 u16 sprom_offset;
1070 u16 sprom_size; /* number of words in sprom */
1071 u8 chip_package;
1072 @@ -400,7 +492,9 @@ extern bool ssb_is_sprom_available(struc
1073
1074 /* Set a fallback SPROM.
1075 * See kdoc at the function definition for complete documentation. */
1076 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
1077 +extern int ssb_arch_register_fallback_sprom(
1078 + int (*sprom_callback)(struct ssb_bus *bus,
1079 + struct ssb_sprom *out));
1080
1081 /* Suspend a SSB bus.
1082 * Call this from the parent bus suspend routine. */
1083 @@ -514,6 +608,7 @@ extern int ssb_bus_may_powerdown(struct
1084 * Otherwise static always-on powercontrol will be used. */
1085 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
1086
1087 +extern void ssb_commit_settings(struct ssb_bus *bus);
1088
1089 /* Various helper functions */
1090 extern u32 ssb_admatch_base(u32 adm);
1091 --- a/include/linux/ssb/ssb_driver_gige.h
1092 +++ b/include/linux/ssb/ssb_driver_gige.h
1093 @@ -2,6 +2,7 @@
1094 #define LINUX_SSB_DRIVER_GIGE_H_
1095
1096 #include <linux/ssb/ssb.h>
1097 +#include <linux/bug.h>
1098 #include <linux/pci.h>
1099 #include <linux/spinlock.h>
1100
1101 @@ -96,16 +97,21 @@ static inline bool ssb_gige_must_flush_p
1102 return 0;
1103 }
1104
1105 -extern char * nvram_get(const char *name);
1106 +#ifdef CONFIG_BCM47XX
1107 +#include <asm/mach-bcm47xx/nvram.h>
1108 /* Get the device MAC address */
1109 static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
1110 {
1111 -#ifdef CONFIG_BCM47XX
1112 - char *res = nvram_get("et0macaddr");
1113 - if (res)
1114 - memcpy(macaddr, res, 6);
1115 -#endif
1116 + char buf[20];
1117 + if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
1118 + return;
1119 + nvram_parse_macaddr(buf, macaddr);
1120 }
1121 +#else
1122 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
1123 +{
1124 +}
1125 +#endif
1126
1127 extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
1128 struct pci_dev *pdev);
1129 --- a/include/linux/ssb/ssb_regs.h
1130 +++ b/include/linux/ssb/ssb_regs.h
1131 @@ -85,6 +85,8 @@
1132 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
1133 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
1134 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
1135 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
1136 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
1137 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
1138 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
1139 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
1140 @@ -95,7 +97,7 @@
1141 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
1142 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
1143 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
1144 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
1145 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
1146 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
1147 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
1148 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
1149 @@ -267,6 +269,8 @@
1150 /* SPROM Revision 4 */
1151 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
1152 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
1153 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
1154 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
1155 #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
1156 #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
1157 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
1158 @@ -298,6 +302,46 @@
1159 #define SSB_SPROM4_AGAIN2_SHIFT 0
1160 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
1161 #define SSB_SPROM4_AGAIN3_SHIFT 8
1162 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
1163 +#define SSB_SPROM4_TXPID2G0 0x00FF
1164 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
1165 +#define SSB_SPROM4_TXPID2G1 0xFF00
1166 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
1167 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
1168 +#define SSB_SPROM4_TXPID2G2 0x00FF
1169 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
1170 +#define SSB_SPROM4_TXPID2G3 0xFF00
1171 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
1172 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
1173 +#define SSB_SPROM4_TXPID5G0 0x00FF
1174 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
1175 +#define SSB_SPROM4_TXPID5G1 0xFF00
1176 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
1177 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
1178 +#define SSB_SPROM4_TXPID5G2 0x00FF
1179 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
1180 +#define SSB_SPROM4_TXPID5G3 0xFF00
1181 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
1182 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
1183 +#define SSB_SPROM4_TXPID5GL0 0x00FF
1184 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
1185 +#define SSB_SPROM4_TXPID5GL1 0xFF00
1186 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
1187 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
1188 +#define SSB_SPROM4_TXPID5GL2 0x00FF
1189 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
1190 +#define SSB_SPROM4_TXPID5GL3 0xFF00
1191 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
1192 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
1193 +#define SSB_SPROM4_TXPID5GH0 0x00FF
1194 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
1195 +#define SSB_SPROM4_TXPID5GH1 0xFF00
1196 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
1197 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
1198 +#define SSB_SPROM4_TXPID5GH2 0x00FF
1199 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
1200 +#define SSB_SPROM4_TXPID5GH3 0xFF00
1201 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
1202 #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
1203 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
1204 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1205 @@ -317,6 +361,8 @@
1206 #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
1207 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
1208 #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
1209 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
1210 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
1211 #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
1212 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
1213 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
1214 @@ -386,6 +432,56 @@
1215 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1216 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1217 #define SSB_SPROM8_RXPO5G_SHIFT 8
1218 +#define SSB_SPROM8_FEM2G 0x00AE
1219 +#define SSB_SPROM8_FEM5G 0x00B0
1220 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
1221 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
1222 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
1223 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
1224 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
1225 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
1226 +#define SSB_SROM8_FEM_TR_ISO 0x0700
1227 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
1228 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
1229 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
1230 +#define SSB_SPROM8_THERMAL 0x00B2
1231 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
1232 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
1233 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
1234 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
1235 +
1236 +/* There are 4 blocks with power info sharing the same layout */
1237 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
1238 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
1239 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
1240 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
1241 +
1242 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
1243 +#define SSB_SPROM8_2G_MAXP 0x00FF
1244 +#define SSB_SPROM8_2G_ITSSI 0xFF00
1245 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
1246 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
1247 +#define SSB_SROM8_2G_PA_1 0x04
1248 +#define SSB_SROM8_2G_PA_2 0x06
1249 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
1250 +#define SSB_SPROM8_5G_MAXP 0x00FF
1251 +#define SSB_SPROM8_5G_ITSSI 0xFF00
1252 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
1253 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
1254 +#define SSB_SPROM8_5GH_MAXP 0x00FF
1255 +#define SSB_SPROM8_5GL_MAXP 0xFF00
1256 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
1257 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
1258 +#define SSB_SROM8_5G_PA_1 0x0E
1259 +#define SSB_SROM8_5G_PA_2 0x10
1260 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
1261 +#define SSB_SROM8_5GL_PA_1 0x14
1262 +#define SSB_SROM8_5GL_PA_2 0x16
1263 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
1264 +#define SSB_SROM8_5GH_PA_1 0x1A
1265 +#define SSB_SROM8_5GH_PA_2 0x1C
1266 +
1267 +/* TODO: Make it deprecated */
1268 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1269 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1270 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1271 @@ -410,12 +506,53 @@
1272 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1273 #define SSB_SPROM8_PA1HIB1 0x00DA
1274 #define SSB_SPROM8_PA1HIB2 0x00DC
1275 +
1276 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1277 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1278 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1279 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1280 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1281
1282 +/* Values for boardflags_lo read from SPROM */
1283 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
1284 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
1285 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
1286 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
1287 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
1288 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
1289 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
1290 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
1291 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
1292 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
1293 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
1294 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
1295 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
1296 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
1297 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
1298 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
1299 +
1300 +/* Values for boardflags_hi read from SPROM */
1301 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
1302 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
1303 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
1304 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
1305 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
1306 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
1307 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
1308 +
1309 +/* Values for boardflags2_lo read from SPROM */
1310 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
1311 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
1312 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
1313 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
1314 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
1315 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
1316 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
1317 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
1318 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
1319 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
1320 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
1321 +
1322 /* Values for SSB_SPROM1_BINF_CCODE */
1323 enum {
1324 SSB_SPROM1CCODE_WORLD = 0,
1325 --- a/drivers/ssb/driver_chipcommon.c
1326 +++ b/drivers/ssb/driver_chipcommon.c
1327 @@ -3,7 +3,7 @@
1328 * Broadcom ChipCommon core driver
1329 *
1330 * Copyright 2005, Broadcom Corporation
1331 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1332 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1333 *
1334 * Licensed under the GNU/GPL. See COPYING for details.
1335 */
1336 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
1337 if (!ccdev)
1338 return;
1339 bus = ccdev->bus;
1340 +
1341 + /* We support SLOW only on 6..9 */
1342 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
1343 + mode = SSB_CLKMODE_DYNAMIC;
1344 +
1345 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
1346 + return; /* PMU controls clockmode, separated function needed */
1347 + SSB_WARN_ON(ccdev->id.revision >= 20);
1348 +
1349 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1350 if (ccdev->id.revision < 6)
1351 return;
1352 - /* chipcommon cores rev10 are a whole new ball game */
1353 +
1354 + /* ChipCommon cores rev10+ need testing */
1355 if (ccdev->id.revision >= 10)
1356 return;
1357 +
1358 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
1359 return;
1360
1361 switch (mode) {
1362 - case SSB_CLKMODE_SLOW:
1363 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
1364 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1365 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1366 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1367 break;
1368 case SSB_CLKMODE_FAST:
1369 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
1370 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1371 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1372 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
1373 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1374 + if (ccdev->id.revision < 10) {
1375 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
1376 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1377 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1378 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
1379 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1380 + } else {
1381 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
1382 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
1383 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
1384 + /* udelay(150); TODO: not available in early init */
1385 + }
1386 break;
1387 case SSB_CLKMODE_DYNAMIC:
1388 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1389 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1390 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
1391 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1392 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
1393 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1394 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1395 -
1396 - /* for dynamic control, we have to release our xtal_pu "force on" */
1397 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
1398 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
1399 + if (ccdev->id.revision < 10) {
1400 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1401 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1402 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
1403 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1404 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
1405 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
1406 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1407 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1408 +
1409 + /* For dynamic control, we have to release our xtal_pu
1410 + * "force on" */
1411 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
1412 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
1413 + } else {
1414 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
1415 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
1416 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
1417 + }
1418 break;
1419 default:
1420 SSB_WARN_ON(1);
1421 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
1422 if (cc->dev->id.revision >= 11)
1423 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
1424 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
1425 +
1426 + if (cc->dev->id.revision >= 20) {
1427 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
1428 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
1429 + }
1430 +
1431 ssb_pmu_init(cc);
1432 chipco_powercontrol_init(cc);
1433 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
1434 --- a/drivers/ssb/driver_chipcommon_pmu.c
1435 +++ b/drivers/ssb/driver_chipcommon_pmu.c
1436 @@ -2,7 +2,7 @@
1437 * Sonics Silicon Backplane
1438 * Broadcom ChipCommon Power Management Unit driver
1439 *
1440 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
1441 + * Copyright 2009, Michael Buesch <m@bues.ch>
1442 * Copyright 2007, Broadcom Corporation
1443 *
1444 * Licensed under the GNU/GPL. See COPYING for details.
1445 @@ -12,6 +12,9 @@
1446 #include <linux/ssb/ssb_regs.h>
1447 #include <linux/ssb/ssb_driver_chipcommon.h>
1448 #include <linux/delay.h>
1449 +#ifdef CONFIG_BCM47XX
1450 +#include <asm/mach-bcm47xx/nvram.h>
1451 +#endif
1452
1453 #include "ssb_private.h"
1454
1455 @@ -91,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
1456 u32 pmuctl, tmp, pllctl;
1457 unsigned int i;
1458
1459 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
1460 - /* The 5354 crystal freq is 25MHz */
1461 - crystalfreq = 25000;
1462 - }
1463 if (crystalfreq)
1464 e = pmu0_plltab_find_entry(crystalfreq);
1465 if (!e)
1466 @@ -320,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
1467 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
1468
1469 if (bus->bustype == SSB_BUSTYPE_SSB) {
1470 - /* TODO: The user may override the crystal frequency. */
1471 +#ifdef CONFIG_BCM47XX
1472 + char buf[20];
1473 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
1474 + crystalfreq = simple_strtoul(buf, NULL, 0);
1475 +#endif
1476 }
1477
1478 switch (bus->chip_id) {
1479 @@ -329,7 +332,11 @@ static void ssb_pmu_pll_init(struct ssb_
1480 ssb_pmu1_pllinit_r0(cc, crystalfreq);
1481 break;
1482 case 0x4328:
1483 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
1484 + break;
1485 case 0x5354:
1486 + if (crystalfreq == 0)
1487 + crystalfreq = 25000;
1488 ssb_pmu0_pllinit_r0(cc, crystalfreq);
1489 break;
1490 case 0x4322:
1491 @@ -417,12 +424,14 @@ static void ssb_pmu_resources_init(struc
1492 u32 min_msk = 0, max_msk = 0;
1493 unsigned int i;
1494 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
1495 - unsigned int updown_tab_size;
1496 + unsigned int updown_tab_size = 0;
1497 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
1498 - unsigned int depend_tab_size;
1499 + unsigned int depend_tab_size = 0;
1500
1501 switch (bus->chip_id) {
1502 case 0x4312:
1503 + min_msk = 0xCBB;
1504 + break;
1505 case 0x4322:
1506 /* We keep the default settings:
1507 * min_msk = 0xCBB
1508 @@ -604,3 +613,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
1509
1510 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
1511 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
1512 +
1513 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
1514 +{
1515 + struct ssb_bus *bus = cc->dev->bus;
1516 +
1517 + switch (bus->chip_id) {
1518 + case 0x5354:
1519 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
1520 + return 240000000;
1521 + default:
1522 + ssb_printk(KERN_ERR PFX
1523 + "ERROR: PMU cpu clock unknown for device %04X\n",
1524 + bus->chip_id);
1525 + return 0;
1526 + }
1527 +}
1528 +
1529 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
1530 +{
1531 + struct ssb_bus *bus = cc->dev->bus;
1532 +
1533 + switch (bus->chip_id) {
1534 + case 0x5354:
1535 + return 120000000;
1536 + default:
1537 + ssb_printk(KERN_ERR PFX
1538 + "ERROR: PMU controlclock unknown for device %04X\n",
1539 + bus->chip_id);
1540 + return 0;
1541 + }
1542 +}
1543 --- a/drivers/ssb/driver_gige.c
1544 +++ b/drivers/ssb/driver_gige.c
1545 @@ -3,7 +3,7 @@
1546 * Broadcom Gigabit Ethernet core driver
1547 *
1548 * Copyright 2008, Broadcom Corporation
1549 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
1550 + * Copyright 2008, Michael Buesch <m@bues.ch>
1551 *
1552 * Licensed under the GNU/GPL. See COPYING for details.
1553 */
1554 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
1555 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
1556 }
1557
1558 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
1559 - int reg, int size, u32 *val)
1560 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
1561 + unsigned int devfn, int reg,
1562 + int size, u32 *val)
1563 {
1564 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
1565 unsigned long flags;
1566 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
1567 return PCIBIOS_SUCCESSFUL;
1568 }
1569
1570 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
1571 - int reg, int size, u32 val)
1572 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
1573 + unsigned int devfn, int reg,
1574 + int size, u32 val)
1575 {
1576 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
1577 unsigned long flags;
1578 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
1579 return PCIBIOS_SUCCESSFUL;
1580 }
1581
1582 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
1583 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
1584 + const struct ssb_device_id *id)
1585 {
1586 struct ssb_gige *dev;
1587 u32 base, tmslow, tmshigh;
1588 --- a/drivers/ssb/driver_pcicore.c
1589 +++ b/drivers/ssb/driver_pcicore.c
1590 @@ -3,7 +3,7 @@
1591 * Broadcom PCI-core driver
1592 *
1593 * Copyright 2005, Broadcom Corporation
1594 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1595 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1596 *
1597 * Licensed under the GNU/GPL. See COPYING for details.
1598 */
1599 @@ -15,6 +15,11 @@
1600
1601 #include "ssb_private.h"
1602
1603 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
1604 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
1605 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
1606 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1607 + u8 address, u16 data);
1608
1609 static inline
1610 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
1611 @@ -69,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
1612 u32 tmp;
1613
1614 /* We do only have one cardbus device behind the bridge. */
1615 - if (pc->cardbusmode && (dev >= 1))
1616 + if (pc->cardbusmode && (dev > 1))
1617 goto out;
1618
1619 if (bus == 0) {
1620 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
1621 return ssb_mips_irq(extpci_core->dev) + 2;
1622 }
1623
1624 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
1625 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
1626 {
1627 u32 val;
1628
1629 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
1630 register_pci_controller(&ssb_pcicore_controller);
1631 }
1632
1633 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
1634 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
1635 {
1636 struct ssb_bus *bus = pc->dev->bus;
1637 u16 chipid_top;
1638 @@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
1639 }
1640 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
1641
1642 +/**************************************************
1643 + * Workarounds.
1644 + **************************************************/
1645 +
1646 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
1647 +{
1648 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
1649 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
1650 + tmp &= ~0xF000;
1651 + tmp |= (pc->dev->core_index << 12);
1652 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
1653 + }
1654 +}
1655 +
1656 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
1657 +{
1658 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
1659 +}
1660 +
1661 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
1662 +{
1663 + const u8 serdes_pll_device = 0x1D;
1664 + const u8 serdes_rx_device = 0x1F;
1665 + u16 tmp;
1666 +
1667 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
1668 + ssb_pcicore_polarity_workaround(pc));
1669 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
1670 + if (tmp & 0x4000)
1671 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
1672 +}
1673 +
1674 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
1675 +{
1676 + struct ssb_device *pdev = pc->dev;
1677 + struct ssb_bus *bus = pdev->bus;
1678 + u32 tmp;
1679 +
1680 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1681 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
1682 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
1683 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1684 +
1685 + if (pdev->id.revision < 5) {
1686 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
1687 + tmp &= ~SSB_IMCFGLO_SERTO;
1688 + tmp |= 2;
1689 + tmp &= ~SSB_IMCFGLO_REQTO;
1690 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1691 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
1692 + ssb_commit_settings(bus);
1693 + } else if (pdev->id.revision >= 11) {
1694 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1695 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
1696 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1697 + }
1698 +}
1699 +
1700 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
1701 +{
1702 + u32 tmp;
1703 + u8 rev = pc->dev->id.revision;
1704 +
1705 + if (rev == 0 || rev == 1) {
1706 + /* TLP Workaround register. */
1707 + tmp = ssb_pcie_read(pc, 0x4);
1708 + tmp |= 0x8;
1709 + ssb_pcie_write(pc, 0x4, tmp);
1710 + }
1711 + if (rev == 1) {
1712 + /* DLLP Link Control register. */
1713 + tmp = ssb_pcie_read(pc, 0x100);
1714 + tmp |= 0x40;
1715 + ssb_pcie_write(pc, 0x100, tmp);
1716 + }
1717 +
1718 + if (rev == 0) {
1719 + const u8 serdes_rx_device = 0x1F;
1720 +
1721 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1722 + 2 /* Timer */, 0x8128);
1723 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1724 + 6 /* CDR */, 0x0100);
1725 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1726 + 7 /* CDR BW */, 0x1466);
1727 + } else if (rev == 3 || rev == 4 || rev == 5) {
1728 + /* TODO: DLLP Power Management Threshold */
1729 + ssb_pcicore_serdes_workaround(pc);
1730 + /* TODO: ASPM */
1731 + } else if (rev == 7) {
1732 + /* TODO: No PLL down */
1733 + }
1734 +
1735 + if (rev >= 6) {
1736 + /* Miscellaneous Configuration Fixup */
1737 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
1738 + if (!(tmp & 0x8000))
1739 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
1740 + tmp | 0x8000);
1741 + }
1742 +}
1743
1744 /**************************************************
1745 * Generic and Clientmode operation code.
1746 **************************************************/
1747
1748 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1749 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1750 {
1751 + struct ssb_device *pdev = pc->dev;
1752 + struct ssb_bus *bus = pdev->bus;
1753 +
1754 + if (bus->bustype == SSB_BUSTYPE_PCI)
1755 + ssb_pcicore_fix_sprom_core_index(pc);
1756 +
1757 /* Disable PCI interrupts. */
1758 - ssb_write32(pc->dev, SSB_INTVEC, 0);
1759 + ssb_write32(pdev, SSB_INTVEC, 0);
1760 +
1761 + /* Additional PCIe always once-executed workarounds */
1762 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
1763 + ssb_pcicore_serdes_workaround(pc);
1764 + /* TODO: ASPM */
1765 + /* TODO: Clock Request Update */
1766 + }
1767 }
1768
1769 -void ssb_pcicore_init(struct ssb_pcicore *pc)
1770 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
1771 {
1772 struct ssb_device *dev = pc->dev;
1773 - struct ssb_bus *bus;
1774
1775 if (!dev)
1776 return;
1777 - bus = dev->bus;
1778 if (!ssb_device_is_enabled(dev))
1779 ssb_device_enable(dev, 0);
1780
1781 @@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc
1782 pcicore_write32(pc, 0x134, data);
1783 }
1784
1785 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1786 - u8 address, u16 data)
1787 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
1788 +{
1789 + const u16 mdio_control = 0x128;
1790 + const u16 mdio_data = 0x12C;
1791 + u32 v;
1792 + int i;
1793 +
1794 + v = (1 << 30); /* Start of Transaction */
1795 + v |= (1 << 28); /* Write Transaction */
1796 + v |= (1 << 17); /* Turnaround */
1797 + v |= (0x1F << 18);
1798 + v |= (phy << 4);
1799 + pcicore_write32(pc, mdio_data, v);
1800 +
1801 + udelay(10);
1802 + for (i = 0; i < 200; i++) {
1803 + v = pcicore_read32(pc, mdio_control);
1804 + if (v & 0x100 /* Trans complete */)
1805 + break;
1806 + msleep(1);
1807 + }
1808 +}
1809 +
1810 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
1811 {
1812 const u16 mdio_control = 0x128;
1813 const u16 mdio_data = 0x12C;
1814 + int max_retries = 10;
1815 + u16 ret = 0;
1816 u32 v;
1817 int i;
1818
1819 @@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s
1820 v |= 0x2; /* MDIO Clock Divisor */
1821 pcicore_write32(pc, mdio_control, v);
1822
1823 + if (pc->dev->id.revision >= 10) {
1824 + max_retries = 200;
1825 + ssb_pcie_mdio_set_phy(pc, device);
1826 + }
1827 +
1828 v = (1 << 30); /* Start of Transaction */
1829 - v |= (1 << 28); /* Write Transaction */
1830 + v |= (1 << 29); /* Read Transaction */
1831 v |= (1 << 17); /* Turnaround */
1832 - v |= (u32)device << 22;
1833 + if (pc->dev->id.revision < 10)
1834 + v |= (u32)device << 22;
1835 v |= (u32)address << 18;
1836 - v |= data;
1837 pcicore_write32(pc, mdio_data, v);
1838 /* Wait for the device to complete the transaction */
1839 udelay(10);
1840 - for (i = 0; i < 10; i++) {
1841 + for (i = 0; i < max_retries; i++) {
1842 v = pcicore_read32(pc, mdio_control);
1843 - if (v & 0x100 /* Trans complete */)
1844 + if (v & 0x100 /* Trans complete */) {
1845 + udelay(10);
1846 + ret = pcicore_read32(pc, mdio_data);
1847 break;
1848 + }
1849 msleep(1);
1850 }
1851 pcicore_write32(pc, mdio_control, 0);
1852 + return ret;
1853 }
1854
1855 -static void ssb_broadcast_value(struct ssb_device *dev,
1856 - u32 address, u32 data)
1857 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1858 + u8 address, u16 data)
1859 {
1860 - /* This is used for both, PCI and ChipCommon core, so be careful. */
1861 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1862 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1863 + const u16 mdio_control = 0x128;
1864 + const u16 mdio_data = 0x12C;
1865 + int max_retries = 10;
1866 + u32 v;
1867 + int i;
1868
1869 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
1870 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
1871 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
1872 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
1873 -}
1874 + v = 0x80; /* Enable Preamble Sequence */
1875 + v |= 0x2; /* MDIO Clock Divisor */
1876 + pcicore_write32(pc, mdio_control, v);
1877
1878 -static void ssb_commit_settings(struct ssb_bus *bus)
1879 -{
1880 - struct ssb_device *dev;
1881 + if (pc->dev->id.revision >= 10) {
1882 + max_retries = 200;
1883 + ssb_pcie_mdio_set_phy(pc, device);
1884 + }
1885
1886 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1887 - if (WARN_ON(!dev))
1888 - return;
1889 - /* This forces an update of the cached registers. */
1890 - ssb_broadcast_value(dev, 0xFD8, 0);
1891 + v = (1 << 30); /* Start of Transaction */
1892 + v |= (1 << 28); /* Write Transaction */
1893 + v |= (1 << 17); /* Turnaround */
1894 + if (pc->dev->id.revision < 10)
1895 + v |= (u32)device << 22;
1896 + v |= (u32)address << 18;
1897 + v |= data;
1898 + pcicore_write32(pc, mdio_data, v);
1899 + /* Wait for the device to complete the transaction */
1900 + udelay(10);
1901 + for (i = 0; i < max_retries; i++) {
1902 + v = pcicore_read32(pc, mdio_control);
1903 + if (v & 0x100 /* Trans complete */)
1904 + break;
1905 + msleep(1);
1906 + }
1907 + pcicore_write32(pc, mdio_control, 0);
1908 }
1909
1910 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
1911 @@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1912 if (pc->setup_done)
1913 goto out;
1914 if (pdev->id.coreid == SSB_DEV_PCI) {
1915 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1916 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1917 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1918 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1919 -
1920 - if (pdev->id.revision < 5) {
1921 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1922 - tmp &= ~SSB_IMCFGLO_SERTO;
1923 - tmp |= 2;
1924 - tmp &= ~SSB_IMCFGLO_REQTO;
1925 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1926 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1927 - ssb_commit_settings(bus);
1928 - } else if (pdev->id.revision >= 11) {
1929 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1930 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1931 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1932 - }
1933 + ssb_pcicore_pci_setup_workarounds(pc);
1934 } else {
1935 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1936 - //TODO: Better make defines for all these magic PCIE values.
1937 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1938 - /* TLP Workaround register. */
1939 - tmp = ssb_pcie_read(pc, 0x4);
1940 - tmp |= 0x8;
1941 - ssb_pcie_write(pc, 0x4, tmp);
1942 - }
1943 - if (pdev->id.revision == 0) {
1944 - const u8 serdes_rx_device = 0x1F;
1945 -
1946 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1947 - 2 /* Timer */, 0x8128);
1948 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1949 - 6 /* CDR */, 0x0100);
1950 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1951 - 7 /* CDR BW */, 0x1466);
1952 - } else if (pdev->id.revision == 1) {
1953 - /* DLLP Link Control register. */
1954 - tmp = ssb_pcie_read(pc, 0x100);
1955 - tmp |= 0x40;
1956 - ssb_pcie_write(pc, 0x100, tmp);
1957 - }
1958 + ssb_pcicore_pcie_setup_workarounds(pc);
1959 }
1960 pc->setup_done = 1;
1961 out:
1962 --- a/drivers/ssb/sprom.c
1963 +++ b/drivers/ssb/sprom.c
1964 @@ -2,7 +2,7 @@
1965 * Sonics Silicon Backplane
1966 * Common SPROM support routines
1967 *
1968 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
1969 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
1970 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1971 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1972 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1973 @@ -17,7 +17,7 @@
1974 #include <linux/slab.h>
1975
1976
1977 -static const struct ssb_sprom *fallback_sprom;
1978 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
1979
1980
1981 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
1982 @@ -145,36 +145,43 @@ out:
1983 }
1984
1985 /**
1986 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
1987 + * ssb_arch_register_fallback_sprom - Registers a method providing a
1988 + * fallback SPROM if no SPROM is found.
1989 *
1990 - * @sprom: The SPROM data structure to register.
1991 + * @sprom_callback: The callback function.
1992 *
1993 - * With this function the architecture implementation may register a fallback
1994 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
1995 - * where no valid SPROM can be found in the shadow registers.
1996 + * With this function the architecture implementation may register a
1997 + * callback handler which fills the SPROM data structure. The fallback is
1998 + * only used for PCI based SSB devices, where no valid SPROM can be found
1999 + * in the shadow registers.
2000 + *
2001 + * This function is useful for weird architectures that have a half-assed
2002 + * SSB device hardwired to their PCI bus.
2003 + *
2004 + * Note that it does only work with PCI attached SSB devices. PCMCIA
2005 + * devices currently don't use this fallback.
2006 + * Architectures must provide the SPROM for native SSB devices anyway, so
2007 + * the fallback also isn't used for native devices.
2008 *
2009 - * This function is useful for weird architectures that have a half-assed SSB device
2010 - * hardwired to their PCI bus.
2011 - *
2012 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
2013 - * don't use this fallback.
2014 - * Architectures must provide the SPROM for native SSB devices anyway,
2015 - * so the fallback also isn't used for native devices.
2016 - *
2017 - * This function is available for architecture code, only. So it is not exported.
2018 + * This function is available for architecture code, only. So it is not
2019 + * exported.
2020 */
2021 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
2022 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
2023 + struct ssb_sprom *out))
2024 {
2025 - if (fallback_sprom)
2026 + if (get_fallback_sprom)
2027 return -EEXIST;
2028 - fallback_sprom = sprom;
2029 + get_fallback_sprom = sprom_callback;
2030
2031 return 0;
2032 }
2033
2034 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
2035 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
2036 {
2037 - return fallback_sprom;
2038 + if (!get_fallback_sprom)
2039 + return -ENOENT;
2040 +
2041 + return get_fallback_sprom(bus, out);
2042 }
2043
2044 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
2045 @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
2046 /* this routine differs from specs as we do not access SPROM directly
2047 on PCMCIA */
2048 if (bus->bustype == SSB_BUSTYPE_PCI &&
2049 - bus->chipco.dev && /* can be unavailible! */
2050 + bus->chipco.dev && /* can be unavailable! */
2051 bus->chipco.dev->id.revision >= 31)
2052 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
2053
2054 --- a/drivers/ssb/ssb_private.h
2055 +++ b/drivers/ssb/ssb_private.h
2056 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2057 const char *buf, size_t count,
2058 int (*sprom_check_crc)(const u16 *sprom, size_t size),
2059 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
2060 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
2061 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
2062 + struct ssb_sprom *out);
2063
2064
2065 /* core.c */
2066 @@ -206,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
2067 }
2068 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
2069
2070 +/* driver_chipcommon_pmu.c */
2071 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
2072 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
2073 +
2074 #endif /* LINUX_SSB_PRIVATE_H_ */
2075 --- a/include/linux/ssb/ssb_driver_chipcommon.h
2076 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
2077 @@ -8,7 +8,7 @@
2078 * gpio interface, extbus, and support for serial and parallel flashes.
2079 *
2080 * Copyright 2005, Broadcom Corporation
2081 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
2082 + * Copyright 2006, Michael Buesch <m@bues.ch>
2083 *
2084 * Licensed under the GPL version 2. See COPYING for details.
2085 */
2086 @@ -123,6 +123,8 @@
2087 #define SSB_CHIPCO_FLASHDATA 0x0048
2088 #define SSB_CHIPCO_BCAST_ADDR 0x0050
2089 #define SSB_CHIPCO_BCAST_DATA 0x0054
2090 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
2091 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
2092 #define SSB_CHIPCO_GPIOIN 0x0060
2093 #define SSB_CHIPCO_GPIOOUT 0x0064
2094 #define SSB_CHIPCO_GPIOOUTEN 0x0068
2095 @@ -131,6 +133,9 @@
2096 #define SSB_CHIPCO_GPIOIRQ 0x0074
2097 #define SSB_CHIPCO_WATCHDOG 0x0080
2098 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
2099 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
2100 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
2101 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
2102 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
2103 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
2104 #define SSB_CHIPCO_CLOCK_N 0x0090
2105 @@ -189,8 +194,10 @@
2106 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
2107 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
2108 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
2109 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
2110 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
2111 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
2112 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
2113 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
2114 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
2115 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
2116 #define SSB_CHIPCO_UART0_DATA 0x0300
2117 #define SSB_CHIPCO_UART0_IMR 0x0304
2118 --- a/drivers/ssb/b43_pci_bridge.c
2119 +++ b/drivers/ssb/b43_pci_bridge.c
2120 @@ -5,12 +5,13 @@
2121 * because of its small size we include it in the SSB core
2122 * instead of creating a standalone module.
2123 *
2124 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
2125 + * Copyright 2007 Michael Buesch <m@bues.ch>
2126 *
2127 * Licensed under the GNU/GPL. See COPYING for details.
2128 */
2129
2130 #include <linux/pci.h>
2131 +#include <linux/module.h>
2132 #include <linux/ssb/ssb.h>
2133
2134 #include "ssb_private.h"
2135 --- a/drivers/ssb/driver_extif.c
2136 +++ b/drivers/ssb/driver_extif.c
2137 @@ -3,7 +3,7 @@
2138 * Broadcom EXTIF core driver
2139 *
2140 * Copyright 2005, Broadcom Corporation
2141 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
2142 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2143 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
2144 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
2145 *
2146 --- a/drivers/ssb/driver_mipscore.c
2147 +++ b/drivers/ssb/driver_mipscore.c
2148 @@ -3,7 +3,7 @@
2149 * Broadcom MIPS core driver
2150 *
2151 * Copyright 2005, Broadcom Corporation
2152 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
2153 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2154 *
2155 * Licensed under the GNU/GPL. See COPYING for details.
2156 */
2157 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
2158 struct ssb_bus *bus = mcore->dev->bus;
2159 u32 pll_type, n, m, rate = 0;
2160
2161 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
2162 + return ssb_pmu_get_cpu_clock(&bus->chipco);
2163 +
2164 if (bus->extif.dev) {
2165 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
2166 } else if (bus->chipco.dev) {
2167 --- a/drivers/ssb/embedded.c
2168 +++ b/drivers/ssb/embedded.c
2169 @@ -3,7 +3,7 @@
2170 * Embedded systems support code
2171 *
2172 * Copyright 2005-2008, Broadcom Corporation
2173 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
2174 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
2175 *
2176 * Licensed under the GNU/GPL. See COPYING for details.
2177 */
2178 --- a/drivers/ssb/pcmcia.c
2179 +++ b/drivers/ssb/pcmcia.c
2180 @@ -3,7 +3,7 @@
2181 * PCMCIA-Hostbus related functions
2182 *
2183 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2184 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
2185 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2186 *
2187 * Licensed under the GNU/GPL. See COPYING for details.
2188 */
2189 @@ -677,14 +677,10 @@ static int ssb_pcmcia_do_get_invariants(
2190 case SSB_PCMCIA_CIS_ANTGAIN:
2191 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2192 "antg tpl size");
2193 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
2194 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
2195 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
2196 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
2197 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
2198 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
2199 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
2200 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
2201 + sprom->antenna_gain.a0 = tuple->TupleData[1];
2202 + sprom->antenna_gain.a1 = tuple->TupleData[1];
2203 + sprom->antenna_gain.a2 = tuple->TupleData[1];
2204 + sprom->antenna_gain.a3 = tuple->TupleData[1];
2205 break;
2206 case SSB_PCMCIA_CIS_BFLAGS:
2207 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
2208 --- a/drivers/ssb/sdio.c
2209 +++ b/drivers/ssb/sdio.c
2210 @@ -6,7 +6,7 @@
2211 *
2212 * Based on drivers/ssb/pcmcia.c
2213 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2214 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
2215 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2216 *
2217 * Licensed under the GNU/GPL. See COPYING for details.
2218 *
2219 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
2220 case SSB_SDIO_CIS_ANTGAIN:
2221 GOTO_ERROR_ON(tuple->size != 2,
2222 "antg tpl size");
2223 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
2224 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
2225 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
2226 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
2227 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
2228 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
2229 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
2230 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
2231 + sprom->antenna_gain.a0 = tuple->data[1];
2232 + sprom->antenna_gain.a1 = tuple->data[1];
2233 + sprom->antenna_gain.a2 = tuple->data[1];
2234 + sprom->antenna_gain.a3 = tuple->data[1];
2235 break;
2236 case SSB_SDIO_CIS_BFLAGS:
2237 GOTO_ERROR_ON((tuple->size != 3) &&
Staging tree of florian