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kernel: move bcma patches pushed to wireless-next
[openwrt/staging/florian.git] / target / linux / generic / patches-3.14 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Makefile
2 +++ b/drivers/bcma/Makefile
3 @@ -3,6 +3,7 @@ bcma-y += driver_chipcommon.o driver
4 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
5 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
6 bcma-y += driver_pci.o
7 +bcma-y += driver_pcie2.o
8 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
9 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
10 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
11 --- a/drivers/bcma/driver_chipcommon_pmu.c
12 +++ b/drivers/bcma/driver_chipcommon_pmu.c
13 @@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
14 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
15 break;
16
17 + case BCMA_CHIP_ID_BCM43131:
18 + case BCMA_CHIP_ID_BCM43217:
19 case BCMA_CHIP_ID_BCM43227:
20 case BCMA_CHIP_ID_BCM43228:
21 case BCMA_CHIP_ID_BCM43428:
22 --- a/drivers/bcma/driver_gpio.c
23 +++ b/drivers/bcma/driver_gpio.c
24 @@ -218,7 +218,15 @@ int bcma_gpio_init(struct bcma_drv_cc *c
25 #if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
26 chip->to_irq = bcma_gpio_to_irq;
27 #endif
28 - chip->ngpio = 16;
29 + switch (cc->core->bus->chipinfo.id) {
30 + case BCMA_CHIP_ID_BCM5357:
31 + case BCMA_CHIP_ID_BCM53572:
32 + chip->ngpio = 32;
33 + break;
34 + default:
35 + chip->ngpio = 16;
36 + }
37 +
38 /* There is just one SoC in one device and its GPIO addresses should be
39 * deterministic to address them more easily. The other buses could get
40 * a random base number. */
41 --- /dev/null
42 +++ b/drivers/bcma/driver_pcie2.c
43 @@ -0,0 +1,175 @@
44 +/*
45 + * Broadcom specific AMBA
46 + * PCIe Gen 2 Core
47 + *
48 + * Copyright 2014, Broadcom Corporation
49 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
50 + *
51 + * Licensed under the GNU/GPL. See COPYING for details.
52 + */
53 +
54 +#include "bcma_private.h"
55 +#include <linux/bcma/bcma.h>
56 +
57 +/**************************************************
58 + * R/W ops.
59 + **************************************************/
60 +
61 +#if 0
62 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
63 +{
64 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
65 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
66 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
67 +}
68 +#endif
69 +
70 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
71 + u32 val)
72 +{
73 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
74 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
75 +}
76 +
77 +/**************************************************
78 + * Init.
79 + **************************************************/
80 +
81 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
82 + bool enable)
83 +{
84 + u32 val;
85 +
86 + /* restore back to default */
87 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
88 + val |= PCIE2_CLKC_DLYPERST;
89 + val &= ~PCIE2_CLKC_DISSPROMLD;
90 + if (enable) {
91 + val &= ~PCIE2_CLKC_DLYPERST;
92 + val |= PCIE2_CLKC_DISSPROMLD;
93 + }
94 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
95 + /* flush */
96 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
97 +}
98 +
99 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
100 +{
101 + /* LTR0 */
102 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
103 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
104 + /* LTR1 */
105 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
106 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
107 + /* LTR2 */
108 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
109 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
110 +}
111 +
112 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
113 +{
114 + u8 core_rev = pcie2->core->id.rev;
115 + u32 devstsctr2;
116 +
117 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
118 + return;
119 +
120 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
121 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
122 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
123 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
124 + /* force the right LTR values */
125 + bcma_core_pcie2_set_ltr_vals(pcie2);
126 +
127 + /* TODO:
128 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
129 +
130 + /* enable the LTR */
131 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
132 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
133 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
134 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
135 +
136 + /* set the LTR state to be active */
137 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
138 + PCIE2_LTR_ACTIVE);
139 + usleep_range(1000, 2000);
140 +
141 + /* set the LTR state to be sleep */
142 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
143 + PCIE2_LTR_SLEEP);
144 + usleep_range(1000, 2000);
145 + }
146 +}
147 +
148 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
149 +{
150 + u8 core_rev = pcie2->core->id.rev;
151 + bool pciewar160, pciewar162;
152 +
153 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
154 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
155 + core_rev == 9 || core_rev == 11;
156 +
157 + if (!pciewar160 && !pciewar162)
158 + return;
159 +
160 +/* TODO */
161 +#if 0
162 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
163 + PCIE_DISABLE_L1CLK_GATING);
164 +#if 0
165 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
166 + PCIEGEN2_COE_PVT_TL_CTRL_0);
167 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
168 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
169 +#endif
170 +#endif
171 +}
172 +
173 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
174 +{
175 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
176 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
177 +}
178 +
179 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
180 +{
181 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
182 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
183 +}
184 +
185 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
186 +{
187 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
188 + u8 core_rev = pcie2->core->id.rev;
189 + u32 alp_khz, pm_value;
190 +
191 + if (core_rev <= 13) {
192 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
193 + pm_value = (1000000 * 2) / alp_khz;
194 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
195 + PCIE2_PVT_REG_PM_CLK_PERIOD);
196 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
197 + }
198 +}
199 +
200 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
201 +{
202 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
203 + u32 tmp;
204 +
205 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
206 + if ((tmp & 0xe) >> 1 == 2)
207 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
208 +
209 + /* TODO: Do we need pcie_reqsize? */
210 +
211 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
212 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
213 + bcma_core_pcie2_hw_ltr_war(pcie2);
214 + pciedev_crwlpciegen2(pcie2);
215 + pciedev_reg_pm_clk_period(pcie2);
216 + pciedev_crwlpciegen2_180(pcie2);
217 + pciedev_crwlpciegen2_182(pcie2);
218 +}
219 --- a/drivers/bcma/host_pci.c
220 +++ b/drivers/bcma/host_pci.c
221 @@ -208,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
222 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
223 bus->boardinfo.type = bus->host_pci->subsystem_device;
224
225 + /* Initialize struct, detect chip */
226 + bcma_init_bus(bus);
227 +
228 /* Register */
229 err = bcma_bus_register(bus);
230 if (err)
231 @@ -279,7 +282,10 @@ static const struct pci_device_id bcma_p
232 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
233 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
234 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
235 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
236 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
237 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
238 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xA8DB */
239 { 0, },
240 };
241 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
242 --- a/drivers/bcma/main.c
243 +++ b/drivers/bcma/main.c
244 @@ -120,10 +120,53 @@ static void bcma_release_core_dev(struct
245 kfree(core);
246 }
247
248 -static int bcma_register_cores(struct bcma_bus *bus)
249 +static bool bcma_is_core_needed_early(u16 core_id)
250 +{
251 + switch (core_id) {
252 + case BCMA_CORE_NS_NAND:
253 + case BCMA_CORE_NS_QSPI:
254 + return true;
255 + }
256 +
257 + return false;
258 +}
259 +
260 +static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
261 +{
262 + int err;
263 +
264 + core->dev.release = bcma_release_core_dev;
265 + core->dev.bus = &bcma_bus_type;
266 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
267 +
268 + switch (bus->hosttype) {
269 + case BCMA_HOSTTYPE_PCI:
270 + core->dev.parent = &bus->host_pci->dev;
271 + core->dma_dev = &bus->host_pci->dev;
272 + core->irq = bus->host_pci->irq;
273 + break;
274 + case BCMA_HOSTTYPE_SOC:
275 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
276 + core->dma_dev = &core->dev;
277 + break;
278 + case BCMA_HOSTTYPE_SDIO:
279 + break;
280 + }
281 +
282 + err = device_register(&core->dev);
283 + if (err) {
284 + bcma_err(bus, "Could not register dev for core 0x%03X\n",
285 + core->id.id);
286 + put_device(&core->dev);
287 + return;
288 + }
289 + core->dev_registered = true;
290 +}
291 +
292 +static int bcma_register_devices(struct bcma_bus *bus)
293 {
294 struct bcma_device *core;
295 - int err, dev_id = 0;
296 + int err;
297
298 list_for_each_entry(core, &bus->cores, list) {
299 /* We support that cores ourself */
300 @@ -132,44 +175,22 @@ static int bcma_register_cores(struct bc
301 case BCMA_CORE_CHIPCOMMON:
302 case BCMA_CORE_PCI:
303 case BCMA_CORE_PCIE:
304 + case BCMA_CORE_PCIE2:
305 case BCMA_CORE_MIPS_74K:
306 case BCMA_CORE_4706_MAC_GBIT_COMMON:
307 continue;
308 }
309
310 + /* Early cores were already registered */
311 + if (bcma_is_core_needed_early(core->id.id))
312 + continue;
313 +
314 /* Only first GMAC core on BCM4706 is connected and working */
315 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
316 core->core_unit > 0)
317 continue;
318
319 - core->dev.release = bcma_release_core_dev;
320 - core->dev.bus = &bcma_bus_type;
321 - dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
322 -
323 - switch (bus->hosttype) {
324 - case BCMA_HOSTTYPE_PCI:
325 - core->dev.parent = &bus->host_pci->dev;
326 - core->dma_dev = &bus->host_pci->dev;
327 - core->irq = bus->host_pci->irq;
328 - break;
329 - case BCMA_HOSTTYPE_SOC:
330 - core->dev.dma_mask = &core->dev.coherent_dma_mask;
331 - core->dma_dev = &core->dev;
332 - break;
333 - case BCMA_HOSTTYPE_SDIO:
334 - break;
335 - }
336 -
337 - err = device_register(&core->dev);
338 - if (err) {
339 - bcma_err(bus,
340 - "Could not register dev for core 0x%03X\n",
341 - core->id.id);
342 - put_device(&core->dev);
343 - continue;
344 - }
345 - core->dev_registered = true;
346 - dev_id++;
347 + bcma_register_core(bus, core);
348 }
349
350 #ifdef CONFIG_BCMA_DRIVER_MIPS
351 @@ -246,6 +267,12 @@ int bcma_bus_register(struct bcma_bus *b
352 bcma_core_chipcommon_early_init(&bus->drv_cc);
353 }
354
355 + /* Cores providing flash access go before SPROM init */
356 + list_for_each_entry(core, &bus->cores, list) {
357 + if (bcma_is_core_needed_early(core->id.id))
358 + bcma_register_core(bus, core);
359 + }
360 +
361 /* Try to get SPROM */
362 err = bcma_sprom_get(bus);
363 if (err == -ENOENT) {
364 @@ -281,6 +308,13 @@ int bcma_bus_register(struct bcma_bus *b
365 bcma_core_pci_init(&bus->drv_pci[1]);
366 }
367
368 + /* Init PCIe Gen 2 core */
369 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
370 + if (core) {
371 + bus->drv_pcie2.core = core;
372 + bcma_core_pcie2_init(&bus->drv_pcie2);
373 + }
374 +
375 /* Init GBIT MAC COMMON core */
376 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
377 if (core) {
378 @@ -289,7 +323,7 @@ int bcma_bus_register(struct bcma_bus *b
379 }
380
381 /* Register found cores */
382 - bcma_register_cores(bus);
383 + bcma_register_devices(bus);
384
385 bcma_info(bus, "Bus registered\n");
386
387 @@ -326,8 +360,6 @@ int __init bcma_bus_early_register(struc
388 struct bcma_device *core;
389 struct bcma_device_id match;
390
391 - bcma_init_bus(bus);
392 -
393 match.manuf = BCMA_MANUF_BCM;
394 match.id = bcma_cc_core_id(bus);
395 match.class = BCMA_CL_SIM;
396 --- a/drivers/bcma/sprom.c
397 +++ b/drivers/bcma/sprom.c
398 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
399 SPEX(_field[7], _offset + 14, _mask, _shift); \
400 } while (0)
401
402 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
403 +{
404 + u16 v;
405 + u8 gain;
406 +
407 + v = in[SPOFF(offset)];
408 + gain = (v & mask) >> shift;
409 + if (gain == 0xFF) {
410 + gain = 8; /* If unset use 2dBm */
411 + } else {
412 + /* Q5.2 Fractional part is stored in 0xC0 */
413 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
414 + }
415 +
416 + return (s8)gain;
417 +}
418 +
419 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
420 {
421 u16 v, o;
422 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
423 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
424
425 /* Extract the antenna gain values. */
426 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
427 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
428 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
429 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
430 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
431 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
432 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
433 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
434 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
435 + SSB_SPROM8_AGAIN01,
436 + SSB_SPROM8_AGAIN0,
437 + SSB_SPROM8_AGAIN0_SHIFT);
438 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
439 + SSB_SPROM8_AGAIN01,
440 + SSB_SPROM8_AGAIN1,
441 + SSB_SPROM8_AGAIN1_SHIFT);
442 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
443 + SSB_SPROM8_AGAIN23,
444 + SSB_SPROM8_AGAIN2,
445 + SSB_SPROM8_AGAIN2_SHIFT);
446 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
447 + SSB_SPROM8_AGAIN23,
448 + SSB_SPROM8_AGAIN3,
449 + SSB_SPROM8_AGAIN3_SHIFT);
450
451 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
452 SSB_SPROM8_LEDDC_ON_SHIFT);
453 @@ -509,6 +534,8 @@ static bool bcma_sprom_onchip_available(
454 /* for these chips OTP is always available */
455 present = true;
456 break;
457 + case BCMA_CHIP_ID_BCM43131:
458 + case BCMA_CHIP_ID_BCM43217:
459 case BCMA_CHIP_ID_BCM43227:
460 case BCMA_CHIP_ID_BCM43228:
461 case BCMA_CHIP_ID_BCM43428:
462 --- a/include/linux/bcma/bcma.h
463 +++ b/include/linux/bcma/bcma.h
464 @@ -6,6 +6,7 @@
465
466 #include <linux/bcma/bcma_driver_chipcommon.h>
467 #include <linux/bcma/bcma_driver_pci.h>
468 +#include <linux/bcma/bcma_driver_pcie2.h>
469 #include <linux/bcma/bcma_driver_mips.h>
470 #include <linux/bcma/bcma_driver_gmac_cmn.h>
471 #include <linux/ssb/ssb.h> /* SPROM sharing */
472 @@ -72,17 +73,17 @@ struct bcma_host_ops {
473 /* Core-ID values. */
474 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
475 #define BCMA_CORE_4706_CHIPCOMMON 0x500
476 -#define BCMA_CORE_PCIEG2 0x501
477 -#define BCMA_CORE_DMA 0x502
478 -#define BCMA_CORE_SDIO3 0x503
479 -#define BCMA_CORE_USB20 0x504
480 -#define BCMA_CORE_USB30 0x505
481 -#define BCMA_CORE_A9JTAG 0x506
482 -#define BCMA_CORE_DDR23 0x507
483 -#define BCMA_CORE_ROM 0x508
484 -#define BCMA_CORE_NAND 0x509
485 -#define BCMA_CORE_QSPI 0x50A
486 -#define BCMA_CORE_CHIPCOMMON_B 0x50B
487 +#define BCMA_CORE_NS_PCIEG2 0x501
488 +#define BCMA_CORE_NS_DMA 0x502
489 +#define BCMA_CORE_NS_SDIO3 0x503
490 +#define BCMA_CORE_NS_USB20 0x504
491 +#define BCMA_CORE_NS_USB30 0x505
492 +#define BCMA_CORE_NS_A9JTAG 0x506
493 +#define BCMA_CORE_NS_DDR23 0x507
494 +#define BCMA_CORE_NS_ROM 0x508
495 +#define BCMA_CORE_NS_NAND 0x509
496 +#define BCMA_CORE_NS_QSPI 0x50A
497 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
498 #define BCMA_CORE_4706_SOC_RAM 0x50E
499 #define BCMA_CORE_ARMCA9 0x510
500 #define BCMA_CORE_4706_MAC_GBIT 0x52D
501 @@ -157,6 +158,9 @@ struct bcma_host_ops {
502 /* Chip IDs of PCIe devices */
503 #define BCMA_CHIP_ID_BCM4313 0x4313
504 #define BCMA_CHIP_ID_BCM43142 43142
505 +#define BCMA_CHIP_ID_BCM43131 43131
506 +#define BCMA_CHIP_ID_BCM43217 43217
507 +#define BCMA_CHIP_ID_BCM43222 43222
508 #define BCMA_CHIP_ID_BCM43224 43224
509 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
510 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
511 @@ -328,11 +332,11 @@ struct bcma_bus {
512 struct bcma_device *mapped_core;
513 struct list_head cores;
514 u8 nr_cores;
515 - u8 init_done:1;
516 u8 num;
517
518 struct bcma_drv_cc drv_cc;
519 struct bcma_drv_pci drv_pci[2];
520 + struct bcma_drv_pcie2 drv_pcie2;
521 struct bcma_drv_mips drv_mips;
522 struct bcma_drv_gmac_cmn drv_gmac_cmn;
523
524 --- /dev/null
525 +++ b/include/linux/bcma/bcma_driver_pcie2.h
526 @@ -0,0 +1,158 @@
527 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
528 +#define LINUX_BCMA_DRIVER_PCIE2_H_
529 +
530 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
531 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
532 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
533 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
534 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
535 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
536 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
537 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
538 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
539 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
540 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
541 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
542 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
543 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
544 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
545 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
546 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
547 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
548 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
549 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
550 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
551 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
552 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
553 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
554 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
555 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
556 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
557 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
558 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
559 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
560 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
561 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
562 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
563 +#define PCIE2_LTR_ACTIVE 2
564 +#define PCIE2_LTR_ACTIVE_IDLE 1
565 +#define PCIE2_LTR_SLEEP 0
566 +#define PCIE2_LTR_FINAL_MASK 0x300
567 +#define PCIE2_LTR_FINAL_SHIFT 8
568 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
569 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
570 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
571 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
572 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
573 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
574 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
575 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
576 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
577 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
578 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
579 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
580 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
581 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
582 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
583 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
584 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
585 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
586 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
587 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
588 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
589 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
590 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
591 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
592 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
593 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
594 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
595 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
596 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
597 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
598 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
599 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
600 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
601 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
602 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
603 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
604 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
605 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
606 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
607 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
608 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
609 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
610 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
611 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
612 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
613 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
614 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
615 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
616 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
617 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
618 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
619 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
620 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
621 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
622 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
623 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
624 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
625 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
626 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
627 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
628 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
629 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
630 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
631 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
632 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
633 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
634 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
635 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
636 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
637 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
638 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
639 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
640 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
641 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
642 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
643 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
644 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
645 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
646 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
647 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
648 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
649 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
650 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
651 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
652 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
653 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
654 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
655 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
656 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
657 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
658 +
659 +/* PCIE gen2 config regs */
660 +#define PCIE2_INTSTATUS 0x090
661 +#define PCIE2_INTMASK 0x094
662 +#define PCIE2_SBMBX 0x098
663 +
664 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
665 +
666 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
667 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
668 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
669 +
670 +struct bcma_drv_pcie2 {
671 + struct bcma_device *core;
672 +};
673 +
674 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
675 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
676 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
677 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
678 +
679 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
680 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
681 +
682 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
683 +
684 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
685 --- a/drivers/bcma/scan.c
686 +++ b/drivers/bcma/scan.c
687 @@ -32,17 +32,17 @@ static const struct bcma_device_id_name
688 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
689 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
690 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
691 - { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
692 - { BCMA_CORE_DMA, "DMA" },
693 - { BCMA_CORE_SDIO3, "SDIO3" },
694 - { BCMA_CORE_USB20, "USB 2.0" },
695 - { BCMA_CORE_USB30, "USB 3.0" },
696 - { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
697 - { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
698 - { BCMA_CORE_ROM, "ROM" },
699 - { BCMA_CORE_NAND, "NAND flash controller" },
700 - { BCMA_CORE_QSPI, "SPI flash controller" },
701 - { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
702 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
703 + { BCMA_CORE_NS_DMA, "DMA" },
704 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
705 + { BCMA_CORE_NS_USB20, "USB 2.0" },
706 + { BCMA_CORE_NS_USB30, "USB 3.0" },
707 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
708 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
709 + { BCMA_CORE_NS_ROM, "ROM" },
710 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
711 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
712 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
713 { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
714 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
715 { BCMA_CORE_ALTA, "ALTA (I2S)" },
716 @@ -421,10 +421,13 @@ static int bcma_get_next_core(struct bcm
717 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
718 if (!core->io_addr)
719 return -ENOMEM;
720 - core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
721 - if (!core->io_wrap) {
722 - iounmap(core->io_addr);
723 - return -ENOMEM;
724 + if (core->wrap) {
725 + core->io_wrap = ioremap_nocache(core->wrap,
726 + BCMA_CORE_SIZE);
727 + if (!core->io_wrap) {
728 + iounmap(core->io_addr);
729 + return -ENOMEM;
730 + }
731 }
732 }
733 return 0;
734 @@ -435,9 +438,6 @@ void bcma_init_bus(struct bcma_bus *bus)
735 s32 tmp;
736 struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
737
738 - if (bus->init_done)
739 - return;
740 -
741 INIT_LIST_HEAD(&bus->cores);
742 bus->nr_cores = 0;
743
744 @@ -449,8 +449,6 @@ void bcma_init_bus(struct bcma_bus *bus)
745 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
746 bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
747 chipinfo->id, chipinfo->rev, chipinfo->pkg);
748 -
749 - bus->init_done = true;
750 }
751
752 int bcma_bus_scan(struct bcma_bus *bus)
753 @@ -460,8 +458,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
754
755 int err, core_num = 0;
756
757 - bcma_init_bus(bus);
758 -
759 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
760 if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
761 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
762 --- a/drivers/bcma/host_soc.c
763 +++ b/drivers/bcma/host_soc.c
764 @@ -134,12 +134,16 @@ static void bcma_host_soc_block_write(st
765
766 static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
767 {
768 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
769 + return ~0;
770 return readl(core->io_wrap + offset);
771 }
772
773 static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
774 u32 value)
775 {
776 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
777 + return;
778 writel(value, core->io_wrap + offset);
779 }
780
781 @@ -161,7 +165,6 @@ static const struct bcma_host_ops bcma_h
782 int __init bcma_host_soc_register(struct bcma_soc *soc)
783 {
784 struct bcma_bus *bus = &soc->bus;
785 - int err;
786
787 /* iomap only first core. We have to read some register on this core
788 * to scan the bus.
789 @@ -174,7 +177,18 @@ int __init bcma_host_soc_register(struct
790 bus->hosttype = BCMA_HOSTTYPE_SOC;
791 bus->ops = &bcma_host_soc_ops;
792
793 - /* Register */
794 + /* Initialize struct, detect chip */
795 + bcma_init_bus(bus);
796 +
797 + return 0;
798 +}
799 +
800 +int __init bcma_host_soc_init(struct bcma_soc *soc)
801 +{
802 + struct bcma_bus *bus = &soc->bus;
803 + int err;
804 +
805 + /* Scan bus and initialize it */
806 err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
807 if (err)
808 iounmap(bus->mmio);
809 --- a/drivers/bcma/driver_mips.c
810 +++ b/drivers/bcma/driver_mips.c
811 @@ -21,6 +21,14 @@
812 #include <linux/serial_reg.h>
813 #include <linux/time.h>
814
815 +enum bcma_boot_dev {
816 + BCMA_BOOT_DEV_UNK = 0,
817 + BCMA_BOOT_DEV_ROM,
818 + BCMA_BOOT_DEV_PARALLEL,
819 + BCMA_BOOT_DEV_SERIAL,
820 + BCMA_BOOT_DEV_NAND,
821 +};
822 +
823 static const char * const part_probes[] = { "bcm47xxpart", NULL };
824
825 static struct physmap_flash_data bcma_pflash_data = {
826 @@ -229,11 +237,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
827 }
828 EXPORT_SYMBOL(bcma_cpu_clock);
829
830 +static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
831 +{
832 + struct bcma_drv_cc *cc = &bus->drv_cc;
833 + u8 cc_rev = cc->core->id.rev;
834 +
835 + if (cc_rev == 42) {
836 + struct bcma_device *core;
837 +
838 + core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
839 + if (core) {
840 + switch (bcma_aread32(core, BCMA_IOST) &
841 + BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
842 + case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
843 + return BCMA_BOOT_DEV_SERIAL;
844 + case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
845 + return BCMA_BOOT_DEV_NAND;
846 + case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
847 + default:
848 + return BCMA_BOOT_DEV_ROM;
849 + }
850 + }
851 + } else {
852 + if (cc_rev == 38) {
853 + if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
854 + return BCMA_BOOT_DEV_NAND;
855 + else if (cc->status & BIT(5))
856 + return BCMA_BOOT_DEV_ROM;
857 + }
858 +
859 + if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
860 + BCMA_CC_FLASHT_PARA)
861 + return BCMA_BOOT_DEV_PARALLEL;
862 + else
863 + return BCMA_BOOT_DEV_SERIAL;
864 + }
865 +
866 + return BCMA_BOOT_DEV_SERIAL;
867 +}
868 +
869 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
870 {
871 struct bcma_bus *bus = mcore->core->bus;
872 struct bcma_drv_cc *cc = &bus->drv_cc;
873 struct bcma_pflash *pflash = &cc->pflash;
874 + enum bcma_boot_dev boot_dev;
875
876 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
877 case BCMA_CC_FLASHT_STSER:
878 @@ -269,6 +317,20 @@ static void bcma_core_mips_flash_detect(
879 bcma_nflash_init(cc);
880 }
881 }
882 +
883 + /* Determine flash type this SoC boots from */
884 + boot_dev = bcma_boot_dev(bus);
885 + switch (boot_dev) {
886 + case BCMA_BOOT_DEV_PARALLEL:
887 + case BCMA_BOOT_DEV_SERIAL:
888 + /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
889 + break;
890 + case BCMA_BOOT_DEV_NAND:
891 + /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
892 + break;
893 + default:
894 + break;
895 + }
896 }
897
898 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
899 --- a/include/linux/bcma/bcma_regs.h
900 +++ b/include/linux/bcma/bcma_regs.h
901 @@ -39,6 +39,11 @@
902 #define BCMA_RESET_CTL_RESET 0x0001
903 #define BCMA_RESET_ST 0x0804
904
905 +#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
906 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
907 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
908 +#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
909 +
910 /* BCMA PCI config space registers. */
911 #define BCMA_PCI_PMCSR 0x44
912 #define BCMA_PCI_PE 0x100
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