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ralink: add mt7621 support
[openwrt/staging/florian.git] / target / linux / ramips / patches-3.10 / 0502-MIPS-ralink-add-MT7621-support.patch
1 From 99342a0481d49b6e1ade90fdb02f597cb75f103f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 2 Dec 2013 16:11:09 +0100
4 Subject: [PATCH 502/507] MIPS: ralink: add MT7621 support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/include/asm/mach-ralink/mt7621.h | 39 +++++
9 arch/mips/ralink/Kconfig | 18 ++
10 arch/mips/ralink/Makefile | 7 +-
11 arch/mips/ralink/Platform | 5 +
12 arch/mips/ralink/irq-gic.c | 255 ++++++++++++++++++++++++++++
13 arch/mips/ralink/malta-amon.c | 81 +++++++++
14 arch/mips/ralink/mt7621.c | 186 ++++++++++++++++++++
15 7 files changed, 590 insertions(+), 1 deletion(-)
16 create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
17 create mode 100644 arch/mips/ralink/irq-gic.c
18 create mode 100644 arch/mips/ralink/malta-amon.c
19 create mode 100644 arch/mips/ralink/mt7621.c
20
21 Index: linux-3.10.21/arch/mips/include/asm/mach-ralink/mt7621.h
22 ===================================================================
23 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
24 +++ linux-3.10.21/arch/mips/include/asm/mach-ralink/mt7621.h 2013-12-09 19:52:51.752677298 +0100
25 @@ -0,0 +1,39 @@
26 +/*
27 + * This program is free software; you can redistribute it and/or modify it
28 + * under the terms of the GNU General Public License version 2 as published
29 + * by the Free Software Foundation.
30 + *
31 + * Parts of this file are based on Ralink's 2.6.21 BSP
32 + *
33 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
34 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
35 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
36 + */
37 +
38 +#ifndef _MT7621_REGS_H_
39 +#define _MT7621_REGS_H_
40 +
41 +#define MT7621_SYSC_BASE 0x1E000000
42 +
43 +#define SYSC_REG_CHIP_NAME0 0x00
44 +#define SYSC_REG_CHIP_NAME1 0x04
45 +#define SYSC_REG_CHIP_REV 0x0c
46 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
47 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
48 +
49 +#define CHIP_REV_PKG_MASK 0x1
50 +#define CHIP_REV_PKG_SHIFT 16
51 +#define CHIP_REV_VER_MASK 0xf
52 +#define CHIP_REV_VER_SHIFT 8
53 +#define CHIP_REV_ECO_MASK 0xf
54 +
55 +#define MT7621_DRAM_BASE 0x0
56 +#define MT7621_DDR2_SIZE_MIN 32
57 +#define MT7621_DDR2_SIZE_MAX 256
58 +
59 +#define MT7621_CHIP_NAME0 0x3637544D
60 +#define MT7621_CHIP_NAME1 0x20203132
61 +
62 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
63 +
64 +#endif
65 Index: linux-3.10.21/arch/mips/ralink/Kconfig
66 ===================================================================
67 --- linux-3.10.21.orig/arch/mips/ralink/Kconfig 2013-12-09 19:51:55.600675960 +0100
68 +++ linux-3.10.21/arch/mips/ralink/Kconfig 2013-12-09 19:52:51.756677296 +0100
69 @@ -1,5 +1,10 @@
70 if RALINK
71
72 +config IRQ_INTC
73 + bool
74 + default y
75 + depends on !SOC_MT7621
76 +
77 config CLKEVT_RT3352
78 bool "Systick Clockevent source"
79 depends on SOC_RT305X || SOC_MT7620
80 @@ -35,6 +40,15 @@
81 select USB_ARCH_HAS_EHCI
82 select HW_HAS_PCI
83
84 + config SOC_MT7621
85 + bool "MT7621"
86 + select MIPS_CPU_SCACHE
87 + select SYS_SUPPORTS_MULTITHREADING
88 + select SYS_SUPPORTS_SMP
89 + select SYS_SUPPORTS_MIPS_CMP
90 + select IRQ_GIC
91 + select HW_HAS_PCI
92 +
93 endchoice
94
95 choice
96 @@ -62,6 +76,10 @@
97 bool "MT7620A eval kit"
98 depends on SOC_MT7620
99
100 + config DTB_MT7621_EVAL
101 + bool "MT7621 eval kit"
102 + depends on SOC_MT7621
103 +
104 endchoice
105
106 endif
107 Index: linux-3.10.21/arch/mips/ralink/Makefile
108 ===================================================================
109 --- linux-3.10.21.orig/arch/mips/ralink/Makefile 2013-12-09 19:51:55.600675960 +0100
110 +++ linux-3.10.21/arch/mips/ralink/Makefile 2013-12-09 19:52:51.756677296 +0100
111 @@ -6,7 +6,11 @@
112 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
113 # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
114
115 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
116 +obj-y := prom.o of.o reset.o clk.o timer.o
117 +
118 +obj-$(CONFIG_IRQ_INTC) += irq.o
119 +obj-$(CONFIG_IRQ_GIC) += irq-gic.o
120 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
121
122 obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
123
124 @@ -16,6 +20,7 @@
125 obj-$(CONFIG_SOC_RT305X) += rt305x.o
126 obj-$(CONFIG_SOC_RT3883) += rt3883.o
127 obj-$(CONFIG_SOC_MT7620) += mt7620.o
128 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
129
130 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
131
132 Index: linux-3.10.21/arch/mips/ralink/Platform
133 ===================================================================
134 --- linux-3.10.21.orig/arch/mips/ralink/Platform 2013-12-09 19:51:55.000000000 +0100
135 +++ linux-3.10.21/arch/mips/ralink/Platform 2013-12-09 19:53:54.660678800 +0100
136 @@ -26,3 +26,10 @@
137 # Ralink MT7620
138 #
139 load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
140 +cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
141 +
142 +#
143 +# Ralink MT7621
144 +#
145 +load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
146 +cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
147 Index: linux-3.10.21/arch/mips/ralink/irq-gic.c
148 ===================================================================
149 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
150 +++ linux-3.10.21/arch/mips/ralink/irq-gic.c 2013-12-09 19:52:51.756677296 +0100
151 @@ -0,0 +1,255 @@
152 +#include <linux/init.h>
153 +#include <linux/sched.h>
154 +#include <linux/slab.h>
155 +#include <linux/interrupt.h>
156 +#include <linux/kernel_stat.h>
157 +#include <linux/hardirq.h>
158 +#include <linux/preempt.h>
159 +#include <linux/irqdomain.h>
160 +#include <linux/of_platform.h>
161 +#include <linux/of_address.h>
162 +#include <linux/of_irq.h>
163 +
164 +#include <asm/irq_cpu.h>
165 +#include <asm/mipsregs.h>
166 +
167 +#include <asm/irq.h>
168 +#include <asm/setup.h>
169 +
170 +#include <asm/gic.h>
171 +#include <asm/gcmpregs.h>
172 +
173 +#include <asm/mach-ralink/mt7621.h>
174 +
175 +static unsigned long _gcmp_base;
176 +static int gic_resched_int_base = 56;
177 +static int gic_call_int_base = 60;
178 +static struct irq_chip *irq_gic;
179 +
180 +#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
181 +#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
182 +
183 +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
184 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //0
185 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
186 + { GIC_UNUSED },
187 + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //FE
188 + { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //PCIE0
189 + { GIC_UNUSED},
190 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
191 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
192 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
193 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //10
194 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
195 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
196 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
197 + { GIC_UNUSED },
198 + { GIC_UNUSED },
199 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
200 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
201 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
202 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
203 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //20
204 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
205 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
206 + { GIC_UNUSED },
207 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
208 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //25
209 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
210 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
211 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
212 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
213 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },//30
214 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
215 +};
216 +
217 +static struct gic_intr_map ipi_intr_map[8] = {
218 + { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
219 + { 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
220 + { 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
221 + { 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
222 + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
223 + { 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
224 + { 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
225 + { 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
226 +};
227 +
228 +static irqreturn_t
229 +ipi_resched_interrupt(int irq, void *dev_id)
230 +{
231 + scheduler_ipi();
232 +
233 + return IRQ_HANDLED;
234 +}
235 +
236 +static irqreturn_t
237 +ipi_call_interrupt(int irq, void *dev_id)
238 +{
239 + smp_call_function_interrupt();
240 +
241 + return IRQ_HANDLED;
242 +}
243 +
244 +static struct irqaction irq_resched = {
245 + .handler = ipi_resched_interrupt,
246 + .flags = IRQF_DISABLED|IRQF_PERCPU,
247 + .name = "ipi resched"
248 +};
249 +
250 +static struct irqaction irq_call = {
251 + .handler = ipi_call_interrupt,
252 + .flags = IRQF_DISABLED|IRQF_PERCPU,
253 + .name = "ipi call"
254 +};
255 +
256 +void
257 +gic_irq_ack(struct irq_data *d)
258 +{
259 + int irq = (d->irq - gic_irq_base);
260 +
261 + GIC_CLR_INTR_MASK(irq);
262 +
263 + if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
264 + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
265 +}
266 +
267 +void
268 +gic_finish_irq(struct irq_data *d)
269 +{
270 + GIC_SET_INTR_MASK(d->irq - gic_irq_base);
271 +}
272 +
273 +void __init
274 +gic_platform_init(int irqs, struct irq_chip *irq_controller)
275 +{
276 + irq_gic = irq_controller;
277 +}
278 +
279 +static void
280 +vi_gic_irqdispatch(void)
281 +{
282 + int irq = gic_get_int();
283 +
284 + if (irq >= 0)
285 + do_IRQ(MIPS_GIC_IRQ_BASE + irq);
286 +}
287 +
288 +static void
289 +vi_timer_irqdispatch(void)
290 +{
291 + do_IRQ(cp0_compare_irq);
292 +}
293 +
294 +unsigned int
295 +plat_ipi_call_int_xlate(unsigned int cpu)
296 +{
297 + return GIC_CALL_INT(cpu);
298 +}
299 +
300 +unsigned int
301 +plat_ipi_resched_int_xlate(unsigned int cpu)
302 +{
303 + return GIC_RESCHED_INT(cpu);
304 +}
305 +
306 +asmlinkage void
307 +plat_irq_dispatch(void)
308 +{
309 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
310 +
311 + if (pending & CAUSEF_IP7)
312 + do_IRQ(cp0_compare_irq);
313 + else if (pending & (CAUSEF_IP4 | CAUSEF_IP3))
314 + vi_gic_irqdispatch();
315 + else
316 + spurious_interrupt();
317 +}
318 +
319 +unsigned int __cpuinit
320 +get_c0_compare_int(void)
321 +{
322 + return CP0_LEGACY_COMPARE_IRQ;
323 +}
324 +
325 +static int
326 +gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
327 +{
328 + irq_set_chip_and_handler(irq, irq_gic, handle_percpu_irq);
329 +
330 + return 0;
331 +}
332 +
333 +static const struct irq_domain_ops irq_domain_ops = {
334 + .xlate = irq_domain_xlate_onecell,
335 + .map = gic_map,
336 +};
337 +
338 +static int __init
339 +of_gic_init(struct device_node *node,
340 + struct device_node *parent)
341 +{
342 + struct irq_domain *domain;
343 + struct resource gcmp = { 0 }, gic = { 0 };
344 + unsigned int gic_rev;
345 + int i;
346 +
347 + if (of_address_to_resource(node, 0, &gic))
348 + panic("Failed to get gic memory range");
349 + if (request_mem_region(gic.start, resource_size(&gic),
350 + gic.name) < 0)
351 + panic("Failed to request gic memory");
352 + if (of_address_to_resource(node, 2, &gcmp))
353 + panic("Failed to get gic memory range");
354 + if (request_mem_region(gcmp.start, resource_size(&gcmp),
355 + gcmp.name) < 0)
356 + panic("Failed to request gcmp memory");
357 +
358 + _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
359 + if (!_gcmp_base)
360 + panic("Failed to remap gcmp memory\n");
361 +
362 + if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
363 + panic("Failed to find gcmp core\n");
364 +
365 + /* tell the gcmp where to find the gic */
366 + GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
367 + gic_present = 1;
368 + if (cpu_has_vint) {
369 + set_vi_handler(3, vi_gic_irqdispatch);
370 + set_vi_handler(4, vi_gic_irqdispatch);
371 + set_vi_handler(7, vi_timer_irqdispatch);
372 + }
373 +
374 + memcpy(&gic_intr_map[gic_resched_int_base], ipi_intr_map, sizeof(ipi_intr_map));
375 + gic_init(gic.start, resource_size(&gic), gic_intr_map,
376 + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
377 +
378 + GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
379 + pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
380 +
381 + domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
382 + 0, &irq_domain_ops, NULL);
383 + if (!domain)
384 + panic("Failed to add irqdomain");
385 +
386 + for (i = 0; i < NR_CPUS; i++) {
387 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
388 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
389 + }
390 +
391 + change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
392 + STATUSF_IP7);
393 + return 0;
394 +}
395 +
396 +static struct of_device_id __initdata of_irq_ids[] = {
397 + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
398 + { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
399 + {},
400 +};
401 +
402 +void __init
403 +arch_init_irq(void)
404 +{
405 + of_irq_init(of_irq_ids);
406 +}
407 Index: linux-3.10.21/arch/mips/ralink/malta-amon.c
408 ===================================================================
409 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
410 +++ linux-3.10.21/arch/mips/ralink/malta-amon.c 2013-12-09 19:52:51.756677296 +0100
411 @@ -0,0 +1,81 @@
412 +/*
413 + * Copyright (C) 2007 MIPS Technologies, Inc.
414 + * All rights reserved.
415 +
416 + * This program is free software; you can distribute it and/or modify it
417 + * under the terms of the GNU General Public License (Version 2) as
418 + * published by the Free Software Foundation.
419 + *
420 + * This program is distributed in the hope it will be useful, but WITHOUT
421 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
422 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
423 + * for more details.
424 + *
425 + * You should have received a copy of the GNU General Public License along
426 + * with this program; if not, write to the Free Software Foundation, Inc.,
427 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
428 + *
429 + * Arbitrary Monitor interface
430 + */
431 +
432 +#include <linux/kernel.h>
433 +#include <linux/init.h>
434 +#include <linux/smp.h>
435 +
436 +#include <asm/addrspace.h>
437 +#include <asm/mips-boards/launch.h>
438 +#include <asm/mipsmtregs.h>
439 +
440 +int amon_cpu_avail(int cpu)
441 +{
442 + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
443 +
444 + if (cpu < 0 || cpu >= NCPULAUNCH) {
445 + pr_debug("avail: cpu%d is out of range\n", cpu);
446 + return 0;
447 + }
448 +
449 + launch += cpu;
450 + if (!(launch->flags & LAUNCH_FREADY)) {
451 + pr_debug("avail: cpu%d is not ready\n", cpu);
452 + return 0;
453 + }
454 + if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
455 + pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
456 + return 0;
457 + }
458 +
459 + return 1;
460 +}
461 +
462 +void amon_cpu_start(int cpu,
463 + unsigned long pc, unsigned long sp,
464 + unsigned long gp, unsigned long a0)
465 +{
466 + volatile struct cpulaunch *launch =
467 + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
468 +
469 + if (!amon_cpu_avail(cpu))
470 + return;
471 + if (cpu == smp_processor_id()) {
472 + pr_debug("launch: I am cpu%d!\n", cpu);
473 + return;
474 + }
475 + launch += cpu;
476 +
477 + pr_debug("launch: starting cpu%d\n", cpu);
478 +
479 + launch->pc = pc;
480 + launch->gp = gp;
481 + launch->sp = sp;
482 + launch->a0 = a0;
483 +
484 + smp_wmb(); /* Target must see parameters before go */
485 + launch->flags |= LAUNCH_FGO;
486 + smp_wmb(); /* Target must see go before we poll */
487 +
488 + while ((launch->flags & LAUNCH_FGONE) == 0)
489 + ;
490 + smp_rmb(); /* Target will be updating flags soon */
491 + pr_debug("launch: cpu%d gone!\n", cpu);
492 +}
493 Index: linux-3.10.21/arch/mips/ralink/mt7621.c
494 ===================================================================
495 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
496 +++ linux-3.10.21/arch/mips/ralink/mt7621.c 2013-12-09 19:52:51.760677296 +0100
497 @@ -0,0 +1,186 @@
498 +/*
499 + * This program is free software; you can redistribute it and/or modify it
500 + * under the terms of the GNU General Public License version 2 as published
501 + * by the Free Software Foundation.
502 + *
503 + * Parts of this file are based on Ralink's 2.6.21 BSP
504 + *
505 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
506 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
507 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
508 + */
509 +
510 +#include <linux/kernel.h>
511 +#include <linux/init.h>
512 +#include <linux/module.h>
513 +#include <asm/gcmpregs.h>
514 +
515 +#include <asm/mipsregs.h>
516 +#include <asm/mach-ralink/ralink_regs.h>
517 +#include <asm/mach-ralink/mt7621.h>
518 +
519 +#include <pinmux.h>
520 +
521 +#include "common.h"
522 +
523 +#define SYSC_REG_SYSCFG 0x10
524 +#define SYSC_REG_CPLL_CLKCFG0 0x2c
525 +#define SYSC_REG_CUR_CLK_STS 0x44
526 +#define CPU_CLK_SEL (BIT(30) | BIT(31))
527 +
528 +#define MT7621_GPIO_MODE_UART1 1
529 +#define MT7621_GPIO_MODE_I2C 2
530 +#define MT7621_GPIO_MODE_UART2 3
531 +#define MT7621_GPIO_MODE_UART3 5
532 +#define MT7621_GPIO_MODE_JTAG 7
533 +#define MT7621_GPIO_MODE_WDT_MASK 0x3
534 +#define MT7621_GPIO_MODE_WDT_SHIFT 8
535 +#define MT7621_GPIO_MODE_WDT_GPIO 1
536 +#define MT7621_GPIO_MODE_PCIE_RST 0
537 +#define MT7621_GPIO_MODE_PCIE_REF 2
538 +#define MT7621_GPIO_MODE_PCIE_MASK 0x3
539 +#define MT7621_GPIO_MODE_PCIE_SHIFT 10
540 +#define MT7621_GPIO_MODE_PCIE_GPIO 1
541 +#define MT7621_GPIO_MODE_MDIO 12
542 +#define MT7621_GPIO_MODE_RGMII1 14
543 +#define MT7621_GPIO_MODE_RGMII2 15
544 +#define MT7621_GPIO_MODE_SPI_MASK 0x3
545 +#define MT7621_GPIO_MODE_SPI_SHIFT 16
546 +#define MT7621_GPIO_MODE_SPI_GPIO 1
547 +#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
548 +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
549 +#define MT7621_GPIO_MODE_SDHCI_GPIO 1
550 +
551 +static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
552 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
553 +static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart3", 0, 5, 4) };
554 +static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart2", 0, 9, 4) };
555 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
556 +static struct rt2880_pmx_func wdt_grp[] = {
557 + FUNC("wdt rst", 0, 18, 1),
558 + FUNC("wdt refclk", 2, 18, 1),
559 +};
560 +static struct rt2880_pmx_func pcie_rst_grp[] = {
561 + FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
562 + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
563 +};
564 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
565 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
566 +static struct rt2880_pmx_func spi_grp[] = {
567 + FUNC("spi", 0, 34, 7),
568 + FUNC("nand", 2, 34, 8),
569 +};
570 +static struct rt2880_pmx_func sdhci_grp[] = {
571 + FUNC("sdhci", 0, 41, 8),
572 + FUNC("nand", 2, 41, 8),
573 +};
574 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
575 +
576 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
577 + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
578 + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
579 + GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
580 + GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
581 + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
582 + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
583 + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
584 + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
585 + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
586 + GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
587 + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
588 + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
589 + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
590 + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
591 + MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
592 + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
593 + { 0 }
594 +};
595 +
596 +void __init ralink_clk_init(void)
597 +{
598 + int cpu_fdiv = 0;
599 + int cpu_ffrac = 0;
600 + int fbdiv = 0;
601 + u32 clk_sts, syscfg;
602 + u8 clk_sel = 0, xtal_mode;
603 + u32 cpu_clk;
604 +
605 + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
606 + clk_sel = 1;
607 +
608 + switch (clk_sel) {
609 + case 0:
610 + clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
611 + cpu_fdiv = ((clk_sts >> 8) & 0x1F);
612 + cpu_ffrac = (clk_sts & 0x1F);
613 + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
614 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
615 + break;
616 +
617 + case 1:
618 + fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
619 + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
620 + xtal_mode = (syscfg >> 6) & 0x7;
621 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
622 + if(xtal_mode >= 6) { //25Mhz Xtal
623 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
624 + cpu_clk = 25 * fbdiv * 1000 * 1000;
625 + } else if(xtal_mode >=3) { //40Mhz Xtal
626 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
627 + cpu_clk = 40 * fbdiv * 1000 * 1000;
628 + } else { // 20Mhz Xtal
629 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
630 + cpu_clk = 20 * fbdiv * 1000 * 1000;
631 + }
632 + break;
633 + }
634 + cpu_clk = 880000000;
635 + ralink_clk_add("cpu", cpu_clk);
636 + ralink_clk_add("1e000b00.spi", 50000000);
637 + ralink_clk_add("1e000c00.uartlite", 50000000);
638 +}
639 +
640 +void __init ralink_of_remap(void)
641 +{
642 + rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
643 + rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
644 +
645 + if (!rt_sysc_membase || !rt_memc_membase)
646 + panic("Failed to remap core resources");
647 +}
648 +
649 +void prom_soc_init(struct ralink_soc_info *soc_info)
650 +{
651 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
652 + unsigned char *name = NULL;
653 + u32 n0;
654 + u32 n1;
655 + u32 rev;
656 +
657 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
658 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
659 +
660 + if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
661 + name = "MT7621";
662 + soc_info->compatible = "mtk,mt7621-soc";
663 + } else {
664 + panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
665 + }
666 +
667 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
668 +
669 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
670 + "Mediatek %s ver:%u eco:%u",
671 + name,
672 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
673 + (rev & CHIP_REV_ECO_MASK));
674 +
675 + soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
676 + soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
677 + soc_info->mem_base = MT7621_DRAM_BASE;
678 +
679 + rt2880_pinmux_data = mt7621_pinmux_data;
680 +
681 + if (register_cmp_smp_ops())
682 + panic("failed to register_vsmp_smp_ops()");
683 +}
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