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Merge xburst target.
[openwrt/staging/florian.git] / target / linux / xburst / files-2.6.32 / arch / mips / jz4740 / gpio.c
1 /*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform GPIO support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19
20 #include <linux/spinlock.h>
21 #include <linux/sysdev.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27
28 #define JZ_GPIO_BASE_A (32*0)
29 #define JZ_GPIO_BASE_B (32*1)
30 #define JZ_GPIO_BASE_C (32*2)
31 #define JZ_GPIO_BASE_D (32*3)
32
33 #define JZ_GPIO_NUM_A 32
34 #define JZ_GPIO_NUM_B 32
35 #define JZ_GPIO_NUM_C 31
36 #define JZ_GPIO_NUM_D 32
37
38 #define JZ_IRQ_GPIO_BASE_A (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_A)
39 #define JZ_IRQ_GPIO_BASE_B (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_B)
40 #define JZ_IRQ_GPIO_BASE_C (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_C)
41 #define JZ_IRQ_GPIO_BASE_D (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_D)
42
43 #define JZ_IRQ_GPIO_A(num) (JZ_IRQ_GPIO_BASE_A + num)
44 #define JZ_IRQ_GPIO_B(num) (JZ_IRQ_GPIO_BASE_B + num)
45 #define JZ_IRQ_GPIO_C(num) (JZ_IRQ_GPIO_BASE_C + num)
46 #define JZ_IRQ_GPIO_D(num) (JZ_IRQ_GPIO_BASE_D + num)
47
48 #define JZ_REG_GPIO_PIN 0x00
49 #define JZ_REG_GPIO_DATA 0x10
50 #define JZ_REG_GPIO_DATA_SET 0x14
51 #define JZ_REG_GPIO_DATA_CLEAR 0x18
52 #define JZ_REG_GPIO_MASK 0x20
53 #define JZ_REG_GPIO_MASK_SET 0x24
54 #define JZ_REG_GPIO_MASK_CLEAR 0x28
55 #define JZ_REG_GPIO_PULL 0x30
56 #define JZ_REG_GPIO_PULL_SET 0x34
57 #define JZ_REG_GPIO_PULL_CLEAR 0x38
58 #define JZ_REG_GPIO_FUNC 0x40
59 #define JZ_REG_GPIO_FUNC_SET 0x44
60 #define JZ_REG_GPIO_FUNC_CLEAR 0x48
61 #define JZ_REG_GPIO_SELECT 0x50
62 #define JZ_REG_GPIO_SELECT_SET 0x54
63 #define JZ_REG_GPIO_SELECT_CLEAR 0x58
64 #define JZ_REG_GPIO_DIRECTION 0x60
65 #define JZ_REG_GPIO_DIRECTION_SET 0x64
66 #define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
67 #define JZ_REG_GPIO_TRIGGER 0x70
68 #define JZ_REG_GPIO_TRIGGER_SET 0x74
69 #define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
70 #define JZ_REG_GPIO_FLAG 0x80
71 #define JZ_REG_GPIO_FLAG_CLEAR 0x14
72
73 #define CHIP_TO_REG(chip, reg) (jz_gpio_base + (((chip)->base) << 3) + reg)
74
75 #define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
76 #define GPIO_TO_REG(gpio, reg) (jz_gpio_base + ((gpio >> 5) << 8) + reg)
77
78 static void __iomem *jz_gpio_base;
79
80 struct jz_gpio_chip {
81 unsigned int irq;
82 unsigned int irq_base;
83 uint32_t wakeup;
84 uint32_t suspend_mask;
85 uint32_t edge_trigger_both;
86 spinlock_t lock;
87 struct gpio_chip gpio_chip;
88 struct irq_chip irq_chip;
89 };
90
91 static struct jz_gpio_chip *jz_irq_to_chip(unsigned int irq)
92 {
93 return get_irq_chip_data(irq);
94 }
95
96 static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
97 {
98 writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
99 }
100
101 int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
102 {
103 if (function == JZ_GPIO_FUNC_NONE) {
104 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
105 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
106 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
107 } else {
108 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
109 switch (function) {
110 case JZ_GPIO_FUNC1:
111 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
112 break;
113 case JZ_GPIO_FUNC3:
114 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
115 case JZ_GPIO_FUNC2: /* Falltrough */
116 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
117 break;
118 default:
119 BUG();
120 break;
121 }
122 }
123
124 return 0;
125 }
126 EXPORT_SYMBOL_GPL(jz_gpio_set_function);
127
128 int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
129 {
130 size_t i;
131 int ret;
132
133 for (i = 0; i < num; ++i, ++request) {
134 ret = gpio_request(request->gpio, request->name);
135 if (ret)
136 goto err;
137 jz_gpio_set_function(request->gpio, request->function);
138 }
139
140 return 0;
141 err:
142 for (--request; i > 0; --i, --request)
143 gpio_free(request->gpio);
144
145 return ret;
146 }
147 EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
148
149 void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
150 {
151 size_t i;
152
153 for (i = 0; i < num; ++i, ++request) {
154 gpio_free(request->gpio);
155 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
156 }
157
158 }
159 EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
160
161 void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
162 {
163 size_t i;
164
165 for (i = 0; i < num; ++i, ++request) {
166 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
167 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_SET);
168 }
169 }
170 EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
171
172 void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
173 {
174 size_t i;
175
176 for (i = 0; i < num; ++i, ++request) {
177 jz_gpio_set_function(request->gpio, request->function);
178 }
179 }
180 EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
181
182 void jz_gpio_enable_pullup(unsigned gpio)
183 {
184 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
185 }
186 EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
187
188 void jz_gpio_disable_pullup(unsigned gpio)
189 {
190 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
191 }
192 EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
193
194 static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
195 {
196 return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
197 }
198
199 static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
200 {
201 uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
202 reg += !value;
203 writel(BIT(gpio), reg);
204 }
205
206 static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
207 {
208 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
209 jz_gpio_set_value(chip, gpio, value);
210
211 return 0;
212 }
213
214 static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
215 {
216 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
217
218 return 0;
219 }
220
221 int jz_gpio_port_direction_input(int port, uint32_t mask)
222 {
223 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
224
225 return 0;
226 }
227 EXPORT_SYMBOL(jz_gpio_port_direction_input);
228
229 int jz_gpio_port_direction_output(int port, uint32_t mask)
230 {
231 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
232
233 return 0;
234 }
235 EXPORT_SYMBOL(jz_gpio_port_direction_output);
236
237 void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
238 {
239 writel((~value) & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
240 writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
241 }
242 EXPORT_SYMBOL(jz_gpio_port_set_value);
243
244 uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
245 {
246 uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
247
248 return value & mask;
249 }
250 EXPORT_SYMBOL(jz_gpio_port_get_value);
251
252
253 #define IRQ_TO_GPIO(irq) (irq - JZ_IRQ_GPIO(0))
254 #define IRQ_TO_BIT(irq) BIT(IRQ_TO_GPIO(irq) & 0x1f)
255
256 #define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg)
257
258 static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
259 {
260 uint32_t flag;
261 unsigned int gpio_irq;
262 unsigned int gpio_bank;
263 struct jz_gpio_chip *chip = get_irq_desc_data(desc);
264
265 gpio_bank = JZ_IRQ_GPIO0 - irq;
266
267 flag = readl(jz_gpio_base + (gpio_bank << 8) + JZ_REG_GPIO_FLAG);
268
269 gpio_irq = ffs(flag) - 1;
270
271 if (chip->edge_trigger_both & BIT(gpio_irq)) {
272 uint32_t value = readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PIN));
273 if (value & BIT(gpio_irq)) {
274 writel(BIT(gpio_irq),
275 CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION_CLEAR));
276 } else {
277 writel(BIT(gpio_irq),
278 CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION_SET));
279 }
280 }
281
282 gpio_irq += (gpio_bank << 5) + JZ_IRQ_GPIO(0);
283
284 generic_handle_irq(gpio_irq);
285 };
286
287 static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
288 {
289 writel(IRQ_TO_BIT(irq), IRQ_TO_REG(irq, reg));
290 }
291
292 static void jz_gpio_irq_mask(unsigned int irq)
293 {
294 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
295 };
296
297 static void jz_gpio_irq_unmask(unsigned int irq)
298 {
299 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
300 };
301
302 /* TODO: Check if function is gpio */
303 static unsigned int jz_gpio_irq_startup(unsigned int irq)
304 {
305 struct irq_desc *desc = irq_to_desc(irq);
306
307 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
308
309 jz_gpio_irq_unmask(irq);
310 desc->status &= ~IRQ_MASKED;
311
312 return 0;
313 }
314
315 static void jz_gpio_irq_shutdown(unsigned int irq)
316 {
317 struct irq_desc *desc = irq_to_desc(irq);
318
319 jz_gpio_irq_mask(irq);
320 desc->status |= IRQ_MASKED;
321
322 /* Set direction to input */
323 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
324 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
325 }
326
327 static void jz_gpio_irq_ack(unsigned int irq)
328 {
329 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
330 };
331
332 static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
333 {
334 struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
335 struct irq_desc *desc = irq_to_desc(irq);
336
337 jz_gpio_irq_mask(irq);
338
339 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
340 uint32_t value = readl(IRQ_TO_REG(irq, JZ_REG_GPIO_PIN));
341 if (value & IRQ_TO_BIT(irq))
342 flow_type = IRQ_TYPE_EDGE_FALLING;
343 else
344 flow_type = IRQ_TYPE_EDGE_RISING;
345 chip->edge_trigger_both |= IRQ_TO_BIT(irq);
346 } else {
347 chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
348 }
349
350 switch(flow_type) {
351 case IRQ_TYPE_EDGE_RISING:
352 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
353 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
354 break;
355 case IRQ_TYPE_EDGE_FALLING:
356 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
357 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
358 break;
359 case IRQ_TYPE_LEVEL_HIGH:
360 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
361 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
362 break;
363 case IRQ_TYPE_LEVEL_LOW:
364 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
365 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
366 break;
367 default:
368 return -EINVAL;
369 }
370
371 if (!(desc->status & IRQ_MASKED))
372 jz_gpio_irq_unmask(irq);
373
374 return 0;
375 }
376
377 static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
378 {
379 struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
380 spin_lock(&chip->lock);
381 if (on)
382 chip->wakeup |= IRQ_TO_BIT(irq);
383 else
384 chip->wakeup &= ~IRQ_TO_BIT(irq);
385 spin_unlock(&chip->lock);
386
387 set_irq_wake(chip->irq, !!(chip->wakeup));
388 return 0;
389 }
390
391 int gpio_to_irq(unsigned gpio)
392 {
393 return JZ_IRQ_GPIO(0) + gpio;
394 }
395 EXPORT_SYMBOL_GPL(gpio_to_irq);
396
397 int irq_to_gpio(unsigned gpio)
398 {
399 return IRQ_TO_GPIO(gpio);
400 }
401 EXPORT_SYMBOL_GPL(irq_to_gpio);
402
403 #define JZ_GPIO_CHIP(_bank) { \
404 .irq_base = JZ_IRQ_GPIO_BASE_ ## _bank, \
405 .gpio_chip = { \
406 .label = "Bank " # _bank, \
407 .owner = THIS_MODULE, \
408 .set = jz_gpio_set_value, \
409 .get = jz_gpio_get_value, \
410 .direction_output = jz_gpio_direction_output, \
411 .direction_input = jz_gpio_direction_input, \
412 .base = JZ_GPIO_BASE_ ## _bank, \
413 .ngpio = JZ_GPIO_NUM_ ## _bank, \
414 }, \
415 .irq_chip = { \
416 .name = "GPIO Bank " # _bank, \
417 .mask = jz_gpio_irq_mask, \
418 .unmask = jz_gpio_irq_unmask, \
419 .ack = jz_gpio_irq_ack, \
420 .startup = jz_gpio_irq_startup, \
421 .shutdown = jz_gpio_irq_shutdown, \
422 .set_type = jz_gpio_irq_set_type, \
423 .set_wake = jz_gpio_irq_set_wake, \
424 }, \
425 }
426
427 static struct jz_gpio_chip jz_gpio_chips[] = {
428 JZ_GPIO_CHIP(A),
429 JZ_GPIO_CHIP(B),
430 JZ_GPIO_CHIP(C),
431 JZ_GPIO_CHIP(D),
432 };
433
434 static int jz_gpio_suspend(struct sys_device *dev, pm_message_t state)
435 {
436 struct jz_gpio_chip *chip = jz_gpio_chips;
437 int i, gpio;
438 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
439 gpio = chip->gpio_chip.base;
440 chip->suspend_mask = readl(GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK));
441 writel(~(chip->wakeup), GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK_SET));
442 }
443
444 return 0;
445 }
446
447 static int jz_gpio_resume(struct sys_device *dev)
448 {
449 struct jz_gpio_chip *chip = jz_gpio_chips;
450 int i;
451 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
452 writel(~(chip->suspend_mask), GPIO_TO_REG(chip->gpio_chip.base, JZ_REG_GPIO_MASK_CLEAR));
453 }
454
455 return 0;
456 }
457
458 static struct sysdev_class jz_gpio_sysdev = {
459 .name = "JZ4740 GPIO",
460 .suspend = jz_gpio_suspend,
461 .resume = jz_gpio_resume,
462 };
463
464 int __init jz_gpiolib_init(void)
465 {
466 struct jz_gpio_chip *chip = jz_gpio_chips;
467 int i, irq;
468
469 jz_gpio_base = ioremap(0x10010000, 0x400);
470
471 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
472 gpiochip_add(&chip->gpio_chip);
473 spin_lock_init(&chip->lock);
474 chip->irq = JZ_IRQ_INTC_GPIO(i);
475 set_irq_data(chip->irq, chip);
476 set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
477 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
478 set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
479 set_irq_chip_data(irq, chip);
480 }
481 }
482
483 sysdev_class_register(&jz_gpio_sysdev);
484
485 printk("JZ GPIO initalized\n");
486
487 return 0;
488 }
489
490
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