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Merge xburst target.
[openwrt/staging/florian.git] / target / linux / xburst / patches-2.6.32 / 001-core.patch
1 From 42789dfb077bb7b640ee19d0e3f7808dc5318adf Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Mon, 11 Jan 2010 04:29:35 +0100
4 Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-core.patch
5
6 ---
7 arch/mips/Kconfig | 29 ++++
8 arch/mips/Makefile | 18 +++
9 arch/mips/boot/Makefile | 23 +++-
10 arch/mips/include/asm/bootinfo.h | 6 +
11 arch/mips/include/asm/cpu.h | 13 ++-
12 arch/mips/include/asm/mach-generic/irq.h | 2 +-
13 arch/mips/include/asm/r4kcache.h | 231 ++++++++++++++++++++++++++++++
14 arch/mips/include/asm/suspend.h | 3 +
15 arch/mips/kernel/cpu-probe.c | 21 +++
16 arch/mips/mm/c-r4k.c | 30 ++++
17 arch/mips/mm/cache.c | 2 +
18 arch/mips/mm/tlbex.c | 5 +
19 12 files changed, 379 insertions(+), 4 deletions(-)
20
21 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
22 index fd7620f..9b40aa8 100644
23 --- a/arch/mips/Kconfig
24 +++ b/arch/mips/Kconfig
25 @@ -174,6 +174,9 @@ config MACH_JAZZ
26 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
27 Olivetti M700-10 workstations.
28
29 +config MACH_JZ
30 + bool "Ingenic JZ4720/JZ4740 based machines"
31 +
32 config LASAT
33 bool "LASAT Networks platforms"
34 select CEVT_R4K
35 @@ -677,6 +680,7 @@ source "arch/mips/alchemy/Kconfig"
36 source "arch/mips/basler/excite/Kconfig"
37 source "arch/mips/bcm63xx/Kconfig"
38 source "arch/mips/jazz/Kconfig"
39 +source "arch/mips/jz4740/Kconfig"
40 source "arch/mips/lasat/Kconfig"
41 source "arch/mips/pmc-sierra/Kconfig"
42 source "arch/mips/sgi-ip27/Kconfig"
43 @@ -1895,6 +1899,14 @@ config NR_CPUS
44
45 source "kernel/time/Kconfig"
46
47 +# the value of (max order + 1)
48 +config FORCE_MAX_ZONEORDER
49 + prompt "MAX_ZONEORDER"
50 + int
51 + default "12"
52 + help
53 + The max memory that can be allocated = 4KB * 2^(CONFIG_FORCE_MAX_ZONEORDER - 1)
54 +
55 #
56 # Timer Interrupt Frequency Configuration
57 #
58 diff --git a/arch/mips/Makefile b/arch/mips/Makefile
59 index 77f5021..1b22297 100644
60 --- a/arch/mips/Makefile
61 +++ b/arch/mips/Makefile
62 @@ -184,6 +184,14 @@ cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
63 load-$(CONFIG_AR7) += 0xffffffff94100000
64
65 #
66 +# Commond Ingenic JZ4740 series
67 +#
68 +
69 +core-$(CONFIG_SOC_JZ4740) += arch/mips/jz4740/
70 +cflags-$(CONFIG_SOC_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740
71 +load-$(CONFIG_SOC_JZ4740) += 0xffffffff80010000
72 +
73 +#
74 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
75 #
76 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
77 @@ -702,6 +710,12 @@ makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
78
79 all: $(all-y)
80
81 +uImage: $(vmlinux-32)
82 + +@$(call makeboot,$@)
83 +
84 +zImage: $(vmlinux-32)
85 + +@$(call makeboot,$@)
86 +
87 vmlinux.bin: $(vmlinux-32)
88 +@$(call makeboot,$@)
89
90 @@ -731,6 +745,7 @@ install:
91
92 archclean:
93 @$(MAKE) $(clean)=arch/mips/boot
94 + @$(MAKE) $(clean)=arch/mips/boot/compressed
95 @$(MAKE) $(clean)=arch/mips/lasat
96
97 define archhelp
98 @@ -738,6 +753,9 @@ define archhelp
99 echo ' vmlinux.ecoff - ECOFF boot image'
100 echo ' vmlinux.bin - Raw binary boot image'
101 echo ' vmlinux.srec - SREC boot image'
102 + echo ' uImage - u-boot format image (arch/$(ARCH)/boot/uImage)'
103 + echo ' zImage - Compressed binary image (arch/$(ARCH)/boot/compressed/zImage)'
104 + echo ' vmlinux.bin - Uncompressed binary image (arch/$(ARCH)/boot/vmlinux.bin)'
105 echo
106 echo ' These will be default as apropriate for a configured platform.'
107 endef
108 diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
109 index 2a209d7..1cfce3e 100644
110 --- a/arch/mips/boot/Makefile
111 +++ b/arch/mips/boot/Makefile
112 @@ -7,6 +7,9 @@
113 # Copyright (C) 2004 Maciej W. Rozycki
114 #
115
116 +# This one must match the LOADADDR in arch/mips/Makefile!
117 +LOADADDR=0x80010000
118 +
119 #
120 # Some DECstations need all possible sections of an ECOFF executable
121 #
122 @@ -25,7 +28,7 @@ strip-flags = $(addprefix --remove-section=,$(drop-sections))
123
124 VMLINUX = vmlinux
125
126 -all: vmlinux.ecoff vmlinux.srec addinitrd
127 +all: vmlinux.ecoff vmlinux.srec addinitrd uImage zImage
128
129 vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
130 $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS)
131 @@ -42,8 +45,24 @@ vmlinux.srec: $(VMLINUX)
132 $(obj)/addinitrd: $(obj)/addinitrd.c
133 $(HOSTCC) -o $@ $^
134
135 +uImage: $(VMLINUX) vmlinux.bin
136 + rm -f $(obj)/vmlinux.bin.gz
137 + gzip -9 $(obj)/vmlinux.bin
138 + mkimage -A mips -O linux -T kernel -C gzip \
139 + -a $(LOADADDR) -e $(shell sh ./$(obj)/tools/entry $(NM) $(VMLINUX) ) \
140 + -n 'Linux-$(KERNELRELEASE)' \
141 + -d $(obj)/vmlinux.bin.gz $(obj)/uImage
142 + @echo ' Kernel: arch/mips/boot/$@ is ready'
143 +
144 +zImage:
145 + $(Q)$(MAKE) $(build)=$(obj)/compressed loadaddr=$(LOADADDR) $@
146 + @echo ' Kernel: arch/mips/boot/compressed/$@ is ready'
147 +
148 clean-files += addinitrd \
149 elf2ecoff \
150 vmlinux.bin \
151 vmlinux.ecoff \
152 - vmlinux.srec
153 + vmlinux.srec \
154 + vmlinux.bin.gz \
155 + uImage \
156 + zImage
157 diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
158 index f5dfaf6..584376f 100644
159 --- a/arch/mips/include/asm/bootinfo.h
160 +++ b/arch/mips/include/asm/bootinfo.h
161 @@ -69,6 +69,12 @@
162 #define MACH_DEXXON_GDIUM2F10 5
163 #define MACH_LOONGSON_END 6
164
165 +/*
166 + * Valid machtype for group INGENIC
167 + */
168 +#define MACH_INGENIC_JZ4720 0 /* JZ4730 SOC */
169 +#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
170 +
171 #define CL_SIZE COMMAND_LINE_SIZE
172
173 extern char *system_type;
174 diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
175 index 4b96d1a..478a527 100644
176 --- a/arch/mips/include/asm/cpu.h
177 +++ b/arch/mips/include/asm/cpu.h
178 @@ -34,7 +34,7 @@
179 #define PRID_COMP_LSI 0x080000
180 #define PRID_COMP_LEXRA 0x0b0000
181 #define PRID_COMP_CAVIUM 0x0d0000
182 -
183 +#define PRID_COMP_INGENIC 0xd00000
184
185 /*
186 * Assigned values for the product ID register. In order to detect a
187 @@ -133,6 +133,12 @@
188 #define PRID_IMP_CAVIUM_CN52XX 0x0700
189
190 /*
191 + * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
192 + */
193 +
194 +#define PRID_IMP_JZRISC 0x0200
195 +
196 +/*
197 * Definitions for 7:0 on legacy processors
198 */
199
200 @@ -224,6 +230,11 @@ enum cpu_type_enum {
201 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
202 CPU_CAVIUM_OCTEON,
203
204 + /*
205 + * Ingenic class processors
206 + */
207 + CPU_JZRISC, CPU_XBURST,
208 +
209 CPU_LAST
210 };
211
212 diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
213 index 70d9a25..73b7a83 100644
214 --- a/arch/mips/include/asm/mach-generic/irq.h
215 +++ b/arch/mips/include/asm/mach-generic/irq.h
216 @@ -9,7 +9,7 @@
217 #define __ASM_MACH_GENERIC_IRQ_H
218
219 #ifndef NR_IRQS
220 -#define NR_IRQS 128
221 +#define NR_IRQS 256
222 #endif
223
224 #ifdef CONFIG_I8259
225 diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
226 index 387bf59..b500056 100644
227 --- a/arch/mips/include/asm/r4kcache.h
228 +++ b/arch/mips/include/asm/r4kcache.h
229 @@ -17,6 +17,58 @@
230 #include <asm/cpu-features.h>
231 #include <asm/mipsmtregs.h>
232
233 +#ifdef CONFIG_JZRISC
234 +
235 +#define K0_TO_K1() \
236 +do { \
237 + unsigned long __k0_addr; \
238 + \
239 + __asm__ __volatile__( \
240 + "la %0, 1f\n\t" \
241 + "or %0, %0, %1\n\t" \
242 + "jr %0\n\t" \
243 + "nop\n\t" \
244 + "1: nop\n" \
245 + : "=&r"(__k0_addr) \
246 + : "r" (0x20000000) ); \
247 +} while(0)
248 +
249 +#define K1_TO_K0() \
250 +do { \
251 + unsigned long __k0_addr; \
252 + __asm__ __volatile__( \
253 + "nop;nop;nop;nop;nop;nop;nop\n\t" \
254 + "la %0, 1f\n\t" \
255 + "jr %0\n\t" \
256 + "nop\n\t" \
257 + "1: nop\n" \
258 + : "=&r" (__k0_addr)); \
259 +} while (0)
260 +
261 +#define INVALIDATE_BTB() \
262 +do { \
263 + unsigned long tmp; \
264 + __asm__ __volatile__( \
265 + ".set mips32\n\t" \
266 + "mfc0 %0, $16, 7\n\t" \
267 + "nop\n\t" \
268 + "ori %0, 2\n\t" \
269 + "mtc0 %0, $16, 7\n\t" \
270 + "nop\n\t" \
271 + : "=&r" (tmp)); \
272 +} while (0)
273 +
274 +#define SYNC_WB() __asm__ __volatile__ ("sync")
275 +
276 +#else /* CONFIG_JZRISC */
277 +
278 +#define K0_TO_K1() do { } while (0)
279 +#define K1_TO_K0() do { } while (0)
280 +#define INVALIDATE_BTB() do { } while (0)
281 +#define SYNC_WB() do { } while (0)
282 +
283 +#endif /* CONFIG_JZRISC */
284 +
285 /*
286 * This macro return a properly sign-extended address suitable as base address
287 * for indexed cache operations. Two issues here:
288 @@ -144,6 +196,7 @@ static inline void flush_icache_line_indexed(unsigned long addr)
289 {
290 __iflush_prologue
291 cache_op(Index_Invalidate_I, addr);
292 + INVALIDATE_BTB();
293 __iflush_epilogue
294 }
295
296 @@ -151,6 +204,7 @@ static inline void flush_dcache_line_indexed(unsigned long addr)
297 {
298 __dflush_prologue
299 cache_op(Index_Writeback_Inv_D, addr);
300 + SYNC_WB();
301 __dflush_epilogue
302 }
303
304 @@ -163,6 +217,7 @@ static inline void flush_icache_line(unsigned long addr)
305 {
306 __iflush_prologue
307 cache_op(Hit_Invalidate_I, addr);
308 + INVALIDATE_BTB();
309 __iflush_epilogue
310 }
311
312 @@ -170,6 +225,7 @@ static inline void flush_dcache_line(unsigned long addr)
313 {
314 __dflush_prologue
315 cache_op(Hit_Writeback_Inv_D, addr);
316 + SYNC_WB();
317 __dflush_epilogue
318 }
319
320 @@ -177,6 +233,7 @@ static inline void invalidate_dcache_line(unsigned long addr)
321 {
322 __dflush_prologue
323 cache_op(Hit_Invalidate_D, addr);
324 + SYNC_WB();
325 __dflush_epilogue
326 }
327
328 @@ -209,6 +266,7 @@ static inline void flush_scache_line(unsigned long addr)
329 static inline void protected_flush_icache_line(unsigned long addr)
330 {
331 protected_cache_op(Hit_Invalidate_I, addr);
332 + INVALIDATE_BTB();
333 }
334
335 /*
336 @@ -220,6 +278,7 @@ static inline void protected_flush_icache_line(unsigned long addr)
337 static inline void protected_writeback_dcache_line(unsigned long addr)
338 {
339 protected_cache_op(Hit_Writeback_Inv_D, addr);
340 + SYNC_WB();
341 }
342
343 static inline void protected_writeback_scache_line(unsigned long addr)
344 @@ -396,8 +455,10 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page)
345 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
346 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
347 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
348 +#ifndef CONFIG_JZRISC
349 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
350 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
351 +#endif
352 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
353 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
354 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
355 @@ -405,12 +466,122 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
356 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
357
358 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
359 +#ifndef CONFIG_JZRISC
360 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
361 +#endif
362 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
363 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
364 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
365 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
366
367 +#ifdef CONFIG_JZRISC
368 +
369 +static inline void blast_dcache32(void)
370 +{
371 + unsigned long start = INDEX_BASE;
372 + unsigned long end = start + current_cpu_data.dcache.waysize;
373 + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
374 + unsigned long ws_end = current_cpu_data.dcache.ways <<
375 + current_cpu_data.dcache.waybit;
376 + unsigned long ws, addr;
377 +
378 + for (ws = 0; ws < ws_end; ws += ws_inc)
379 + for (addr = start; addr < end; addr += 0x400)
380 + cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
381 +
382 + SYNC_WB();
383 +}
384 +
385 +static inline void blast_dcache32_page(unsigned long page)
386 +{
387 + unsigned long start = page;
388 + unsigned long end = page + PAGE_SIZE;
389 +
390 + do {
391 + cache32_unroll32(start,Hit_Writeback_Inv_D);
392 + start += 0x400;
393 + } while (start < end);
394 +
395 + SYNC_WB();
396 +}
397 +
398 +static inline void blast_dcache32_page_indexed(unsigned long page)
399 +{
400 + unsigned long indexmask = current_cpu_data.dcache.waysize - 1;
401 + unsigned long start = INDEX_BASE + (page & indexmask);
402 + unsigned long end = start + PAGE_SIZE;
403 + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
404 + unsigned long ws_end = current_cpu_data.dcache.ways <<
405 + current_cpu_data.dcache.waybit;
406 + unsigned long ws, addr;
407 +
408 + for (ws = 0; ws < ws_end; ws += ws_inc)
409 + for (addr = start; addr < end; addr += 0x400)
410 + cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
411 +
412 + SYNC_WB();
413 +}
414 +
415 +static inline void blast_icache32(void)
416 +{
417 + unsigned long start = INDEX_BASE;
418 + unsigned long end = start + current_cpu_data.icache.waysize;
419 + unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
420 + unsigned long ws_end = current_cpu_data.icache.ways <<
421 + current_cpu_data.icache.waybit;
422 + unsigned long ws, addr;
423 +
424 + K0_TO_K1();
425 +
426 + for (ws = 0; ws < ws_end; ws += ws_inc)
427 + for (addr = start; addr < end; addr += 0x400)
428 + cache32_unroll32(addr|ws,Index_Invalidate_I);
429 +
430 + INVALIDATE_BTB();
431 +
432 + K1_TO_K0();
433 +}
434 +
435 +static inline void blast_icache32_page(unsigned long page)
436 +{
437 + unsigned long start = page;
438 + unsigned long end = page + PAGE_SIZE;
439 +
440 + K0_TO_K1();
441 +
442 + do {
443 + cache32_unroll32(start,Hit_Invalidate_I);
444 + start += 0x400;
445 + } while (start < end);
446 +
447 + INVALIDATE_BTB();
448 +
449 + K1_TO_K0();
450 +}
451 +
452 +static inline void blast_icache32_page_indexed(unsigned long page)
453 +{
454 + unsigned long indexmask = current_cpu_data.icache.waysize - 1;
455 + unsigned long start = INDEX_BASE + (page & indexmask);
456 + unsigned long end = start + PAGE_SIZE;
457 + unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
458 + unsigned long ws_end = current_cpu_data.icache.ways <<
459 + current_cpu_data.icache.waybit;
460 + unsigned long ws, addr;
461 +
462 + K0_TO_K1();
463 +
464 + for (ws = 0; ws < ws_end; ws += ws_inc)
465 + for (addr = start; addr < end; addr += 0x400)
466 + cache32_unroll32(addr|ws,Index_Invalidate_I);
467 +
468 + INVALIDATE_BTB();
469 +
470 + K1_TO_K0();
471 +}
472 +
473 +#endif /* CONFIG_JZRISC */
474 +
475 /* build blast_xxx_range, protected_blast_xxx_range */
476 #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
477 static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
478 @@ -432,13 +603,73 @@ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
479 __##pfx##flush_epilogue \
480 }
481
482 +#ifndef CONFIG_JZRISC
483 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
484 +#endif
485 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
486 +#ifndef CONFIG_JZRISC
487 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
488 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
489 +#endif
490 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
491 /* blast_inv_dcache_range */
492 __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
493 __BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
494
495 +#ifdef CONFIG_JZRISC
496 +
497 +static inline void protected_blast_dcache_range(unsigned long start,
498 + unsigned long end)
499 +{
500 + unsigned long lsize = cpu_dcache_line_size();
501 + unsigned long addr = start & ~(lsize - 1);
502 + unsigned long aend = (end - 1) & ~(lsize - 1);
503 +
504 + while (1) {
505 + protected_cache_op(Hit_Writeback_Inv_D, addr);
506 + if (addr == aend)
507 + break;
508 + addr += lsize;
509 + }
510 + SYNC_WB();
511 +}
512 +
513 +static inline void protected_blast_icache_range(unsigned long start,
514 + unsigned long end)
515 +{
516 + unsigned long lsize = cpu_icache_line_size();
517 + unsigned long addr = start & ~(lsize - 1);
518 + unsigned long aend = (end - 1) & ~(lsize - 1);
519 +
520 + K0_TO_K1();
521 +
522 + while (1) {
523 + protected_cache_op(Hit_Invalidate_I, addr);
524 + if (addr == aend)
525 + break;
526 + addr += lsize;
527 + }
528 + INVALIDATE_BTB();
529 +
530 + K1_TO_K0();
531 +}
532 +
533 +static inline void blast_dcache_range(unsigned long start,
534 + unsigned long end)
535 +{
536 + unsigned long lsize = cpu_dcache_line_size();
537 + unsigned long addr = start & ~(lsize - 1);
538 + unsigned long aend = (end - 1) & ~(lsize - 1);
539 +
540 + while (1) {
541 + cache_op(Hit_Writeback_Inv_D, addr);
542 + if (addr == aend)
543 + break;
544 + addr += lsize;
545 + }
546 + SYNC_WB();
547 +}
548 +
549 +#endif /* CONFIG_JZRISC */
550 +
551 #endif /* _ASM_R4KCACHE_H */
552 diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h
553 index 294cdb6..94dc597 100644
554 --- a/arch/mips/include/asm/suspend.h
555 +++ b/arch/mips/include/asm/suspend.h
556 @@ -2,6 +2,9 @@
557 #define __ASM_SUSPEND_H
558
559 static inline int arch_prepare_suspend(void) { return 0; }
560 +#if defined(CONFIG_PM) && defined(CONFIG_JZSOC)
561 +extern int jz_pm_init(void);
562 +#endif
563
564 /* References to section boundaries */
565 extern const void __nosave_begin, __nosave_end;
566 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
567 index 7a51866..fd12b0c 100644
568 --- a/arch/mips/kernel/cpu-probe.c
569 +++ b/arch/mips/kernel/cpu-probe.c
570 @@ -160,6 +160,7 @@ void __init check_wait(void)
571 case CPU_BCM6348:
572 case CPU_BCM6358:
573 case CPU_CAVIUM_OCTEON:
574 + case CPU_JZRISC:
575 cpu_wait = r4k_wait;
576 break;
577
578 @@ -902,6 +903,23 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
579 }
580 }
581
582 +static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
583 +{
584 + decode_configs(c);
585 + c->options &= ~MIPS_CPU_COUNTER; /* JZRISC does not implement the CP0 counter. */
586 + switch (c->processor_id & 0xff00) {
587 + case PRID_IMP_JZRISC:
588 + c->cputype = CPU_JZRISC;
589 + c->isa_level = MIPS_CPU_ISA_M32R1;
590 + c->tlbsize = 32;
591 + __cpu_name[cpu] = "Ingenic JZRISC";
592 + break;
593 + default:
594 + panic("Unknown Ingenic Processor ID!");
595 + break;
596 + }
597 +}
598 +
599 const char *__cpu_name[NR_CPUS];
600
601 __cpuinit void cpu_probe(void)
602 @@ -939,6 +957,9 @@ __cpuinit void cpu_probe(void)
603 case PRID_COMP_CAVIUM:
604 cpu_probe_cavium(c, cpu);
605 break;
606 + case PRID_COMP_INGENIC:
607 + cpu_probe_ingenic(c, cpu);
608 + break;
609 }
610
611 BUG_ON(!__cpu_name[cpu]);
612 diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
613 index 6721ee2..dd4b70b 100644
614 --- a/arch/mips/mm/c-r4k.c
615 +++ b/arch/mips/mm/c-r4k.c
616 @@ -928,6 +928,36 @@ static void __cpuinit probe_pcache(void)
617 c->dcache.waybit = 0;
618 break;
619
620 + case CPU_JZRISC:
621 + config1 = read_c0_config1();
622 + config1 = (config1 >> 22) & 0x07;
623 + if (config1 == 0x07)
624 + config1 = 10;
625 + else
626 + config1 = config1 + 11;
627 + config1 += 2;
628 + icache_size = (1 << config1);
629 + c->icache.linesz = 32;
630 + c->icache.ways = 4;
631 + c->icache.waybit = __ffs(icache_size / c->icache.ways);
632 +
633 + config1 = read_c0_config1();
634 + config1 = (config1 >> 13) & 0x07;
635 + if (config1 == 0x07)
636 + config1 = 10;
637 + else
638 + config1 = config1 + 11;
639 + config1 += 2;
640 + dcache_size = (1 << config1);
641 + c->dcache.linesz = 32;
642 + c->dcache.ways = 4;
643 + c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
644 +
645 + c->dcache.flags = 0;
646 + c->options |= MIPS_CPU_PREFETCH;
647 +
648 + break;
649 +
650 default:
651 if (!(config & MIPS_CONF_M))
652 panic("Don't know how to probe P-caches on this cpu.");
653 diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
654 index 694d51f..4b2bc95 100644
655 --- a/arch/mips/mm/cache.c
656 +++ b/arch/mips/mm/cache.c
657 @@ -52,6 +52,8 @@ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
658 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
659
660 EXPORT_SYMBOL(_dma_cache_wback_inv);
661 +EXPORT_SYMBOL(_dma_cache_wback);
662 +EXPORT_SYMBOL(_dma_cache_inv);
663
664 #endif /* CONFIG_DMA_NONCOHERENT */
665
666 diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
667 index bb1719a..13c128d 100644
668 --- a/arch/mips/mm/tlbex.c
669 +++ b/arch/mips/mm/tlbex.c
670 @@ -389,6 +389,11 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
671 tlbw(p);
672 break;
673
674 + case CPU_JZRISC:
675 + tlbw(p);
676 + uasm_i_nop(p);
677 + break;
678 +
679 default:
680 panic("No TLB refill handler yet (CPU type: %d)",
681 current_cpu_data.cputype);
682 --
683 1.5.6.5
684
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