target/linux/mediatek/patches-4.14/0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch

   1 From d96cf7e724105dc73f623c2019ab5bc78cef036e Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Wed, 20 Dec 2017 17:47:06 +0800
   4 Subject: [PATCH 175/224] net: mediatek: remove superfluous pin setup for
   5  MT7622 SoC
   6
   7 Remove superfluous pin setup to get out of accessing invalid I/O pin
   8 registers because the way for pin configuring tends to be different from
   9 various SoCs and thus it should be better being managed and controlled by
  10 the pinctrl driver which MT7622 already can support.
  11
  12 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  13 Signed-off-by: David S. Miller <davem@davemloft.net>
  14 ---
  15  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------
  16  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  3 +++
  17  2 files changed, 24 insertions(+), 14 deletions(-)
  18
  19 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  20 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  21 @@ -1976,14 +1976,16 @@ static int mtk_hw_init(struct mtk_eth *e
  22         }
  23         regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
  24
  25 -       /* Set GE2 driving and slew rate */
  26 -       regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
  27 +       if (eth->pctl) {
  28 +               /* Set GE2 driving and slew rate */
  29 +               regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
  30
  31 -       /* set GE2 TDSEL */
  32 -       regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
  33 +               /* set GE2 TDSEL */
  34 +               regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
  35
  36 -       /* set GE2 TUNE */
  37 -       regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
  38 +               /* set GE2 TUNE */
  39 +               regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
  40 +       }
  41
  42         /* Set linkdown as the default for each GMAC. Its own MCR would be set
  43          * up with the more appropriate value when mtk_phy_link_adjust call is
  44 @@ -2568,11 +2570,13 @@ static int mtk_probe(struct platform_dev
  45                 }
  46         }
  47
  48 -       eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  49 -                                                   "mediatek,pctl");
  50 -       if (IS_ERR(eth->pctl)) {
  51 -               dev_err(&pdev->dev, "no pctl regmap found\n");
  52 -               return PTR_ERR(eth->pctl);
  53 +       if (eth->soc->required_pctl) {
  54 +               eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  55 +                                                           "mediatek,pctl");
  56 +               if (IS_ERR(eth->pctl)) {
  57 +                       dev_err(&pdev->dev, "no pctl regmap found\n");
  58 +                       return PTR_ERR(eth->pctl);
  59 +               }
  60         }
  61
  62         for (i = 0; i < 3; i++) {
  63 @@ -2698,17 +2702,20 @@ static int mtk_remove(struct platform_de
  64
  65  static const struct mtk_soc_data mt2701_data = {
  66         .caps = MTK_GMAC1_TRGMII,
  67 -       .required_clks = MT7623_CLKS_BITMAP
  68 +       .required_clks = MT7623_CLKS_BITMAP,
  69 +       .required_pctl = true,
  70  };
  71
  72  static const struct mtk_soc_data mt7622_data = {
  73         .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,
  74 -       .required_clks = MT7622_CLKS_BITMAP
  75 +       .required_clks = MT7622_CLKS_BITMAP,
  76 +       .required_pctl = false,
  77  };
  78
  79  static const struct mtk_soc_data mt7623_data = {
  80         .caps = MTK_GMAC1_TRGMII,
  81 -       .required_clks = MT7623_CLKS_BITMAP
  82 +       .required_clks = MT7623_CLKS_BITMAP,
  83 +       .required_pctl = true,
  84  };
  85
  86  const struct of_device_id of_mtk_match[] = {
  87 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  88 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  89 @@ -574,10 +574,13 @@ struct mtk_rx_ring {
  90   * @caps                       Flags shown the extra capability for the SoC
  91   * @required_clks              Flags shown the bitmap for required clocks on
  92   *                             the target SoC
  93 + * @required_pctl              A bool value to show whether the SoC requires
  94 + *                             the extra setup for those pins used by GMAC.
  95   */
  96  struct mtk_soc_data {
  97         u32             caps;
  98         u32             required_clks;
  99 +       bool            required_pctl;
 100  };
 101
 102  /* currently no SoC has more than 2 macs */