target/linux/mediatek/patches-4.9/0044-net-next-dsa-mediatek-tell-GDMA-when-we-are-turning-.patch

   1 From 6a5932028a4f3217ed7c9d602f269611d95dd8ca Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Wed, 9 Aug 2017 15:13:19 +0200
   4 Subject: [PATCH 44/57] net-next: dsa: mediatek: tell GDMA when we are turning
   5  on the special tag
   6
   7 Enabling this bit will make the RX DMA descriptor enable the SP bit for all
   8 ingress traffic inside the return descriptor. The PPE needs this to know
   9 that a SP is present.
  10
  11 Signed-off-by: John Crispin <john@phrozen.org>
  12 ---
  13  drivers/net/dsa/mt7530.c | 5 +++++
  14  drivers/net/dsa/mt7530.h | 4 ++++
  15  2 files changed, 9 insertions(+)
  16
  17 --- a/drivers/net/dsa/mt7530.c
  18 +++ b/drivers/net/dsa/mt7530.c
  19 @@ -742,6 +742,11 @@ mt7530_cpu_port_enable(struct mt7530_pri
  20         mt7530_write(priv, MT7530_PVC_P(port),
  21                      PORT_SPEC_TAG);
  22
  23 +       /* Enable Mediatek header mode on the GMAC that the cpu port
  24 +        * connects to */
  25 +       regmap_write_bits(priv->ethernet, MTK_GDMA_FWD_CFG(port),
  26 +                         GDMA_SPEC_TAG, GDMA_SPEC_TAG);
  27 +
  28         /* Setup the MAC by default for the cpu port */
  29         mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
  30
  31 --- a/drivers/net/dsa/mt7530.h
  32 +++ b/drivers/net/dsa/mt7530.h
  33 @@ -22,6 +22,10 @@
  34
  35  #define TRGMII_BASE(x)                 (0x10000 + (x))
  36
  37 +/* Registers for GDMA configuration access */
  38 +#define MTK_GDMA_FWD_CFG(x)            (0x500 + (x * 0x1000))
  39 +#define GDMA_SPEC_TAG                  BIT(24)
  40 +
  41  /* Registers to ethsys access */
  42  #define ETHSYS_CLKCFG0                 0x2c
  43  #define  ETHSYS_TRGMII_CLK_SEL362_5    BIT(11)