kernel: add Intel/Lantiq VRX518 EP driver
[openwrt/staging/ldir.git] / package / kernel / lantiq / vrx518_ep / src / include / net / dc_ep.h
1 /*******************************************************************************
2
3 Intel SmartPHY DSL PCIe Endpoint/ACA Linux driver
4 Copyright(c) 2016 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 *******************************************************************************/
23
24 #ifndef DC_EP_H
25 #define DC_EP_H
26
27 #include <linux/types.h>
28 #include <linux/pci.h>
29 #include <linux/device.h>
30
31 /* @{ */
32 /*! \def DC_EP_MAX_PEER
33 * \brief how many EP partners existed. In most cases, this number should be
34 * one for bonding application. For the future extension, it could be bigger
35 * value. For example, multiple bonding
36 */
37 #define DC_EP_MAX_PEER 1
38
39 /* Reset related module bit definition */
40 #define RST_GPIO BIT(2)
41 #define RST_DSL_IF BIT(3)
42 #define RST_DFE BIT(7)
43 #define RST_PPE BIT(8)
44 #define RST_CDMA BIT(9)
45 #define RST_SPI BIT(10)
46 #define RST_IMCU BIT(11)
47 #define RST_ACA_DMA BIT(14)
48 #define RST_AFE BIT(16)
49 #define RST_ACA_HOSTIF BIT(17)
50 #define RST_PCIE BIT(22)
51 #define RST_PPE_ATM_TC BIT(23)
52 #define RST_FPI_SLAVE BIT(25)
53 #define RST_GLOBAL BIT(30)
54
55 /* PMU related module definition */
56 #define PMU_ADMA BIT(0)
57 #define PMU_CDMA BIT(2)
58 #define PMU_SPI BIT(8)
59 #define PMU_DSL BIT(9)
60 #define PMU_PPE_QSB BIT(18)
61 #define PMU_PPE_SLL01 BIT(19)
62 #define PMU_PPE_TC BIT(21)
63 #define PMU_EMA BIT(22)
64 #define PMU_PPM2 BIT(23)
65 #define PMU_PPE_TOP BIT(29)
66
67 /* IMER bit definition */
68 #define PPE2HOST_INT0 BIT(0)
69 #define PPE2HOST_INT1 BIT(1)
70 #define DYING_GASP_INT BIT(3)
71 #define MEI_IRQ BIT(8)
72 #define ACA_XBAR_INT BIT(9)
73 #define MODEM_XBAR_INT BIT(12)
74 #define LED0_INT BIT(13)
75 #define LED1_INT BIT(14)
76 #define NMI_PLL BIT(15)
77 #define DMA_TX BIT(16)
78 #define DMA_RX BIT(17)
79 #define ACA_HOSTIF_TX BIT(20)
80 #define ACA_HOSTIF_RX BIT(21)
81 #define ACA_RXOUT_PD_RING_FULL BIT(22)
82 #define ACA_TXOUT_PD_RING_FULL BIT(23)
83
84 /*
85 * Structure used to specify available pin mux functions for gpio pinx
86 * It will be used in pinmux_set() function
87 */
88 enum gpio_padc_func {
89 MUX_FUNC_GPIO = 0,
90 MUX_FUNC_ALT1,
91 MUX_FUNC_ALT2,
92 MUX_FUNC_RES,
93 };
94
95 /*
96 * Structure used to specify interrupt source so that EP can assign unique
97 * interruot to it
98 */
99 enum dc_ep_int {
100 DC_EP_INT_PPE, /*!< PPE2HOST_INT 0/1 */
101 DC_EP_INT_MEI, /*!< DSL MEI_IRQ */
102 DC_EP_INT_MAX,
103 };
104
105 /* Clock setting for system clock */
106 enum {
107 SYS_CLK_36MHZ = 0,
108 SYS_CLK_288MHZ,
109 SYS_CLK_MAX,
110 };
111
112 /* Clock setting for PPE clock */
113 enum {
114 PPE_CLK_36MHZ = 0,
115 PPE_CLK_576MHZ,
116 PPE_CLK_494MHZ,
117 PPE_CLK_432MHZ,
118 PPE_CLK_288MHZ,
119 PPE_CLK_MAX,
120 };
121
122 /* GPIO direction IN/OUT */
123 enum {
124 GPIO_DIR_IN = 0,
125 GPIO_DIR_OUT,
126 GPIO_DIR_MAX,
127 };
128
129 /* GPIO Pullup/Pulldown setting */
130 enum {
131 GPIO_PUPD_DISABLE = 0,
132 GPIO_PULL_UP,
133 GPIO_PULL_DOWN,
134 GPIO_PUPD_BOTH,
135 };
136
137 /* GPIO slew rate setting */
138 enum {
139 GPIO_SLEW_RATE_SLOW = 0,
140 GPIO_SLEW_RATE_FAST,
141 };
142
143 /* GPIO driver current setting */
144 enum {
145 GPIO_DRV_CUR_2MA = 0,
146 GPIO_DRV_CUR_4MA,
147 GPIO_DRV_CUR_8MA,
148 GPIO_DRV_CUR_12MA,
149 GPIO_DRV_CUR_MAX,
150 };
151
152 enum {
153 ACA_LITTLE_ENDIAN = 0,
154 ACA_BIG_ENDIAN,
155 ACA_ENDIAN_MAX,
156 };
157
158 enum {
159 ACA_TXIN = 0,
160 ACA_TXOUT,
161 ACA_RXIN,
162 ACA_RXOUT,
163 ACA_MAX,
164 };
165
166 /* ACA four major direction functions for start/stop */
167 #define ACA_TXIN_EN BIT(0)
168 #define ACA_TXOUT_EN BIT(1)
169 #define ACA_RXIN_EN BIT(2)
170 #define ACA_RXOUT_EN BIT(3)
171 #define ACA_ALL_EN 0xF
172
173 struct dc_ep_dev;
174
175 /*
176 * ACA SoC specific parameters. The caller needs to fill up all necessary info
177 * according to specific SoC and specific project
178 * For each function, different parameters are needed.
179 */
180 struct aca_cfg_param {
181 u32 soc_desc_base; /*!< SoC CBM or DDR descriptor base address */
182 u32 soc_desc_num; /*!< SoC and HostIF (same) descriptor number */
183 u32 soc_cmlt_cnt_addr; /*! SoC cumulative counter address */
184 u32 pp_buf_desc_num; /*!< ACA ping pong buffer descriptor number */
185 u32 pd_desc_base; /*!< Packet Descriptor base address in modem */
186 u32 pd_desc_num; /*!< Packet Descriptor number in modem */
187 u32 hd_size_in_dw; /*!< Host(SoC) descriptor size in dwords */
188 u32 pd_size_in_dw; /*!< Packet descriptor size in dwords */
189 u32 byteswap; /*!< Byte swap enabled or not in ACA FW */
190 u32 prefill_cnt; /*!< Prefill counter special required for some platform */
191 };
192
193 struct aca_param {
194 struct aca_cfg_param aca_txin;
195 struct aca_cfg_param aca_txout;
196 struct aca_cfg_param aca_rxin;
197 struct aca_cfg_param aca_rxout;
198 };
199
200 /* ACA project/modem specific parameters. It is only valid for VRX518 */
201 struct aca_proj_param {
202 u32 stat; /*!< Target state */
203 u32 pd; /*!< Target packet descripor */
204 u32 acc_cnt; /*!< Target accumulate counter */
205 };
206
207 /* Project specific configuration */
208 struct aca_modem_param {
209 struct aca_proj_param mdm_txout;
210 struct aca_proj_param mdm_rxin;
211 struct aca_proj_param mdm_rxout;
212 };
213
214 /* Event trigger register address <offset> */
215 struct aca_event_reg_addr {
216 u32 txin_acc_sub;
217 u32 txout_acc_add;
218 u32 rxin_acc_sub;
219 u32 rxout_acc_add;
220 };
221
222 /*
223 * ACA common hardware low level APIs, presented as callbacks instead of
224 * separate APIs to support mulitple instances
225 */
226 struct aca_hw_ops {
227 /* RCU Callbacks */
228 void (*reset_assert)(struct dc_ep_dev *pdev, u32 rd);
229 void (*reset_deassert)(struct dc_ep_dev *pdev, u32 rd);
230 /* For hardware self-clear reset, most apply except PCIe */
231 int (*reset_device)(struct dc_ep_dev *pdev, u32 hd);
232
233 /* PMU Callbacks */
234 int (*clk_on)(struct dc_ep_dev *pdev, u32 cd);
235 int (*clk_off)(struct dc_ep_dev *pdev, u32 cd);
236
237 /* CGU Callbacks */
238 int (*clk_set)(struct dc_ep_dev *pdev, u32 sysclk, u32 ppeclk);
239 int (*clk_get)(struct dc_ep_dev *pdev, u32 *sysclk, u32 *ppeclk);
240
241 /* GPIO Callbacks */
242 int (*gpio_dir)(struct dc_ep_dev *pdev, u32 gpio, int dir);
243 int (*gpio_set)(struct dc_ep_dev *pdev, u32 gpio, int val);
244 int (*gpio_get)(struct dc_ep_dev *pdev, u32 gpio, int *val);
245
246 /* PinMux Callbacks */
247 int (*pinmux_set)(struct dc_ep_dev *pdev, u32 gpio, int func);
248 int (*pinmux_get)(struct dc_ep_dev *pdev, u32 gpio, int *func);
249 int (*gpio_pupd_set)(struct dc_ep_dev *pdev, u32 gpio, u32 val);
250 int (*gpio_od_set)(struct dc_ep_dev *pdev, u32 gpio, int val);
251 int (*gpio_src_set)(struct dc_ep_dev *pdev, u32 gpio, int val);
252 int (*gpio_dcc_set)(struct dc_ep_dev *pdev, u32 gpio, u32 val);
253
254 /* ICU Callbacks */
255 void (*icu_en)(struct dc_ep_dev *pdev, u32 bit);
256 void (*icu_mask)(struct dc_ep_dev *pdev, u32 bit);
257
258 /* ACA related stuff */
259 int (*aca_start)(struct dc_ep_dev *pdev, u32 func, int start);
260 int (*aca_stop)(struct dc_ep_dev *pdev, u32 *func, int reset);
261 /* If there is no project specific parameters, input NULL */
262 int (*aca_init)(struct dc_ep_dev *pdev, struct aca_param *aca,
263 struct aca_modem_param *mdm);
264 void (*aca_event_addr_get)(struct dc_ep_dev *pdev,
265 struct aca_event_reg_addr *regs);
266 /* UMT address needed for SoC filled in to trigger UMT msg */
267 u32 (*umt_msg_addr)(struct dc_ep_dev *pdev, u32 endian, u32 type);
268 /* TXIN accum sub to ack PPE already processed */
269 void (*aca_txin_ack_sub)(struct dc_ep_dev *pdev, u32 val);
270 u32 (*aca_txin_hd_cnt)(struct dc_ep_dev *pdev);
271 };
272
273 /*
274 * Structure used to extract attached EP detailed information
275 * for PPE/DSL_MEI driver/Bonding
276 */
277 struct dc_ep_dev {
278 struct device *dev;
279 u32 irq; /*!< MSI interrupt number for this device */
280 u32 aca_tx_irq; /*!< ACA Non-empty TX irq number for PPE driver */
281 u32 aca_rx_irq; /*!< ACA Non-empty RX irq number for PPE driver */
282 /*!< The EP inbound memory base address derived from BAR0, SoC
283 virtual address for PPE/DSL_MEI driver
284 */
285 bool switch_attached; /*!< EP attach switch */
286 u8 __iomem *membase; /*!< virtual memory base address to access EP */
287 u32 phy_membase; /*!< The EP inbound memory base address derived
288 from BAR0, physical address for PPE FW
289 */
290 u32 peer_num; /*!< Bonding peer number available */
291 /*!< The bonding peer EP inbound memory base address derived from
292 its BAR0, SoC virtual address for PPE/DSL_MEI driver
293 */
294 u8 __iomem *peer_membase[DC_EP_MAX_PEER];
295 /*!< The bonding peer EP inbound memory base address derived from
296 its BAR0, physical address for PPE FW
297 */
298 u32 peer_phy_membase[DC_EP_MAX_PEER];
299 const struct aca_hw_ops *hw_ops;
300 void *priv; /* Pointer to driver proprietary data for internal use */
301 };
302
303 /*
304 * This function returns the total number of EPs attached. Normally,
305 * the number should be one <standard smartPHY EP> or two <smartPHY
306 * off-chip bonding cases>. Extended case is also considered
307
308 * \param[in/out] dev_num Pointer to detected EP numbers in total.
309 * \return -EIO Invalid total EP number which means this
310 * module is not initialized properly
311 * \return 0 Successfully return the detected EP numbers
312 */
313 int dc_ep_dev_num_get(int *dev_num);
314
315 /*
316 * This function returns detailed EP device information for PPE/DSL/Bonding
317 * partner by its logical index obtained
318 * by \ref dc_ep_dev_num_get and its interrupt module number
319 * \ref dc_ep_int
320
321 * \param[in] dev_idx Logical device index referred to the related
322 * device
323 * \param[in] module EP interrupt module user<PPE/MEI>
324 * \param[in/out] dev Pointer to returned detail device structure
325 * \ref dc_ep_dev
326 * \return -EIO Invalid logical device index or too many modules
327 * referred to this module
328 * \return 0 Successfully return required device information
329
330 * \remarks This function normally will be called to trace the detailed device
331 * information after calling \ref dc_ep_dev_num_get
332 */
333 int dc_ep_dev_info_req(int dev_idx, enum dc_ep_int module,
334 struct dc_ep_dev *dev);
335
336 /*
337 * This function releases the usage of this module by PPE/DSL
338
339 * \param[in] dev_idx Logical device index referred to the related device
340 * \return -EIO Invalid logical device index or release too many
341 * times to refer to this module
342 * \return 0 Successfully release the usage of this module
343
344 * \remarks This function should be called once their reference is over.
345 * The reference usage must matches \ref dc_ep_dev_info_req
346 */
347 int dc_ep_dev_info_release(int dev_idx);
348
349 #endif /* DC_EP_H */