package/kernel/lantiq/vrx518_ep/src/test/ep_test.h

   1 /*******************************************************************************
   2
   3   Intel SmartPHY DSL PCIe Endpoint/ACA Linux driver
   4   Copyright(c) 2016 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22 *******************************************************************************/
  23
  24 #ifndef EP_TEST_H
  25 #define EP_TEST_H
  26
  27 /* SB address on xBar */
  28 #define SB_XBAR_BASE            0x280000
  29 #define SB_XBAR_DES_RXBASE      SB_XBAR_BASE
  30 #define SB_XBAR_DES_TXBASE      (SB_XBAR_BASE + 0x400)
  31 #define SB_XBAR_DATA_BASE       (SB_XBAR_BASE + 0x800)
  32 #define SB_XBAR_ADDR(x)         (SB_XBAR_BASE + ((((x) - 0xA000)) << 2))
  33
  34 /*----------------------------------------------------------
  35  * ACA Shadow Registers
  36  * 3 * 4 = 12
  37  * *_STATUS need to be initialized to nonzero by PPE driver
  38  *----------------------------------------------------------
  39  */
  40
  41 #define __ACA_SHADOW_REG_BASE                   0xADF0
  42
  43 #define __TX_IN_ACA_ACCUM_COUNT                 0xADF0
  44
  45 #define __TX_IN_ACA_ACCUM_STATUS                0xADF1
  46
  47 #define __TX_IN_QUEUE_PD_BASE_ADDR_OFFSET       0xADF2
  48
  49 #define __TX_OUT_ACA_ACCUM_COUNT                0xADF3
  50
  51 #define __TX_OUT_ACA_ACCUM_STATUS               0xADF4
  52
  53 #define __TX_OUT_QUEUE_PD_BASE_ADDR_OFFSET      0xADF5
  54
  55 #define __RX_IN_ACA_ACCUM_COUNT                 0xADF6
  56
  57 #define __RX_IN_ACA_ACCUM_STATUS                0xADF7
  58
  59 #define __RX_IN_QUEUE_PD_BASE_ADDR_OFFSET       0xADF8
  60
  61 #define __RX_OUT_ACA_ACCUM_COUNT                0xADF9
  62
  63 #define __RX_OUT_ACA_ACCUM_STATUS               0xADFA
  64
  65 #define __RX_OUT_QUEUE_PD_BASE_ADDR_OFFSET      0xADFB
  66
  67 #define TXIN_PD_DES_NUM         64
  68 #define TXIN_PD_DBASE           0x105400
  69 #define TXIN_SOC_DES_NUM        32
  70 #define TXIN_SOC_DBASE          0x24000000
  71 #define TXIN_HOST_DES_NUM       32
  72 #define TXIN_HD_DES_SIZE        4 /* size in DWORD */
  73 #define TXIN_PD_DES_SIZE        2 /* size in DWORD */
  74
  75 #define TXOUT_PD_DES_NUM        32
  76 #define TXOUT_PD_DBASE          0x105700
  77 #define TXOUT_SOC_DES_NUM       32
  78 #define TXOUT_SOC_DBASE         0x24001000
  79 #define TXOUT_HOST_DES_NUM      32
  80 #define TXOUT_HD_DES_SIZE       1 /* size in DWORD */
  81 #define TXOUT_PD_DES_SIZE       2 /* size in DWORD */
  82
  83 #define RXOUT_PD_DES_NUM        32
  84 #define RXOUT_PD_DBASE          0x105C00
  85 #define RXOUT_SOC_DES_NUM       32
  86 #define RXOUT_SOC_DBASE         0x24002000
  87 #define RXOUT_HOST_DES_NUM      32
  88 #define RXOUT_HD_DES_SIZE       4 /* size in DWORD */
  89 #define RXOUT_PD_DES_SIZE       2 /* size in DWORD */
  90
  91 /* PPE interrupt */
  92 #define PPE_MBOX_TEST_BIT       0x1
  93 #define PPE_MBOX_IRQ_TEST_NUM   100
  94
  95 #define PPE_MBOX_BASE           0x334800
  96
  97 #define MBOX_REG(X)     (PPE_MBOX_BASE + (X))
  98 #define MBOX_IGU0_ISRS  MBOX_REG(0x0)
  99 #define MBOX_IGU0_ISRC  MBOX_REG(0x4)
 100 #define MBOX_IGU0_ISR   MBOX_REG(0x8)
 101 #define MBOX_IGU0_IER   MBOX_REG(0xc)
 102
 103 #define HOST_IF_BASE            0x50000
 104 #define HOST_IF_REG(X)          (HOST_IF_BASE + (X))
 105 #define TXIN_CONV_CFG           HOST_IF_REG(0x14)
 106 #define RXIN_HD_ACCUM_ADD       HOST_IF_REG(0xC8) /* UMT Message trigger */
 107 #define TXIN_HD_ACCUM_ADD       HOST_IF_REG(0xCC) /* UMT Message trigger */
 108 #define RXOUT_ACA_ACCUM_ADD     HOST_IF_REG(0xE0) /* PPE FW tigger */
 109 #define TXOUT_ACA_ACCUM_ADD     HOST_IF_REG(0xE4) /* PPE FW tigger */
 110
 111 #define CDMA_BASE       0x2D0000
 112 #define CDMA_REG(X)     (CDMA_BASE + (X))
 113
 114 #define DMA_CLC         CDMA_REG(0x00)
 115 #define DMA_ID          CDMA_REG(0x08)
 116 #define DMA_CTRL        CDMA_REG(0x10)
 117
 118 #define DMA_CTRL_RST            BIT(0)
 119 #define DMA_CTRL_DSRAM_PATH     BIT(1)
 120 #define DMA_CTRL_CH_FL          BIT(6)
 121 #define DMA_CTRL_DS_FOD         BIT(7)
 122 #define DMA_CTRL_DRB            BIT(8)
 123 #define DMA_CTRL_ENBE           BIT(9)
 124 #define DMA_CTRL_PRELOAD_INT_S  10
 125 #define DMA_CTRL_PRELOAD_INT    0x0C00u
 126 #define DMA_CTRL_PRELOAD_EN     BIT(12)
 127 #define DMA_CTRL_MBRST_CNT_S    16
 128 #define DMA_CTRL_MBRST_CNT      0x3FF0000u
 129 #define DMA_CTRL_MBRSTARB       BIT(30)
 130 #define DMA_CTRL_PKTARB         BIT(31)
 131
 132 #define DMA_CPOLL       CDMA_REG(0x14)
 133 #define DMA_CPOLL_CNT_S         4
 134 #define DMA_CPOLL_CNT           0xFFF0u
 135 #define DMA_CPOLL_EN            BIT(31)
 136
 137 #define DMA_CS          CDMA_REG(0x18)
 138 #define DMA_CCTRL       CDMA_REG(0x1C)
 139 #define DMA_CCTRL_ON            BIT(0)
 140 #define DMA_CCTRL_RST           BIT(1)
 141 #define DMA_CCTRL_DIR_TX        BIT(8)
 142 #define DMA_CCTRL_CLASS_S       9
 143 #define DMA_CCTRL_CLASS         0xE00u
 144 #define DMA_CCTRL_PRTNR_S       12
 145 #define DMA_CCTRL_PRTNR         0xF000u
 146 #define DMA_CCTRL_TXWGT_S       16
 147 #define DMA_CCTRL_TXWGT         0x30000u
 148 #define DMA_CCTRL_CLASSH_S      18
 149 #define DMA_CCTRL_CLASSH        0xC0000u
 150 #define DMA_CCTRL_PDEN          BIT(23)
 151 #define DMA_CCTRL_P2PCPY        BIT(24)
 152 #define DMA_CCTRL_LBEN          BIT(25)
 153 #define DMA_CCTRL_LBCHNR_S      26
 154 #define DMA_CCTRL_LBCHNR        0xFC000000u
 155
 156 #define DMA_CDBA        CDMA_REG(0x20)
 157 #define DMA_CDLEN       CDMA_REG(0x24)
 158 #define DMA_CIS         CDMA_REG(0x28)
 159 #define DMA_CIE         CDMA_REG(0x2C)
 160
 161 #define DMA_CI_EOP              BIT(1)
 162 #define DMA_CI_DUR              BIT(2)
 163 #define DMA_CI_DESCPT           BIT(3)
 164 #define DMA_CI_CHOFF            BIT(4)
 165 #define DMA_CI_RDERR            BIT(5)
 166 #define DMA_CI_ALL      (DMA_CI_EOP | DMA_CI_DUR | DMA_CI_DESCPT\
 167                         | DMA_CI_CHOFF | DMA_CI_RDERR)
 168
 169 #define DMA_CI_DEFAULT  (DMA_CI_EOP | DMA_CI_DESCPT)
 170 #define DMA_CDPTNRD     CDMA_REG(0x34)
 171
 172 #define DMA_PS          CDMA_REG(0x40)
 173 #define DMA_PCTRL       CDMA_REG(0x44)
 174 #define DMA_PCTRL_RXBL16        BIT(0)
 175 #define DMA_PCTRL_TXBL16        BIT(1)
 176 #define DMA_PCTRL_RXBL_S        2
 177 #define DMA_PCTRL_RXBL          0xCu
 178 #define DMA_PCTRL_TXBL_S        4
 179 #define DMA_PCTRL_TXBL          0x30u
 180 #define DMA_PCTRL_PDEN          BIT(6)
 181 #define DMA_PCTRL_PDEN_S        6
 182 #define DMA_PCTRL_RXENDI_S      8
 183 #define DMA_PCTRL_RXENDI        0x300u
 184 #define DMA_PCTRL_TXENDI_S      10
 185 #define DMA_PCTRL_TXENDI        0xC00u
 186 #define DMA_PCTRL_TXWGT_S       12
 187 #define DMA_PCTRL_TXWGT         0x7000u
 188 #define DMA_PCTRL_MEM_FLUSH     BIT(16)
 189
 190 #define DMA_IRNEN       CDMA_REG(0xF4)
 191 #define DMA_IRNCR       CDMA_REG(0xF8)
 192 #define DMA_IRNICR      CDMA_REG(0xFC)
 193
 194 #ifdef CONFIG_CPU_BIG_ENDIAN
 195 struct aca_dma_desc {
 196         /* DW0 */
 197         u32 dw0;
 198         /* DW1 */
 199         u32 dw1;
 200         /* DW2 */
 201         u32 data_pointer;
 202         /* DW3 */
 203         u32 own:1;
 204         u32 c:1;
 205         u32 sop:1;
 206         u32 eop:1;
 207         u32 dic:1;
 208         u32 pdu_type:1;
 209         u32 byte_off:3;
 210         u32 qid:4;
 211         u32 mpoa_pt:1;
 212         u32 mpoa_mode:2;
 213         u32 data_len:16;
 214 }__packed __aligned(16);
 215
 216 /* 2 DWs format descriptor */
 217 struct aca_dma_desc_2dw {
 218         u32 data_pointer; /* Descriptor data pointer */
 219         union {
 220                 struct {
 221                         u32 own:1;
 222                         u32 c:1;
 223                         u32 sop:1;
 224                         u32 eop:1;
 225                         u32 meta_data0:2;
 226                         u32 byte_offset:3;
 227                         u32 meta_data1:7;
 228                         u32 data_len:16;
 229                 } __packed field;
 230                 u32 word;
 231         } __packed status;
 232 } __packed __aligned(8);
 233 #else
 234 struct aca_dma_desc {
 235         /* DW0 */
 236         u32 dw0;
 237         /* DW1 */
 238         u32 dw1;
 239         /* DW2 */
 240         u32 data_pointer;
 241         /* DW 3 */
 242         u32 data_len:16;
 243         u32 mpoa_mode:2;
 244         u32 mpoa_pt:1;
 245         u32 qid:4;
 246         u32 byte_off:3;
 247         u32 pdu_type:1;
 248         u32 dic:1;
 249         u32 eop:1;
 250         u32 sop:1;
 251         u32 c:1;
 252         u32 own:1;
 253 }__packed __aligned(16);
 254
 255 /* 2 DWs format descriptor */
 256 struct aca_dma_desc_2dw {
 257         u32 data_pointer; /* Descriptor data pointer */
 258         union {
 259                 struct {
 260                         u32 data_len:16;
 261                         u32 meta_data1:7;
 262                         u32 byte_offset:3;
 263                         u32 meta_data0:2;
 264                         u32 eop:1;
 265                         u32 sop:1;
 266                         u32 c:1;
 267                         u32 own:1;
 268                 } __packed field;
 269                 u32 word;
 270         } __packed status;
 271 } __packed __aligned(8);
 272 #endif
 273 #endif /* EP_TEST_H */