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realtek: dsa: support active-high LEDs
[openwrt/staging/ldir.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl930x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/inetdevice.h>
5
6 #include "rtl83xx.h"
7
8 #define RTL930X_VLAN_PORT_TAG_STS_INTERNAL 0x0
9 #define RTL930X_VLAN_PORT_TAG_STS_UNTAG 0x1
10 #define RTL930X_VLAN_PORT_TAG_STS_TAGGED 0x2
11 #define RTL930X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3
12
13 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE 0xCE24
14 /* port 0-28 */
15 #define RTL930X_VLAN_PORT_TAG_STS_CTRL(port) \
16 RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
17 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK GENMASK(7,6)
18 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK GENMASK(5,4)
19 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3)
20 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2)
21 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1)
22 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0)
23
24 #define RTL930X_LED_GLB_ACTIVE_LOW BIT(22)
25
26 extern struct mutex smi_lock;
27 extern struct rtl83xx_soc_info soc_info;
28
29 /* Definition of the RTL930X-specific template field IDs as used in the PIE */
30 enum template_field_id {
31 TEMPLATE_FIELD_SPM0 = 0, /* Source portmask ports 0-15 */
32 TEMPLATE_FIELD_SPM1 = 1, /* Source portmask ports 16-31 */
33 TEMPLATE_FIELD_DMAC0 = 2, /* Destination MAC [15:0] */
34 TEMPLATE_FIELD_DMAC1 = 3, /* Destination MAC [31:16] */
35 TEMPLATE_FIELD_DMAC2 = 4, /* Destination MAC [47:32] */
36 TEMPLATE_FIELD_SMAC0 = 5, /* Source MAC [15:0] */
37 TEMPLATE_FIELD_SMAC1 = 6, /* Source MAC [31:16] */
38 TEMPLATE_FIELD_SMAC2 = 7, /* Source MAC [47:32] */
39 TEMPLATE_FIELD_ETHERTYPE = 8, /* Ethernet frame type field */
40 TEMPLATE_FIELD_OTAG = 9,
41 TEMPLATE_FIELD_ITAG = 10,
42 TEMPLATE_FIELD_SIP0 = 11,
43 TEMPLATE_FIELD_SIP1 = 12,
44 TEMPLATE_FIELD_DIP0 = 13,
45 TEMPLATE_FIELD_DIP1 = 14,
46 TEMPLATE_FIELD_IP_TOS_PROTO = 15,
47 TEMPLATE_FIELD_L4_SPORT = 16,
48 TEMPLATE_FIELD_L4_DPORT = 17,
49 TEMPLATE_FIELD_L34_HEADER = 18,
50 TEMPLATE_FIELD_TCP_INFO = 19,
51 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 20,
52 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 21,
53 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 22,
54 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 23,
55 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 24,
56 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 25,
57 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 26,
58 TEMPLATE_FIELD_SIP2 = 27,
59 TEMPLATE_FIELD_SIP3 = 28,
60 TEMPLATE_FIELD_SIP4 = 29,
61 TEMPLATE_FIELD_SIP5 = 30,
62 TEMPLATE_FIELD_SIP6 = 31,
63 TEMPLATE_FIELD_SIP7 = 32,
64 TEMPLATE_FIELD_DIP2 = 33,
65 TEMPLATE_FIELD_DIP3 = 34,
66 TEMPLATE_FIELD_DIP4 = 35,
67 TEMPLATE_FIELD_DIP5 = 36,
68 TEMPLATE_FIELD_DIP6 = 37,
69 TEMPLATE_FIELD_DIP7 = 38,
70 TEMPLATE_FIELD_PKT_INFO = 39,
71 TEMPLATE_FIELD_FLOW_LABEL = 40,
72 TEMPLATE_FIELD_DSAP_SSAP = 41,
73 TEMPLATE_FIELD_SNAP_OUI = 42,
74 TEMPLATE_FIELD_FWD_VID = 43,
75 TEMPLATE_FIELD_RANGE_CHK = 44,
76 TEMPLATE_FIELD_VLAN_GMSK = 45, /* VLAN Group Mask/IP range check */
77 TEMPLATE_FIELD_DLP = 46,
78 TEMPLATE_FIELD_META_DATA = 47,
79 TEMPLATE_FIELD_SRC_FWD_VID = 48,
80 TEMPLATE_FIELD_SLP = 49,
81 };
82
83 /* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
84 * RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
85 */
86 #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
87
88 /* Number of fixed templates predefined in the RTL9300 SoC */
89 #define N_FIXED_TEMPLATES 5
90 /* RTL9300 specific predefined templates */
91 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
92 {
93 {
94 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
95 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
96 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,
97 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
98 }, {
99 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
100 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,
101 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,
102 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
103 }, {
104 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
105 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
106 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
107 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
108 }, {
109 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
110 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
111 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,
112 TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
113 }, {
114 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
115 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
116 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_VLAN,
117 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM1
118 },
119 };
120
121 void rtl930x_print_matrix(void)
122 {
123 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
124
125 for (int i = 0; i < 29; i++) {
126 rtl_table_read(r, i);
127 pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0)));
128 }
129 rtl_table_release(r);
130 }
131
132 inline void rtl930x_exec_tbl0_cmd(u32 cmd)
133 {
134 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0);
135 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17));
136 }
137
138 inline void rtl930x_exec_tbl1_cmd(u32 cmd)
139 {
140 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1);
141 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17));
142 }
143
144 inline int rtl930x_tbl_access_data_0(int i)
145 {
146 return RTL930X_TBL_ACCESS_DATA_0(i);
147 }
148
149 static inline int rtl930x_l2_port_new_salrn(int p)
150 {
151 return RTL930X_L2_PORT_SALRN(p);
152 }
153
154 static inline int rtl930x_l2_port_new_sa_fwd(int p)
155 {
156 /* TODO: The definition of the fields changed, because of the master-cpu in a stack */
157 return RTL930X_L2_PORT_NEW_SA_FWD(p);
158 }
159
160 inline static int rtl930x_trk_mbr_ctr(int group)
161 {
162 return RTL930X_TRK_MBR_CTRL + (group << 2);
163 }
164
165 static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
166 {
167 u32 v, w;
168 /* Read VLAN table (1) via register 0 */
169 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
170
171 rtl_table_read(r, vlan);
172 v = sw_r32(rtl_table_data(r, 0));
173 w = sw_r32(rtl_table_data(r, 1));
174 pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w);
175 rtl_table_release(r);
176
177 info->tagged_ports = v >> 3;
178 info->profile_id = (w >> 24) & 7;
179 info->hash_mc_fid = !!(w & BIT(27));
180 info->hash_uc_fid = !!(w & BIT(28));
181 info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7);
182
183 /* Read UNTAG table via table register 2 */
184 r = rtl_table_get(RTL9300_TBL_2, 0);
185 rtl_table_read(r, vlan);
186 v = sw_r32(rtl_table_data(r, 0));
187 rtl_table_release(r);
188
189 info->untagged_ports = v >> 3;
190 }
191
192 static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
193 {
194 u32 v, w;
195 /* Access VLAN table (1) via register 0 */
196 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
197
198 v = info->tagged_ports << 3;
199 v |= ((u32)info->fid) >> 3;
200
201 w = ((u32)info->fid) << 29;
202 w |= info->hash_mc_fid ? BIT(27) : 0;
203 w |= info->hash_uc_fid ? BIT(28) : 0;
204 w |= info->profile_id << 24;
205
206 sw_w32(v, rtl_table_data(r, 0));
207 sw_w32(w, rtl_table_data(r, 1));
208
209 rtl_table_write(r, vlan);
210 rtl_table_release(r);
211 }
212
213 void rtl930x_vlan_profile_dump(int profile)
214 {
215 u32 p[5];
216
217 if (profile < 0 || profile > 7)
218 return;
219
220 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
221 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
222 p[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8) & 0x1FFFFFFF;
223 p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF;
224 p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF;
225
226 pr_info("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
227 profile, p[0] & (3 << 21), p[2], p[3], p[4]);
228 pr_info(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
229 p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',
230 p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');
231 pr_info(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
232 p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');
233 pr_info("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
234 profile, p[0], p[1], p[2], p[3], p[4]);
235 }
236
237 static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask)
238 {
239 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0);
240
241 sw_w32(portmask << 3, rtl_table_data(r, 0));
242 rtl_table_write(r, vlan);
243 rtl_table_release(r);
244 }
245
246 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */
247 static void rtl930x_vlan_fwd_on_inner(int port, bool is_set)
248 {
249 /* Always set all tag modes to fwd based on either inner or outer tag */
250 if (is_set)
251 sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2));
252 else
253 sw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD + (port << 2));
254 }
255
256 static void rtl930x_vlan_profile_setup(int profile)
257 {
258 u32 p[5];
259
260 pr_info("In %s\n", __func__);
261 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
262 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
263
264 /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */
265 p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);
266 p[2] = 0x1fffffff; /* L2 unknown MC flooding portmask all ports, including the CPU-port */
267 p[3] = 0x1fffffff; /* IPv4 unknown MC flooding portmask */
268 p[4] = 0x1fffffff; /* IPv6 unknown MC flooding portmask */
269
270 sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile));
271 sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4);
272 sw_w32(p[2], RTL930X_VLAN_PROFILE_SET(profile) + 8);
273 sw_w32(p[3], RTL930X_VLAN_PROFILE_SET(profile) + 12);
274 sw_w32(p[4], RTL930X_VLAN_PROFILE_SET(profile) + 16);
275 }
276
277 static void rtl930x_l2_learning_setup(void)
278 {
279 /* Portmask for flooding broadcast traffic */
280 sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK);
281
282 /* Portmask for flooding unicast traffic with unknown destination */
283 sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK);
284
285 /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */
286 sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL);
287 }
288
289 static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
290 {
291 u32 cmd = 1 << 17 | /* Execute cmd */
292 0 << 16 | /* Read */
293 4 << 12 | /* Table type 0b10 */
294 (msti & 0xfff);
295 priv->r->exec_tbl0_cmd(cmd);
296
297 for (int i = 0; i < 2; i++)
298 port_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i));
299 pr_debug("MSTI: %d STATE: %08x, %08x\n", msti, port_state[0], port_state[1]);
300 }
301
302 static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
303 {
304 u32 cmd = 1 << 17 | /* Execute cmd */
305 1 << 16 | /* Write */
306 4 << 12 | /* Table type 4 */
307 (msti & 0xfff);
308
309 for (int i = 0; i < 2; i++)
310 sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i));
311 priv->r->exec_tbl0_cmd(cmd);
312 }
313
314 static inline int rtl930x_mac_force_mode_ctrl(int p)
315 {
316 return RTL930X_MAC_FORCE_MODE_CTRL + (p << 2);
317 }
318
319 static inline int rtl930x_mac_port_ctrl(int p)
320 {
321 return RTL930X_MAC_L2_PORT_CTRL(p);
322 }
323
324 static inline int rtl930x_mac_link_spd_sts(int p)
325 {
326 return RTL930X_MAC_LINK_SPD_STS(p);
327 }
328
329 static u64 rtl930x_l2_hash_seed(u64 mac, u32 vid)
330 {
331 u64 v = vid;
332
333 v <<= 48;
334 v |= mac;
335
336 return v;
337 }
338
339 /* Calculate both the block 0 and the block 1 hash by applyingthe same hash
340 * algorithm as the one used currently by the ASIC to the seed, and return
341 * both hashes in the lower and higher word of the return value since only 12 bit of
342 * the hash are significant
343 */
344 static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
345 {
346 u32 k0, k1, h1, h2, h;
347
348 k0 = (u32) (((seed >> 55) & 0x1f) ^
349 ((seed >> 44) & 0x7ff) ^
350 ((seed >> 33) & 0x7ff) ^
351 ((seed >> 22) & 0x7ff) ^
352 ((seed >> 11) & 0x7ff) ^
353 (seed & 0x7ff));
354
355 h1 = (seed >> 11) & 0x7ff;
356 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
357
358 h2 = (seed >> 33) & 0x7ff;
359 h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
360
361 k1 = (u32) (((seed << 55) & 0x1f) ^
362 ((seed >> 44) & 0x7ff) ^
363 h2 ^
364 ((seed >> 22) & 0x7ff) ^
365 h1 ^
366 (seed & 0x7ff));
367
368 /* Algorithm choice for block 0 */
369 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
370 h = k1;
371 else
372 h = k0;
373
374 /* Algorithm choice for block 1
375 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
376 * half of hash-space
377 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
378 * divided by 2 to divide the hash space in 2
379 */
380 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
381 h |= (k1 + 2048) << 16;
382 else
383 h |= (k0 + 2048) << 16;
384
385 return h;
386 }
387
388 /* Fills an L2 entry structure from the SoC registers */
389 static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
390 {
391 pr_debug("In %s valid?\n", __func__);
392 e->valid = !!(r[2] & BIT(31));
393 if (!e->valid)
394 return;
395
396 pr_debug("In %s is valid\n", __func__);
397 e->is_ip_mc = false;
398 e->is_ipv6_mc = false;
399
400 /* TODO: Is there not a function to copy directly MAC memory? */
401 e->mac[0] = (r[0] >> 24);
402 e->mac[1] = (r[0] >> 16);
403 e->mac[2] = (r[0] >> 8);
404 e->mac[3] = r[0];
405 e->mac[4] = (r[1] >> 24);
406 e->mac[5] = (r[1] >> 16);
407
408 e->next_hop = !!(r[2] & BIT(12));
409 e->rvid = r[1] & 0xfff;
410
411 /* Is it a unicast entry? check multicast bit */
412 if (!(e->mac[0] & 1)) {
413 e->type = L2_UNICAST;
414 e->is_static = !!(r[2] & BIT(14));
415 e->port = (r[2] >> 20) & 0x3ff;
416 /* Check for trunk port */
417 if (r[2] & BIT(30)) {
418 e->is_trunk = true;
419 e->stack_dev = (e->port >> 9) & 1;
420 e->trunk = e->port & 0x3f;
421 } else {
422 e->is_trunk = false;
423 e->stack_dev = (e->port >> 6) & 0xf;
424 e->port = e->port & 0x3f;
425 }
426
427 e->block_da = !!(r[2] & BIT(15));
428 e->block_sa = !!(r[2] & BIT(16));
429 e->suspended = !!(r[2] & BIT(13));
430 e->age = (r[2] >> 17) & 3;
431 e->valid = true;
432 /* the UC_VID field in hardware is used for the VID or for the route id */
433 if (e->next_hop) {
434 e->nh_route_id = r[2] & 0x7ff;
435 e->vid = 0;
436 } else {
437 e->vid = r[2] & 0xfff;
438 e->nh_route_id = 0;
439 }
440 } else {
441 e->valid = true;
442 e->type = L2_MULTICAST;
443 e->mc_portmask_index = (r[2] >> 16) & 0x3ff;
444 }
445 }
446
447 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
448 static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
449 {
450 u32 port;
451
452 if (!e->valid) {
453 r[0] = r[1] = r[2] = 0;
454 return;
455 }
456
457 r[2] = BIT(31); /* Set valid bit */
458
459 r[0] = ((u32)e->mac[0]) << 24 |
460 ((u32)e->mac[1]) << 16 |
461 ((u32)e->mac[2]) << 8 |
462 ((u32)e->mac[3]);
463 r[1] = ((u32)e->mac[4]) << 24 |
464 ((u32)e->mac[5]) << 16;
465
466 r[2] |= e->next_hop ? BIT(12) : 0;
467
468 if (e->type == L2_UNICAST) {
469 r[2] |= e->is_static ? BIT(14) : 0;
470 r[1] |= e->rvid & 0xfff;
471 r[2] |= (e->port & 0x3ff) << 20;
472 if (e->is_trunk) {
473 r[2] |= BIT(30);
474 port = e->stack_dev << 9 | (e->port & 0x3f);
475 } else {
476 port = (e->stack_dev & 0xf) << 6;
477 port |= e->port & 0x3f;
478 }
479 r[2] |= port << 20;
480 r[2] |= e->block_da ? BIT(15) : 0;
481 r[2] |= e->block_sa ? BIT(17) : 0;
482 r[2] |= e->suspended ? BIT(13) : 0;
483 r[2] |= (e->age & 0x3) << 17;
484 /* the UC_VID field in hardware is used for the VID or for the route id */
485 if (e->next_hop)
486 r[2] |= e->nh_route_id & 0x7ff;
487 else
488 r[2] |= e->vid & 0xfff;
489 } else { /* L2_MULTICAST */
490 r[2] |= (e->mc_portmask_index & 0x3ff) << 16;
491 r[2] |= e->mc_mac_index & 0x7ff;
492 }
493 }
494
495 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
496 * hash is the id of the bucket and pos is the position of the entry in that bucket
497 * The data read from the SoC is filled into rtl838x_l2_entry
498 */
499 static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
500 {
501 u32 r[3];
502 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
503 u32 idx;
504 u64 mac;
505 u64 seed;
506
507 pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos);
508
509 /* On the RTL93xx, 2 different hash algorithms are used making it a
510 * total of 8 buckets that need to be searched, 4 for each hash-half
511 * Use second hash space when bucket is between 4 and 8
512 */
513 if (pos >= 4) {
514 pos -= 4;
515 hash >>= 16;
516 } else {
517 hash &= 0xffff;
518 }
519
520 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
521 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos);
522
523 rtl_table_read(q, idx);
524 for (int i = 0; i < 3; i++)
525 r[i] = sw_r32(rtl_table_data(q, i));
526
527 rtl_table_release(q);
528
529 rtl930x_fill_l2_entry(r, e);
530
531 pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop);
532 if (!e->valid)
533 return 0;
534
535 mac = ((u64)e->mac[0]) << 40 |
536 ((u64)e->mac[1]) << 32 |
537 ((u64)e->mac[2]) << 24 |
538 ((u64)e->mac[3]) << 16 |
539 ((u64)e->mac[4]) << 8 |
540 ((u64)e->mac[5]);
541
542 seed = rtl930x_l2_hash_seed(mac, e->rvid);
543 pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed);
544
545 /* return vid with concatenated mac as unique id */
546 return seed;
547 }
548
549 static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
550 {
551 u32 r[3];
552 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
553 u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
554
555 pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
556 pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
557 e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
558
559 rtl930x_fill_l2_row(r, e);
560
561 for (int i = 0; i < 3; i++)
562 sw_w32(r[i], rtl_table_data(q, i));
563
564 rtl_table_write(q, idx);
565 rtl_table_release(q);
566 }
567
568 static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e)
569 {
570 u32 r[3];
571 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1);
572
573 rtl_table_read(q, idx);
574 for (int i = 0; i < 3; i++)
575 r[i] = sw_r32(rtl_table_data(q, i));
576
577 rtl_table_release(q);
578
579 rtl930x_fill_l2_entry(r, e);
580 if (!e->valid)
581 return 0;
582
583 /* return mac with concatenated vid as unique id */
584 return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid;
585 }
586
587 static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e)
588 {
589 u32 r[3];
590 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); /* Access L2 Table 1 */
591
592 rtl930x_fill_l2_row(r, e);
593
594 for (int i = 0; i < 3; i++)
595 sw_w32(r[i], rtl_table_data(q, i));
596
597 rtl_table_write(q, idx);
598 rtl_table_release(q);
599 }
600
601 static u64 rtl930x_read_mcast_pmask(int idx)
602 {
603 u32 portmask;
604 /* Read MC_PORTMASK (2) via register RTL9300_TBL_L2 */
605 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
606
607 rtl_table_read(q, idx);
608 portmask = sw_r32(rtl_table_data(q, 0));
609 portmask >>= 3;
610 rtl_table_release(q);
611
612 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, portmask);
613
614 return portmask;
615 }
616
617 static void rtl930x_write_mcast_pmask(int idx, u64 portmask)
618 {
619 u32 pm = portmask;
620
621 /* Access MC_PORTMASK (2) via register RTL9300_TBL_L2 */
622 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
623
624 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm);
625 pm <<= 3;
626 sw_w32(pm, rtl_table_data(q, 0));
627 rtl_table_write(q, idx);
628 rtl_table_release(q);
629 }
630
631 u64 rtl930x_traffic_get(int source)
632 {
633 u32 v;
634 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
635
636 rtl_table_read(r, source);
637 v = sw_r32(rtl_table_data(r, 0));
638 rtl_table_release(r);
639 v = v >> 3;
640
641 return v;
642 }
643
644 /* Enable traffic between a source port and a destination port matrix */
645 void rtl930x_traffic_set(int source, u64 dest_matrix)
646 {
647 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
648
649 sw_w32((dest_matrix << 3), rtl_table_data(r, 0));
650 rtl_table_write(r, source);
651 rtl_table_release(r);
652 }
653
654 void rtl930x_traffic_enable(int source, int dest)
655 {
656 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
657 rtl_table_read(r, source);
658 sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
659 rtl_table_write(r, source);
660 rtl_table_release(r);
661 }
662
663 void rtl930x_traffic_disable(int source, int dest)
664 {
665 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
666 rtl_table_read(r, source);
667 sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
668 rtl_table_write(r, source);
669 rtl_table_release(r);
670 }
671
672 void rtl9300_dump_debug(void)
673 {
674 u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0;
675
676 for (int i = 0; i < 10; i ++) {
677 pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
678 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
679 sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
680 r += 32;
681 }
682 pr_info("# %08x %08x %08x %08x %08x\n",
683 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));
684 rtl930x_print_matrix();
685 pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
686 sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)
687
688 );
689 }
690
691 irqreturn_t rtl930x_switch_irq(int irq, void *dev_id)
692 {
693 struct dsa_switch *ds = dev_id;
694 u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG);
695 u32 link;
696
697 /* Clear status */
698 sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG);
699
700 for (int i = 0; i < 28; i++) {
701 if (ports & BIT(i)) {
702 /* Read the register twice because of issues with latency at least
703 * with the external RTL8226 PHY on the XGS1210
704 */
705 link = sw_r32(RTL930X_MAC_LINK_STS);
706 link = sw_r32(RTL930X_MAC_LINK_STS);
707 if (link & BIT(i))
708 dsa_port_phylink_mac_change(ds, i, true);
709 else
710 dsa_port_phylink_mac_change(ds, i, false);
711 }
712 }
713
714 return IRQ_HANDLED;
715 }
716
717 int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val)
718 {
719 u32 v;
720 int err = 0;
721
722 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, val);
723
724 if (port > 63 || page > 4095 || reg > 31)
725 return -ENOTSUPP;
726
727 val &= 0xffff;
728 mutex_lock(&smi_lock);
729
730 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
731 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
732 v = reg << 20 | page << 3 | 0x1f << 15 | BIT(2) | BIT(0);
733 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
734
735 do {
736 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
737 } while (v & 0x1);
738
739 if (v & 0x2)
740 err = -EIO;
741
742 mutex_unlock(&smi_lock);
743
744 return err;
745 }
746
747 int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
748 {
749 u32 v;
750 int err = 0;
751
752 if (port > 63 || page > 4095 || reg > 31)
753 return -ENOTSUPP;
754
755 mutex_lock(&smi_lock);
756
757 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
758 v = reg << 20 | page << 3 | 0x1f << 15 | 1;
759 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
760
761 do {
762 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
763 } while ( v & 0x1);
764
765 if (v & BIT(25)) {
766 pr_debug("Error reading phy %d, register %d\n", port, reg);
767 err = -EIO;
768 }
769 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
770
771 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val);
772
773 mutex_unlock(&smi_lock);
774
775 return err;
776 }
777
778 /* Write to an mmd register of the PHY */
779 int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
780 {
781 int err = 0;
782 u32 v;
783
784 mutex_lock(&smi_lock);
785
786 /* Set PHY to access */
787 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
788
789 /* Set data to write */
790 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
791
792 /* Set MMD device number and register to write to */
793 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
794
795 v = BIT(2) | BIT(1) | BIT(0); /* WRITE | MMD-access | EXEC */
796 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
797
798 do {
799 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
800 } while (v & BIT(0));
801
802 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
803 mutex_unlock(&smi_lock);
804 return err;
805 }
806
807 /* Read an mmd register of the PHY */
808 int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
809 {
810 int err = 0;
811 u32 v;
812
813 mutex_lock(&smi_lock);
814
815 /* Set PHY to access */
816 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
817
818 /* Set MMD device number and register to write to */
819 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
820
821 v = BIT(1) | BIT(0); /* MMD-access | EXEC */
822 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
823
824 do {
825 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
826 } while (v & BIT(0));
827 /* There is no error-checking via BIT 25 of v, as it does not seem to be set correctly */
828 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
829 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
830
831 mutex_unlock(&smi_lock);
832
833 return err;
834 }
835
836 /* Calculate both the block 0 and the block 1 hash, and return in
837 * lower and higher word of the return value since only 12 bit of
838 * the hash are significant
839 */
840 u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed)
841 {
842 u32 k0, k1, h1, h2, h;
843
844 k0 = (u32) (((seed >> 55) & 0x1f) ^
845 ((seed >> 44) & 0x7ff) ^
846 ((seed >> 33) & 0x7ff) ^
847 ((seed >> 22) & 0x7ff) ^
848 ((seed >> 11) & 0x7ff) ^
849 (seed & 0x7ff));
850
851 h1 = (seed >> 11) & 0x7ff;
852 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
853
854 h2 = (seed >> 33) & 0x7ff;
855 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x3f);
856
857 k1 = (u32) (((seed << 55) & 0x1f) ^
858 ((seed >> 44) & 0x7ff) ^
859 h2 ^
860 ((seed >> 22) & 0x7ff) ^
861 h1 ^
862 (seed & 0x7ff));
863
864 /* Algorithm choice for block 0 */
865 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
866 h = k1;
867 else
868 h = k0;
869
870 /* Algorithm choice for block 1
871 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
872 * half of hash-space
873 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
874 * divided by 2 to divide the hash space in 2
875 */
876 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
877 h |= (k1 + 2048) << 16;
878 else
879 h |= (k0 + 2048) << 16;
880
881 return h;
882 }
883
884 /* Enables or disables the EEE/EEEP capability of a port */
885 void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
886 {
887 u32 v;
888
889 /* This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP */
890 if (port >= 26)
891 return;
892
893 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
894 v = enable ? 0x3f : 0x0;
895
896 /* Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit */
897 sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port));
898
899 /* Set TX/RX EEE state */
900 v = enable ? 0x3 : 0x0;
901 sw_w32(v, RTL930X_EEE_CTRL(port));
902
903 priv->ports[port].eee_enabled = enable;
904 }
905
906 /* Get EEE own capabilities and negotiation result */
907 int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
908 {
909 u32 link, a;
910
911 if (port >= 26)
912 return -ENOTSUPP;
913
914 pr_info("In %s, port %d\n", __func__, port);
915 link = sw_r32(RTL930X_MAC_LINK_STS);
916 link = sw_r32(RTL930X_MAC_LINK_STS);
917 if (!(link & BIT(port)))
918 return 0;
919
920 pr_info("Setting advertised\n");
921 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(10))
922 e->advertised |= ADVERTISED_100baseT_Full;
923
924 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(12))
925 e->advertised |= ADVERTISED_1000baseT_Full;
926
927 if (priv->ports[port].is2G5 && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(13)) {
928 pr_info("ADVERTISING 2.5G EEE\n");
929 e->advertised |= ADVERTISED_2500baseX_Full;
930 }
931
932 if (priv->ports[port].is10G && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(15))
933 e->advertised |= ADVERTISED_10000baseT_Full;
934
935 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
936 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
937 pr_info("Link partner: %08x\n", a);
938 if (a & BIT(port)) {
939 e->lp_advertised = ADVERTISED_100baseT_Full;
940 e->lp_advertised |= ADVERTISED_1000baseT_Full;
941 if (priv->ports[port].is2G5)
942 e->lp_advertised |= ADVERTISED_2500baseX_Full;
943 if (priv->ports[port].is10G)
944 e->lp_advertised |= ADVERTISED_10000baseT_Full;
945 }
946
947 /* Read 2x to clear latched state */
948 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
949 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
950 pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a);
951
952 return 0;
953 }
954
955 static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
956 {
957 pr_info("Setting up EEE, state: %d\n", enable);
958
959 /* Setup EEE on all ports */
960 for (int i = 0; i < priv->cpu_port; i++) {
961 if (priv->ports[i].phy)
962 rtl930x_port_eee_set(priv, i, enable);
963 }
964
965 priv->eee_enabled = enable;
966 }
967 #define HASH_PICK(val, lsb, len) ((val & (((1 << len) - 1) << lsb)) >> lsb)
968
969 static u32 rtl930x_l3_hash4(u32 ip, int algorithm, bool move_dip)
970 {
971 u32 rows[4];
972 u32 hash;
973 u32 s0, s1, pH;
974
975 memset(rows, 0, sizeof(rows));
976
977 rows[0] = HASH_PICK(ip, 27, 5);
978 rows[1] = HASH_PICK(ip, 18, 9);
979 rows[2] = HASH_PICK(ip, 9, 9);
980
981 if (!move_dip)
982 rows[3] = HASH_PICK(ip, 0, 9);
983
984 if (!algorithm) {
985 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3];
986 } else {
987 s0 = rows[0] + rows[1] + rows[2];
988 s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
989 pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
990 hash = pH ^ rows[3];
991 }
992 return hash;
993 }
994
995 static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip)
996 {
997 u32 rows[16];
998 u32 hash;
999 u32 s0, s1, pH;
1000
1001 rows[0] = (HASH_PICK(ip6->s6_addr[0], 6, 2) << 0);
1002 rows[1] = (HASH_PICK(ip6->s6_addr[0], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[1], 5, 3);
1003 rows[2] = (HASH_PICK(ip6->s6_addr[1], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[2], 4, 4);
1004 rows[3] = (HASH_PICK(ip6->s6_addr[2], 0, 4) << 5) | HASH_PICK(ip6->s6_addr[3], 3, 5);
1005 rows[4] = (HASH_PICK(ip6->s6_addr[3], 0, 3) << 6) | HASH_PICK(ip6->s6_addr[4], 2, 6);
1006 rows[5] = (HASH_PICK(ip6->s6_addr[4], 0, 2) << 7) | HASH_PICK(ip6->s6_addr[5], 1, 7);
1007 rows[6] = (HASH_PICK(ip6->s6_addr[5], 0, 1) << 8) | HASH_PICK(ip6->s6_addr[6], 0, 8);
1008 rows[7] = (HASH_PICK(ip6->s6_addr[7], 0, 8) << 1) | HASH_PICK(ip6->s6_addr[8], 7, 1);
1009 rows[8] = (HASH_PICK(ip6->s6_addr[8], 0, 7) << 2) | HASH_PICK(ip6->s6_addr[9], 6, 2);
1010 rows[9] = (HASH_PICK(ip6->s6_addr[9], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[10], 5, 3);
1011 rows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4);
1012 if (!algorithm) {
1013 rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5) |
1014 (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1015 rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) |
1016 (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0);
1017 rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) |
1018 (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0);
1019 if (!move_dip) {
1020 rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) |
1021 (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1022 }
1023 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^
1024 rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^
1025 rows[10] ^ rows[11] ^ rows[12] ^ rows[13] ^ rows[14];
1026 } else {
1027 rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5);
1028 rows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1029 rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) |
1030 HASH_PICK(ip6->s6_addr[13], 2, 6);
1031 rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) |
1032 HASH_PICK(ip6->s6_addr[14], 1, 7);
1033 if (!move_dip) {
1034 rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) |
1035 (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1036 }
1037 s0 = rows[12] + rows[13] + rows[14];
1038 s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
1039 pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
1040 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^
1041 rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^
1042 rows[10] ^ rows[11] ^ pH ^ rows[15];
1043 }
1044 return hash;
1045 }
1046
1047 /* Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table
1048 * We currently only support IPv4 and IPv6 unicast route
1049 */
1050 static void rtl930x_route_read(int idx, struct rtl83xx_route *rt)
1051 {
1052 u32 v, ip4_m;
1053 bool host_route, default_route;
1054 struct in6_addr ip6_m;
1055
1056 /* Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */
1057 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1058
1059 rtl_table_read(r, idx);
1060 /* The table has a size of 11 registers */
1061 rt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31));
1062 if (!rt->attr.valid)
1063 goto out;
1064
1065 rt->attr.type = (sw_r32(rtl_table_data(r, 0)) >> 29) & 0x3;
1066
1067 v = sw_r32(rtl_table_data(r, 10));
1068 host_route = !!(v & BIT(21));
1069 default_route = !!(v & BIT(20));
1070 rt->prefix_len = -1;
1071 pr_info("%s: host route %d, default_route %d\n", __func__, host_route, default_route);
1072
1073 switch (rt->attr.type) {
1074 case 0: /* IPv4 Unicast route */
1075 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1076 ip4_m = sw_r32(rtl_table_data(r, 9));
1077 pr_info("%s: Read ip4 mask: %08x\n", __func__, ip4_m);
1078 rt->prefix_len = host_route ? 32 : -1;
1079 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1080 if (rt->prefix_len < 0)
1081 rt->prefix_len = inet_mask_len(ip4_m);
1082 break;
1083 case 2: /* IPv6 Unicast route */
1084 ipv6_addr_set(&rt->dst_ip6,
1085 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1086 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)));
1087 ipv6_addr_set(&ip6_m,
1088 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)),
1089 sw_r32(rtl_table_data(r, 8)), sw_r32(rtl_table_data(r, 9)));
1090 rt->prefix_len = host_route ? 128 : 0;
1091 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1092 if (rt->prefix_len < 0)
1093 rt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32,
1094 128);
1095 break;
1096 case 1: /* IPv4 Multicast route */
1097 case 3: /* IPv6 Multicast route */
1098 pr_warn("%s: route type not supported\n", __func__);
1099 goto out;
1100 }
1101
1102 rt->attr.hit = !!(v & BIT(22));
1103 rt->attr.action = (v >> 18) & 3;
1104 rt->nh.id = (v >> 7) & 0x7ff;
1105 rt->attr.ttl_dec = !!(v & BIT(6));
1106 rt->attr.ttl_check = !!(v & BIT(5));
1107 rt->attr.dst_null = !!(v & BIT(4));
1108 rt->attr.qos_as = !!(v & BIT(3));
1109 rt->attr.qos_prio = v & 0x7;
1110 pr_info("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1111 pr_info("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1112 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1113 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1114 pr_info("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1115 out:
1116 rtl_table_release(r);
1117 }
1118
1119 static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m)
1120 {
1121 int o, b;
1122 /* Define network mask */
1123 o = prefix_len >> 3;
1124 b = prefix_len & 0x7;
1125 memset(ip6_m->s6_addr, 0xff, o);
1126 ip6_m->s6_addr[o] |= b ? 0xff00 >> b : 0x00;
1127 }
1128
1129 /* Read a host route entry from the table using its index
1130 * We currently only support IPv4 and IPv6 unicast route
1131 */
1132 static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt)
1133 {
1134 u32 v;
1135 /* Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */
1136 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1137
1138 idx = ((idx / 6) * 8) + (idx % 6);
1139
1140 pr_debug("In %s, physical index %d\n", __func__, idx);
1141 rtl_table_read(r, idx);
1142 /* The table has a size of 5 (for UC, 11 for MC) registers */
1143 v = sw_r32(rtl_table_data(r, 0));
1144 rt->attr.valid = !!(v & BIT(31));
1145 if (!rt->attr.valid)
1146 goto out;
1147 rt->attr.type = (v >> 29) & 0x3;
1148 switch (rt->attr.type) {
1149 case 0: /* IPv4 Unicast route */
1150 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1151 break;
1152 case 2: /* IPv6 Unicast route */
1153 ipv6_addr_set(&rt->dst_ip6,
1154 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)),
1155 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0)));
1156 break;
1157 case 1: /* IPv4 Multicast route */
1158 case 3: /* IPv6 Multicast route */
1159 pr_warn("%s: route type not supported\n", __func__);
1160 goto out;
1161 }
1162
1163 rt->attr.hit = !!(v & BIT(20));
1164 rt->attr.dst_null = !!(v & BIT(19));
1165 rt->attr.action = (v >> 17) & 3;
1166 rt->nh.id = (v >> 6) & 0x7ff;
1167 rt->attr.ttl_dec = !!(v & BIT(5));
1168 rt->attr.ttl_check = !!(v & BIT(4));
1169 rt->attr.qos_as = !!(v & BIT(3));
1170 rt->attr.qos_prio = v & 0x7;
1171 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1172 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1173 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1174 rt->attr.dst_null);
1175 pr_debug("%s: Destination: %pI4\n", __func__, &rt->dst_ip);
1176
1177 out:
1178 rtl_table_release(r);
1179 }
1180
1181 /* Write a host route entry from the table using its index
1182 * We currently only support IPv4 and IPv6 unicast route
1183 */
1184 static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt)
1185 {
1186 u32 v;
1187 /* Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */
1188 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1189 /* The table has a size of 5 (for UC, 11 for MC) registers */
1190
1191 idx = ((idx / 6) * 8) + (idx % 6);
1192
1193 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1194 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1195 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1196 rt->attr.dst_null);
1197 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1198
1199 v = BIT(31); /* Entry is valid */
1200 v |= (rt->attr.type & 0x3) << 29;
1201 v |= rt->attr.hit ? BIT(20) : 0;
1202 v |= rt->attr.dst_null ? BIT(19) : 0;
1203 v |= (rt->attr.action & 0x3) << 17;
1204 v |= (rt->nh.id & 0x7ff) << 6;
1205 v |= rt->attr.ttl_dec ? BIT(5) : 0;
1206 v |= rt->attr.ttl_check ? BIT(4) : 0;
1207 v |= rt->attr.qos_as ? BIT(3) : 0;
1208 v |= rt->attr.qos_prio & 0x7;
1209
1210 sw_w32(v, rtl_table_data(r, 0));
1211 switch (rt->attr.type) {
1212 case 0: /* IPv4 Unicast route */
1213 sw_w32(0, rtl_table_data(r, 1));
1214 sw_w32(0, rtl_table_data(r, 2));
1215 sw_w32(0, rtl_table_data(r, 3));
1216 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1217 break;
1218 case 2: /* IPv6 Unicast route */
1219 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1220 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1221 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1222 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1223 break;
1224 case 1: /* IPv4 Multicast route */
1225 case 3: /* IPv6 Multicast route */
1226 pr_warn("%s: route type not supported\n", __func__);
1227 goto out;
1228 }
1229
1230 rtl_table_write(r, idx);
1231
1232 out:
1233 rtl_table_release(r);
1234 }
1235
1236 /* Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes
1237 * using hardware offload.
1238 */
1239 static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt)
1240 {
1241 u32 ip4_m, v;
1242 struct in6_addr ip6_m;
1243
1244 if (rt->attr.type == 1 || rt->attr.type == 3) /* Hardware only supports UC routes */
1245 return -1;
1246
1247 sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL);
1248 if (rt->attr.type) { /* IPv6 */
1249 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1250 for (int i = 0; i < 4; i++)
1251 sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0],
1252 RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2));
1253 } else { /* IPv4 */
1254 ip4_m = inet_make_mask(rt->prefix_len);
1255 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL);
1256 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4);
1257 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 8);
1258 v = rt->dst_ip & ip4_m;
1259 pr_info("%s: searching for %pI4\n", __func__, &v);
1260 sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12);
1261 }
1262
1263 /* Execute CAM lookup in SoC */
1264 sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL);
1265
1266 /* Wait until execute bit clears and result is ready */
1267 do {
1268 v = sw_r32(RTL930X_L3_HW_LU_CTRL);
1269 } while (v & BIT(15));
1270
1271 pr_info("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff);
1272
1273 /* Test if search successful (BIT 14 set) */
1274 if (v & BIT(14))
1275 return v & 0x1ff;
1276
1277 return -1;
1278 }
1279
1280 static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist)
1281 {
1282 int slot_width, algorithm, addr, idx;
1283 u32 hash;
1284 struct rtl83xx_route route_entry;
1285
1286 /* IPv6 entries take up 3 slots */
1287 slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3;
1288
1289 for (int t = 0; t < 2; t++) {
1290 algorithm = (sw_r32(RTL930X_L3_HOST_TBL_CTRL) >> (2 + t)) & 0x1;
1291 hash = rtl930x_l3_hash4(rt->dst_ip, algorithm, false);
1292
1293 pr_debug("%s: table %d, algorithm %d, hash %04x\n", __func__, t, algorithm, hash);
1294
1295 for (int s = 0; s < 6; s += slot_width) {
1296 addr = (t << 12) | ((hash & 0x1ff) << 3) | s;
1297 pr_debug("%s physical address %d\n", __func__, addr);
1298 idx = ((addr / 8) * 6) + (addr % 8);
1299 pr_debug("%s logical address %d\n", __func__, idx);
1300
1301 rtl930x_host_route_read(idx, &route_entry);
1302 pr_debug("%s route valid %d, route dest: %pI4, hit %d\n", __func__,
1303 rt->attr.valid, &rt->dst_ip, rt->attr.hit);
1304 if (!must_exist && rt->attr.valid)
1305 return idx;
1306 if (must_exist && route_entry.dst_ip == rt->dst_ip)
1307 return idx;
1308 }
1309 }
1310
1311 return -1;
1312 }
1313
1314 /* Write a prefix route into the routing table CAM at position idx
1315 * Currently only IPv4 and IPv6 unicast routes are supported
1316 */
1317 static void rtl930x_route_write(int idx, struct rtl83xx_route *rt)
1318 {
1319 u32 v, ip4_m;
1320 struct in6_addr ip6_m;
1321 /* Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */
1322 /* The table has a size of 11 registers (20 for MC) */
1323 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1324
1325 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1326 pr_debug("%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1327 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1328 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1329 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1330
1331 v = rt->attr.valid ? BIT(31) : 0;
1332 v |= (rt->attr.type & 0x3) << 29;
1333 sw_w32(v, rtl_table_data(r, 0));
1334
1335 v = rt->attr.hit ? BIT(22) : 0;
1336 v |= (rt->attr.action & 0x3) << 18;
1337 v |= (rt->nh.id & 0x7ff) << 7;
1338 v |= rt->attr.ttl_dec ? BIT(6) : 0;
1339 v |= rt->attr.ttl_check ? BIT(5) : 0;
1340 v |= rt->attr.dst_null ? BIT(6) : 0;
1341 v |= rt->attr.qos_as ? BIT(6) : 0;
1342 v |= rt->attr.qos_prio & 0x7;
1343 v |= rt->prefix_len == 0 ? BIT(20) : 0; /* set default route bit */
1344
1345 /* set bit mask for entry type always to 0x3 */
1346 sw_w32(0x3 << 29, rtl_table_data(r, 5));
1347
1348 switch (rt->attr.type) {
1349 case 0: /* IPv4 Unicast route */
1350 sw_w32(0, rtl_table_data(r, 1));
1351 sw_w32(0, rtl_table_data(r, 2));
1352 sw_w32(0, rtl_table_data(r, 3));
1353 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1354
1355 v |= rt->prefix_len == 32 ? BIT(21) : 0; /* set host-route bit */
1356 ip4_m = inet_make_mask(rt->prefix_len);
1357 sw_w32(0, rtl_table_data(r, 6));
1358 sw_w32(0, rtl_table_data(r, 7));
1359 sw_w32(0, rtl_table_data(r, 8));
1360 sw_w32(ip4_m, rtl_table_data(r, 9));
1361 break;
1362 case 2: /* IPv6 Unicast route */
1363 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1364 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1365 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1366 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1367
1368 v |= rt->prefix_len == 128 ? BIT(21) : 0; /* set host-route bit */
1369
1370 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1371
1372 sw_w32(ip6_m.s6_addr32[0], rtl_table_data(r, 6));
1373 sw_w32(ip6_m.s6_addr32[1], rtl_table_data(r, 7));
1374 sw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8));
1375 sw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9));
1376 break;
1377 case 1: /* IPv4 Multicast route */
1378 case 3: /* IPv6 Multicast route */
1379 pr_warn("%s: route type not supported\n", __func__);
1380 rtl_table_release(r);
1381 return;
1382 }
1383 sw_w32(v, rtl_table_data(r, 10));
1384
1385 pr_debug("%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", __func__,
1386 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1387 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
1388 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)),
1389 sw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10)));
1390
1391 rtl_table_write(r, idx);
1392 rtl_table_release(r);
1393 }
1394
1395
1396 /* Get the destination MAC and L3 egress interface ID of a nexthop entry from
1397 * the SoC's L3_NEXTHOP table
1398 */
1399 static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface)
1400 {
1401 u32 v;
1402 /* Read L3_NEXTHOP table (3) via register RTL9300_TBL_1 */
1403 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1404
1405 rtl_table_read(r, idx);
1406 /* The table has a size of 1 register */
1407 v = sw_r32(rtl_table_data(r, 0));
1408 rtl_table_release(r);
1409
1410 *dmac_id = (v >> 7) & 0x7fff;
1411 *interface = v & 0x7f;
1412 }
1413
1414 static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu)
1415 {
1416 int i;
1417
1418 for (i = 0; i < MAX_INTF_MTUS; i++) {
1419 if (mtu == priv->intf_mtus[i])
1420 break;
1421 }
1422 if (i >= MAX_INTF_MTUS || !priv->intf_mtu_count[i]) {
1423 pr_err("%s: No MTU slot found for MTU: %d\n", __func__, mtu);
1424 return -EINVAL;
1425 }
1426
1427 priv->intf_mtu_count[i]--;
1428 }
1429
1430 static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu)
1431 {
1432 int i, free_mtu;
1433 int mtu_id;
1434
1435 /* Try to find an existing mtu-value or a free slot */
1436 free_mtu = MAX_INTF_MTUS;
1437 for (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) {
1438 if ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS))
1439 free_mtu = i;
1440 }
1441 i = (i < MAX_INTF_MTUS) ? i : free_mtu;
1442 if (i < MAX_INTF_MTUS) {
1443 mtu_id = i;
1444 } else {
1445 pr_err("%s: No free MTU slot available!\n", __func__);
1446 return -EINVAL;
1447 }
1448
1449 priv->intf_mtus[i] = mtu;
1450 pr_info("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i);
1451 /* Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots */
1452 sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1453 RTL930X_L3_IP_MTU_CTRL(i));
1454 sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1455 RTL930X_L3_IP6_MTU_CTRL(i));
1456
1457 priv->intf_mtu_count[i]++;
1458
1459 return mtu_id;
1460 }
1461
1462 /* Creates an interface for a route by setting up the HW tables in the SoC */
1463 static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)
1464 {
1465 int i, intf_id, mtu_id;
1466 /* number of MTU-values < 16384 */
1467
1468 /* Use the same IPv6 mtu as the ip4 mtu for this route if unset */
1469 intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu;
1470
1471 mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu);
1472 pr_info("%s: added mtu %d with mtu-id %d\n", __func__, intf->ip4_mtu, mtu_id);
1473 if (mtu_id < 0)
1474 return -ENOSPC;
1475 intf->ip4_mtu_id = mtu_id;
1476 intf->ip6_mtu_id = mtu_id;
1477
1478 for (i = 0; i < MAX_INTERFACES; i++) {
1479 if (!priv->interfaces[i])
1480 break;
1481 }
1482 if (i >= MAX_INTERFACES) {
1483 pr_err("%s: cannot find free interface entry\n", __func__);
1484 return -EINVAL;
1485 }
1486 intf_id = i;
1487 priv->interfaces[i] = kzalloc(sizeof(struct rtl838x_l3_intf), GFP_KERNEL);
1488 if (!priv->interfaces[i]) {
1489 pr_err("%s: no memory to allocate new interface\n", __func__);
1490 return -ENOMEM;
1491 }
1492 }
1493
1494 /* Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's
1495 * L3_NEXTHOP table. The nexthop entry is identified by idx.
1496 * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are
1497 * 0x7ffe: TRAP2CPU
1498 * 0x7ffd: TRAP2MASTERCPU
1499 * 0x7fff: DMAC_ID_DROP
1500 */
1501 static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface)
1502 {
1503 /* Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 */
1504 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1505
1506 pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n",
1507 __func__, idx, dmac_id, interface);
1508 sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0));
1509
1510 pr_info("%s: %08x\n", __func__, sw_r32(rtl_table_data(r,0)));
1511 rtl_table_write(r, idx);
1512 rtl_table_release(r);
1513 }
1514
1515 static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
1516 {
1517 int block = index / PIE_BLOCK_SIZE;
1518
1519 sw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL);
1520 }
1521
1522 /* Reads the intermediate representation of the templated match-fields of the
1523 * PIE rule in the pie_rule structure and fills in the raw data fields in the
1524 * raw register space r[].
1525 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1526 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
1527 * on all SoCs
1528 * On the RTL9300 the mask fields are not word-aligend!
1529 */
1530 static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1531 {
1532 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1533 enum template_field_id field_type = t[i];
1534 u16 data = 0, data_m = 0;
1535
1536 switch (field_type) {
1537 case TEMPLATE_FIELD_SPM0:
1538 data = pr->spm;
1539 data_m = pr->spm_m;
1540 break;
1541 case TEMPLATE_FIELD_SPM1:
1542 data = pr->spm >> 16;
1543 data_m = pr->spm_m >> 16;
1544 break;
1545 case TEMPLATE_FIELD_OTAG:
1546 data = pr->otag;
1547 data_m = pr->otag_m;
1548 break;
1549 case TEMPLATE_FIELD_SMAC0:
1550 data = pr->smac[4];
1551 data = (data << 8) | pr->smac[5];
1552 data_m = pr->smac_m[4];
1553 data_m = (data_m << 8) | pr->smac_m[5];
1554 break;
1555 case TEMPLATE_FIELD_SMAC1:
1556 data = pr->smac[2];
1557 data = (data << 8) | pr->smac[3];
1558 data_m = pr->smac_m[2];
1559 data_m = (data_m << 8) | pr->smac_m[3];
1560 break;
1561 case TEMPLATE_FIELD_SMAC2:
1562 data = pr->smac[0];
1563 data = (data << 8) | pr->smac[1];
1564 data_m = pr->smac_m[0];
1565 data_m = (data_m << 8) | pr->smac_m[1];
1566 break;
1567 case TEMPLATE_FIELD_DMAC0:
1568 data = pr->dmac[4];
1569 data = (data << 8) | pr->dmac[5];
1570 data_m = pr->dmac_m[4];
1571 data_m = (data_m << 8) | pr->dmac_m[5];
1572 break;
1573 case TEMPLATE_FIELD_DMAC1:
1574 data = pr->dmac[2];
1575 data = (data << 8) | pr->dmac[3];
1576 data_m = pr->dmac_m[2];
1577 data_m = (data_m << 8) | pr->dmac_m[3];
1578 break;
1579 case TEMPLATE_FIELD_DMAC2:
1580 data = pr->dmac[0];
1581 data = (data << 8) | pr->dmac[1];
1582 data_m = pr->dmac_m[0];
1583 data_m = (data_m << 8) | pr->dmac_m[1];
1584 break;
1585 case TEMPLATE_FIELD_ETHERTYPE:
1586 data = pr->ethertype;
1587 data_m = pr->ethertype_m;
1588 break;
1589 case TEMPLATE_FIELD_ITAG:
1590 data = pr->itag;
1591 data_m = pr->itag_m;
1592 break;
1593 case TEMPLATE_FIELD_SIP0:
1594 if (pr->is_ipv6) {
1595 data = pr->sip6.s6_addr16[7];
1596 data_m = pr->sip6_m.s6_addr16[7];
1597 } else {
1598 data = pr->sip;
1599 data_m = pr->sip_m;
1600 }
1601 break;
1602 case TEMPLATE_FIELD_SIP1:
1603 if (pr->is_ipv6) {
1604 data = pr->sip6.s6_addr16[6];
1605 data_m = pr->sip6_m.s6_addr16[6];
1606 } else {
1607 data = pr->sip >> 16;
1608 data_m = pr->sip_m >> 16;
1609 }
1610 break;
1611 case TEMPLATE_FIELD_SIP2:
1612 case TEMPLATE_FIELD_SIP3:
1613 case TEMPLATE_FIELD_SIP4:
1614 case TEMPLATE_FIELD_SIP5:
1615 case TEMPLATE_FIELD_SIP6:
1616 case TEMPLATE_FIELD_SIP7:
1617 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1618 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1619 break;
1620 case TEMPLATE_FIELD_DIP0:
1621 if (pr->is_ipv6) {
1622 data = pr->dip6.s6_addr16[7];
1623 data_m = pr->dip6_m.s6_addr16[7];
1624 } else {
1625 data = pr->dip;
1626 data_m = pr->dip_m;
1627 }
1628 break;
1629 case TEMPLATE_FIELD_DIP1:
1630 if (pr->is_ipv6) {
1631 data = pr->dip6.s6_addr16[6];
1632 data_m = pr->dip6_m.s6_addr16[6];
1633 } else {
1634 data = pr->dip >> 16;
1635 data_m = pr->dip_m >> 16;
1636 }
1637 break;
1638 case TEMPLATE_FIELD_DIP2:
1639 case TEMPLATE_FIELD_DIP3:
1640 case TEMPLATE_FIELD_DIP4:
1641 case TEMPLATE_FIELD_DIP5:
1642 case TEMPLATE_FIELD_DIP6:
1643 case TEMPLATE_FIELD_DIP7:
1644 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1645 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1646 break;
1647 case TEMPLATE_FIELD_IP_TOS_PROTO:
1648 data = pr->tos_proto;
1649 data_m = pr->tos_proto_m;
1650 break;
1651 case TEMPLATE_FIELD_L4_SPORT:
1652 data = pr->sport;
1653 data_m = pr->sport_m;
1654 break;
1655 case TEMPLATE_FIELD_L4_DPORT:
1656 data = pr->dport;
1657 data_m = pr->dport_m;
1658 break;
1659 case TEMPLATE_FIELD_DSAP_SSAP:
1660 data = pr->dsap_ssap;
1661 data_m = pr->dsap_ssap_m;
1662 break;
1663 case TEMPLATE_FIELD_TCP_INFO:
1664 data = pr->tcp_info;
1665 data_m = pr->tcp_info_m;
1666 break;
1667 case TEMPLATE_FIELD_RANGE_CHK:
1668 pr_warn("Warning: TEMPLATE_FIELD_RANGE_CHK: not configured\n");
1669 break;
1670 default:
1671 pr_info("%s: unknown field %d\n", __func__, field_type);
1672 }
1673
1674 /* On the RTL9300, the mask fields are not word aligned! */
1675 if (!(i % 2)) {
1676 r[5 - i / 2] = data;
1677 r[12 - i / 2] |= ((u32)data_m << 8);
1678 } else {
1679 r[5 - i / 2] |= ((u32)data) << 16;
1680 r[12 - i / 2] |= ((u32)data_m) << 24;
1681 r[11 - i / 2] |= ((u32)data_m) >> 8;
1682 }
1683 }
1684 }
1685
1686 static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1687 {
1688 pr->stacking_port = r[6] & BIT(31);
1689 pr->spn = (r[6] >> 24) & 0x7f;
1690 pr->mgnt_vlan = r[6] & BIT(23);
1691 if (pr->phase == PHASE_IACL)
1692 pr->dmac_hit_sw = r[6] & BIT(22);
1693 else
1694 pr->content_too_deep = r[6] & BIT(22);
1695 pr->not_first_frag = r[6] & BIT(21);
1696 pr->frame_type_l4 = (r[6] >> 18) & 7;
1697 pr->frame_type = (r[6] >> 16) & 3;
1698 pr->otag_fmt = (r[6] >> 15) & 1;
1699 pr->itag_fmt = (r[6] >> 14) & 1;
1700 pr->otag_exist = (r[6] >> 13) & 1;
1701 pr->itag_exist = (r[6] >> 12) & 1;
1702 pr->frame_type_l2 = (r[6] >> 10) & 3;
1703 pr->igr_normal_port = (r[6] >> 9) & 1;
1704 pr->tid = (r[6] >> 8) & 1;
1705
1706 pr->stacking_port_m = r[12] & BIT(7);
1707 pr->spn_m = r[12] & 0x7f;
1708 pr->mgnt_vlan_m = r[13] & BIT(31);
1709 if (pr->phase == PHASE_IACL)
1710 pr->dmac_hit_sw_m = r[13] & BIT(30);
1711 else
1712 pr->content_too_deep_m = r[13] & BIT(30);
1713 pr->not_first_frag_m = r[13] & BIT(29);
1714 pr->frame_type_l4_m = (r[13] >> 26) & 7;
1715 pr->frame_type_m = (r[13] >> 24) & 3;
1716 pr->otag_fmt_m = r[13] & BIT(23);
1717 pr->itag_fmt_m = r[13] & BIT(22);
1718 pr->otag_exist_m = r[13] & BIT(21);
1719 pr->itag_exist_m = r[13] & BIT (20);
1720 pr->frame_type_l2_m = (r[13] >> 18) & 3;
1721 pr->igr_normal_port_m = r[13] & BIT(17);
1722 pr->tid_m = (r[13] >> 16) & 1;
1723
1724 pr->valid = r[13] & BIT(15);
1725 pr->cond_not = r[13] & BIT(14);
1726 pr->cond_and1 = r[13] & BIT(13);
1727 pr->cond_and2 = r[13] & BIT(12);
1728 }
1729
1730 static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1731 {
1732 r[6] = pr->stacking_port ? BIT(31) : 0;
1733 r[6] |= ((u32) (pr->spn & 0x7f)) << 24;
1734 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1735 if (pr->phase == PHASE_IACL)
1736 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1737 else
1738 r[6] |= pr->content_too_deep ? BIT(22) : 0;
1739 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1740 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1741 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1742 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1743 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1744 r[6] |= pr->otag_exist ? BIT(13) : 0;
1745 r[6] |= pr->itag_exist ? BIT(12) : 0;
1746 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1747 r[6] |= pr->igr_normal_port ? BIT(9) : 0;
1748 r[6] |= ((u32) (pr->tid & 0x1)) << 8;
1749
1750 r[12] |= pr->stacking_port_m ? BIT(7) : 0;
1751 r[12] |= (u32) (pr->spn_m & 0x7f);
1752 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1753 if (pr->phase == PHASE_IACL)
1754 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1755 else
1756 r[13] |= pr->content_too_deep_m ? BIT(30) : 0;
1757 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1758 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1759 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1760 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1761 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1762 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1763 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1764 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1765 r[13] |= pr->igr_normal_port_m ? BIT(17) : 0;
1766 r[13] |= ((u32) (pr->tid_m & 0x1)) << 16;
1767
1768 r[13] |= pr->valid ? BIT(15) : 0;
1769 r[13] |= pr->cond_not ? BIT(14) : 0;
1770 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1771 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1772 }
1773
1774 static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr)
1775 {
1776 /* Either drop or forward */
1777 if (pr->drop) {
1778 r[14] |= BIT(24) | BIT(25) | BIT(26); /* Do Green, Yellow and Red drops */
1779 /* Actually DROP, not PERMIT in Green / Yellow / Red */
1780 r[14] |= BIT(23) | BIT(22) | BIT(20);
1781 } else {
1782 r[14] |= pr->fwd_sel ? BIT(27) : 0;
1783 r[14] |= pr->fwd_act << 18;
1784 r[14] |= BIT(14); /* We overwrite any drop */
1785 }
1786 if (pr->phase == PHASE_VACL)
1787 r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0;
1788 r[13] |= pr->bypass_sel ? BIT(5) : 0;
1789 r[13] |= pr->nopri_sel ? BIT(4) : 0;
1790 r[13] |= pr->tagst_sel ? BIT(3) : 0;
1791 r[13] |= pr->ovid_sel ? BIT(1) : 0;
1792 r[14] |= pr->ivid_sel ? BIT(31) : 0;
1793 r[14] |= pr->meter_sel ? BIT(30) : 0;
1794 r[14] |= pr->mir_sel ? BIT(29) : 0;
1795 r[14] |= pr->log_sel ? BIT(28) : 0;
1796
1797 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 3;
1798 r[15] |= pr->log_octets ? BIT(31) : 0;
1799 r[15] |= (u32)(pr->meter_data) << 23;
1800
1801 r[15] |= ((u32)(pr->ivid_act) << 21) & 0x3;
1802 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1803 r[16] |= ((u32)(pr->ovid_act) << 30) & 0x3;
1804 r[16] |= ((u32)(pr->ovid_data) & 0xfff) << 16;
1805 r[16] |= (pr->mir_data & 0x3) << 6;
1806 r[17] |= ((u32)(pr->tagst_data) & 0xf) << 28;
1807 r[17] |= ((u32)(pr->nopri_data) & 0x7) << 25;
1808 r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;
1809 }
1810
1811 void rtl930x_pie_rule_dump_raw(u32 r[])
1812 {
1813 pr_info("Raw IACL table entry:\n");
1814 pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1815 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
1816 pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1817 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
1818 pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
1819 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1820 pr_info("Fixed : %06x\n", r[6] >> 8);
1821 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1822 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1823 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1824 (r[11] << 24) | (r[12] >> 8));
1825 pr_info("R[13]: %08x\n", r[13]);
1826 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1827 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1828 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1829 }
1830
1831 static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1832 {
1833 /* Access IACL table (2) via register 0 */
1834 struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2);
1835 u32 r[19];
1836 int block = idx / PIE_BLOCK_SIZE;
1837 u32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block));
1838
1839 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1840
1841 for (int i = 0; i < 19; i++)
1842 r[i] = 0;
1843
1844 if (!pr->valid) {
1845 rtl_table_write(q, idx);
1846 rtl_table_release(q);
1847 return 0;
1848 }
1849 rtl930x_write_pie_fixed_fields(r, pr);
1850
1851 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
1852 rtl930x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);
1853
1854 rtl930x_write_pie_action(r, pr);
1855
1856 /* rtl930x_pie_rule_dump_raw(r); */
1857
1858 for (int i = 0; i < 19; i++)
1859 sw_w32(r[i], rtl_table_data(q, i));
1860
1861 rtl_table_write(q, idx);
1862 rtl_table_release(q);
1863
1864 return 0;
1865 }
1866
1867 static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type)
1868 {
1869 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1870 enum template_field_id ft = fixed_templates[t][i];
1871 if (field_type == ft)
1872 return true;
1873 }
1874
1875 return false;
1876 }
1877
1878 /* Verify that the rule pr is compatible with a given template t in block block
1879 * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
1880 * depend on the SoC
1881 */
1882 static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv,
1883 struct pie_rule *pr, int t, int block)
1884 {
1885 int i;
1886
1887 if (!pr->is_ipv6 && pr->sip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1888 return -1;
1889
1890 if (!pr->is_ipv6 && pr->dip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1891 return -1;
1892
1893 if (pr->is_ipv6) {
1894 if ((pr->sip6_m.s6_addr32[0] ||
1895 pr->sip6_m.s6_addr32[1] ||
1896 pr->sip6_m.s6_addr32[2] ||
1897 pr->sip6_m.s6_addr32[3]) &&
1898 !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1899 return -1;
1900 if ((pr->dip6_m.s6_addr32[0] ||
1901 pr->dip6_m.s6_addr32[1] ||
1902 pr->dip6_m.s6_addr32[2] ||
1903 pr->dip6_m.s6_addr32[3]) &&
1904 !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1905 return -1;
1906 }
1907
1908 if (ether_addr_to_u64(pr->smac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1909 return -1;
1910
1911 if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1912 return -1;
1913
1914 /* TODO: Check more */
1915
1916 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1917
1918 if (i >= PIE_BLOCK_SIZE)
1919 return -1;
1920
1921 return i + PIE_BLOCK_SIZE * block;
1922 }
1923
1924 static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1925 {
1926 int idx, block, j, t;
1927 int min_block = 0;
1928 int max_block = priv->n_pie_blocks / 2;
1929
1930 if (pr->is_egress) {
1931 min_block = max_block;
1932 max_block = priv->n_pie_blocks;
1933 }
1934 pr_debug("In %s\n", __func__);
1935
1936 mutex_lock(&priv->pie_mutex);
1937
1938 for (block = min_block; block < max_block; block++) {
1939 for (j = 0; j < 2; j++) {
1940 t = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
1941 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1942 pr_debug("%s: %08x\n",
1943 __func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)));
1944 idx = rtl930x_pie_verify_template(priv, pr, t, block);
1945 if (idx >= 0)
1946 break;
1947 }
1948 if (j < 2)
1949 break;
1950 }
1951
1952 if (block >= priv->n_pie_blocks) {
1953 mutex_unlock(&priv->pie_mutex);
1954 return -EOPNOTSUPP;
1955 }
1956
1957 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1958 set_bit(idx, priv->pie_use_bm);
1959
1960 pr->valid = true;
1961 pr->tid = j; /* Mapped to template number */
1962 pr->tid_m = 0x1;
1963 pr->id = idx;
1964
1965 rtl930x_pie_lookup_enable(priv, idx);
1966 rtl930x_pie_rule_write(priv, idx, pr);
1967
1968 mutex_unlock(&priv->pie_mutex);
1969 return 0;
1970 }
1971
1972 /* Delete a range of Packet Inspection Engine rules */
1973 static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
1974 {
1975 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
1976
1977 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
1978 mutex_lock(&priv->reg_mutex);
1979
1980 /* Write from-to and execute bit into control register */
1981 sw_w32(v, RTL930X_PIE_CLR_CTRL);
1982
1983 /* Wait until command has completed */
1984 do {
1985 } while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0));
1986
1987 mutex_unlock(&priv->reg_mutex);
1988 return 0;
1989 }
1990
1991 static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1992 {
1993 int idx = pr->id;
1994
1995 rtl930x_pie_rule_del(priv, idx, idx);
1996 clear_bit(idx, priv->pie_use_bm);
1997 }
1998
1999 static void rtl930x_pie_init(struct rtl838x_switch_priv *priv)
2000 {
2001 u32 template_selectors;
2002
2003 mutex_init(&priv->pie_mutex);
2004
2005 pr_info("%s\n", __func__);
2006 /* Enable ACL lookup on all ports, including CPU_PORT */
2007 for (int i = 0; i <= priv->cpu_port; i++)
2008 sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i));
2009
2010 /* Include IPG in metering */
2011 sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL);
2012
2013 /* Delete all present rules, block size is 128 on all SoC families */
2014 rtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);
2015
2016 /* Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) */
2017 sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL);
2018
2019 /* Enable predefined templates 0, 1 for first quarter of all blocks */
2020 template_selectors = 0 | (1 << 4);
2021 for (int i = 0; i < priv->n_pie_blocks / 4; i++)
2022 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2023
2024 /* Enable predefined templates 2, 3 for second quarter of all blocks */
2025 template_selectors = 2 | (3 << 4);
2026 for (int i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)
2027 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2028
2029 /* Enable predefined templates 0, 1 for third half of all blocks */
2030 template_selectors = 0 | (1 << 4);
2031 for (int i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)
2032 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2033
2034 /* Enable predefined templates 2, 3 for fourth quater of all blocks */
2035 template_selectors = 2 | (3 << 4);
2036 for (int i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
2037 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2038
2039 }
2040
2041 /* Sets up an egress interface for L3 actions
2042 * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are:
2043 * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU
2044 * 6: HARDDROP
2045 * idx is the index in the HW interface table: idx < 0x80
2046 */
2047 static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf)
2048 {
2049 u32 u, v;
2050 /* Read L3_EGR_INTF table (4) via register RTL9300_TBL_1 */
2051 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4);
2052
2053 /* The table has 2 registers */
2054 u = (intf->vid & 0xfff) << 9;
2055 u |= (intf->smac_idx & 0x3f) << 3;
2056 u |= (intf->ip4_mtu_id & 0x7);
2057
2058 v = (intf->ip6_mtu_id & 0x7) << 28;
2059 v |= (intf->ttl_scope & 0xff) << 20;
2060 v |= (intf->hl_scope & 0xff) << 12;
2061 v |= (intf->ip4_icmp_redirect & 0x7) << 9;
2062 v |= (intf->ip6_icmp_redirect & 0x7)<< 6;
2063 v |= (intf->ip4_pbr_icmp_redirect & 0x7) << 3;
2064 v |= (intf->ip6_pbr_icmp_redirect & 0x7);
2065
2066 sw_w32(u, rtl_table_data(r, 0));
2067 sw_w32(v, rtl_table_data(r, 1));
2068
2069 pr_info("%s writing to index %d: %08x %08x\n", __func__, idx, u, v);
2070 rtl_table_write(r, idx & 0x7f);
2071 rtl_table_release(r);
2072 }
2073
2074 /* Reads a MAC entry for L3 termination as entry point for routing
2075 * from the hardware table
2076 * idx is the index into the L3_ROUTER_MAC table
2077 */
2078 static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2079 {
2080 u32 v, w;
2081 /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */
2082 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2083
2084 rtl_table_read(r, idx);
2085 /* The table has a size of 7 registers, 64 entries */
2086 v = sw_r32(rtl_table_data(r, 0));
2087 w = sw_r32(rtl_table_data(r, 3));
2088 m->valid = !!(v & BIT(20));
2089 if (!m->valid)
2090 goto out;
2091
2092 m->p_type = !!(v & BIT(19));
2093 m->p_id = (v >> 13) & 0x3f; /* trunk id of port */
2094 m->vid = v & 0xfff;
2095 m->vid_mask = w & 0xfff;
2096 m->action = sw_r32(rtl_table_data(r, 6)) & 0x7;
2097 m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL) |
2098 (sw_r32(rtl_table_data(r, 4)));
2099 m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) |
2100 (sw_r32(rtl_table_data(r, 2)));
2101 /* Bits L3_INTF and BMSK_L3_INTF are 0 */
2102
2103 out:
2104 rtl_table_release(r);
2105 }
2106
2107 /* Writes a MAC entry for L3 termination as entry point for routing
2108 * into the hardware table
2109 * idx is the index into the L3_ROUTER_MAC table
2110 */
2111 static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2112 {
2113 u32 v, w;
2114 /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */
2115 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2116
2117 /* The table has a size of 7 registers, 64 entries */
2118 v = BIT(20); /* mac entry valid, port type is 0: individual */
2119 v |= (m->p_id & 0x3f) << 13;
2120 v |= (m->vid & 0xfff); /* Set the interface_id to the vlan id */
2121
2122 w = m->vid_mask;
2123 w |= (m->p_id_mask & 0x3f) << 13;
2124
2125 sw_w32(v, rtl_table_data(r, 0));
2126 sw_w32(w, rtl_table_data(r, 3));
2127
2128 /* Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 */
2129 sw_w32((u32)(m->mac), rtl_table_data(r, 2));
2130 sw_w32(m->mac >> 32, rtl_table_data(r, 1));
2131
2132 /* Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0 */
2133 sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4));
2134 sw_w32((u32)m->mac_mask, rtl_table_data(r, 5));
2135
2136 sw_w32(m->action & 0x7, rtl_table_data(r, 6));
2137
2138 pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx,
2139 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
2140 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
2141 sw_r32(rtl_table_data(r, 6))
2142 );
2143 rtl_table_write(r, idx);
2144 rtl_table_release(r);
2145 }
2146
2147 /* Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets
2148 * from the SoC's L3_EGR_INTF_MAC table
2149 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2150 */
2151 static u64 rtl930x_get_l3_egress_mac(u32 idx)
2152 {
2153 u64 mac;
2154 /* Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */
2155 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2156
2157 rtl_table_read(r, idx);
2158 /* The table has a size of 2 registers */
2159 mac = sw_r32(rtl_table_data(r, 0));
2160 mac <<= 32;
2161 mac |= sw_r32(rtl_table_data(r, 1));
2162 rtl_table_release(r);
2163
2164 return mac;
2165 }
2166
2167 /* Set the Destination-MAC of a route or the Source MAC of an L3 egress interface
2168 * in the SoC's L3_EGR_INTF_MAC table
2169 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2170 */
2171 static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac)
2172 {
2173 /* Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */
2174 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2175
2176 /* The table has a size of 2 registers */
2177 sw_w32(mac >> 32, rtl_table_data(r, 0));
2178 sw_w32(mac, rtl_table_data(r, 1));
2179
2180 pr_debug("%s: setting index %d to %016llx\n", __func__, idx, mac);
2181 rtl_table_write(r, idx);
2182 rtl_table_release(r);
2183 }
2184
2185 /* Configure L3 routing settings of the device:
2186 * - MTUs
2187 * - Egress interface
2188 * - The router's MAC address on which routed packets are expected
2189 * - MAC addresses used as source macs of routed packets
2190 */
2191 int rtl930x_l3_setup(struct rtl838x_switch_priv *priv)
2192 {
2193 /* Setup MTU with id 0 for default interface */
2194 for (int i = 0; i < MAX_INTF_MTUS; i++)
2195 priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0;
2196
2197 priv->intf_mtu_count[0] = 0; /* Needs to stay forever */
2198 priv->intf_mtus[0] = DEFAULT_MTU;
2199 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0));
2200 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0));
2201 priv->intf_mtus[1] = DEFAULT_MTU;
2202 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(0));
2203 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(0));
2204
2205 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(1));
2206 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(1));
2207 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1));
2208 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1));
2209
2210 /* Clear all source port MACs */
2211 for (int i = 0; i < MAX_SMACS; i++)
2212 rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL);
2213
2214 /* Configure the default L3 hash algorithm */
2215 sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 0 = 0 */
2216 sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 1 = 1 */
2217
2218 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2219 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2220 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2221 sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL);
2222 sw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL);
2223 sw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL);
2224 sw_w32_mask(0, 1, RTL930X_L3_IP6MC_ROUTE_CTRL);
2225
2226 sw_w32(0x00002001, RTL930X_L3_IPUC_ROUTE_CTRL);
2227 sw_w32(0x00014581, RTL930X_L3_IP6UC_ROUTE_CTRL);
2228 sw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL);
2229 sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL);
2230
2231 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2232 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2233 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2234
2235 /* Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) */
2236 sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL);
2237 pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL));
2238
2239 /* PORT_ISO_RESTRICT_ROUTE_CTRL? */
2240
2241 /* Do not use prefix route 0 because of HW limitations */
2242 set_bit(0, priv->route_use_bm);
2243
2244 return 0;
2245 }
2246
2247 static u32 rtl930x_packet_cntr_read(int counter)
2248 {
2249 u32 v;
2250
2251 /* Read LOG table (3) via register RTL9300_TBL_0 */
2252 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2253
2254 pr_debug("In %s, id %d\n", __func__, counter);
2255 rtl_table_read(r, counter / 2);
2256
2257 pr_debug("Registers: %08x %08x\n",
2258 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
2259 /* The table has a size of 2 registers */
2260 if (counter % 2)
2261 v = sw_r32(rtl_table_data(r, 0));
2262 else
2263 v = sw_r32(rtl_table_data(r, 1));
2264
2265 rtl_table_release(r);
2266
2267 return v;
2268 }
2269
2270 static void rtl930x_packet_cntr_clear(int counter)
2271 {
2272 /* Access LOG table (3) via register RTL9300_TBL_0 */
2273 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2274
2275 pr_info("In %s, id %d\n", __func__, counter);
2276 /* The table has a size of 2 registers */
2277 if (counter % 2)
2278 sw_w32(0, rtl_table_data(r, 0));
2279 else
2280 sw_w32(0, rtl_table_data(r, 1));
2281
2282 rtl_table_write(r, counter / 2);
2283
2284 rtl_table_release(r);
2285 }
2286
2287 void rtl930x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
2288 {
2289 sw_w32(FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK,
2290 keep_outer ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG) |
2291 FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK,
2292 keep_inner ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG),
2293 RTL930X_VLAN_PORT_TAG_STS_CTRL(port));
2294 }
2295
2296 void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
2297 {
2298 if (type == PBVLAN_TYPE_INNER)
2299 sw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2300 else
2301 sw_w32_mask(0x3 << 14, mode << 14 ,RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2302 }
2303
2304 void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
2305 {
2306 if (type == PBVLAN_TYPE_INNER)
2307 sw_w32_mask(0xfff << 2, pvid << 2, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2308 else
2309 sw_w32_mask(0xfff << 16, pvid << 16, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2310 }
2311
2312 static int rtl930x_set_ageing_time(unsigned long msec)
2313 {
2314 int t = sw_r32(RTL930X_L2_AGE_CTRL);
2315
2316 t &= 0x1FFFFF;
2317 t = (t * 7) / 10;
2318 pr_debug("L2 AGING time: %d sec\n", t);
2319
2320 t = (msec / 100 + 6) / 7;
2321 t = t > 0x1FFFFF ? 0x1FFFFF : t;
2322 sw_w32_mask(0x1FFFFF, t, RTL930X_L2_AGE_CTRL);
2323 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL930X_L2_PORT_AGE_CTRL));
2324
2325 return 0;
2326 }
2327
2328 static void rtl930x_set_igr_filter(int port, enum igr_filter state)
2329 {
2330 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
2331 RTL930X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
2332 }
2333
2334 static void rtl930x_set_egr_filter(int port, enum egr_filter state)
2335 {
2336 sw_w32_mask(0x1 << (port % 0x1D), state << (port % 0x1D),
2337 RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
2338 }
2339
2340 void rtl930x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
2341 {
2342 u32 l3shift = 0;
2343 u32 newmask = 0;
2344
2345 /* TODO: for now we set algoidx to 0 */
2346 algoidx = 0;
2347 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {
2348 l3shift = 4;
2349 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;
2350 }
2351 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {
2352 l3shift = 4;
2353 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;
2354 }
2355 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
2356 l3shift = 4;
2357 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
2358 }
2359 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
2360 l3shift = 4;
2361 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
2362 }
2363
2364 if (l3shift == 4) {
2365 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
2366 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;
2367
2368 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
2369 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;
2370 } else {
2371 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
2372 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;
2373 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
2374 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;
2375 }
2376
2377 sw_w32(newmask << l3shift, RTL930X_TRK_HASH_CTRL + (algoidx << 2));
2378 }
2379
2380 static void rtl930x_led_init(struct rtl838x_switch_priv *priv)
2381 {
2382 struct device_node *node;
2383 u32 pm = 0;
2384
2385 pr_info("%s called\n", __func__);
2386 node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds");
2387 if (!node) {
2388 pr_info("%s No compatible LED node found\n", __func__);
2389 return;
2390 }
2391
2392 for (int i = 0; i < priv->cpu_port; i++) {
2393 int pos = (i << 1) % 32;
2394 u32 set;
2395 u32 v;
2396
2397 sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));
2398 sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));
2399
2400 if (!priv->ports[i].phy)
2401 continue;
2402
2403 v = 0x1;
2404 if (priv->ports[i].is10G)
2405 v = 0x3;
2406 if (priv->ports[i].phy_is_integrated)
2407 v = 0x1;
2408 sw_w32_mask(0x3 << pos, v << pos, RTL930X_LED_PORT_NUM_CTRL(i));
2409
2410 pm |= BIT(i);
2411
2412 set = priv->ports[i].led_set;
2413 sw_w32_mask(0, set << pos, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));
2414 sw_w32_mask(0, set << pos, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));
2415 }
2416
2417 for (int i = 0; i < 4; i++) {
2418 const __be32 *led_set;
2419 char set_name[9];
2420 u32 setlen;
2421 u32 v;
2422
2423 sprintf(set_name, "led_set%d", i);
2424 led_set = of_get_property(node, set_name, &setlen);
2425 if (!led_set || setlen != 16)
2426 break;
2427 v = be32_to_cpup(led_set) << 16 | be32_to_cpup(led_set + 1);
2428 sw_w32(v, RTL930X_LED_SET0_0_CTRL - 4 - i * 8);
2429 v = be32_to_cpup(led_set + 2) << 16 | be32_to_cpup(led_set + 3);
2430 sw_w32(v, RTL930X_LED_SET0_0_CTRL - i * 8);
2431 }
2432
2433 /* Set LED mode to serial (0x1) */
2434 sw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL);
2435
2436 /* Set LED active state */
2437 if (of_property_read_bool(node, "active-low"))
2438 sw_w32_mask(RTL930X_LED_GLB_ACTIVE_LOW, 0, RTL930X_LED_GLB_CTRL);
2439 else
2440 sw_w32_mask(0, RTL930X_LED_GLB_ACTIVE_LOW, RTL930X_LED_GLB_CTRL);
2441
2442 /* Set port type masks */
2443 sw_w32(pm, RTL930X_LED_PORT_COPR_MASK_CTRL);
2444 sw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL);
2445 sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL);
2446
2447 for (int i = 0; i < 24; i++)
2448 pr_info("%s %08x: %08x\n",__func__, 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4));
2449 }
2450
2451 const struct rtl838x_reg rtl930x_reg = {
2452 .mask_port_reg_be = rtl838x_mask_port_reg,
2453 .set_port_reg_be = rtl838x_set_port_reg,
2454 .get_port_reg_be = rtl838x_get_port_reg,
2455 .mask_port_reg_le = rtl838x_mask_port_reg,
2456 .set_port_reg_le = rtl838x_set_port_reg,
2457 .get_port_reg_le = rtl838x_get_port_reg,
2458 .stat_port_rst = RTL930X_STAT_PORT_RST,
2459 .stat_rst = RTL930X_STAT_RST,
2460 .stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR,
2461 .traffic_enable = rtl930x_traffic_enable,
2462 .traffic_disable = rtl930x_traffic_disable,
2463 .traffic_get = rtl930x_traffic_get,
2464 .traffic_set = rtl930x_traffic_set,
2465 .l2_ctrl_0 = RTL930X_L2_CTRL,
2466 .l2_ctrl_1 = RTL930X_L2_AGE_CTRL,
2467 .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL,
2468 .set_ageing_time = rtl930x_set_ageing_time,
2469 .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, /* TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL */
2470 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
2471 .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd,
2472 .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd,
2473 .tbl_access_data_0 = rtl930x_tbl_access_data_0,
2474 .isr_glb_src = RTL930X_ISR_GLB,
2475 .isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG,
2476 .imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG,
2477 .imr_glb = RTL930X_IMR_GLB,
2478 .vlan_tables_read = rtl930x_vlan_tables_read,
2479 .vlan_set_tagged = rtl930x_vlan_set_tagged,
2480 .vlan_set_untagged = rtl930x_vlan_set_untagged,
2481 .vlan_profile_dump = rtl930x_vlan_profile_dump,
2482 .vlan_profile_setup = rtl930x_vlan_profile_setup,
2483 .vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner,
2484 .set_vlan_igr_filter = rtl930x_set_igr_filter,
2485 .set_vlan_egr_filter = rtl930x_set_egr_filter,
2486 .stp_get = rtl930x_stp_get,
2487 .stp_set = rtl930x_stp_set,
2488 .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl,
2489 .mac_port_ctrl = rtl930x_mac_port_ctrl,
2490 .l2_port_new_salrn = rtl930x_l2_port_new_salrn,
2491 .l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd,
2492 .mir_ctrl = RTL930X_MIR_CTRL,
2493 .mir_dpm = RTL930X_MIR_DPM_CTRL,
2494 .mir_spm = RTL930X_MIR_SPM_CTRL,
2495 .mac_link_sts = RTL930X_MAC_LINK_STS,
2496 .mac_link_dup_sts = RTL930X_MAC_LINK_DUP_STS,
2497 .mac_link_spd_sts = rtl930x_mac_link_spd_sts,
2498 .mac_rx_pause_sts = RTL930X_MAC_RX_PAUSE_STS,
2499 .mac_tx_pause_sts = RTL930X_MAC_TX_PAUSE_STS,
2500 .read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash,
2501 .write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash,
2502 .read_cam = rtl930x_read_cam,
2503 .write_cam = rtl930x_write_cam,
2504 .vlan_port_keep_tag_set = rtl930x_vlan_port_keep_tag_set,
2505 .vlan_port_pvidmode_set = rtl930x_vlan_port_pvidmode_set,
2506 .vlan_port_pvid_set = rtl930x_vlan_port_pvid_set,
2507 .trk_mbr_ctr = rtl930x_trk_mbr_ctr,
2508 .rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK,
2509 .init_eee = rtl930x_init_eee,
2510 .port_eee_set = rtl930x_port_eee_set,
2511 .eee_port_ability = rtl930x_eee_port_ability,
2512 .l2_hash_seed = rtl930x_l2_hash_seed,
2513 .l2_hash_key = rtl930x_l2_hash_key,
2514 .read_mcast_pmask = rtl930x_read_mcast_pmask,
2515 .write_mcast_pmask = rtl930x_write_mcast_pmask,
2516 .pie_init = rtl930x_pie_init,
2517 .pie_rule_write = rtl930x_pie_rule_write,
2518 .pie_rule_add = rtl930x_pie_rule_add,
2519 .pie_rule_rm = rtl930x_pie_rule_rm,
2520 .l2_learning_setup = rtl930x_l2_learning_setup,
2521 .packet_cntr_read = rtl930x_packet_cntr_read,
2522 .packet_cntr_clear = rtl930x_packet_cntr_clear,
2523 .route_read = rtl930x_route_read,
2524 .route_write = rtl930x_route_write,
2525 .host_route_write = rtl930x_host_route_write,
2526 .l3_setup = rtl930x_l3_setup,
2527 .set_l3_nexthop = rtl930x_set_l3_nexthop,
2528 .get_l3_nexthop = rtl930x_get_l3_nexthop,
2529 .get_l3_egress_mac = rtl930x_get_l3_egress_mac,
2530 .set_l3_egress_mac = rtl930x_set_l3_egress_mac,
2531 .find_l3_slot = rtl930x_find_l3_slot,
2532 .route_lookup_hw = rtl930x_route_lookup_hw,
2533 .get_l3_router_mac = rtl930x_get_l3_router_mac,
2534 .set_l3_router_mac = rtl930x_set_l3_router_mac,
2535 .set_l3_egress_intf = rtl930x_set_l3_egress_intf,
2536 .set_distribution_algorithm = rtl930x_set_distribution_algorithm,
2537 .led_init = rtl930x_led_init,
2538 };
Kevin D-Bs staging tree