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ar71xx: add a helper function for setting up PHY4 swapping on ar933x
[openwrt/staging/lynxis.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/irq.h>
26
27 #include "common.h"
28 #include "dev-eth.h"
29
30 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
31
32 static struct resource ath79_mdio0_resources[] = {
33 {
34 .name = "mdio_base",
35 .flags = IORESOURCE_MEM,
36 .start = AR71XX_GE0_BASE,
37 .end = AR71XX_GE0_BASE + 0x200 - 1,
38 }
39 };
40
41 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
42
43 struct platform_device ath79_mdio0_device = {
44 .name = "ag71xx-mdio",
45 .id = 0,
46 .resource = ath79_mdio0_resources,
47 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
48 .dev = {
49 .platform_data = &ath79_mdio0_data,
50 },
51 };
52
53 static struct resource ath79_mdio1_resources[] = {
54 {
55 .name = "mdio_base",
56 .flags = IORESOURCE_MEM,
57 .start = AR71XX_GE1_BASE,
58 .end = AR71XX_GE1_BASE + 0x200 - 1,
59 }
60 };
61
62 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
63
64 struct platform_device ath79_mdio1_device = {
65 .name = "ag71xx-mdio",
66 .id = 1,
67 .resource = ath79_mdio1_resources,
68 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
69 .dev = {
70 .platform_data = &ath79_mdio1_data,
71 },
72 };
73
74 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
75 {
76 void __iomem *base;
77 u32 t;
78
79 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
80
81 t = __raw_readl(base + cfg_reg);
82 t &= ~(3 << shift);
83 t |= (2 << shift);
84 __raw_writel(t, base + cfg_reg);
85 udelay(100);
86
87 __raw_writel(pll_val, base + pll_reg);
88
89 t |= (3 << shift);
90 __raw_writel(t, base + cfg_reg);
91 udelay(100);
92
93 t &= ~(3 << shift);
94 __raw_writel(t, base + cfg_reg);
95 udelay(100);
96
97 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
98 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
99
100 iounmap(base);
101 }
102
103 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
104 unsigned int mii_if)
105 {
106 void __iomem *base;
107 u32 t;
108
109 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
110
111 t = __raw_readl(base + reg);
112 t &= ~(AR71XX_MII_CTRL_IF_MASK);
113 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
114 __raw_writel(t, base + reg);
115
116 iounmap(base);
117 }
118
119 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
120 {
121 void __iomem *base;
122 unsigned int mii_speed;
123 u32 t;
124
125 switch (speed) {
126 case SPEED_10:
127 mii_speed = AR71XX_MII_CTRL_SPEED_10;
128 break;
129 case SPEED_100:
130 mii_speed = AR71XX_MII_CTRL_SPEED_100;
131 break;
132 case SPEED_1000:
133 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
134 break;
135 default:
136 BUG();
137 }
138
139 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
140
141 t = __raw_readl(base + reg);
142 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
143 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
144 __raw_writel(t, base + reg);
145
146 iounmap(base);
147 }
148
149 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
150 {
151 struct platform_device *mdio_dev;
152 struct ag71xx_mdio_platform_data *mdio_data;
153 unsigned int max_id;
154
155 if (ath79_soc == ATH79_SOC_AR9341 ||
156 ath79_soc == ATH79_SOC_AR9342 ||
157 ath79_soc == ATH79_SOC_AR9344)
158 max_id = 1;
159 else
160 max_id = 0;
161
162 if (id > max_id) {
163 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
164 return;
165 }
166
167 switch (ath79_soc) {
168 case ATH79_SOC_AR7241:
169 case ATH79_SOC_AR9330:
170 case ATH79_SOC_AR9331:
171 mdio_dev = &ath79_mdio1_device;
172 mdio_data = &ath79_mdio1_data;
173 break;
174
175 case ATH79_SOC_AR9341:
176 case ATH79_SOC_AR9342:
177 case ATH79_SOC_AR9344:
178 if (id == 0) {
179 mdio_dev = &ath79_mdio0_device;
180 mdio_data = &ath79_mdio0_data;
181 } else {
182 mdio_dev = &ath79_mdio1_device;
183 mdio_data = &ath79_mdio1_data;
184 }
185 break;
186
187 case ATH79_SOC_AR7242:
188 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
189 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
190 AR71XX_ETH0_PLL_SHIFT);
191 /* fall through */
192 default:
193 mdio_dev = &ath79_mdio0_device;
194 mdio_data = &ath79_mdio0_data;
195 break;
196 }
197
198 mdio_data->phy_mask = phy_mask;
199
200 switch (ath79_soc) {
201 case ATH79_SOC_AR7240:
202 mdio_data->is_ar7240 = 1;
203 /* fall through */
204 case ATH79_SOC_AR7241:
205 mdio_data->builtin_switch = 1;
206 break;
207
208 case ATH79_SOC_AR9330:
209 mdio_data->is_ar9330 = 1;
210 /* fall through */
211 case ATH79_SOC_AR9331:
212 mdio_data->builtin_switch = 1;
213 break;
214
215 case ATH79_SOC_AR9341:
216 case ATH79_SOC_AR9342:
217 case ATH79_SOC_AR9344:
218 if (id == 1)
219 mdio_data->builtin_switch = 1;
220 mdio_data->is_ar934x = 1;
221 break;
222
223 default:
224 break;
225 }
226
227 platform_device_register(mdio_dev);
228 }
229
230 struct ath79_eth_pll_data ath79_eth0_pll_data;
231 struct ath79_eth_pll_data ath79_eth1_pll_data;
232
233 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
234 {
235 struct ath79_eth_pll_data *pll_data;
236 u32 pll_val;
237
238 switch (mac) {
239 case 0:
240 pll_data = &ath79_eth0_pll_data;
241 break;
242 case 1:
243 pll_data = &ath79_eth1_pll_data;
244 break;
245 default:
246 BUG();
247 }
248
249 switch (speed) {
250 case SPEED_10:
251 pll_val = pll_data->pll_10;
252 break;
253 case SPEED_100:
254 pll_val = pll_data->pll_100;
255 break;
256 case SPEED_1000:
257 pll_val = pll_data->pll_1000;
258 break;
259 default:
260 BUG();
261 }
262
263 return pll_val;
264 }
265
266 static void ath79_set_speed_ge0(int speed)
267 {
268 u32 val = ath79_get_eth_pll(0, speed);
269
270 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
271 val, AR71XX_ETH0_PLL_SHIFT);
272 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
273 }
274
275 static void ath79_set_speed_ge1(int speed)
276 {
277 u32 val = ath79_get_eth_pll(1, speed);
278
279 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
280 val, AR71XX_ETH1_PLL_SHIFT);
281 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
282 }
283
284 static void ar7242_set_speed_ge0(int speed)
285 {
286 u32 val = ath79_get_eth_pll(0, speed);
287 void __iomem *base;
288
289 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
290 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
291 iounmap(base);
292 }
293
294 static void ar91xx_set_speed_ge0(int speed)
295 {
296 u32 val = ath79_get_eth_pll(0, speed);
297
298 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
299 val, AR913X_ETH0_PLL_SHIFT);
300 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
301 }
302
303 static void ar91xx_set_speed_ge1(int speed)
304 {
305 u32 val = ath79_get_eth_pll(1, speed);
306
307 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
308 val, AR913X_ETH1_PLL_SHIFT);
309 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
310 }
311
312 static void ar934x_set_speed_ge0(int speed)
313 {
314 void __iomem *base;
315 u32 val = ath79_get_eth_pll(0, speed);
316
317 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
318 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
319 iounmap(base);
320 }
321
322 static void ath79_set_speed_dummy(int speed)
323 {
324 }
325
326 static void ath79_ddr_no_flush(void)
327 {
328 }
329
330 static void ath79_ddr_flush_ge0(void)
331 {
332 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
333 }
334
335 static void ath79_ddr_flush_ge1(void)
336 {
337 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
338 }
339
340 static void ar724x_ddr_flush_ge0(void)
341 {
342 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
343 }
344
345 static void ar724x_ddr_flush_ge1(void)
346 {
347 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
348 }
349
350 static void ar91xx_ddr_flush_ge0(void)
351 {
352 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
353 }
354
355 static void ar91xx_ddr_flush_ge1(void)
356 {
357 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
358 }
359
360 static void ar933x_ddr_flush_ge0(void)
361 {
362 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
363 }
364
365 static void ar933x_ddr_flush_ge1(void)
366 {
367 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
368 }
369
370 static struct resource ath79_eth0_resources[] = {
371 {
372 .name = "mac_base",
373 .flags = IORESOURCE_MEM,
374 .start = AR71XX_GE0_BASE,
375 .end = AR71XX_GE0_BASE + 0x200 - 1,
376 }, {
377 .name = "mac_irq",
378 .flags = IORESOURCE_IRQ,
379 .start = ATH79_CPU_IRQ_GE0,
380 .end = ATH79_CPU_IRQ_GE0,
381 },
382 };
383
384 struct ag71xx_platform_data ath79_eth0_data = {
385 .reset_bit = AR71XX_RESET_GE0_MAC,
386 };
387
388 struct platform_device ath79_eth0_device = {
389 .name = "ag71xx",
390 .id = 0,
391 .resource = ath79_eth0_resources,
392 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
393 .dev = {
394 .platform_data = &ath79_eth0_data,
395 },
396 };
397
398 static struct resource ath79_eth1_resources[] = {
399 {
400 .name = "mac_base",
401 .flags = IORESOURCE_MEM,
402 .start = AR71XX_GE1_BASE,
403 .end = AR71XX_GE1_BASE + 0x200 - 1,
404 }, {
405 .name = "mac_irq",
406 .flags = IORESOURCE_IRQ,
407 .start = ATH79_CPU_IRQ_GE1,
408 .end = ATH79_CPU_IRQ_GE1,
409 },
410 };
411
412 struct ag71xx_platform_data ath79_eth1_data = {
413 .reset_bit = AR71XX_RESET_GE1_MAC,
414 };
415
416 struct platform_device ath79_eth1_device = {
417 .name = "ag71xx",
418 .id = 1,
419 .resource = ath79_eth1_resources,
420 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
421 .dev = {
422 .platform_data = &ath79_eth1_data,
423 },
424 };
425
426 struct ag71xx_switch_platform_data ath79_switch_data;
427
428 #define AR71XX_PLL_VAL_1000 0x00110000
429 #define AR71XX_PLL_VAL_100 0x00001099
430 #define AR71XX_PLL_VAL_10 0x00991099
431
432 #define AR724X_PLL_VAL_1000 0x00110000
433 #define AR724X_PLL_VAL_100 0x00001099
434 #define AR724X_PLL_VAL_10 0x00991099
435
436 #define AR7242_PLL_VAL_1000 0x16000000
437 #define AR7242_PLL_VAL_100 0x00000101
438 #define AR7242_PLL_VAL_10 0x00001616
439
440 #define AR913X_PLL_VAL_1000 0x1a000000
441 #define AR913X_PLL_VAL_100 0x13000a44
442 #define AR913X_PLL_VAL_10 0x00441099
443
444 #define AR933X_PLL_VAL_1000 0x00110000
445 #define AR933X_PLL_VAL_100 0x00001099
446 #define AR933X_PLL_VAL_10 0x00991099
447
448 #define AR934X_PLL_VAL_1000 0x16000000
449 #define AR934X_PLL_VAL_100 0x00000101
450 #define AR934X_PLL_VAL_10 0x00001616
451
452 static void __init ath79_init_eth_pll_data(unsigned int id)
453 {
454 struct ath79_eth_pll_data *pll_data;
455 u32 pll_10, pll_100, pll_1000;
456
457 switch (id) {
458 case 0:
459 pll_data = &ath79_eth0_pll_data;
460 break;
461 case 1:
462 pll_data = &ath79_eth1_pll_data;
463 break;
464 default:
465 BUG();
466 }
467
468 switch (ath79_soc) {
469 case ATH79_SOC_AR7130:
470 case ATH79_SOC_AR7141:
471 case ATH79_SOC_AR7161:
472 pll_10 = AR71XX_PLL_VAL_10;
473 pll_100 = AR71XX_PLL_VAL_100;
474 pll_1000 = AR71XX_PLL_VAL_1000;
475 break;
476
477 case ATH79_SOC_AR7240:
478 case ATH79_SOC_AR7241:
479 pll_10 = AR724X_PLL_VAL_10;
480 pll_100 = AR724X_PLL_VAL_100;
481 pll_1000 = AR724X_PLL_VAL_1000;
482 break;
483
484 case ATH79_SOC_AR7242:
485 pll_10 = AR7242_PLL_VAL_10;
486 pll_100 = AR7242_PLL_VAL_100;
487 pll_1000 = AR7242_PLL_VAL_1000;
488 break;
489
490 case ATH79_SOC_AR9130:
491 case ATH79_SOC_AR9132:
492 pll_10 = AR913X_PLL_VAL_10;
493 pll_100 = AR913X_PLL_VAL_100;
494 pll_1000 = AR913X_PLL_VAL_1000;
495 break;
496
497 case ATH79_SOC_AR9330:
498 case ATH79_SOC_AR9331:
499 pll_10 = AR933X_PLL_VAL_10;
500 pll_100 = AR933X_PLL_VAL_100;
501 pll_1000 = AR933X_PLL_VAL_1000;
502 break;
503
504 case ATH79_SOC_AR9341:
505 case ATH79_SOC_AR9342:
506 case ATH79_SOC_AR9344:
507 pll_10 = AR934X_PLL_VAL_10;
508 pll_100 = AR934X_PLL_VAL_100;
509 pll_1000 = AR934X_PLL_VAL_1000;
510 break;
511
512 default:
513 BUG();
514 }
515
516 if (!pll_data->pll_10)
517 pll_data->pll_10 = pll_10;
518
519 if (!pll_data->pll_100)
520 pll_data->pll_100 = pll_100;
521
522 if (!pll_data->pll_1000)
523 pll_data->pll_1000 = pll_1000;
524 }
525
526 static int __init ath79_setup_phy_if_mode(unsigned int id,
527 struct ag71xx_platform_data *pdata)
528 {
529 unsigned int mii_if;
530
531 switch (id) {
532 case 0:
533 switch (ath79_soc) {
534 case ATH79_SOC_AR7130:
535 case ATH79_SOC_AR7141:
536 case ATH79_SOC_AR7161:
537 case ATH79_SOC_AR9130:
538 case ATH79_SOC_AR9132:
539 switch (pdata->phy_if_mode) {
540 case PHY_INTERFACE_MODE_MII:
541 mii_if = AR71XX_MII0_CTRL_IF_MII;
542 break;
543 case PHY_INTERFACE_MODE_GMII:
544 mii_if = AR71XX_MII0_CTRL_IF_GMII;
545 break;
546 case PHY_INTERFACE_MODE_RGMII:
547 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
548 break;
549 case PHY_INTERFACE_MODE_RMII:
550 mii_if = AR71XX_MII0_CTRL_IF_RMII;
551 break;
552 default:
553 return -EINVAL;
554 }
555 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
556 break;
557
558 case ATH79_SOC_AR7240:
559 case ATH79_SOC_AR7241:
560 case ATH79_SOC_AR9330:
561 case ATH79_SOC_AR9331:
562 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
563 break;
564
565 case ATH79_SOC_AR7242:
566 /* FIXME */
567
568 case ATH79_SOC_AR9341:
569 case ATH79_SOC_AR9342:
570 case ATH79_SOC_AR9344:
571 switch (pdata->phy_if_mode) {
572 case PHY_INTERFACE_MODE_MII:
573 case PHY_INTERFACE_MODE_GMII:
574 case PHY_INTERFACE_MODE_RGMII:
575 case PHY_INTERFACE_MODE_RMII:
576 break;
577 default:
578 return -EINVAL;
579 }
580 break;
581
582 default:
583 BUG();
584 }
585 break;
586 case 1:
587 switch (ath79_soc) {
588 case ATH79_SOC_AR7130:
589 case ATH79_SOC_AR7141:
590 case ATH79_SOC_AR7161:
591 case ATH79_SOC_AR9130:
592 case ATH79_SOC_AR9132:
593 switch (pdata->phy_if_mode) {
594 case PHY_INTERFACE_MODE_RMII:
595 mii_if = AR71XX_MII1_CTRL_IF_RMII;
596 break;
597 case PHY_INTERFACE_MODE_RGMII:
598 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
599 break;
600 default:
601 return -EINVAL;
602 }
603 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
604 break;
605
606 case ATH79_SOC_AR7240:
607 case ATH79_SOC_AR7241:
608 case ATH79_SOC_AR9330:
609 case ATH79_SOC_AR9331:
610 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
611 break;
612
613 case ATH79_SOC_AR7242:
614 /* FIXME */
615
616 case ATH79_SOC_AR9341:
617 case ATH79_SOC_AR9342:
618 case ATH79_SOC_AR9344:
619 switch (pdata->phy_if_mode) {
620 case PHY_INTERFACE_MODE_MII:
621 case PHY_INTERFACE_MODE_GMII:
622 break;
623 default:
624 return -EINVAL;
625 }
626 break;
627
628 default:
629 BUG();
630 }
631 break;
632 }
633
634 return 0;
635 }
636
637 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
638 {
639 void __iomem *base;
640 u32 t;
641
642 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
643
644 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
645 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
646 if (mac)
647 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
648 if (mdio)
649 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
650 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
651
652 iounmap(base);
653 }
654
655 static int ath79_eth_instance __initdata;
656 void __init ath79_register_eth(unsigned int id)
657 {
658 struct platform_device *pdev;
659 struct ag71xx_platform_data *pdata;
660 int err;
661
662 if (id > 1) {
663 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
664 return;
665 }
666
667 ath79_init_eth_pll_data(id);
668
669 if (id == 0)
670 pdev = &ath79_eth0_device;
671 else
672 pdev = &ath79_eth1_device;
673
674 pdata = pdev->dev.platform_data;
675
676 err = ath79_setup_phy_if_mode(id, pdata);
677 if (err) {
678 printk(KERN_ERR
679 "ar71xx: invalid PHY interface mode for GE%u\n", id);
680 return;
681 }
682
683 switch (ath79_soc) {
684 case ATH79_SOC_AR7130:
685 if (id == 0) {
686 pdata->ddr_flush = ath79_ddr_flush_ge0;
687 pdata->set_speed = ath79_set_speed_ge0;
688 } else {
689 pdata->ddr_flush = ath79_ddr_flush_ge1;
690 pdata->set_speed = ath79_set_speed_ge1;
691 }
692 break;
693
694 case ATH79_SOC_AR7141:
695 case ATH79_SOC_AR7161:
696 if (id == 0) {
697 pdata->ddr_flush = ath79_ddr_flush_ge0;
698 pdata->set_speed = ath79_set_speed_ge0;
699 } else {
700 pdata->ddr_flush = ath79_ddr_flush_ge1;
701 pdata->set_speed = ath79_set_speed_ge1;
702 }
703 pdata->has_gbit = 1;
704 break;
705
706 case ATH79_SOC_AR7242:
707 if (id == 0) {
708 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
709 AR71XX_RESET_GE0_PHY;
710 pdata->ddr_flush = ar724x_ddr_flush_ge0;
711 pdata->set_speed = ar7242_set_speed_ge0;
712 } else {
713 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
714 AR71XX_RESET_GE1_PHY;
715 pdata->ddr_flush = ar724x_ddr_flush_ge1;
716 pdata->set_speed = ath79_set_speed_dummy;
717 }
718 pdata->has_gbit = 1;
719 pdata->is_ar724x = 1;
720
721 if (!pdata->fifo_cfg1)
722 pdata->fifo_cfg1 = 0x0010ffff;
723 if (!pdata->fifo_cfg2)
724 pdata->fifo_cfg2 = 0x015500aa;
725 if (!pdata->fifo_cfg3)
726 pdata->fifo_cfg3 = 0x01f00140;
727 break;
728
729 case ATH79_SOC_AR7241:
730 if (id == 0)
731 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
732 else
733 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
734 /* fall through */
735 case ATH79_SOC_AR7240:
736 if (id == 0) {
737 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
738 pdata->ddr_flush = ar724x_ddr_flush_ge0;
739 pdata->set_speed = ath79_set_speed_dummy;
740
741 pdata->phy_mask = BIT(4);
742 } else {
743 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
744 pdata->ddr_flush = ar724x_ddr_flush_ge1;
745 pdata->set_speed = ath79_set_speed_dummy;
746
747 pdata->speed = SPEED_1000;
748 pdata->duplex = DUPLEX_FULL;
749 pdata->switch_data = &ath79_switch_data;
750
751 ath79_switch_data.phy_poll_mask |= BIT(4);
752 }
753 pdata->has_gbit = 1;
754 pdata->is_ar724x = 1;
755 if (ath79_soc == ATH79_SOC_AR7240)
756 pdata->is_ar7240 = 1;
757
758 if (!pdata->fifo_cfg1)
759 pdata->fifo_cfg1 = 0x0010ffff;
760 if (!pdata->fifo_cfg2)
761 pdata->fifo_cfg2 = 0x015500aa;
762 if (!pdata->fifo_cfg3)
763 pdata->fifo_cfg3 = 0x01f00140;
764 break;
765
766 case ATH79_SOC_AR9130:
767 if (id == 0) {
768 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
769 pdata->set_speed = ar91xx_set_speed_ge0;
770 } else {
771 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
772 pdata->set_speed = ar91xx_set_speed_ge1;
773 }
774 pdata->is_ar91xx = 1;
775 break;
776
777 case ATH79_SOC_AR9132:
778 if (id == 0) {
779 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
780 pdata->set_speed = ar91xx_set_speed_ge0;
781 } else {
782 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
783 pdata->set_speed = ar91xx_set_speed_ge1;
784 }
785 pdata->is_ar91xx = 1;
786 pdata->has_gbit = 1;
787 break;
788
789 case ATH79_SOC_AR9330:
790 case ATH79_SOC_AR9331:
791 if (id == 0) {
792 pdata->reset_bit = AR933X_RESET_GE0_MAC |
793 AR933X_RESET_GE0_MDIO;
794 pdata->ddr_flush = ar933x_ddr_flush_ge0;
795 pdata->set_speed = ath79_set_speed_dummy;
796
797 pdata->phy_mask = BIT(4);
798 } else {
799 pdata->reset_bit = AR933X_RESET_GE1_MAC |
800 AR933X_RESET_GE1_MDIO;
801 pdata->ddr_flush = ar933x_ddr_flush_ge1;
802 pdata->set_speed = ath79_set_speed_dummy;
803
804 pdata->speed = SPEED_1000;
805 pdata->duplex = DUPLEX_FULL;
806 pdata->switch_data = &ath79_switch_data;
807
808 ath79_switch_data.phy_poll_mask |= BIT(4);
809 }
810
811 pdata->has_gbit = 1;
812 pdata->is_ar724x = 1;
813
814 if (!pdata->fifo_cfg1)
815 pdata->fifo_cfg1 = 0x0010ffff;
816 if (!pdata->fifo_cfg2)
817 pdata->fifo_cfg2 = 0x015500aa;
818 if (!pdata->fifo_cfg3)
819 pdata->fifo_cfg3 = 0x01f00140;
820 break;
821
822 case ATH79_SOC_AR9341:
823 case ATH79_SOC_AR9342:
824 case ATH79_SOC_AR9344:
825 if (id == 0) {
826 pdata->reset_bit = AR934X_RESET_GE0_MAC |
827 AR934X_RESET_GE0_MDIO;
828 pdata->set_speed = ar934x_set_speed_ge0;
829 } else {
830 pdata->reset_bit = AR934X_RESET_GE1_MAC |
831 AR934X_RESET_GE1_MDIO;
832 pdata->set_speed = ath79_set_speed_dummy;
833
834 pdata->switch_data = &ath79_switch_data;
835
836 /* reset the built-in switch */
837 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
838 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
839 }
840
841 pdata->ddr_flush = ath79_ddr_no_flush;
842 pdata->has_gbit = 1;
843 pdata->is_ar724x = 1;
844
845 if (!pdata->fifo_cfg1)
846 pdata->fifo_cfg1 = 0x0010ffff;
847 if (!pdata->fifo_cfg2)
848 pdata->fifo_cfg2 = 0x015500aa;
849 if (!pdata->fifo_cfg3)
850 pdata->fifo_cfg3 = 0x01f00140;
851 break;
852
853 default:
854 BUG();
855 }
856
857 switch (pdata->phy_if_mode) {
858 case PHY_INTERFACE_MODE_GMII:
859 case PHY_INTERFACE_MODE_RGMII:
860 if (!pdata->has_gbit) {
861 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
862 id);
863 return;
864 }
865 /* fallthrough */
866 default:
867 break;
868 }
869
870 if (!is_valid_ether_addr(pdata->mac_addr)) {
871 random_ether_addr(pdata->mac_addr);
872 printk(KERN_DEBUG
873 "ar71xx: using random MAC address for eth%d\n",
874 ath79_eth_instance);
875 }
876
877 if (pdata->mii_bus_dev == NULL) {
878 switch (ath79_soc) {
879 case ATH79_SOC_AR9341:
880 case ATH79_SOC_AR9342:
881 case ATH79_SOC_AR9344:
882 if (id == 0)
883 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
884 else
885 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
886 break;
887
888 case ATH79_SOC_AR7241:
889 case ATH79_SOC_AR9330:
890 case ATH79_SOC_AR9331:
891 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
892 break;
893
894 default:
895 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
896 break;
897 }
898 }
899
900 /* Reset the device */
901 ath79_device_reset_set(pdata->reset_bit);
902 mdelay(100);
903
904 ath79_device_reset_clear(pdata->reset_bit);
905 mdelay(100);
906
907 platform_device_register(pdev);
908 ath79_eth_instance++;
909 }
910
911 void __init ath79_set_mac_base(unsigned char *mac)
912 {
913 memcpy(ath79_mac_base, mac, ETH_ALEN);
914 }
915
916 void __init ath79_parse_mac_addr(char *mac_str)
917 {
918 u8 tmp[ETH_ALEN];
919 int t;
920
921 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
922 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
923
924 if (t != ETH_ALEN)
925 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
926 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
927
928 if (t == ETH_ALEN)
929 ath79_set_mac_base(tmp);
930 else
931 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
932 "\"%s\"\n", mac_str);
933 }
934
935 static int __init ath79_ethaddr_setup(char *str)
936 {
937 ath79_parse_mac_addr(str);
938 return 1;
939 }
940 __setup("ethaddr=", ath79_ethaddr_setup);
941
942 static int __init ath79_kmac_setup(char *str)
943 {
944 ath79_parse_mac_addr(str);
945 return 1;
946 }
947 __setup("kmac=", ath79_kmac_setup);
948
949 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
950 int offset)
951 {
952 int t;
953
954 if (!is_valid_ether_addr(src)) {
955 memset(dst, '\0', ETH_ALEN);
956 return;
957 }
958
959 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
960 t += offset;
961
962 dst[0] = src[0];
963 dst[1] = src[1];
964 dst[2] = src[2];
965 dst[3] = (t >> 16) & 0xff;
966 dst[4] = (t >> 8) & 0xff;
967 dst[5] = t & 0xff;
968 }
969
970 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
971 {
972 int i;
973
974 if (!is_valid_ether_addr(src)) {
975 memset(dst, '\0', ETH_ALEN);
976 return;
977 }
978
979 for (i = 0; i < ETH_ALEN; i++)
980 dst[i] = src[i];
981 dst[0] |= 0x02;
982 }
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