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WIP: rework image builder code for x86
[openwrt/staging/lynxis.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define ETH_SWITCH_HEADER_LEN 2
32
33 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
34 static void ag71xx_qca955x_sgmii_init(void);
35
36 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
37 {
38 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
39 }
40
41 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
42 {
43 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
44 ag->dev->name,
45 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
46 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
47 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
48
49 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
50 ag->dev->name,
51 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
52 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
53 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
54 }
55
56 static void ag71xx_dump_regs(struct ag71xx *ag)
57 {
58 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
59 ag->dev->name,
60 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
61 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
62 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
63 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
64 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
65 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
68 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
69 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
70 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
71 ag->dev->name,
72 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
73 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
74 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
75 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
76 ag->dev->name,
77 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
78 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
79 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
80 }
81
82 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
83 {
84 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
85 ag->dev->name, label, intr,
86 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
87 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
88 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
89 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
90 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
91 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
92 }
93
94 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
95 {
96 struct ag71xx_ring *ring = &ag->tx_ring;
97 struct net_device *dev = ag->dev;
98 int ring_mask = BIT(ring->order) - 1;
99 u32 bytes_compl = 0, pkts_compl = 0;
100
101 while (ring->curr != ring->dirty) {
102 struct ag71xx_desc *desc;
103 u32 i = ring->dirty & ring_mask;
104
105 desc = ag71xx_ring_desc(ring, i);
106 if (!ag71xx_desc_empty(desc)) {
107 desc->ctrl = 0;
108 dev->stats.tx_errors++;
109 }
110
111 if (ring->buf[i].skb) {
112 bytes_compl += ring->buf[i].len;
113 pkts_compl++;
114 dev_kfree_skb_any(ring->buf[i].skb);
115 }
116 ring->buf[i].skb = NULL;
117 ring->dirty++;
118 }
119
120 /* flush descriptors */
121 wmb();
122
123 netdev_completed_queue(dev, pkts_compl, bytes_compl);
124 }
125
126 static void ag71xx_ring_tx_init(struct ag71xx *ag)
127 {
128 struct ag71xx_ring *ring = &ag->tx_ring;
129 int ring_size = BIT(ring->order);
130 int ring_mask = ring_size - 1;
131 int i;
132
133 for (i = 0; i < ring_size; i++) {
134 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
135
136 desc->next = (u32) (ring->descs_dma +
137 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
138
139 desc->ctrl = DESC_EMPTY;
140 ring->buf[i].skb = NULL;
141 }
142
143 /* flush descriptors */
144 wmb();
145
146 ring->curr = 0;
147 ring->dirty = 0;
148 netdev_reset_queue(ag->dev);
149 }
150
151 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
152 {
153 struct ag71xx_ring *ring = &ag->rx_ring;
154 int ring_size = BIT(ring->order);
155 int i;
156
157 if (!ring->buf)
158 return;
159
160 for (i = 0; i < ring_size; i++)
161 if (ring->buf[i].rx_buf) {
162 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
163 ag->rx_buf_size, DMA_FROM_DEVICE);
164 skb_free_frag(ring->buf[i].rx_buf);
165 }
166 }
167
168 static int ag71xx_buffer_offset(struct ag71xx *ag)
169 {
170 int offset = NET_SKB_PAD;
171
172 /*
173 * On AR71xx/AR91xx packets must be 4-byte aligned.
174 *
175 * When using builtin AR8216 support, hardware adds a 2-byte header,
176 * so we don't need any extra alignment in that case.
177 */
178 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
179 return offset;
180
181 return offset + NET_IP_ALIGN;
182 }
183
184 static int ag71xx_buffer_size(struct ag71xx *ag)
185 {
186 return ag->rx_buf_size +
187 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
188 }
189
190 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
191 int offset,
192 void *(*alloc)(unsigned int size))
193 {
194 struct ag71xx_ring *ring = &ag->rx_ring;
195 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
196 void *data;
197
198 data = alloc(ag71xx_buffer_size(ag));
199 if (!data)
200 return false;
201
202 buf->rx_buf = data;
203 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
204 DMA_FROM_DEVICE);
205 desc->data = (u32) buf->dma_addr + offset;
206 return true;
207 }
208
209 static int ag71xx_ring_rx_init(struct ag71xx *ag)
210 {
211 struct ag71xx_ring *ring = &ag->rx_ring;
212 int ring_size = BIT(ring->order);
213 int ring_mask = BIT(ring->order) - 1;
214 unsigned int i;
215 int ret;
216 int offset = ag71xx_buffer_offset(ag);
217
218 ret = 0;
219 for (i = 0; i < ring_size; i++) {
220 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
221
222 desc->next = (u32) (ring->descs_dma +
223 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
224
225 DBG("ag71xx: RX desc at %p, next is %08x\n",
226 desc, desc->next);
227 }
228
229 for (i = 0; i < ring_size; i++) {
230 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
231
232 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
233 netdev_alloc_frag)) {
234 ret = -ENOMEM;
235 break;
236 }
237
238 desc->ctrl = DESC_EMPTY;
239 }
240
241 /* flush descriptors */
242 wmb();
243
244 ring->curr = 0;
245 ring->dirty = 0;
246
247 return ret;
248 }
249
250 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
251 {
252 struct ag71xx_ring *ring = &ag->rx_ring;
253 int ring_mask = BIT(ring->order) - 1;
254 unsigned int count;
255 int offset = ag71xx_buffer_offset(ag);
256
257 count = 0;
258 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
259 struct ag71xx_desc *desc;
260 unsigned int i;
261
262 i = ring->dirty & ring_mask;
263 desc = ag71xx_ring_desc(ring, i);
264
265 if (!ring->buf[i].rx_buf &&
266 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
267 napi_alloc_frag))
268 break;
269
270 desc->ctrl = DESC_EMPTY;
271 count++;
272 }
273
274 /* flush descriptors */
275 wmb();
276
277 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
278
279 return count;
280 }
281
282 static int ag71xx_rings_init(struct ag71xx *ag)
283 {
284 struct ag71xx_ring *tx = &ag->tx_ring;
285 struct ag71xx_ring *rx = &ag->rx_ring;
286 int ring_size = BIT(tx->order) + BIT(rx->order);
287 int tx_size = BIT(tx->order);
288
289 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
290 if (!tx->buf)
291 return -ENOMEM;
292
293 tx->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
294 &tx->descs_dma, GFP_ATOMIC);
295 if (!tx->descs_cpu) {
296 kfree(tx->buf);
297 tx->buf = NULL;
298 return -ENOMEM;
299 }
300
301 rx->buf = &tx->buf[BIT(tx->order)];
302 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
303 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
304
305 ag71xx_ring_tx_init(ag);
306 return ag71xx_ring_rx_init(ag);
307 }
308
309 static void ag71xx_rings_free(struct ag71xx *ag)
310 {
311 struct ag71xx_ring *tx = &ag->tx_ring;
312 struct ag71xx_ring *rx = &ag->rx_ring;
313 int ring_size = BIT(tx->order) + BIT(rx->order);
314
315 if (tx->descs_cpu)
316 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
317 tx->descs_cpu, tx->descs_dma);
318
319 kfree(tx->buf);
320
321 tx->descs_cpu = NULL;
322 rx->descs_cpu = NULL;
323 tx->buf = NULL;
324 rx->buf = NULL;
325 }
326
327 static void ag71xx_rings_cleanup(struct ag71xx *ag)
328 {
329 ag71xx_ring_rx_clean(ag);
330 ag71xx_ring_tx_clean(ag);
331 ag71xx_rings_free(ag);
332
333 netdev_reset_queue(ag->dev);
334 }
335
336 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
337 {
338 switch (ag->speed) {
339 case SPEED_1000:
340 return "1000";
341 case SPEED_100:
342 return "100";
343 case SPEED_10:
344 return "10";
345 }
346
347 return "?";
348 }
349
350 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
351 {
352 u32 t;
353
354 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
355 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
356
357 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
358
359 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
360 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
361 }
362
363 static void ag71xx_dma_reset(struct ag71xx *ag)
364 {
365 u32 val;
366 int i;
367
368 ag71xx_dump_dma_regs(ag);
369
370 /* stop RX and TX */
371 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
372 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
373
374 /*
375 * give the hardware some time to really stop all rx/tx activity
376 * clearing the descriptors too early causes random memory corruption
377 */
378 mdelay(1);
379
380 /* clear descriptor addresses */
381 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
382 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
383
384 /* clear pending RX/TX interrupts */
385 for (i = 0; i < 256; i++) {
386 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
387 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
388 }
389
390 /* clear pending errors */
391 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
392 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
393
394 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
395 if (val)
396 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
397 ag->dev->name, val);
398
399 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
400
401 /* mask out reserved bits */
402 val &= ~0xff000000;
403
404 if (val)
405 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
406 ag->dev->name, val);
407
408 ag71xx_dump_dma_regs(ag);
409 }
410
411 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
412 MAC_CFG1_SRX | MAC_CFG1_STX)
413
414 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
415
416 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
417 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
418 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
419 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
420 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
421 FIFO_CFG4_VT)
422
423 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
424 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
425 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
426 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
427 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
428 FIFO_CFG5_17 | FIFO_CFG5_SF)
429
430 static void ag71xx_hw_stop(struct ag71xx *ag)
431 {
432 /* disable all interrupts and stop the rx/tx engine */
433 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
434 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
435 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
436 }
437
438 static void ag71xx_hw_setup(struct ag71xx *ag)
439 {
440 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
441 u32 init = MAC_CFG1_INIT;
442
443 /* setup MAC configuration registers */
444 if (pdata->use_flow_control)
445 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
446 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
447
448 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
449 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
450
451 /* setup max frame length to zero */
452 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
453
454 /* setup FIFO configuration registers */
455 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
456 if (pdata->is_ar724x) {
457 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0010ffff);
458 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x015500aa);
459 } else {
460 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
461 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
462 }
463 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
464 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
465 }
466
467 static void ag71xx_hw_init(struct ag71xx *ag)
468 {
469 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
470 u32 reset_mask = pdata->reset_bit;
471
472 ag71xx_hw_stop(ag);
473
474 if (pdata->is_ar724x) {
475 u32 reset_phy = reset_mask;
476
477 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
478 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
479
480 ath79_device_reset_set(reset_phy);
481 msleep(50);
482 ath79_device_reset_clear(reset_phy);
483 msleep(200);
484 }
485
486 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
487 udelay(20);
488
489 ath79_device_reset_set(reset_mask);
490 msleep(100);
491 ath79_device_reset_clear(reset_mask);
492 msleep(200);
493
494 ag71xx_hw_setup(ag);
495
496 ag71xx_dma_reset(ag);
497 }
498
499 static void ag71xx_fast_reset(struct ag71xx *ag)
500 {
501 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
502 struct net_device *dev = ag->dev;
503 u32 reset_mask = pdata->reset_bit;
504 u32 rx_ds;
505 u32 mii_reg;
506
507 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
508
509 ag71xx_hw_stop(ag);
510 wmb();
511
512 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
513 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
514
515 ag71xx_tx_packets(ag, true);
516
517 ath79_device_reset_set(reset_mask);
518 udelay(10);
519 ath79_device_reset_clear(reset_mask);
520 udelay(10);
521
522 ag71xx_dma_reset(ag);
523 ag71xx_hw_setup(ag);
524 ag->tx_ring.curr = 0;
525 ag->tx_ring.dirty = 0;
526 netdev_reset_queue(ag->dev);
527
528 /* setup max frame length */
529 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
530 ag71xx_max_frame_len(ag->dev->mtu));
531
532 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
533 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
534 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
535
536 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
537 }
538
539 static void ag71xx_hw_start(struct ag71xx *ag)
540 {
541 /* start RX engine */
542 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
543
544 /* enable interrupts */
545 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
546
547 netif_wake_queue(ag->dev);
548 }
549
550 static void
551 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
552 {
553 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
554 u32 cfg2;
555 u32 ifctl;
556 u32 fifo5;
557 u32 fifo3;
558
559 if (!ag->link && update) {
560 ag71xx_hw_stop(ag);
561 netif_carrier_off(ag->dev);
562 if (netif_msg_link(ag))
563 pr_info("%s: link down\n", ag->dev->name);
564 return;
565 }
566
567 if (pdata->is_ar724x)
568 ag71xx_fast_reset(ag);
569
570 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
571 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
572 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
573
574 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
575 ifctl &= ~(MAC_IFCTL_SPEED);
576
577 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
578 fifo5 &= ~FIFO_CFG5_BM;
579
580 switch (ag->speed) {
581 case SPEED_1000:
582 cfg2 |= MAC_CFG2_IF_1000;
583 fifo5 |= FIFO_CFG5_BM;
584 break;
585 case SPEED_100:
586 cfg2 |= MAC_CFG2_IF_10_100;
587 ifctl |= MAC_IFCTL_SPEED;
588 break;
589 case SPEED_10:
590 cfg2 |= MAC_CFG2_IF_10_100;
591 break;
592 default:
593 BUG();
594 return;
595 }
596
597 if (pdata->is_ar91xx)
598 fifo3 = 0x00780fff;
599 else if (pdata->is_ar724x)
600 fifo3 = 0x01f00140;
601 else
602 fifo3 = 0x008001ff;
603
604 if (ag->tx_ring.desc_split) {
605 fifo3 &= 0xffff;
606 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
607 }
608
609 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
610
611 if (update && pdata->set_speed)
612 pdata->set_speed(ag->speed);
613
614 if (update && pdata->enable_sgmii_fixup)
615 ag71xx_qca955x_sgmii_init();
616
617 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
618 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
619 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
620
621 if (pdata->disable_inline_checksum_engine) {
622 /*
623 * The rx ring buffer can stall on small packets on QCA953x and
624 * QCA956x. Disabling the inline checksum engine fixes the stall.
625 * The wr, rr functions cannot be used since this hidden register
626 * is outside of the normal ag71xx register block.
627 */
628 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
629 if (dam) {
630 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
631 (void)__raw_readl(dam);
632 iounmap(dam);
633 }
634 }
635
636 ag71xx_hw_start(ag);
637
638 netif_carrier_on(ag->dev);
639 if (update && netif_msg_link(ag))
640 pr_info("%s: link up (%sMbps/%s duplex)\n",
641 ag->dev->name,
642 ag71xx_speed_str(ag),
643 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
644
645 ag71xx_dump_regs(ag);
646 }
647
648 void ag71xx_link_adjust(struct ag71xx *ag)
649 {
650 __ag71xx_link_adjust(ag, true);
651 }
652
653 static int ag71xx_hw_enable(struct ag71xx *ag)
654 {
655 int ret;
656
657 ret = ag71xx_rings_init(ag);
658 if (ret)
659 return ret;
660
661 napi_enable(&ag->napi);
662 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
663 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
664 netif_start_queue(ag->dev);
665
666 return 0;
667 }
668
669 static void ag71xx_hw_disable(struct ag71xx *ag)
670 {
671 unsigned long flags;
672
673 spin_lock_irqsave(&ag->lock, flags);
674
675 netif_stop_queue(ag->dev);
676
677 ag71xx_hw_stop(ag);
678 ag71xx_dma_reset(ag);
679
680 napi_disable(&ag->napi);
681 del_timer_sync(&ag->oom_timer);
682
683 spin_unlock_irqrestore(&ag->lock, flags);
684
685 ag71xx_rings_cleanup(ag);
686 }
687
688 static int ag71xx_open(struct net_device *dev)
689 {
690 struct ag71xx *ag = netdev_priv(dev);
691 unsigned int max_frame_len;
692 int ret;
693
694 netif_carrier_off(dev);
695 max_frame_len = ag71xx_max_frame_len(dev->mtu);
696 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
697
698 /* setup max frame length */
699 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
700 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
701
702 ret = ag71xx_hw_enable(ag);
703 if (ret)
704 goto err;
705
706 ag71xx_phy_start(ag);
707
708 return 0;
709
710 err:
711 ag71xx_rings_cleanup(ag);
712 return ret;
713 }
714
715 static int ag71xx_stop(struct net_device *dev)
716 {
717 struct ag71xx *ag = netdev_priv(dev);
718
719 netif_carrier_off(dev);
720 ag71xx_phy_stop(ag);
721 ag71xx_hw_disable(ag);
722
723 return 0;
724 }
725
726 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
727 {
728 int i;
729 struct ag71xx_desc *desc;
730 int ring_mask = BIT(ring->order) - 1;
731 int ndesc = 0;
732 int split = ring->desc_split;
733
734 if (!split)
735 split = len;
736
737 while (len > 0) {
738 unsigned int cur_len = len;
739
740 i = (ring->curr + ndesc) & ring_mask;
741 desc = ag71xx_ring_desc(ring, i);
742
743 if (!ag71xx_desc_empty(desc))
744 return -1;
745
746 if (cur_len > split) {
747 cur_len = split;
748
749 /*
750 * TX will hang if DMA transfers <= 4 bytes,
751 * make sure next segment is more than 4 bytes long.
752 */
753 if (len <= split + 4)
754 cur_len -= 4;
755 }
756
757 desc->data = addr;
758 addr += cur_len;
759 len -= cur_len;
760
761 if (len > 0)
762 cur_len |= DESC_MORE;
763
764 /* prevent early tx attempt of this descriptor */
765 if (!ndesc)
766 cur_len |= DESC_EMPTY;
767
768 desc->ctrl = cur_len;
769 ndesc++;
770 }
771
772 return ndesc;
773 }
774
775 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
776 struct net_device *dev)
777 {
778 struct ag71xx *ag = netdev_priv(dev);
779 struct ag71xx_ring *ring = &ag->tx_ring;
780 int ring_mask = BIT(ring->order) - 1;
781 int ring_size = BIT(ring->order);
782 struct ag71xx_desc *desc;
783 dma_addr_t dma_addr;
784 int i, n, ring_min;
785
786 if (ag71xx_has_ar8216(ag))
787 ag71xx_add_ar8216_header(ag, skb);
788
789 if (skb->len <= 4) {
790 DBG("%s: packet len is too small\n", ag->dev->name);
791 goto err_drop;
792 }
793
794 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
795 DMA_TO_DEVICE);
796
797 i = ring->curr & ring_mask;
798 desc = ag71xx_ring_desc(ring, i);
799
800 /* setup descriptor fields */
801 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
802 if (n < 0)
803 goto err_drop_unmap;
804
805 i = (ring->curr + n - 1) & ring_mask;
806 ring->buf[i].len = skb->len;
807 ring->buf[i].skb = skb;
808
809 netdev_sent_queue(dev, skb->len);
810
811 skb_tx_timestamp(skb);
812
813 desc->ctrl &= ~DESC_EMPTY;
814 ring->curr += n;
815
816 /* flush descriptor */
817 wmb();
818
819 ring_min = 2;
820 if (ring->desc_split)
821 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
822
823 if (ring->curr - ring->dirty >= ring_size - ring_min) {
824 DBG("%s: tx queue full\n", dev->name);
825 netif_stop_queue(dev);
826 }
827
828 DBG("%s: packet injected into TX queue\n", ag->dev->name);
829
830 /* enable TX engine */
831 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
832
833 return NETDEV_TX_OK;
834
835 err_drop_unmap:
836 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
837
838 err_drop:
839 dev->stats.tx_dropped++;
840
841 dev_kfree_skb(skb);
842 return NETDEV_TX_OK;
843 }
844
845 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
846 {
847 struct ag71xx *ag = netdev_priv(dev);
848
849 switch (cmd) {
850 case SIOCSIFHWADDR:
851 if (copy_from_user
852 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
853 return -EFAULT;
854 return 0;
855
856 case SIOCGIFHWADDR:
857 if (copy_to_user
858 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
859 return -EFAULT;
860 return 0;
861
862 case SIOCGMIIPHY:
863 case SIOCGMIIREG:
864 case SIOCSMIIREG:
865 if (ag->phy_dev == NULL)
866 break;
867
868 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
869
870 default:
871 break;
872 }
873
874 return -EOPNOTSUPP;
875 }
876
877 static void ag71xx_oom_timer_handler(unsigned long data)
878 {
879 struct net_device *dev = (struct net_device *) data;
880 struct ag71xx *ag = netdev_priv(dev);
881
882 napi_schedule(&ag->napi);
883 }
884
885 static void ag71xx_tx_timeout(struct net_device *dev)
886 {
887 struct ag71xx *ag = netdev_priv(dev);
888
889 if (netif_msg_tx_err(ag))
890 pr_info("%s: tx timeout\n", ag->dev->name);
891
892 schedule_delayed_work(&ag->restart_work, 1);
893 }
894
895 static void ag71xx_bit_set(void __iomem *reg, u32 bit)
896 {
897 u32 val = __raw_readl(reg) | bit;
898 __raw_writel(val, reg);
899 __raw_readl(reg);
900 }
901
902 static void ag71xx_bit_clear(void __iomem *reg, u32 bit)
903 {
904 u32 val = __raw_readl(reg) & ~bit;
905 __raw_writel(val, reg);
906 __raw_readl(reg);
907 }
908
909 static void ag71xx_qca955x_sgmii_init()
910 {
911 void __iomem *gmac_base;
912 u32 mr_an_status, sgmii_status;
913 u8 tries = 0;
914
915 gmac_base = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
916
917 if (!gmac_base)
918 goto sgmii_out;
919
920 mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS);
921 if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY))
922 goto sgmii_out;
923
924 __raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET ,
925 gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
926 __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
927 udelay(10);
928
929 /* Init sequence */
930 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
931 QCA955X_SGMII_RESET_HW_RX_125M_N);
932 udelay(10);
933
934 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
935 QCA955X_SGMII_RESET_RX_125M_N);
936 udelay(10);
937
938 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
939 QCA955X_SGMII_RESET_TX_125M_N);
940 udelay(10);
941
942 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
943 QCA955X_SGMII_RESET_RX_CLK_N);
944 udelay(10);
945
946 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
947 QCA955X_SGMII_RESET_TX_CLK_N);
948 udelay(10);
949
950 do {
951 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
952 QCA955X_MR_AN_CONTROL_PHY_RESET |
953 QCA955X_MR_AN_CONTROL_AN_ENABLE);
954 udelay(100);
955 ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
956 QCA955X_MR_AN_CONTROL_PHY_RESET);
957 mdelay(10);
958 sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) & 0xF;
959
960 if (tries++ >= QCA955X_SGMII_LINK_WAR_MAX_TRY) {
961 pr_warn("ag71xx: max retries for SGMII fixup exceeded!\n");
962 break;
963 }
964 } while (!(sgmii_status == 0xf || sgmii_status == 0x10));
965
966 sgmii_out:
967 iounmap(gmac_base);
968 }
969
970 static void ag71xx_restart_work_func(struct work_struct *work)
971 {
972 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
973
974 rtnl_lock();
975 ag71xx_hw_disable(ag);
976 ag71xx_hw_enable(ag);
977 if (ag->link)
978 __ag71xx_link_adjust(ag, false);
979 rtnl_unlock();
980 }
981
982 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
983 {
984 unsigned long timestamp;
985 u32 rx_sm, tx_sm, rx_fd;
986
987 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
988 if (likely(time_before(jiffies, timestamp + HZ/10)))
989 return false;
990
991 if (!netif_carrier_ok(ag->dev))
992 return false;
993
994 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
995 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
996 return true;
997
998 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
999 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
1000 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
1001 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
1002 return true;
1003
1004 return false;
1005 }
1006
1007 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
1008 {
1009 struct ag71xx_ring *ring = &ag->tx_ring;
1010 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1011 bool dma_stuck = false;
1012 int ring_mask = BIT(ring->order) - 1;
1013 int ring_size = BIT(ring->order);
1014 int sent = 0;
1015 int bytes_compl = 0;
1016 int n = 0;
1017
1018 DBG("%s: processing TX ring\n", ag->dev->name);
1019
1020 while (ring->dirty + n != ring->curr) {
1021 unsigned int i = (ring->dirty + n) & ring_mask;
1022 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1023 struct sk_buff *skb = ring->buf[i].skb;
1024
1025 if (!flush && !ag71xx_desc_empty(desc)) {
1026 if (pdata->is_ar724x &&
1027 ag71xx_check_dma_stuck(ag)) {
1028 schedule_delayed_work(&ag->restart_work, HZ / 2);
1029 dma_stuck = true;
1030 }
1031 break;
1032 }
1033
1034 if (flush)
1035 desc->ctrl |= DESC_EMPTY;
1036
1037 n++;
1038 if (!skb)
1039 continue;
1040
1041 dev_kfree_skb_any(skb);
1042 ring->buf[i].skb = NULL;
1043
1044 bytes_compl += ring->buf[i].len;
1045
1046 sent++;
1047 ring->dirty += n;
1048
1049 while (n > 0) {
1050 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1051 n--;
1052 }
1053 }
1054
1055 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1056
1057 if (!sent)
1058 return 0;
1059
1060 ag->dev->stats.tx_bytes += bytes_compl;
1061 ag->dev->stats.tx_packets += sent;
1062
1063 netdev_completed_queue(ag->dev, sent, bytes_compl);
1064 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1065 netif_wake_queue(ag->dev);
1066
1067 if (!dma_stuck)
1068 cancel_delayed_work(&ag->restart_work);
1069
1070 return sent;
1071 }
1072
1073 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1074 {
1075 struct net_device *dev = ag->dev;
1076 struct ag71xx_ring *ring = &ag->rx_ring;
1077 int offset = ag71xx_buffer_offset(ag);
1078 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1079 int ring_mask = BIT(ring->order) - 1;
1080 int ring_size = BIT(ring->order);
1081 struct sk_buff_head queue;
1082 struct sk_buff *skb;
1083 int done = 0;
1084
1085 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1086 dev->name, limit, ring->curr, ring->dirty);
1087
1088 skb_queue_head_init(&queue);
1089
1090 while (done < limit) {
1091 unsigned int i = ring->curr & ring_mask;
1092 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1093 int pktlen;
1094 int err = 0;
1095
1096 if (ag71xx_desc_empty(desc))
1097 break;
1098
1099 if ((ring->dirty + ring_size) == ring->curr) {
1100 ag71xx_assert(0);
1101 break;
1102 }
1103
1104 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1105
1106 pktlen = desc->ctrl & pktlen_mask;
1107 pktlen -= ETH_FCS_LEN;
1108
1109 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1110 ag->rx_buf_size, DMA_FROM_DEVICE);
1111
1112 dev->stats.rx_packets++;
1113 dev->stats.rx_bytes += pktlen;
1114
1115 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1116 if (!skb) {
1117 skb_free_frag(ring->buf[i].rx_buf);
1118 goto next;
1119 }
1120
1121 skb_reserve(skb, offset);
1122 skb_put(skb, pktlen);
1123
1124 if (ag71xx_has_ar8216(ag))
1125 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
1126
1127 if (err) {
1128 dev->stats.rx_dropped++;
1129 kfree_skb(skb);
1130 } else {
1131 skb->dev = dev;
1132 skb->ip_summed = CHECKSUM_NONE;
1133 __skb_queue_tail(&queue, skb);
1134 }
1135
1136 next:
1137 ring->buf[i].rx_buf = NULL;
1138 done++;
1139
1140 ring->curr++;
1141 }
1142
1143 ag71xx_ring_rx_refill(ag);
1144
1145 while ((skb = __skb_dequeue(&queue)) != NULL) {
1146 skb->protocol = eth_type_trans(skb, dev);
1147 netif_receive_skb(skb);
1148 }
1149
1150 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1151 dev->name, ring->curr, ring->dirty, done);
1152
1153 return done;
1154 }
1155
1156 static int ag71xx_poll(struct napi_struct *napi, int limit)
1157 {
1158 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1159 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1160 struct net_device *dev = ag->dev;
1161 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1162 int rx_ring_size = BIT(rx_ring->order);
1163 unsigned long flags;
1164 u32 status;
1165 int tx_done;
1166 int rx_done;
1167
1168 pdata->ddr_flush();
1169 tx_done = ag71xx_tx_packets(ag, false);
1170
1171 DBG("%s: processing RX ring\n", dev->name);
1172 rx_done = ag71xx_rx_packets(ag, limit);
1173
1174 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1175
1176 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1177 goto oom;
1178
1179 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1180 if (unlikely(status & RX_STATUS_OF)) {
1181 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1182 dev->stats.rx_fifo_errors++;
1183
1184 /* restart RX */
1185 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1186 }
1187
1188 if (rx_done < limit) {
1189 if (status & RX_STATUS_PR)
1190 goto more;
1191
1192 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1193 if (status & TX_STATUS_PS)
1194 goto more;
1195
1196 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1197 dev->name, rx_done, tx_done, limit);
1198
1199 napi_complete(napi);
1200
1201 /* enable interrupts */
1202 spin_lock_irqsave(&ag->lock, flags);
1203 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1204 spin_unlock_irqrestore(&ag->lock, flags);
1205 return rx_done;
1206 }
1207
1208 more:
1209 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1210 dev->name, rx_done, tx_done, limit);
1211 return limit;
1212
1213 oom:
1214 if (netif_msg_rx_err(ag))
1215 pr_info("%s: out of memory\n", dev->name);
1216
1217 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1218 napi_complete(napi);
1219 return 0;
1220 }
1221
1222 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1223 {
1224 struct net_device *dev = dev_id;
1225 struct ag71xx *ag = netdev_priv(dev);
1226 u32 status;
1227
1228 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1229 ag71xx_dump_intr(ag, "raw", status);
1230
1231 if (unlikely(!status))
1232 return IRQ_NONE;
1233
1234 if (unlikely(status & AG71XX_INT_ERR)) {
1235 if (status & AG71XX_INT_TX_BE) {
1236 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1237 dev_err(&dev->dev, "TX BUS error\n");
1238 }
1239 if (status & AG71XX_INT_RX_BE) {
1240 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1241 dev_err(&dev->dev, "RX BUS error\n");
1242 }
1243 }
1244
1245 if (likely(status & AG71XX_INT_POLL)) {
1246 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1247 DBG("%s: enable polling mode\n", dev->name);
1248 napi_schedule(&ag->napi);
1249 }
1250
1251 ag71xx_debugfs_update_int_stats(ag, status);
1252
1253 return IRQ_HANDLED;
1254 }
1255
1256 #ifdef CONFIG_NET_POLL_CONTROLLER
1257 /*
1258 * Polling 'interrupt' - used by things like netconsole to send skbs
1259 * without having to re-enable interrupts. It's not called while
1260 * the interrupt routine is executing.
1261 */
1262 static void ag71xx_netpoll(struct net_device *dev)
1263 {
1264 disable_irq(dev->irq);
1265 ag71xx_interrupt(dev->irq, dev);
1266 enable_irq(dev->irq);
1267 }
1268 #endif
1269
1270 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1271 {
1272 struct ag71xx *ag = netdev_priv(dev);
1273 unsigned int max_frame_len;
1274
1275 max_frame_len = ag71xx_max_frame_len(new_mtu);
1276 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1277 return -EINVAL;
1278
1279 if (netif_running(dev))
1280 return -EBUSY;
1281
1282 dev->mtu = new_mtu;
1283 return 0;
1284 }
1285
1286 static const struct net_device_ops ag71xx_netdev_ops = {
1287 .ndo_open = ag71xx_open,
1288 .ndo_stop = ag71xx_stop,
1289 .ndo_start_xmit = ag71xx_hard_start_xmit,
1290 .ndo_do_ioctl = ag71xx_do_ioctl,
1291 .ndo_tx_timeout = ag71xx_tx_timeout,
1292 .ndo_change_mtu = ag71xx_change_mtu,
1293 .ndo_set_mac_address = eth_mac_addr,
1294 .ndo_validate_addr = eth_validate_addr,
1295 #ifdef CONFIG_NET_POLL_CONTROLLER
1296 .ndo_poll_controller = ag71xx_netpoll,
1297 #endif
1298 };
1299
1300 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1301 {
1302 switch (mode) {
1303 case PHY_INTERFACE_MODE_MII:
1304 return "MII";
1305 case PHY_INTERFACE_MODE_GMII:
1306 return "GMII";
1307 case PHY_INTERFACE_MODE_RMII:
1308 return "RMII";
1309 case PHY_INTERFACE_MODE_RGMII:
1310 return "RGMII";
1311 case PHY_INTERFACE_MODE_SGMII:
1312 return "SGMII";
1313 default:
1314 break;
1315 }
1316
1317 return "unknown";
1318 }
1319
1320
1321 static int ag71xx_probe(struct platform_device *pdev)
1322 {
1323 struct net_device *dev;
1324 struct resource *res;
1325 struct ag71xx *ag;
1326 struct ag71xx_platform_data *pdata;
1327 int tx_size, err;
1328
1329 pdata = pdev->dev.platform_data;
1330 if (!pdata) {
1331 dev_err(&pdev->dev, "no platform data specified\n");
1332 err = -ENXIO;
1333 goto err_out;
1334 }
1335
1336 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1337 dev_err(&pdev->dev, "no MII bus device specified\n");
1338 err = -EINVAL;
1339 goto err_out;
1340 }
1341
1342 dev = alloc_etherdev(sizeof(*ag));
1343 if (!dev) {
1344 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1345 err = -ENOMEM;
1346 goto err_out;
1347 }
1348
1349 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1350 return -EINVAL;
1351
1352 SET_NETDEV_DEV(dev, &pdev->dev);
1353
1354 ag = netdev_priv(dev);
1355 ag->pdev = pdev;
1356 ag->dev = dev;
1357 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1358 AG71XX_DEFAULT_MSG_ENABLE);
1359 spin_lock_init(&ag->lock);
1360
1361 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1362 if (!res) {
1363 dev_err(&pdev->dev, "no mac_base resource found\n");
1364 err = -ENXIO;
1365 goto err_out;
1366 }
1367
1368 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1369 if (!ag->mac_base) {
1370 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1371 err = -ENOMEM;
1372 goto err_free_dev;
1373 }
1374
1375 dev->irq = platform_get_irq(pdev, 0);
1376 err = request_irq(dev->irq, ag71xx_interrupt,
1377 0x0,
1378 dev->name, dev);
1379 if (err) {
1380 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1381 goto err_unmap_base;
1382 }
1383
1384 dev->base_addr = (unsigned long)ag->mac_base;
1385 dev->netdev_ops = &ag71xx_netdev_ops;
1386 dev->ethtool_ops = &ag71xx_ethtool_ops;
1387
1388 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1389
1390 init_timer(&ag->oom_timer);
1391 ag->oom_timer.data = (unsigned long) dev;
1392 ag->oom_timer.function = ag71xx_oom_timer_handler;
1393
1394 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1395 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1396
1397 ag->max_frame_len = pdata->max_frame_len;
1398 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1399
1400 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1401 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1402 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1403 }
1404 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1405
1406 ag->stop_desc = dma_alloc_coherent(NULL,
1407 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1408
1409 if (!ag->stop_desc)
1410 goto err_free_irq;
1411
1412 ag->stop_desc->data = 0;
1413 ag->stop_desc->ctrl = 0;
1414 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1415
1416 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1417
1418 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1419
1420 ag71xx_dump_regs(ag);
1421
1422 ag71xx_hw_init(ag);
1423
1424 ag71xx_dump_regs(ag);
1425
1426 err = ag71xx_phy_connect(ag);
1427 if (err)
1428 goto err_free_desc;
1429
1430 err = ag71xx_debugfs_init(ag);
1431 if (err)
1432 goto err_phy_disconnect;
1433
1434 platform_set_drvdata(pdev, dev);
1435
1436 err = register_netdev(dev);
1437 if (err) {
1438 dev_err(&pdev->dev, "unable to register net device\n");
1439 goto err_debugfs_exit;
1440 }
1441
1442 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1443 dev->name, dev->base_addr, dev->irq,
1444 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1445
1446 return 0;
1447
1448 err_debugfs_exit:
1449 ag71xx_debugfs_exit(ag);
1450 err_phy_disconnect:
1451 ag71xx_phy_disconnect(ag);
1452 err_free_desc:
1453 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1454 ag->stop_desc_dma);
1455 err_free_irq:
1456 free_irq(dev->irq, dev);
1457 err_unmap_base:
1458 iounmap(ag->mac_base);
1459 err_free_dev:
1460 kfree(dev);
1461 err_out:
1462 platform_set_drvdata(pdev, NULL);
1463 return err;
1464 }
1465
1466 static int ag71xx_remove(struct platform_device *pdev)
1467 {
1468 struct net_device *dev = platform_get_drvdata(pdev);
1469
1470 if (dev) {
1471 struct ag71xx *ag = netdev_priv(dev);
1472
1473 ag71xx_debugfs_exit(ag);
1474 ag71xx_phy_disconnect(ag);
1475 unregister_netdev(dev);
1476 free_irq(dev->irq, dev);
1477 iounmap(ag->mac_base);
1478 kfree(dev);
1479 platform_set_drvdata(pdev, NULL);
1480 }
1481
1482 return 0;
1483 }
1484
1485 static struct platform_driver ag71xx_driver = {
1486 .probe = ag71xx_probe,
1487 .remove = ag71xx_remove,
1488 .driver = {
1489 .name = AG71XX_DRV_NAME,
1490 }
1491 };
1492
1493 static int __init ag71xx_module_init(void)
1494 {
1495 int ret;
1496
1497 ret = ag71xx_debugfs_root_init();
1498 if (ret)
1499 goto err_out;
1500
1501 ret = ag71xx_mdio_driver_init();
1502 if (ret)
1503 goto err_debugfs_exit;
1504
1505 ret = platform_driver_register(&ag71xx_driver);
1506 if (ret)
1507 goto err_mdio_exit;
1508
1509 return 0;
1510
1511 err_mdio_exit:
1512 ag71xx_mdio_driver_exit();
1513 err_debugfs_exit:
1514 ag71xx_debugfs_root_exit();
1515 err_out:
1516 return ret;
1517 }
1518
1519 static void __exit ag71xx_module_exit(void)
1520 {
1521 platform_driver_unregister(&ag71xx_driver);
1522 ag71xx_mdio_driver_exit();
1523 ag71xx_debugfs_root_exit();
1524 }
1525
1526 module_init(ag71xx_module_init);
1527 module_exit(ag71xx_module_exit);
1528
1529 MODULE_VERSION(AG71XX_DRV_VERSION);
1530 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1531 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1532 MODULE_LICENSE("GPL v2");
1533 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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