target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch

   1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   3 @@ -21,6 +21,10 @@
   4  #include <linux/bitops.h>
   5
   6  #define AR71XX_APB_BASE                0x18000000
   7 +#define AR71XX_GE0_BASE                0x19000000
   8 +#define AR71XX_GE0_SIZE                0x10000
   9 +#define AR71XX_GE1_BASE                0x1a000000
  10 +#define AR71XX_GE1_SIZE                0x10000
  11  #define AR71XX_EHCI_BASE       0x1b000000
  12  #define AR71XX_EHCI_SIZE       0x1000
  13  #define AR71XX_OHCI_BASE       0x1c000000
  14 @@ -40,6 +44,8 @@
  15  #define AR71XX_PLL_SIZE                0x100
  16  #define AR71XX_RESET_BASE      (AR71XX_APB_BASE + 0x00060000)
  17  #define AR71XX_RESET_SIZE      0x100
  18 +#define AR71XX_MII_BASE                (AR71XX_APB_BASE + 0x00070000)
  19 +#define AR71XX_MII_SIZE                0x100
  20
  21  #define AR71XX_PCI_MEM_BASE    0x10000000
  22  #define AR71XX_PCI_MEM_SIZE    0x07000000
  23 @@ -82,11 +88,15 @@
  24
  25  #define AR933X_UART_BASE       (AR71XX_APB_BASE + 0x00020000)
  26  #define AR933X_UART_SIZE       0x14
  27 +#define AR933X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
  28 +#define AR933X_GMAC_SIZE       0x04
  29  #define AR933X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
  30  #define AR933X_WMAC_SIZE       0x20000
  31  #define AR933X_EHCI_BASE       0x1b000000
  32  #define AR933X_EHCI_SIZE       0x1000
  33
  34 +#define AR934X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
  35 +#define AR934X_GMAC_SIZE       0x14
  36  #define AR934X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
  37  #define AR934X_WMAC_SIZE       0x20000
  38  #define AR934X_EHCI_BASE       0x1b000000
  39 @@ -112,6 +122,8 @@
  40  #define QCA955X_EHCI0_BASE     0x1b000000
  41  #define QCA955X_EHCI1_BASE     0x1b400000
  42  #define QCA955X_EHCI_SIZE      0x1000
  43 +#define QCA955X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
  44 +#define QCA955X_GMAC_SIZE      0x40
  45
  46  /*
  47   * DDR_CTRL block
  48 @@ -167,6 +179,9 @@
  49  #define AR71XX_AHB_DIV_SHIFT           20
  50  #define AR71XX_AHB_DIV_MASK            0x7
  51
  52 +#define AR71XX_ETH0_PLL_SHIFT          17
  53 +#define AR71XX_ETH1_PLL_SHIFT          19
  54 +
  55  #define AR724X_PLL_REG_CPU_CONFIG      0x00
  56  #define AR724X_PLL_REG_PCIE_CONFIG     0x18
  57
  58 @@ -179,6 +194,8 @@
  59  #define AR724X_DDR_DIV_SHIFT           22
  60  #define AR724X_DDR_DIV_MASK            0x3
  61
  62 +#define AR7242_PLL_REG_ETH0_INT_CLOCK  0x2c
  63 +
  64  #define AR913X_PLL_REG_CPU_CONFIG      0x00
  65  #define AR913X_PLL_REG_ETH_CONFIG      0x04
  66  #define AR913X_PLL_REG_ETH0_INT_CLOCK  0x14
  67 @@ -191,6 +208,9 @@
  68  #define AR913X_AHB_DIV_SHIFT           19
  69  #define AR913X_AHB_DIV_MASK            0x1
  70
  71 +#define AR913X_ETH0_PLL_SHIFT          20
  72 +#define AR913X_ETH1_PLL_SHIFT          22
  73 +
  74  #define AR933X_PLL_CPU_CONFIG_REG      0x00
  75  #define AR933X_PLL_CLOCK_CTRL_REG      0x08
  76
  77 @@ -212,6 +232,8 @@
  78  #define AR934X_PLL_CPU_CONFIG_REG              0x00
  79  #define AR934X_PLL_DDR_CONFIG_REG              0x04
  80  #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG                0x08
  81 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG    0x24
  82 +#define AR934X_PLL_ETH_XMII_CONTROL_REG                0x2c
  83
  84  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT      0
  85  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK       0x3f
  86 @@ -244,6 +266,8 @@
  87  #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
  88  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  89
  90 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   BIT(6)
  91 +
  92  #define QCA955X_PLL_CPU_CONFIG_REG             0x00
  93  #define QCA955X_PLL_DDR_CONFIG_REG             0x04
  94  #define QCA955X_PLL_CLK_CTRL_REG               0x08
  95 @@ -370,16 +394,50 @@
  96  #define AR913X_RESET_USB_HOST          BIT(5)
  97  #define AR913X_RESET_USB_PHY           BIT(4)
  98
  99 +#define AR933X_RESET_GE1_MDIO          BIT(23)
 100 +#define AR933X_RESET_GE0_MDIO          BIT(22)
 101 +#define AR933X_RESET_GE1_MAC           BIT(13)
 102  #define AR933X_RESET_WMAC              BIT(11)
 103 +#define AR933X_RESET_GE0_MAC           BIT(9)
 104  #define AR933X_RESET_USB_HOST          BIT(5)
 105  #define AR933X_RESET_USB_PHY           BIT(4)
 106  #define AR933X_RESET_USBSUS_OVERRIDE   BIT(3)
 107
 108 +#define AR934X_RESET_HOST              BIT(31)
 109 +#define AR934X_RESET_SLIC              BIT(30)
 110 +#define AR934X_RESET_HDMA              BIT(29)
 111 +#define AR934X_RESET_EXTERNAL          BIT(28)
 112 +#define AR934X_RESET_RTC               BIT(27)
 113 +#define AR934X_RESET_PCIE_EP_INT       BIT(26)
 114 +#define AR934X_RESET_CHKSUM_ACC                BIT(25)
 115 +#define AR934X_RESET_FULL_CHIP         BIT(24)
 116 +#define AR934X_RESET_GE1_MDIO          BIT(23)
 117 +#define AR934X_RESET_GE0_MDIO          BIT(22)
 118 +#define AR934X_RESET_CPU_NMI           BIT(21)
 119 +#define AR934X_RESET_CPU_COLD          BIT(20)
 120 +#define AR934X_RESET_HOST_RESET_INT    BIT(19)
 121 +#define AR934X_RESET_PCIE_EP           BIT(18)
 122 +#define AR934X_RESET_UART1             BIT(17)
 123 +#define AR934X_RESET_DDR               BIT(16)
 124 +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
 125 +#define AR934X_RESET_NANDF             BIT(14)
 126 +#define AR934X_RESET_GE1_MAC           BIT(13)
 127 +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
 128  #define AR934X_RESET_USB_PHY_ANALOG    BIT(11)
 129 +#define AR934X_RESET_HOST_DMA_INT      BIT(10)
 130 +#define AR934X_RESET_GE0_MAC           BIT(9)
 131 +#define AR934X_RESET_ETH_SWITCH                BIT(8)
 132 +#define AR934X_RESET_PCIE_PHY          BIT(7)
 133 +#define AR934X_RESET_PCIE              BIT(6)
 134  #define AR934X_RESET_USB_HOST          BIT(5)
 135  #define AR934X_RESET_USB_PHY           BIT(4)
 136  #define AR934X_RESET_USBSUS_OVERRIDE   BIT(3)
 137 +#define AR934X_RESET_LUT               BIT(2)
 138 +#define AR934X_RESET_MBOX              BIT(1)
 139 +#define AR934X_RESET_I2S               BIT(0)
 140
 141 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN  BIT(18)
 142 +#define AR933X_BOOTSTRAP_EEPBUSY       BIT(4)
 143  #define AR933X_BOOTSTRAP_REF_CLK_40    BIT(0)
 144
 145  #define AR934X_BOOTSTRAP_SW_OPTION8    BIT(23)
 146 @@ -520,6 +578,14 @@
 147  #define AR71XX_GPIO_REG_INT_ENABLE     0x24
 148  #define AR71XX_GPIO_REG_FUNC           0x28
 149
 150 +#define AR934X_GPIO_REG_OUT_FUNC0      0x2c
 151 +#define AR934X_GPIO_REG_OUT_FUNC1      0x30
 152 +#define AR934X_GPIO_REG_OUT_FUNC2      0x34
 153 +#define AR934X_GPIO_REG_OUT_FUNC3      0x38
 154 +#define AR934X_GPIO_REG_OUT_FUNC4      0x3c
 155 +#define AR934X_GPIO_REG_OUT_FUNC5      0x40
 156 +#define AR934X_GPIO_REG_FUNC           0x6c
 157 +
 158  #define AR71XX_GPIO_COUNT              16
 159  #define AR724X_GPIO_COUNT              18
 160  #define AR913X_GPIO_COUNT              22
 161 @@ -548,4 +614,133 @@
 162  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
 163  #define AR934X_SRIF_DPLL2_OUTDIV_MASK  0x7
 164
 165 +#define AR71XX_GPIO_FUNC_STEREO_EN             BIT(17)
 166 +#define AR71XX_GPIO_FUNC_SLIC_EN               BIT(16)
 167 +#define AR71XX_GPIO_FUNC_SPI_CS2_EN            BIT(13)
 168 +#define AR71XX_GPIO_FUNC_SPI_CS1_EN            BIT(12)
 169 +#define AR71XX_GPIO_FUNC_UART_EN               BIT(8)
 170 +#define AR71XX_GPIO_FUNC_USB_OC_EN             BIT(4)
 171 +#define AR71XX_GPIO_FUNC_USB_CLK_EN            BIT(0)
 172 +
 173 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN                BIT(19)
 174 +#define AR724X_GPIO_FUNC_SPI_EN                        BIT(18)
 175 +#define AR724X_GPIO_FUNC_SPI_CS_EN2            BIT(14)
 176 +#define AR724X_GPIO_FUNC_SPI_CS_EN1            BIT(13)
 177 +#define AR724X_GPIO_FUNC_CLK_OBS5_EN           BIT(12)
 178 +#define AR724X_GPIO_FUNC_CLK_OBS4_EN           BIT(11)
 179 +#define AR724X_GPIO_FUNC_CLK_OBS3_EN           BIT(10)
 180 +#define AR724X_GPIO_FUNC_CLK_OBS2_EN           BIT(9)
 181 +#define AR724X_GPIO_FUNC_CLK_OBS1_EN           BIT(8)
 182 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN    BIT(7)
 183 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN    BIT(6)
 184 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN    BIT(5)
 185 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN    BIT(4)
 186 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN    BIT(3)
 187 +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN       BIT(2)
 188 +#define AR724X_GPIO_FUNC_UART_EN               BIT(1)
 189 +#define AR724X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
 190 +
 191 +#define AR913X_GPIO_FUNC_WMAC_LED_EN           BIT(22)
 192 +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN                BIT(21)
 193 +#define AR913X_GPIO_FUNC_I2S_REFCLKEN          BIT(20)
 194 +#define AR913X_GPIO_FUNC_I2S_MCKEN             BIT(19)
 195 +#define AR913X_GPIO_FUNC_I2S1_EN               BIT(18)
 196 +#define AR913X_GPIO_FUNC_I2S0_EN               BIT(17)
 197 +#define AR913X_GPIO_FUNC_SLIC_EN               BIT(16)
 198 +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN                BIT(9)
 199 +#define AR913X_GPIO_FUNC_UART_EN               BIT(8)
 200 +#define AR913X_GPIO_FUNC_USB_CLK_EN            BIT(4)
 201 +
 202 +#define AR933X_GPIO_FUNC_SPDIF2TCK             BIT(31)
 203 +#define AR933X_GPIO_FUNC_SPDIF_EN              BIT(30)
 204 +#define AR933X_GPIO_FUNC_I2SO_22_18_EN         BIT(29)
 205 +#define AR933X_GPIO_FUNC_I2S_MCK_EN            BIT(27)
 206 +#define AR933X_GPIO_FUNC_I2SO_EN               BIT(26)
 207 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL   BIT(25)
 208 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL   BIT(24)
 209 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT    BIT(23)
 210 +#define AR933X_GPIO_FUNC_SPI_EN                        BIT(18)
 211 +#define AR933X_GPIO_FUNC_SPI_CS_EN2            BIT(14)
 212 +#define AR933X_GPIO_FUNC_SPI_CS_EN1            BIT(13)
 213 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN    BIT(7)
 214 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN    BIT(6)
 215 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN    BIT(5)
 216 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN    BIT(4)
 217 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN    BIT(3)
 218 +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN       BIT(2)
 219 +#define AR933X_GPIO_FUNC_UART_EN               BIT(1)
 220 +#define AR933X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
 221 +
 222 +#define AR934X_GPIO_FUNC_DDR_DQOE_EN   BIT(17)
 223 +#define AR934X_GPIO_FUNC_SPI_CS_1_EN   BIT(14)
 224 +#define AR934X_GPIO_FUNC_SPI_CS_0_EN   BIT(13)
 225 +
 226 +#define AR934X_GPIO_OUT_GPIO           0x00
 227 +
 228 +/*
 229 + * MII_CTRL block
 230 + */
 231 +#define AR71XX_MII_REG_MII0_CTRL       0x00
 232 +#define AR71XX_MII_REG_MII1_CTRL       0x04
 233 +
 234 +#define AR71XX_MII_CTRL_IF_MASK                3
 235 +#define AR71XX_MII_CTRL_SPEED_SHIFT    4
 236 +#define AR71XX_MII_CTRL_SPEED_MASK     3
 237 +#define AR71XX_MII_CTRL_SPEED_10       0
 238 +#define AR71XX_MII_CTRL_SPEED_100      1
 239 +#define AR71XX_MII_CTRL_SPEED_1000     2
 240 +
 241 +#define AR71XX_MII0_CTRL_IF_GMII       0
 242 +#define AR71XX_MII0_CTRL_IF_MII                1
 243 +#define AR71XX_MII0_CTRL_IF_RGMII      2
 244 +#define AR71XX_MII0_CTRL_IF_RMII       3
 245 +
 246 +#define AR71XX_MII1_CTRL_IF_RGMII      0
 247 +#define AR71XX_MII1_CTRL_IF_RMII       1
 248 +
 249 +/*
 250 + * AR933X GMAC interface
 251 + */
 252 +#define AR933X_GMAC_REG_ETH_CFG                0x00
 253 +
 254 +#define AR933X_ETH_CFG_RGMII_GE0       BIT(0)
 255 +#define AR933X_ETH_CFG_MII_GE0         BIT(1)
 256 +#define AR933X_ETH_CFG_GMII_GE0                BIT(2)
 257 +#define AR933X_ETH_CFG_MII_GE0_MASTER  BIT(3)
 258 +#define AR933X_ETH_CFG_MII_GE0_SLAVE   BIT(4)
 259 +#define AR933X_ETH_CFG_MII_GE0_ERR_EN  BIT(5)
 260 +#define AR933X_ETH_CFG_SW_PHY_SWAP     BIT(7)
 261 +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP        BIT(8)
 262 +#define AR933X_ETH_CFG_RMII_GE0                BIT(9)
 263 +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
 264 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100        BIT(10)
 265 +
 266 +/*
 267 + * AR934X GMAC Interface
 268 + */
 269 +#define AR934X_GMAC_REG_ETH_CFG                0x00
 270 +
 271 +#define AR934X_ETH_CFG_RGMII_GMAC0     BIT(0)
 272 +#define AR934X_ETH_CFG_MII_GMAC0       BIT(1)
 273 +#define AR934X_ETH_CFG_GMII_GMAC0      BIT(2)
 274 +#define AR934X_ETH_CFG_MII_GMAC0_MASTER        BIT(3)
 275 +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
 276 +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN        BIT(5)
 277 +#define AR934X_ETH_CFG_SW_ONLY_MODE    BIT(6)
 278 +#define AR934X_ETH_CFG_SW_PHY_SWAP     BIT(7)
 279 +#define AR934X_ETH_CFG_SW_APB_ACCESS   BIT(9)
 280 +#define AR934X_ETH_CFG_RMII_GMAC0      BIT(10)
 281 +#define AR933X_ETH_CFG_MII_CNTL_SPEED  BIT(11)
 282 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
 283 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST        BIT(13)
 284 +
 285 +/*
 286 + * QCA955X GMAC Interface
 287 + */
 288 +
 289 +#define QCA955X_GMAC_REG_ETH_CFG       0x00
 290 +
 291 +#define QCA955X_ETH_CFG_RGMII_GMAC0    BIT(0)
 292 +#define QCA955X_ETH_CFG_SGMII_GMAC0    BIT(6)
 293 +
 294  #endif /* __ASM_MACH_AR71XX_REGS_H */