target/linux/ipq806x/patches-4.9/0035-clk-mux-Split-out-register-accessors-for-reuse.patch

   1 From 9d381d65eae163d8f50d97a3ad9033bba176f62b Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 20 Mar 2015 23:45:21 -0700
   4 Subject: [PATCH 35/69] clk: mux: Split out register accessors for reuse
   5
   6 We want to reuse the logic in clk-mux.c for other clock drivers
   7 that don't use readl as register accessors. Fortunately, there
   8 really isn't much to the mux code besides the table indirection
   9 and quirk flags if you assume any bit shifting and masking has
  10 been done already. Pull that logic out into reusable functions
  11 that operate on an optional table and some flags so that other
  12 drivers can use the same logic.
  13
  14 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  15 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
  16 ---
  17  drivers/clk/clk-mux.c        | 76 ++++++++++++++++++++++++++++----------------
  18  include/linux/clk-provider.h | 11 +++++--
  19  2 files changed, 57 insertions(+), 30 deletions(-)
  20
  21 --- a/drivers/clk/clk-mux.c
  22 +++ b/drivers/clk/clk-mux.c
  23 @@ -26,35 +26,27 @@
  24   * parent - parent is adjustable through clk_set_parent
  25   */
  26
  27 -static u8 clk_mux_get_parent(struct clk_hw *hw)
  28 +#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
  29 +
  30 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
  31 +                               unsigned int *table, unsigned long flags)
  32  {
  33         struct clk_mux *mux = to_clk_mux(hw);
  34         int num_parents = clk_hw_get_num_parents(hw);
  35 -       u32 val;
  36
  37 -       /*
  38 -        * FIXME need a mux-specific flag to determine if val is bitwise or numeric
  39 -        * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
  40 -        * to 0x7 (index starts at one)
  41 -        * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  42 -        * val = 0x4 really means "bit 2, index starts at bit 0"
  43 -        */
  44 -       val = clk_readl(mux->reg) >> mux->shift;
  45 -       val &= mux->mask;
  46 -
  47 -       if (mux->table) {
  48 +       if (table) {
  49                 int i;
  50
  51                 for (i = 0; i < num_parents; i++)
  52 -                       if (mux->table[i] == val)
  53 +                       if (table[i] == val)
  54                                 return i;
  55                 return -EINVAL;
  56         }
  57
  58 -       if (val && (mux->flags & CLK_MUX_INDEX_BIT))
  59 +       if (val && (flags & CLK_MUX_INDEX_BIT))
  60                 val = ffs(val) - 1;
  61
  62 -       if (val && (mux->flags & CLK_MUX_INDEX_ONE))
  63 +       if (val && (flags & CLK_MUX_INDEX_ONE))
  64                 val--;
  65
  66         if (val >= num_parents)
  67 @@ -62,23 +54,53 @@ static u8 clk_mux_get_parent(struct clk_
  68
  69         return val;
  70  }
  71 +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
  72
  73 -static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
  74 +static u8 _clk_mux_get_parent(struct clk_hw *hw)
  75  {
  76         struct clk_mux *mux = to_clk_mux(hw);
  77         u32 val;
  78 -       unsigned long flags = 0;
  79
  80 -       if (mux->table) {
  81 -               index = mux->table[index];
  82 +       /*
  83 +        * FIXME need a mux-specific flag to determine if val is bitwise or numeric
  84 +        * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
  85 +        * to 0x7 (index starts at one)
  86 +        * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  87 +        * val = 0x4 really means "bit 2, index starts at bit 0"
  88 +        */
  89 +       val = clk_readl(mux->reg) >> mux->shift;
  90 +       val &= mux->mask;
  91 +
  92 +       return clk_mux_get_parent(hw, val, mux->table, mux->flags);
  93 +}
  94 +
  95 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
  96 +                            unsigned long flags)
  97 +{
  98 +       unsigned int val = index;
  99 +
 100 +       if (table) {
 101 +               val = table[val];
 102         } else {
 103 -               if (mux->flags & CLK_MUX_INDEX_BIT)
 104 -                       index = 1 << index;
 105 +               if (flags & CLK_MUX_INDEX_BIT)
 106 +                       val = 1 << index;
 107
 108 -               if (mux->flags & CLK_MUX_INDEX_ONE)
 109 -                       index++;
 110 +               if (flags & CLK_MUX_INDEX_ONE)
 111 +                       val++;
 112         }
 113
 114 +       return val;
 115 +}
 116 +EXPORT_SYMBOL_GPL(clk_mux_reindex);
 117 +
 118 +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 119 +{
 120 +       struct clk_mux *mux = to_clk_mux(hw);
 121 +       u32 val;
 122 +       unsigned long flags = 0;
 123 +
 124 +       index = clk_mux_reindex(index, mux->table, mux->flags);
 125 +
 126         if (mux->lock)
 127                 spin_lock_irqsave(mux->lock, flags);
 128         else
 129 @@ -102,14 +124,14 @@ static int clk_mux_set_parent(struct clk
 130  }
 131
 132  const struct clk_ops clk_mux_ops = {
 133 -       .get_parent = clk_mux_get_parent,
 134 +       .get_parent = _clk_mux_get_parent,
 135         .set_parent = clk_mux_set_parent,
 136         .determine_rate = __clk_mux_determine_rate,
 137  };
 138  EXPORT_SYMBOL_GPL(clk_mux_ops);
 139
 140  const struct clk_ops clk_mux_ro_ops = {
 141 -       .get_parent = clk_mux_get_parent,
 142 +       .get_parent = _clk_mux_get_parent,
 143  };
 144  EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
 145
 146 @@ -117,7 +139,7 @@ struct clk_hw *clk_hw_register_mux_table
 147                 const char * const *parent_names, u8 num_parents,
 148                 unsigned long flags,
 149                 void __iomem *reg, u8 shift, u32 mask,
 150 -               u8 clk_mux_flags, u32 *table, spinlock_t *lock)
 151 +               u8 clk_mux_flags, unsigned int *table, spinlock_t *lock)
 152  {
 153         struct clk_mux *mux;
 154         struct clk_hw *hw;
 155 --- a/include/linux/clk-provider.h
 156 +++ b/include/linux/clk-provider.h
 157 @@ -466,7 +466,7 @@ void clk_hw_unregister_divider(struct cl
 158  struct clk_mux {
 159         struct clk_hw   hw;
 160         void __iomem    *reg;
 161 -       u32             *table;
 162 +       unsigned int    *table;
 163         u32             mask;
 164         u8              shift;
 165         u8              flags;
 166 @@ -484,6 +484,11 @@ struct clk_mux {
 167  extern const struct clk_ops clk_mux_ops;
 168  extern const struct clk_ops clk_mux_ro_ops;
 169
 170 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
 171 +                               unsigned int *table, unsigned long flags);
 172 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
 173 +                            unsigned long flags);
 174 +
 175  struct clk *clk_register_mux(struct device *dev, const char *name,
 176                 const char * const *parent_names, u8 num_parents,
 177                 unsigned long flags,
 178 @@ -499,12 +504,12 @@ struct clk *clk_register_mux_table(struc
 179                 const char * const *parent_names, u8 num_parents,
 180                 unsigned long flags,
 181                 void __iomem *reg, u8 shift, u32 mask,
 182 -               u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 183 +               u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
 184  struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
 185                 const char * const *parent_names, u8 num_parents,
 186                 unsigned long flags,
 187                 void __iomem *reg, u8 shift, u32 mask,
 188 -               u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 189 +               u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
 190
 191  void clk_unregister_mux(struct clk *clk);
 192  void clk_hw_unregister_mux(struct clk_hw *hw);