package/b43/src/phy.h

   1 #ifndef B43_PHY_H_
   2 #define B43_PHY_H_
   3
   4 #include <linux/types.h>
   5
   6 struct b43_wldev;
   7 struct b43_phy;
   8
   9 /*** PHY Registers ***/
  10
  11 /* Routing */
  12 #define B43_PHYROUTE                    0x0C00 /* PHY register routing bits mask */
  13 #define  B43_PHYROUTE_BASE              0x0000 /* Base registers */
  14 #define  B43_PHYROUTE_OFDM_GPHY         0x0400 /* OFDM register routing for G-PHYs */
  15 #define  B43_PHYROUTE_EXT_GPHY          0x0800 /* Extended G-PHY registers */
  16 #define  B43_PHYROUTE_N_BMODE           0x0C00 /* N-PHY BMODE registers */
  17
  18 /* CCK (B-PHY) registers. */
  19 #define B43_PHY_CCK(reg)                ((reg) | B43_PHYROUTE_BASE)
  20 /* N-PHY registers. */
  21 #define B43_PHY_N(reg)                  ((reg) | B43_PHYROUTE_BASE)
  22 /* N-PHY BMODE registers. */
  23 #define B43_PHY_N_BMODE(reg)            ((reg) | B43_PHYROUTE_N_BMODE)
  24 /* OFDM (A-PHY) registers. */
  25 #define B43_PHY_OFDM(reg)               ((reg) | B43_PHYROUTE_OFDM_GPHY)
  26 /* Extended G-PHY registers. */
  27 #define B43_PHY_EXTG(reg)               ((reg) | B43_PHYROUTE_EXT_GPHY)
  28
  29 /* OFDM (A) PHY Registers */
  30 #define B43_PHY_VERSION_OFDM            B43_PHY_OFDM(0x00)      /* Versioning register for A-PHY */
  31 #define B43_PHY_BBANDCFG                B43_PHY_OFDM(0x01)      /* Baseband config */
  32 #define  B43_PHY_BBANDCFG_RXANT         0x180   /* RX Antenna selection */
  33 #define  B43_PHY_BBANDCFG_RXANT_SHIFT   7
  34 #define B43_PHY_PWRDOWN                 B43_PHY_OFDM(0x03)      /* Powerdown */
  35 #define B43_PHY_CRSTHRES1_R1            B43_PHY_OFDM(0x06)      /* CRS Threshold 1 (phy.rev 1 only) */
  36 #define B43_PHY_LNAHPFCTL               B43_PHY_OFDM(0x1C)      /* LNA/HPF control */
  37 #define B43_PHY_LPFGAINCTL              B43_PHY_OFDM(0x20)      /* LPF Gain control */
  38 #define B43_PHY_ADIVRELATED             B43_PHY_OFDM(0x27)      /* FIXME rename */
  39 #define B43_PHY_CRS0                    B43_PHY_OFDM(0x29)
  40 #define  B43_PHY_CRS0_EN                0x4000
  41 #define B43_PHY_PEAK_COUNT              B43_PHY_OFDM(0x30)
  42 #define B43_PHY_ANTDWELL                B43_PHY_OFDM(0x2B)      /* Antenna dwell */
  43 #define  B43_PHY_ANTDWELL_AUTODIV1      0x0100  /* Automatic RX diversity start antenna */
  44 #define B43_PHY_ENCORE                  B43_PHY_OFDM(0x49)      /* "Encore" (RangeMax / BroadRange) */
  45 #define  B43_PHY_ENCORE_EN              0x0200  /* Encore enable */
  46 #define B43_PHY_LMS                     B43_PHY_OFDM(0x55)
  47 #define B43_PHY_OFDM61                  B43_PHY_OFDM(0x61)      /* FIXME rename */
  48 #define  B43_PHY_OFDM61_10              0x0010  /* FIXME rename */
  49 #define B43_PHY_IQBAL                   B43_PHY_OFDM(0x69)      /* I/Q balance */
  50 #define B43_PHY_BBTXDC_BIAS             B43_PHY_OFDM(0x6B)      /* Baseband TX DC bias */
  51 #define B43_PHY_OTABLECTL               B43_PHY_OFDM(0x72)      /* OFDM table control (see below) */
  52 #define  B43_PHY_OTABLEOFF              0x03FF  /* OFDM table offset (see below) */
  53 #define  B43_PHY_OTABLENR               0xFC00  /* OFDM table number (see below) */
  54 #define  B43_PHY_OTABLENR_SHIFT         10
  55 #define B43_PHY_OTABLEI                 B43_PHY_OFDM(0x73)      /* OFDM table data I */
  56 #define B43_PHY_OTABLEQ                 B43_PHY_OFDM(0x74)      /* OFDM table data Q */
  57 #define B43_PHY_HPWR_TSSICTL            B43_PHY_OFDM(0x78)      /* Hardware power TSSI control */
  58 #define B43_PHY_ADCCTL                  B43_PHY_OFDM(0x7A)      /* ADC control */
  59 #define B43_PHY_IDLE_TSSI               B43_PHY_OFDM(0x7B)
  60 #define B43_PHY_A_TEMP_SENSE            B43_PHY_OFDM(0x7C)      /* A PHY temperature sense */
  61 #define B43_PHY_NRSSITHRES              B43_PHY_OFDM(0x8A)      /* NRSSI threshold */
  62 #define B43_PHY_ANTWRSETT               B43_PHY_OFDM(0x8C)      /* Antenna WR settle */
  63 #define  B43_PHY_ANTWRSETT_ARXDIV       0x2000  /* Automatic RX diversity enabled */
  64 #define B43_PHY_CLIPPWRDOWNT            B43_PHY_OFDM(0x93)      /* Clip powerdown threshold */
  65 #define B43_PHY_OFDM9B                  B43_PHY_OFDM(0x9B)      /* FIXME rename */
  66 #define B43_PHY_N1P1GAIN                B43_PHY_OFDM(0xA0)
  67 #define B43_PHY_P1P2GAIN                B43_PHY_OFDM(0xA1)
  68 #define B43_PHY_N1N2GAIN                B43_PHY_OFDM(0xA2)
  69 #define B43_PHY_CLIPTHRES               B43_PHY_OFDM(0xA3)
  70 #define B43_PHY_CLIPN1P2THRES           B43_PHY_OFDM(0xA4)
  71 #define B43_PHY_CCKSHIFTBITS_WA         B43_PHY_OFDM(0xA5)      /* CCK shiftbits workaround, FIXME rename */
  72 #define B43_PHY_CCKSHIFTBITS            B43_PHY_OFDM(0xA7)      /* FIXME rename */
  73 #define B43_PHY_DIVSRCHIDX              B43_PHY_OFDM(0xA8)      /* Divider search gain/index */
  74 #define B43_PHY_CLIPP2THRES             B43_PHY_OFDM(0xA9)
  75 #define B43_PHY_CLIPP3THRES             B43_PHY_OFDM(0xAA)
  76 #define B43_PHY_DIVP1P2GAIN             B43_PHY_OFDM(0xAB)
  77 #define B43_PHY_DIVSRCHGAINBACK         B43_PHY_OFDM(0xAD)      /* Divider search gain back */
  78 #define B43_PHY_DIVSRCHGAINCHNG         B43_PHY_OFDM(0xAE)      /* Divider search gain change */
  79 #define B43_PHY_CRSTHRES1               B43_PHY_OFDM(0xC0)      /* CRS Threshold 1 (phy.rev >= 2 only) */
  80 #define B43_PHY_CRSTHRES2               B43_PHY_OFDM(0xC1)      /* CRS Threshold 2 (phy.rev >= 2 only) */
  81 #define B43_PHY_TSSIP_LTBASE            B43_PHY_OFDM(0x380)     /* TSSI power lookup table base */
  82 #define B43_PHY_DC_LTBASE               B43_PHY_OFDM(0x3A0)     /* DC lookup table base */
  83 #define B43_PHY_GAIN_LTBASE             B43_PHY_OFDM(0x3C0)     /* Gain lookup table base */
  84
  85 /* CCK (B) PHY Registers */
  86 #define B43_PHY_VERSION_CCK             B43_PHY_CCK(0x00)       /* Versioning register for B-PHY */
  87 #define B43_PHY_CCKBBANDCFG             B43_PHY_CCK(0x01)       /* Contains antenna 0/1 control bit */
  88 #define B43_PHY_PGACTL                  B43_PHY_CCK(0x15)       /* PGA control */
  89 #define  B43_PHY_PGACTL_LPF             0x1000  /* Low pass filter (?) */
  90 #define  B43_PHY_PGACTL_LOWBANDW        0x0040  /* Low bandwidth flag */
  91 #define  B43_PHY_PGACTL_UNKNOWN         0xEFA0
  92 #define B43_PHY_FBCTL1                  B43_PHY_CCK(0x18)       /* Frequency bandwidth control 1 */
  93 #define B43_PHY_ITSSI                   B43_PHY_CCK(0x29)       /* Idle TSSI */
  94 #define B43_PHY_LO_LEAKAGE              B43_PHY_CCK(0x2D)       /* Measured LO leakage */
  95 #define B43_PHY_ENERGY                  B43_PHY_CCK(0x33)       /* Energy */
  96 #define B43_PHY_SYNCCTL                 B43_PHY_CCK(0x35)
  97 #define B43_PHY_FBCTL2                  B43_PHY_CCK(0x38)       /* Frequency bandwidth control 2 */
  98 #define B43_PHY_DACCTL                  B43_PHY_CCK(0x60)       /* DAC control */
  99 #define B43_PHY_RCCALOVER               B43_PHY_CCK(0x78)       /* RC calibration override */
 100
 101 /* Extended G-PHY Registers */
 102 #define B43_PHY_CLASSCTL                B43_PHY_EXTG(0x02)      /* Classify control */
 103 #define B43_PHY_GTABCTL                 B43_PHY_EXTG(0x03)      /* G-PHY table control (see below) */
 104 #define  B43_PHY_GTABOFF                0x03FF  /* G-PHY table offset (see below) */
 105 #define  B43_PHY_GTABNR                 0xFC00  /* G-PHY table number (see below) */
 106 #define  B43_PHY_GTABNR_SHIFT           10
 107 #define B43_PHY_GTABDATA                B43_PHY_EXTG(0x04)      /* G-PHY table data */
 108 #define B43_PHY_LO_MASK                 B43_PHY_EXTG(0x0F)      /* Local Oscillator control mask */
 109 #define B43_PHY_LO_CTL                  B43_PHY_EXTG(0x10)      /* Local Oscillator control */
 110 #define B43_PHY_RFOVER                  B43_PHY_EXTG(0x11)      /* RF override */
 111 #define B43_PHY_RFOVERVAL               B43_PHY_EXTG(0x12)      /* RF override value */
 112 #define  B43_PHY_RFOVERVAL_EXTLNA       0x8000
 113 #define  B43_PHY_RFOVERVAL_LNA          0x7000
 114 #define  B43_PHY_RFOVERVAL_LNA_SHIFT    12
 115 #define  B43_PHY_RFOVERVAL_PGA          0x0F00
 116 #define  B43_PHY_RFOVERVAL_PGA_SHIFT    8
 117 #define  B43_PHY_RFOVERVAL_UNK          0x0010  /* Unknown, always set. */
 118 #define  B43_PHY_RFOVERVAL_TRSWRX       0x00E0
 119 #define  B43_PHY_RFOVERVAL_BW           0x0003  /* Bandwidth flags */
 120 #define   B43_PHY_RFOVERVAL_BW_LPF      0x0001  /* Low Pass Filter */
 121 #define   B43_PHY_RFOVERVAL_BW_LBW      0x0002  /* Low Bandwidth (when set), high when unset */
 122 #define B43_PHY_ANALOGOVER              B43_PHY_EXTG(0x14)      /* Analog override */
 123 #define B43_PHY_ANALOGOVERVAL           B43_PHY_EXTG(0x15)      /* Analog override value */
 124
 125 /*** OFDM table numbers ***/
 126 #define B43_OFDMTAB(number, offset)     (((number) << B43_PHY_OTABLENR_SHIFT) | (offset))
 127 #define B43_OFDMTAB_AGC1                B43_OFDMTAB(0x00, 0)
 128 #define B43_OFDMTAB_GAIN0               B43_OFDMTAB(0x00, 0)
 129 #define B43_OFDMTAB_GAINX               B43_OFDMTAB(0x01, 0)    //TODO rename
 130 #define B43_OFDMTAB_GAIN1               B43_OFDMTAB(0x01, 4)
 131 #define B43_OFDMTAB_AGC3                B43_OFDMTAB(0x02, 0)
 132 #define B43_OFDMTAB_GAIN2               B43_OFDMTAB(0x02, 3)
 133 #define B43_OFDMTAB_LNAHPFGAIN1         B43_OFDMTAB(0x03, 0)
 134 #define B43_OFDMTAB_WRSSI               B43_OFDMTAB(0x04, 0)
 135 #define B43_OFDMTAB_LNAHPFGAIN2         B43_OFDMTAB(0x04, 0)
 136 #define B43_OFDMTAB_NOISESCALE          B43_OFDMTAB(0x05, 0)
 137 #define B43_OFDMTAB_AGC2                B43_OFDMTAB(0x06, 0)
 138 #define B43_OFDMTAB_ROTOR               B43_OFDMTAB(0x08, 0)
 139 #define B43_OFDMTAB_ADVRETARD           B43_OFDMTAB(0x09, 0)
 140 #define B43_OFDMTAB_DAC                 B43_OFDMTAB(0x0C, 0)
 141 #define B43_OFDMTAB_DC                  B43_OFDMTAB(0x0E, 7)
 142 #define B43_OFDMTAB_PWRDYN2             B43_OFDMTAB(0x0E, 12)
 143 #define B43_OFDMTAB_LNAGAIN             B43_OFDMTAB(0x0E, 13)
 144 #define B43_OFDMTAB_UNKNOWN_0F          B43_OFDMTAB(0x0F, 0)    //TODO rename
 145 #define B43_OFDMTAB_UNKNOWN_APHY        B43_OFDMTAB(0x0F, 7)    //TODO rename
 146 #define B43_OFDMTAB_LPFGAIN             B43_OFDMTAB(0x0F, 12)
 147 #define B43_OFDMTAB_RSSI                B43_OFDMTAB(0x10, 0)
 148 #define B43_OFDMTAB_UNKNOWN_11          B43_OFDMTAB(0x11, 4)    //TODO rename
 149 #define B43_OFDMTAB_AGC1_R1             B43_OFDMTAB(0x13, 0)
 150 #define B43_OFDMTAB_GAINX_R1            B43_OFDMTAB(0x14, 0)    //TODO remove!
 151 #define B43_OFDMTAB_MINSIGSQ            B43_OFDMTAB(0x14, 0)
 152 #define B43_OFDMTAB_AGC3_R1             B43_OFDMTAB(0x15, 0)
 153 #define B43_OFDMTAB_WRSSI_R1            B43_OFDMTAB(0x15, 4)
 154 #define B43_OFDMTAB_TSSI                B43_OFDMTAB(0x15, 0)
 155 #define B43_OFDMTAB_DACRFPABB           B43_OFDMTAB(0x16, 0)
 156 #define B43_OFDMTAB_DACOFF              B43_OFDMTAB(0x17, 0)
 157 #define B43_OFDMTAB_DCBIAS              B43_OFDMTAB(0x18, 0)
 158
 159 u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
 160 void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
 161                          u16 offset, u16 value);
 162 u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
 163 void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
 164                          u16 offset, u32 value);
 165
 166 /*** G-PHY table numbers */
 167 #define B43_GTAB(number, offset)        (((number) << B43_PHY_GTABNR_SHIFT) | (offset))
 168 #define B43_GTAB_NRSSI                  B43_GTAB(0x00, 0)
 169 #define B43_GTAB_TRFEMW                 B43_GTAB(0x0C, 0x120)
 170 #define B43_GTAB_ORIGTR                 B43_GTAB(0x2E, 0x298)
 171
 172 u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset);        //TODO implement
 173 void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value);   //TODO implement
 174
 175 #define B43_DEFAULT_CHANNEL_A   36
 176 #define B43_DEFAULT_CHANNEL_BG  6
 177
 178 enum {
 179         B43_ANTENNA0,           /* Antenna 0 */
 180         B43_ANTENNA1,           /* Antenna 0 */
 181         B43_ANTENNA_AUTO1,      /* Automatic, starting with antenna 1 */
 182         B43_ANTENNA_AUTO0,      /* Automatic, starting with antenna 0 */
 183         B43_ANTENNA2,
 184         B43_ANTENNA3 = 8,
 185
 186         B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
 187         B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
 188 };
 189
 190 enum {
 191         B43_INTERFMODE_NONE,
 192         B43_INTERFMODE_NONWLAN,
 193         B43_INTERFMODE_MANUALWLAN,
 194         B43_INTERFMODE_AUTOWLAN,
 195 };
 196
 197 /* Masks for the different PHY versioning registers. */
 198 #define B43_PHYVER_ANALOG               0xF000
 199 #define B43_PHYVER_ANALOG_SHIFT         12
 200 #define B43_PHYVER_TYPE                 0x0F00
 201 #define B43_PHYVER_TYPE_SHIFT           8
 202 #define B43_PHYVER_VERSION              0x00FF
 203
 204 void b43_phy_lock(struct b43_wldev *dev);
 205 void b43_phy_unlock(struct b43_wldev *dev);
 206
 207
 208 /* Read a value from a PHY register */
 209 u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
 210 /* Write a value to a PHY register */
 211 void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);
 212 /* Mask a PHY register with a mask */
 213 void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask);
 214 /* OR a PHY register with a bitmap */
 215 void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set);
 216 /* Mask and OR a PHY register with a mask and bitmap */
 217 void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
 218
 219
 220 int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev);
 221
 222 void b43_phy_early_init(struct b43_wldev *dev);
 223 int b43_phy_init(struct b43_wldev *dev);
 224
 225 void b43_set_rx_antenna(struct b43_wldev *dev, int antenna);
 226
 227 void b43_phy_xmitpower(struct b43_wldev *dev);
 228 void b43_gphy_dc_lt_init(struct b43_wldev *dev);
 229
 230 /* Returns the boolean whether the board has HardwarePowerControl */
 231 bool b43_has_hardware_pctl(struct b43_phy *phy);
 232 /* Returns the boolean whether "TX Magnification" is enabled. */
 233 #define has_tx_magnification(phy) \
 234         (((phy)->rev >= 2) &&                   \
 235          ((phy)->radio_ver == 0x2050) &&        \
 236          ((phy)->radio_rev == 8))
 237 /* Card uses the loopback gain stuff */
 238 #define has_loopback_gain(phy) \
 239         (((phy)->rev > 1) || ((phy)->gmode))
 240
 241 /* Radio Attenuation (RF Attenuation) */
 242 struct b43_rfatt {
 243         u8 att;                 /* Attenuation value */
 244         bool with_padmix;       /* Flag, PAD Mixer enabled. */
 245 };
 246 struct b43_rfatt_list {
 247         /* Attenuation values list */
 248         const struct b43_rfatt *list;
 249         u8 len;
 250         /* Minimum/Maximum attenuation values */
 251         u8 min_val;
 252         u8 max_val;
 253 };
 254
 255 /* Baseband Attenuation */
 256 struct b43_bbatt {
 257         u8 att;                 /* Attenuation value */
 258 };
 259 struct b43_bbatt_list {
 260         /* Attenuation values list */
 261         const struct b43_bbatt *list;
 262         u8 len;
 263         /* Minimum/Maximum attenuation values */
 264         u8 min_val;
 265         u8 max_val;
 266 };
 267
 268 /* tx_control bits. */
 269 #define B43_TXCTL_PA3DB         0x40    /* PA Gain 3dB */
 270 #define B43_TXCTL_PA2DB         0x20    /* PA Gain 2dB */
 271 #define B43_TXCTL_TXMIX         0x10    /* TX Mixer Gain */
 272
 273 /* Write BasebandAttenuation value to the device. */
 274 void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
 275                                       u16 baseband_attenuation);
 276
 277 extern const u8 b43_radio_channel_codes_bg[];
 278
 279 void b43_radio_lock(struct b43_wldev *dev);
 280 void b43_radio_unlock(struct b43_wldev *dev);
 281
 282
 283 /* Read a value from a 16bit radio register */
 284 u16 b43_radio_read16(struct b43_wldev *dev, u16 offset);
 285 /* Write a value to a 16bit radio register */
 286 void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val);
 287 /* Mask a 16bit radio register with a mask */
 288 void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask);
 289 /* OR a 16bit radio register with a bitmap */
 290 void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set);
 291 /* Mask and OR a PHY register with a mask and bitmap */
 292 void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
 293
 294
 295 u16 b43_radio_init2050(struct b43_wldev *dev);
 296 void b43_radio_init2060(struct b43_wldev *dev);
 297
 298 void b43_radio_turn_on(struct b43_wldev *dev);
 299 void b43_radio_turn_off(struct b43_wldev *dev, bool force);
 300
 301 int b43_radio_selectchannel(struct b43_wldev *dev, u8 channel,
 302                             int synthetic_pu_workaround);
 303
 304 u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel);
 305 u8 b43_radio_aci_scan(struct b43_wldev *dev);
 306
 307 int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode);
 308
 309 void b43_calc_nrssi_slope(struct b43_wldev *dev);
 310 void b43_calc_nrssi_threshold(struct b43_wldev *dev);
 311 s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset);
 312 void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val);
 313 void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val);
 314 void b43_nrssi_mem_update(struct b43_wldev *dev);
 315
 316 void b43_radio_set_tx_iq(struct b43_wldev *dev);
 317 u16 b43_radio_calibrationvalue(struct b43_wldev *dev);
 318
 319 void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
 320                                      int *_bbatt, int *_rfatt);
 321
 322 void b43_set_txpower_g(struct b43_wldev *dev,
 323                        const struct b43_bbatt *bbatt,
 324                        const struct b43_rfatt *rfatt, u8 tx_control);
 325
 326 #endif /* B43_PHY_H_ */