target/linux/ar7/files/arch/mips/ar7/clock.c

   1 /*
   2  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
   3  * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/types.h>
  22 #include <linux/module.h>
  23 #include <linux/delay.h>
  24 #include <asm/addrspace.h>
  25 #include <asm/io.h>
  26 #include <asm/ar7/ar7.h>
  27
  28 #define BOOT_PLL_SOURCE_MASK    0x3
  29 #define CPU_PLL_SOURCE_SHIFT    16
  30 #define BUS_PLL_SOURCE_SHIFT    14
  31 #define USB_PLL_SOURCE_SHIFT    18
  32 #define DSP_PLL_SOURCE_SHIFT    22
  33 #define BOOT_PLL_SOURCE_AFE     0
  34 #define BOOT_PLL_SOURCE_BUS     0
  35 #define BOOT_PLL_SOURCE_REF     1
  36 #define BOOT_PLL_SOURCE_XTAL    2
  37 #define BOOT_PLL_SOURCE_CPU     3
  38 #define BOOT_PLL_BYPASS         0x00000020
  39 #define BOOT_PLL_ASYNC_MODE     0x02000000
  40 #define BOOT_PLL_2TO1_MODE      0x00008000
  41
  42 #define TNETD7200_CLOCK_ID_CPU  0
  43 #define TNETD7200_CLOCK_ID_DSP  1
  44 #define TNETD7200_CLOCK_ID_USB  2
  45
  46 #define TNETD7200_DEF_CPU_CLK   211000000
  47 #define TNETD7200_DEF_DSP_CLK   125000000
  48 #define TNETD7200_DEF_USB_CLK   48000000
  49
  50 struct tnetd7300_clock {
  51         u32 ctrl;
  52 #define PREDIV_MASK     0x001f0000
  53 #define PREDIV_SHIFT    16
  54 #define POSTDIV_MASK    0x0000001f
  55         u32 unused1[3];
  56         u32 pll;
  57 #define MUL_MASK        0x0000f000
  58 #define MUL_SHIFT       12
  59 #define PLL_MODE_MASK   0x00000001
  60 #define PLL_NDIV        0x00000800
  61 #define PLL_DIV         0x00000002
  62 #define PLL_STATUS      0x00000001
  63         u32 unused2[3];
  64 };
  65
  66 struct tnetd7300_clocks {
  67         struct tnetd7300_clock bus;
  68         struct tnetd7300_clock cpu;
  69         struct tnetd7300_clock usb;
  70         struct tnetd7300_clock dsp;
  71 };
  72
  73 struct tnetd7200_clock {
  74         u32 ctrl;
  75         u32 unused1[3];
  76 #define DIVISOR_ENABLE_MASK 0x00008000
  77         u32 mul;
  78         u32 prediv;
  79         u32 postdiv;
  80         u32 postdiv2;
  81         u32 unused2[6];
  82         u32 cmd;
  83         u32 status;
  84         u32 cmden;
  85         u32 padding[15];
  86 };
  87
  88 struct tnetd7200_clocks {
  89         struct tnetd7200_clock cpu;
  90         struct tnetd7200_clock dsp;
  91         struct tnetd7200_clock usb;
  92 };
  93
  94 int ar7_cpu_clock = 150000000;
  95 EXPORT_SYMBOL(ar7_cpu_clock);
  96 int ar7_bus_clock = 125000000;
  97 EXPORT_SYMBOL(ar7_bus_clock);
  98 int ar7_dsp_clock;
  99 EXPORT_SYMBOL(ar7_dsp_clock);
 100
 101 static int gcd(int a, int b)
 102 {
 103         int c;
 104
 105         if (a < b) {
 106                 c = a;
 107                 a = b;
 108                 b = c;
 109         }
 110         while ((c = (a % b))) {
 111                 a = b;
 112                 b = c;
 113         }
 114         return b;
 115 }
 116
 117 static void approximate(int base, int target, int *prediv,
 118                         int *postdiv, int *mul)
 119 {
 120         int i, j, k, freq, res = target;
 121         for (i = 1; i <= 16; i++)
 122                 for (j = 1; j <= 32; j++)
 123                         for (k = 1; k <= 32; k++) {
 124                                 freq = abs(base / j * i / k - target);
 125                                 if (freq < res) {
 126                                         res = freq;
 127                                         *mul = i;
 128                                         *prediv = j;
 129                                         *postdiv = k;
 130                                 }
 131                         }
 132 }
 133
 134 static void calculate(int base, int target, int *prediv, int *postdiv,
 135         int *mul)
 136 {
 137         int tmp_gcd, tmp_base, tmp_freq;
 138
 139         for (*prediv = 1; *prediv <= 32; (*prediv)++) {
 140                 tmp_base = base / *prediv;
 141                 tmp_gcd = gcd(target, tmp_base);
 142                 *mul = target / tmp_gcd;
 143                 *postdiv = tmp_base / tmp_gcd;
 144                 if ((*mul < 1) || (*mul >= 16))
 145                         continue;
 146                 if ((*postdiv > 0) & (*postdiv <= 32))
 147                         break;
 148         }
 149
 150         if (base / (*prediv) * (*mul) / (*postdiv) != target) {
 151                 approximate(base, target, prediv, postdiv, mul);
 152                 tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
 153                 printk(KERN_WARNING
 154                        "Adjusted requested frequency %d to %d\n",
 155                        target, tmp_freq);
 156         }
 157
 158         printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
 159                *prediv, *postdiv, *mul);
 160 }
 161
 162 static int tnetd7300_dsp_clock(void)
 163 {
 164         u32 didr1, didr2;
 165         u8 rev = ar7_chip_rev();
 166         didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
 167         didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
 168         if (didr2 & (1 << 23))
 169                 return 0;
 170         if ((rev >= 0x23) && (rev != 0x57))
 171                 return 250000000;
 172         if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
 173             > 4208000)
 174                 return 250000000;
 175         return 0;
 176 }
 177
 178 static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
 179         u32 *bootcr, u32 bus_clock)
 180 {
 181         int product;
 182         int base_clock = AR7_REF_CLOCK;
 183         u32 ctrl = clock->ctrl;
 184         u32 pll = clock->pll;
 185         int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
 186         int postdiv = (ctrl & POSTDIV_MASK) + 1;
 187         int divisor = prediv * postdiv;
 188         int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
 189
 190         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
 191         case BOOT_PLL_SOURCE_BUS:
 192                 base_clock = bus_clock;
 193                 break;
 194         case BOOT_PLL_SOURCE_REF:
 195                 base_clock = AR7_REF_CLOCK;
 196                 break;
 197         case BOOT_PLL_SOURCE_XTAL:
 198                 base_clock = AR7_XTAL_CLOCK;
 199                 break;
 200         case BOOT_PLL_SOURCE_CPU:
 201                 base_clock = ar7_cpu_clock;
 202                 break;
 203         }
 204
 205         if (*bootcr & BOOT_PLL_BYPASS)
 206                 return base_clock / divisor;
 207
 208         if ((pll & PLL_MODE_MASK) == 0)
 209                 return (base_clock >> (mul / 16 + 1)) / divisor;
 210
 211         if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
 212                 product = (mul & 1) ?
 213                         (base_clock * mul) >> 1 :
 214                         (base_clock * (mul - 1)) >> 2;
 215                 return product / divisor;
 216         }
 217
 218         if (mul == 16)
 219                 return base_clock / divisor;
 220
 221         return base_clock * mul / divisor;
 222 }
 223
 224 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
 225         u32 *bootcr, u32 frequency)
 226 {
 227         u32 status;
 228         int prediv, postdiv, mul;
 229         int base_clock = ar7_bus_clock;
 230
 231         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
 232         case BOOT_PLL_SOURCE_BUS:
 233                 base_clock = ar7_bus_clock;
 234                 break;
 235         case BOOT_PLL_SOURCE_REF:
 236                 base_clock = AR7_REF_CLOCK;
 237                 break;
 238         case BOOT_PLL_SOURCE_XTAL:
 239                 base_clock = AR7_XTAL_CLOCK;
 240                 break;
 241         case BOOT_PLL_SOURCE_CPU:
 242                 base_clock = ar7_cpu_clock;
 243                 break;
 244         }
 245
 246         calculate(base_clock, frequency, &prediv, &postdiv, &mul);
 247
 248         clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
 249         mdelay(1);
 250         clock->pll = 4;
 251         do
 252                 status = clock->pll;
 253         while (status & PLL_STATUS);
 254         clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
 255         mdelay(75);
 256 }
 257
 258 static void __init tnetd7300_init_clocks(void)
 259 {
 260         u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 261         struct tnetd7300_clocks *clocks =
 262                                         (struct tnetd7300_clocks *)
 263                                         ioremap_nocache(AR7_REGS_POWER + 0x20,
 264                                         sizeof(struct tnetd7300_clocks));
 265
 266         ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
 267                 &clocks->bus, bootcr, AR7_AFE_CLOCK);
 268
 269         if (*bootcr & BOOT_PLL_ASYNC_MODE)
 270                 ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
 271                         &clocks->cpu, bootcr, AR7_AFE_CLOCK);
 272         else
 273                 ar7_cpu_clock = ar7_bus_clock;
 274 /*
 275         tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
 276                 bootcr, 48000000);
 277 */
 278         if (ar7_dsp_clock == 250000000)
 279                 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
 280                         bootcr, ar7_dsp_clock);
 281
 282         iounmap(clocks);
 283         iounmap(bootcr);
 284 }
 285
 286 static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
 287         u32 *bootcr, u32 bus_clock)
 288 {
 289         int divisor = ((clock->prediv & 0x1f) + 1) *
 290                 ((clock->postdiv & 0x1f) + 1);
 291
 292         if (*bootcr & BOOT_PLL_BYPASS)
 293                 return base / divisor;
 294
 295         return base * ((clock->mul & 0xf) + 1) / divisor;
 296 }
 297
 298
 299 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
 300         int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
 301 {
 302         printk(KERN_INFO
 303                 "Clocks: base = %d, frequency = %u, prediv = %d, "
 304                 "postdiv = %d, postdiv2 = %d, mul = %d\n",
 305                 base, frequency, prediv, postdiv, postdiv2, mul);
 306
 307         clock->ctrl = 0;
 308         clock->prediv = DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F);
 309         clock->mul = ((mul - 1) & 0xF);
 310
 311         for (mul = 0; mul < 2000; mul++) /* nop */;
 312
 313         while (clock->status & 0x1) /* nop */;
 314
 315         clock->postdiv = DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F);
 316
 317         clock->cmden |= 1;
 318         clock->cmd |= 1;
 319
 320         while (clock->status & 0x1) /* nop */;
 321
 322         clock->postdiv2 = DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F);
 323
 324         clock->cmden |= 1;
 325         clock->cmd |= 1;
 326
 327         while (clock->status & 0x1) /* nop */;
 328
 329         clock->ctrl |= 1;
 330 }
 331
 332 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
 333 {
 334         if (*bootcr & BOOT_PLL_ASYNC_MODE)
 335                 /* Async */
 336                 switch (clock_id) {
 337                 case TNETD7200_CLOCK_ID_DSP:
 338                         return AR7_REF_CLOCK;
 339                 default:
 340                         return AR7_AFE_CLOCK;
 341                 }
 342         else
 343                 /* Sync */
 344                 if (*bootcr & BOOT_PLL_2TO1_MODE)
 345                         /* 2:1 */
 346                         switch (clock_id) {
 347                         case TNETD7200_CLOCK_ID_DSP:
 348                                 return AR7_REF_CLOCK;
 349                         default:
 350                                 return AR7_AFE_CLOCK;
 351                         }
 352                 else
 353                         /* 1:1 */
 354                         return AR7_REF_CLOCK;
 355 }
 356
 357
 358 static void __init tnetd7200_init_clocks(void)
 359 {
 360         u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 361         struct tnetd7200_clocks *clocks =
 362                                         (struct tnetd7200_clocks *)
 363                                         ioremap_nocache(AR7_REGS_POWER + 0x80,
 364                                         sizeof(struct tnetd7200_clocks));
 365         int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
 366         int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
 367         int usb_base, usb_mul, usb_prediv, usb_postdiv;
 368
 369 /*
 370         Log from Fritz!Box 7170 Annex B:
 371
 372         CPU revision is: 00018448
 373         Clocks: Async mode
 374         Clocks: Setting DSP clock
 375         Clocks: prediv: 1, postdiv: 1, mul: 5
 376         Clocks: base = 25000000, frequency = 125000000, prediv = 1,
 377                         postdiv = 2, postdiv2 = 1, mul = 10
 378         Clocks: Setting CPU clock
 379         Adjusted requested frequency 211000000 to 211968000
 380         Clocks: prediv: 1, postdiv: 1, mul: 6
 381         Clocks: base = 35328000, frequency = 211968000, prediv = 1,
 382                         postdiv = 1, postdiv2 = -1, mul = 6
 383         Clocks: Setting USB clock
 384         Adjusted requested frequency 48000000 to 48076920
 385         Clocks: prediv: 13, postdiv: 1, mul: 5
 386         Clocks: base = 125000000, frequency = 48000000, prediv = 13,
 387                         postdiv = 1, postdiv2 = -1, mul = 5
 388
 389         DSL didn't work if you didn't set the postdiv 2:1 postdiv2 combination,
 390         driver hung on startup.
 391         Haven't tested this on a synchronous board,
 392         neither do i know what to do with ar7_dsp_clock
 393 */
 394
 395         cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
 396         dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
 397
 398         if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 399                 printk(KERN_INFO "Clocks: Async mode\n");
 400
 401                 printk(KERN_INFO "Clocks: Setting DSP clock\n");
 402                 calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
 403                         &dsp_prediv, &dsp_postdiv, &dsp_mul);
 404                 ar7_bus_clock =
 405                         ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
 406                 tnetd7200_set_clock(dsp_base, &clocks->dsp,
 407                         dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
 408                         ar7_bus_clock);
 409
 410                 printk(KERN_INFO "Clocks: Setting CPU clock\n");
 411                 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
 412                         &cpu_postdiv, &cpu_mul);
 413                 ar7_cpu_clock =
 414                         ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
 415                 tnetd7200_set_clock(cpu_base, &clocks->cpu,
 416                         cpu_prediv, cpu_postdiv, -1, cpu_mul,
 417                         ar7_cpu_clock);
 418
 419         } else
 420                 if (*bootcr & BOOT_PLL_2TO1_MODE) {
 421                         printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
 422
 423                         printk(KERN_INFO "Clocks: Setting CPU clock\n");
 424                         calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
 425                                 &cpu_postdiv, &cpu_mul);
 426                         ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul)
 427                                                                 / cpu_postdiv;
 428                         tnetd7200_set_clock(cpu_base, &clocks->cpu,
 429                                 cpu_prediv, cpu_postdiv, -1, cpu_mul,
 430                                 ar7_cpu_clock);
 431
 432                         printk(KERN_INFO "Clocks: Setting DSP clock\n");
 433                         calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
 434                                 &dsp_postdiv, &dsp_mul);
 435                         ar7_bus_clock = ar7_cpu_clock / 2;
 436                         tnetd7200_set_clock(dsp_base, &clocks->dsp,
 437                                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
 438                                 dsp_mul * 2, ar7_bus_clock);
 439                 } else {
 440                         printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
 441
 442                         printk(KERN_INFO "Clocks: Setting DSP clock\n");
 443                         calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv,
 444                                 &dsp_postdiv, &dsp_mul);
 445                         ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul)
 446                                                                 / dsp_postdiv;
 447                         tnetd7200_set_clock(dsp_base, &clocks->dsp,
 448                                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
 449                                 dsp_mul * 2, ar7_bus_clock);
 450
 451                         ar7_cpu_clock = ar7_bus_clock;
 452                 }
 453
 454         printk(KERN_INFO "Clocks: Setting USB clock\n");
 455         usb_base = ar7_bus_clock;
 456         calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
 457                 &usb_postdiv, &usb_mul);
 458         tnetd7200_set_clock(usb_base, &clocks->usb,
 459                 usb_prediv, usb_postdiv, -1, usb_mul,
 460                 TNETD7200_DEF_USB_CLK);
 461
 462         #warning FIXME
 463         ar7_dsp_clock = ar7_cpu_clock;
 464
 465         iounmap(clocks);
 466         iounmap(bootcr);
 467 }
 468
 469 void __init ar7_init_clocks(void)
 470 {
 471         switch (ar7_chip_id()) {
 472         case AR7_CHIP_7100:
 473 #warning FIXME: Check if the new 7200 clock init works for 7100
 474                 tnetd7200_init_clocks();
 475                 break;
 476         case AR7_CHIP_7200:
 477                 tnetd7200_init_clocks();
 478                 break;
 479         case AR7_CHIP_7300:
 480                 ar7_dsp_clock = tnetd7300_dsp_clock();
 481                 tnetd7300_init_clocks();
 482                 break;
 483         default:
 484                 break;
 485         }
 486 }