target/linux/atheros/patches-2.6.32/002-mips_clocksource_init_war.patch

   1 Index: linux-2.6.32.7/arch/mips/kernel/cevt-r4k.c
   2 ===================================================================
   3 --- linux-2.6.32.7.orig/arch/mips/kernel/cevt-r4k.c     2010-02-03 16:59:28.310430064 +0100
   4 +++ linux-2.6.32.7/arch/mips/kernel/cevt-r4k.c  2010-02-03 16:59:54.578430015 +0100
   5 @@ -16,6 +16,22 @@
   6  #include <asm/cevt-r4k.h>
   7
   8  /*
   9 + * Compare interrupt can be routed and latched outside the core,
  10 + * so a single execution hazard barrier may not be enough to give
  11 + * it time to clear as seen in the Cause register.  4 time the
  12 + * pipeline depth seems reasonably conservative, and empirically
  13 + * works better in configurations with high CPU/bus clock ratios.
  14 + */
  15 +
  16 +#define compare_change_hazard() \
  17 +       do { \
  18 +               irq_disable_hazard(); \
  19 +               irq_disable_hazard(); \
  20 +               irq_disable_hazard(); \
  21 +               irq_disable_hazard(); \
  22 +       } while (0)
  23 +
  24 +/*
  25   * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
  26   * of these routines with SMTC-specific variants.
  27   */
  28 @@ -31,6 +47,7 @@
  29         cnt = read_c0_count();
  30         cnt += delta;
  31         write_c0_compare(cnt);
  32 +       compare_change_hazard();
  33         res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
  34         return res;
  35  }
  36 @@ -100,22 +117,6 @@
  37         return (read_c0_cause() >> cp0_compare_irq) & 0x100;
  38  }
  39
  40 -/*
  41 - * Compare interrupt can be routed and latched outside the core,
  42 - * so a single execution hazard barrier may not be enough to give
  43 - * it time to clear as seen in the Cause register.  4 time the
  44 - * pipeline depth seems reasonably conservative, and empirically
  45 - * works better in configurations with high CPU/bus clock ratios.
  46 - */
  47 -
  48 -#define compare_change_hazard() \
  49 -       do { \
  50 -               irq_disable_hazard(); \
  51 -               irq_disable_hazard(); \
  52 -               irq_disable_hazard(); \
  53 -               irq_disable_hazard(); \
  54 -       } while (0)
  55 -
  56  int c0_compare_int_usable(void)
  57  {
  58         unsigned int delta;