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avr32: update to latest atmel sources
[openwrt/staging/lynxis/omap.git] / target / linux / avr32 / patches / 100-git_sync.patch
1 --- a/Documentation/serial/driver
2 +++ b/Documentation/serial/driver
3 @@ -186,6 +186,17 @@
4 Locking: port_sem taken.
5 Interrupts: caller dependent.
6
7 + flush_buffer(port)
8 + Flush any write buffers, reset any DMA state and stop any
9 + ongoing DMA transfers.
10 +
11 + This will be called whenever the port->info->xmit circular
12 + buffer is cleared.
13 +
14 + Locking: port->lock taken.
15 + Interrupts: locally disabled.
16 + This call must not sleep
17 +
18 set_termios(port,termios,oldtermios)
19 Change the port parameters, including word length, parity, stop
20 bits. Update read_status_mask and ignore_status_mask to indicate
21 --- a/arch/avr32/Kconfig
22 +++ b/arch/avr32/Kconfig
23 @@ -47,6 +47,9 @@
24 config GENERIC_TIME
25 def_bool y
26
27 +config GENERIC_CLOCKEVENTS
28 + def_bool y
29 +
30 config RWSEM_XCHGADD_ALGORITHM
31 def_bool n
32
33 @@ -70,6 +73,8 @@
34
35 menu "System Type and features"
36
37 +source "kernel/time/Kconfig"
38 +
39 config SUBARCH_AVR32B
40 bool
41 config MMU
42 @@ -83,6 +88,7 @@
43 select MMU
44 select PERFORMANCE_COUNTERS
45 select HAVE_GPIO_LIB
46 + select GENERIC_ALLOCATOR
47
48 #
49 # CPU types
50 @@ -117,6 +123,9 @@
51 if BOARD_ATSTK1000
52 source "arch/avr32/boards/atstk1000/Kconfig"
53 endif
54 +if BOARD_ATNGW100
55 +source "arch/avr32/boards/atngw100/Kconfig"
56 +endif
57
58 choice
59 prompt "Boot loader type"
60 @@ -142,6 +151,9 @@
61
62 source "kernel/Kconfig.preempt"
63
64 +config QUICKLIST
65 + def_bool y
66 +
67 config HAVE_ARCH_BOOTMEM_NODE
68 def_bool n
69
70 @@ -180,6 +192,10 @@
71 be dumped to the console when a Non-Maskable Interrupt
72 happens.
73
74 +config DW_DMAC
75 + tristate "Synopsys DesignWare DMA Controller support"
76 + default y if CPU_AT32AP7000
77 +
78 # FPU emulation goes here
79
80 source "kernel/Kconfig.hz"
81 @@ -196,6 +212,11 @@
82
83 menu "Power management options"
84
85 +config ARCH_SUSPEND_POSSIBLE
86 + def_bool y
87 +
88 +source "kernel/power/Kconfig"
89 +
90 menu "CPU Frequency scaling"
91
92 source "drivers/cpufreq/Kconfig"
93 --- a/arch/avr32/Makefile
94 +++ b/arch/avr32/Makefile
95 @@ -32,6 +32,7 @@
96 core-y += arch/avr32/kernel/
97 core-y += arch/avr32/mm/
98 drivers-$(CONFIG_OPROFILE) += arch/avr32/oprofile/
99 +drivers-y += arch/avr32/drivers/
100 libs-y += arch/avr32/lib/
101
102 archincdir-$(CONFIG_PLATFORM_AT32AP) := arch-at32ap
103 --- /dev/null
104 +++ b/arch/avr32/boards/atngw100/Kconfig
105 @@ -0,0 +1,12 @@
106 +# NGW100 customization
107 +
108 +config BOARD_ATNGW100_I2C_GPIO
109 + bool "Use GPIO for i2c instead of built-in TWI module"
110 + help
111 + The driver for the built-in TWI module has been plagued by
112 + various problems, while the i2c-gpio driver is based on the
113 + trusty old i2c-algo-bit bitbanging engine, making it work
114 + on pretty much any setup.
115 +
116 + Choose 'Y' here if you're having i2c-related problems and
117 + want to rule out the i2c bus driver.
118 --- a/arch/avr32/boards/atngw100/setup.c
119 +++ b/arch/avr32/boards/atngw100/setup.c
120 @@ -25,6 +25,13 @@
121 #include <asm/arch/init.h>
122 #include <asm/arch/portmux.h>
123
124 +/* Oscillator frequencies. These are board-specific */
125 +unsigned long at32_board_osc_rates[3] = {
126 + [0] = 32768, /* 32.768 kHz on RTC osc */
127 + [1] = 20000000, /* 20 MHz on osc0 */
128 + [2] = 12000000, /* 12 MHz on osc1 */
129 +};
130 +
131 /* Initialized by bootloader-specific startup code. */
132 struct tag *bootloader_tags __initdata;
133
134 @@ -37,11 +44,16 @@
135 static struct spi_board_info spi0_board_info[] __initdata = {
136 {
137 .modalias = "mtd_dataflash",
138 - .max_speed_hz = 10000000,
139 + .max_speed_hz = 8000000,
140 .chip_select = 0,
141 },
142 };
143
144 +static struct mci_platform_data __initdata mci0_data = {
145 + .detect_pin = GPIO_PIN_PC(25),
146 + .wp_pin = GPIO_PIN_PE(0),
147 +};
148 +
149 /*
150 * The next two functions should go away as the boot loader is
151 * supposed to initialize the macb address registers with a valid
152 @@ -124,6 +136,7 @@
153 }
154 };
155
156 +#ifdef CONFIG_BOARD_ATNGW100_I2C_GPIO
157 static struct i2c_gpio_platform_data i2c_gpio_data = {
158 .sda_pin = GPIO_PIN_PA(6),
159 .scl_pin = GPIO_PIN_PA(7),
160 @@ -139,6 +152,7 @@
161 .platform_data = &i2c_gpio_data,
162 },
163 };
164 +#endif
165
166 static int __init atngw100_init(void)
167 {
168 @@ -157,6 +171,7 @@
169 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
170
171 at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
172 + at32_add_device_mci(0, &mci0_data);
173 at32_add_device_usba(0, NULL);
174
175 for (i = 0; i < ARRAY_SIZE(ngw_leds); i++) {
176 @@ -165,11 +180,15 @@
177 }
178 platform_device_register(&ngw_gpio_leds);
179
180 +#ifdef CONFIG_BOARD_ATNGW100_I2C_GPIO
181 at32_select_gpio(i2c_gpio_data.sda_pin,
182 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
183 at32_select_gpio(i2c_gpio_data.scl_pin,
184 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
185 platform_device_register(&i2c_gpio_device);
186 +#else
187 + at32_add_device_twi(0, NULL, 0);
188 +#endif
189
190 return 0;
191 }
192 --- a/arch/avr32/boards/atstk1000/Kconfig
193 +++ b/arch/avr32/boards/atstk1000/Kconfig
194 @@ -18,6 +18,10 @@
195 bool "ATSTK1004"
196 select CPU_AT32AP7002
197
198 +config BOARD_ATSTK1006
199 + bool "ATSTK1006"
200 + select CPU_AT32AP7000
201 +
202 endchoice
203
204
205 @@ -102,4 +106,60 @@
206 depends on !BOARD_ATSTK100X_SW1_CUSTOM && !BOARD_ATSTK100X_SW3_CUSTOM
207 default y
208
209 +config BOARD_ATSTK100X_ENABLE_AC97
210 + bool "Use AC97C instead of ABDAC"
211 + help
212 + Select this if you want to use the built-in AC97 controller
213 + instead of the built-in Audio Bitstream DAC. These share
214 + the same I/O pins on the AP7000, so both can't be enabled
215 + at the same time.
216 +
217 + Note that the STK1000 kit doesn't ship with an AC97 codec on
218 + board, so say N unless you've got an expansion board with an
219 + AC97 codec on it that you want to use.
220 +
221 +config BOARD_ATSTK1000_CF_HACKS
222 + bool "ATSTK1000 CompactFlash hacks"
223 + depends on !BOARD_ATSTK100X_SW4_CUSTOM
224 + help
225 + Select this if you have re-routed the CompactFlash RESET and
226 + CD signals to GPIOs on your STK1000. This is necessary for
227 + reset and card detection to work properly, although some CF
228 + cards may be able to cope without reset.
229 +
230 +config BOARD_ATSTK1000_CF_RESET_PIN
231 + hex "CompactFlash RESET pin"
232 + default 0x30
233 + depends on BOARD_ATSTK1000_CF_HACKS
234 + help
235 + Select which GPIO pin to use for the CompactFlash RESET
236 + signal. This is specified as a hexadecimal number and should
237 + be defined as 0x20 * gpio_port + pin.
238 +
239 + The default is 0x30, which is pin 16 on PIOB, aka GPIO14.
240 +
241 +config BOARD_ATSTK1000_CF_DETECT_PIN
242 + hex "CompactFlash DETECT pin"
243 + default 0x3e
244 + depends on BOARD_ATSTK1000_CF_HACKS
245 + help
246 + Select which GPIO pin to use for the CompactFlash CD
247 + signal. This is specified as a hexadecimal number and should
248 + be defined as 0x20 * gpio_port + pin.
249 +
250 + The default is 0x3e, which is pin 30 on PIOB, aka GPIO15.
251 +
252 +config BOARD_ATSTK100X_ENABLE_PSIF
253 + bool "Enable PSIF peripheral (PS/2 support)"
254 + default n
255 + help
256 + Select this if you want to use the PSIF peripheral to hook up PS/2
257 + devices to your STK1000. This will require a hardware modification to
258 + work correctly, since PS/2 devices require 5 volt power and signals,
259 + while the STK1000 only provides 3.3 volt.
260 +
261 + Say N if you have not modified the hardware to boost the voltage, say
262 + Y if you have level convertion hardware or a PS/2 device capable of
263 + operating on 3.3 volt.
264 +
265 endif # stk 1000
266 --- a/arch/avr32/boards/atstk1000/Makefile
267 +++ b/arch/avr32/boards/atstk1000/Makefile
268 @@ -2,3 +2,4 @@
269 obj-$(CONFIG_BOARD_ATSTK1002) += atstk1002.o
270 obj-$(CONFIG_BOARD_ATSTK1003) += atstk1003.o
271 obj-$(CONFIG_BOARD_ATSTK1004) += atstk1004.o
272 +obj-$(CONFIG_BOARD_ATSTK1006) += atstk1002.o
273 --- a/arch/avr32/boards/atstk1000/atstk1002.c
274 +++ b/arch/avr32/boards/atstk1000/atstk1002.c
275 @@ -1,7 +1,7 @@
276 /*
277 - * ATSTK1002 daughterboard-specific init code
278 + * ATSTK1002/ATSTK1006 daughterboard-specific init code
279 *
280 - * Copyright (C) 2005-2006 Atmel Corporation
281 + * Copyright (C) 2005-2007 Atmel Corporation
282 *
283 * This program is free software; you can redistribute it and/or modify
284 * it under the terms of the GNU General Public License version 2 as
285 @@ -28,6 +28,80 @@
286
287 #include "atstk1000.h"
288
289 +/* Oscillator frequencies. These are board specific */
290 +unsigned long at32_board_osc_rates[3] = {
291 + [0] = 32768, /* 32.768 kHz on RTC osc */
292 + [1] = 20000000, /* 20 MHz on osc0 */
293 + [2] = 12000000, /* 12 MHz on osc1 */
294 +};
295 +
296 +/*
297 + * The ATSTK1006 daughterboard is very similar to the ATSTK1002. Both
298 + * have the AT32AP7000 chip on board; the difference is that the
299 + * STK1006 has 128 MB SDRAM (the STK1002 uses the 8 MB SDRAM chip on
300 + * the STK1000 motherboard) and 256 MB NAND flash (the STK1002 has
301 + * none.)
302 + *
303 + * The RAM difference is handled by the boot loader, so the only
304 + * difference we end up handling here is the NAND flash.
305 + */
306 +#ifdef CONFIG_BOARD_ATSTK1006
307 +#include <linux/mtd/partitions.h>
308 +#include <asm/arch/smc.h>
309 +
310 +static struct smc_timing nand_timing __initdata = {
311 + .ncs_read_setup = 0,
312 + .nrd_setup = 10,
313 + .ncs_write_setup = 0,
314 + .nwe_setup = 10,
315 +
316 + .ncs_read_pulse = 30,
317 + .nrd_pulse = 15,
318 + .ncs_write_pulse = 30,
319 + .nwe_pulse = 15,
320 +
321 + .read_cycle = 30,
322 + .write_cycle = 30,
323 +
324 + .ncs_read_recover = 0,
325 + .nrd_recover = 15,
326 + .ncs_write_recover = 0,
327 + /* WE# high -> RE# low min 60 ns */
328 + .nwe_recover = 50,
329 +};
330 +
331 +static struct smc_config nand_config __initdata = {
332 + .bus_width = 1,
333 + .nrd_controlled = 1,
334 + .nwe_controlled = 1,
335 + .nwait_mode = 0,
336 + .byte_write = 0,
337 + .tdf_cycles = 2,
338 + .tdf_mode = 0,
339 +};
340 +
341 +static struct mtd_partition nand_partitions[] = {
342 + {
343 + .name = "main",
344 + .offset = 0x00000000,
345 + .size = MTDPART_SIZ_FULL,
346 + },
347 +};
348 +
349 +static struct mtd_partition *nand_part_info(int size, int *num_partitions)
350 +{
351 + *num_partitions = ARRAY_SIZE(nand_partitions);
352 + return nand_partitions;
353 +}
354 +
355 +static struct atmel_nand_data atstk1006_nand_data __initdata = {
356 + .cle = 21,
357 + .ale = 22,
358 + .rdy_pin = GPIO_PIN_PB(30),
359 + .enable_pin = GPIO_PIN_PB(29),
360 + .partition_info = nand_part_info,
361 +};
362 +#endif
363
364 struct eth_addr {
365 u8 addr[6];
366 @@ -83,6 +157,19 @@
367 } };
368 #endif
369
370 +static struct cf_platform_data __initdata cf0_data = {
371 +#ifdef CONFIG_BOARD_ATSTK1000_CF_HACKS
372 + .detect_pin = CONFIG_BOARD_ATSTK1000_CF_DETECT_PIN,
373 + .reset_pin = CONFIG_BOARD_ATSTK1000_CF_RESET_PIN,
374 +#else
375 + .detect_pin = GPIO_PIN_NONE,
376 + .reset_pin = GPIO_PIN_NONE,
377 +#endif
378 + .vcc_pin = GPIO_PIN_NONE,
379 + .ready_pin = GPIO_PIN_PB(27),
380 + .cs = 4,
381 +};
382 +
383 /*
384 * The next two functions should go away as the boot loader is
385 * supposed to initialize the macb address registers with a valid
386 @@ -212,6 +299,12 @@
387
388 at32_add_system_devices();
389
390 +#ifdef CONFIG_BOARD_ATSTK1006
391 + smc_set_timing(&nand_config, &nand_timing);
392 + smc_set_configuration(3, &nand_config);
393 + at32_add_device_nand(0, &atstk1006_nand_data);
394 +#endif
395 +
396 #ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
397 at32_add_device_usart(1);
398 #else
399 @@ -228,16 +321,30 @@
400 #ifdef CONFIG_BOARD_ATSTK100X_SPI1
401 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
402 #endif
403 + at32_add_device_twi(0, NULL, 0);
404 +#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
405 + at32_add_device_mci(0, NULL);
406 +#endif
407 #ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
408 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
409 #else
410 at32_add_device_lcdc(0, &atstk1000_lcdc_data,
411 - fbmem_start, fbmem_size);
412 + fbmem_start, fbmem_size, 0);
413 #endif
414 at32_add_device_usba(0, NULL);
415 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
416 + at32_add_device_ac97c(0, NULL);
417 +#else
418 + at32_add_device_abdac(0);
419 +#endif
420 #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
421 at32_add_device_ssc(0, ATMEL_SSC_TX);
422 #endif
423 + at32_add_device_cf(0, 2, &cf0_data);
424 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
425 + at32_add_device_psif(0);
426 + at32_add_device_psif(1);
427 +#endif
428
429 atstk1000_setup_j2_leds();
430 atstk1002_setup_extdac();
431 --- a/arch/avr32/boards/atstk1000/atstk1003.c
432 +++ b/arch/avr32/boards/atstk1000/atstk1003.c
433 @@ -27,6 +27,13 @@
434
435 #include "atstk1000.h"
436
437 +/* Oscillator frequencies. These are board specific */
438 +unsigned long at32_board_osc_rates[3] = {
439 + [0] = 32768, /* 32.768 kHz on RTC osc */
440 + [1] = 20000000, /* 20 MHz on osc0 */
441 + [2] = 12000000, /* 12 MHz on osc1 */
442 +};
443 +
444 #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
445 static struct at73c213_board_info at73c213_data = {
446 .ssc_id = 0,
447 @@ -59,6 +66,19 @@
448 } };
449 #endif
450
451 +static struct cf_platform_data __initdata cf0_data = {
452 +#ifdef CONFIG_BOARD_ATSTK1000_CF_HACKS
453 + .detect_pin = CONFIG_BOARD_ATSTK1000_CF_DETECT_PIN,
454 + .reset_pin = CONFIG_BOARD_ATSTK1000_CF_RESET_PIN,
455 +#else
456 + .detect_pin = GPIO_PIN_NONE,
457 + .reset_pin = GPIO_PIN_NONE,
458 +#endif
459 + .vcc_pin = GPIO_PIN_NONE,
460 + .ready_pin = GPIO_PIN_PB(27),
461 + .cs = 4,
462 +};
463 +
464 #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
465 static void __init atstk1003_setup_extdac(void)
466 {
467 @@ -147,12 +167,22 @@
468 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
469 #endif
470 #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
471 - at32_add_device_mci(0);
472 + at32_add_device_mci(0, NULL);
473 #endif
474 at32_add_device_usba(0, NULL);
475 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
476 + at32_add_device_ac97c(0, NULL);
477 +#else
478 + at32_add_device_abdac(0);
479 +#endif
480 #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
481 at32_add_device_ssc(0, ATMEL_SSC_TX);
482 #endif
483 + at32_add_device_cf(0, 2, &cf0_data);
484 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
485 + at32_add_device_psif(0);
486 + at32_add_device_psif(1);
487 +#endif
488
489 atstk1000_setup_j2_leds();
490 atstk1003_setup_extdac();
491 --- a/arch/avr32/boards/atstk1000/atstk1004.c
492 +++ b/arch/avr32/boards/atstk1000/atstk1004.c
493 @@ -29,6 +29,13 @@
494
495 #include "atstk1000.h"
496
497 +/* Oscillator frequencies. These are board specific */
498 +unsigned long at32_board_osc_rates[3] = {
499 + [0] = 32768, /* 32.768 kHz on RTC osc */
500 + [1] = 20000000, /* 20 MHz on osc0 */
501 + [2] = 12000000, /* 12 MHz on osc1 */
502 +};
503 +
504 #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
505 static struct at73c213_board_info at73c213_data = {
506 .ssc_id = 0,
507 @@ -130,14 +137,23 @@
508 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
509 #endif
510 #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
511 - at32_add_device_mci(0);
512 + at32_add_device_mci(0, NULL);
513 #endif
514 at32_add_device_lcdc(0, &atstk1000_lcdc_data,
515 - fbmem_start, fbmem_size);
516 + fbmem_start, fbmem_size, 0);
517 at32_add_device_usba(0, NULL);
518 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
519 + at32_add_device_ac97c(0, NULL);
520 +#else
521 + at32_add_device_abdac(0);
522 +#endif
523 #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
524 at32_add_device_ssc(0, ATMEL_SSC_TX);
525 #endif
526 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
527 + at32_add_device_psif(0);
528 + at32_add_device_psif(1);
529 +#endif
530
531 atstk1000_setup_j2_leds();
532 atstk1004_setup_extdac();
533 --- a/arch/avr32/configs/atngw100_defconfig
534 +++ b/arch/avr32/configs/atngw100_defconfig
535 @@ -1,7 +1,7 @@
536 #
537 # Automatically generated make config: don't edit
538 -# Linux kernel version: 2.6.24-rc7
539 -# Wed Jan 9 23:20:41 2008
540 +# Linux kernel version: 2.6.25.4
541 +# Wed Jun 11 15:23:36 2008
542 #
543 CONFIG_AVR32=y
544 CONFIG_GENERIC_GPIO=y
545 @@ -13,10 +13,10 @@
546 CONFIG_GENERIC_IRQ_PROBE=y
547 CONFIG_RWSEM_GENERIC_SPINLOCK=y
548 CONFIG_GENERIC_TIME=y
549 +CONFIG_GENERIC_CLOCKEVENTS=y
550 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
551 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
552 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
553 -CONFIG_ARCH_SUPPORTS_OPROFILE=y
554 CONFIG_GENERIC_HWEIGHT=y
555 CONFIG_GENERIC_CALIBRATE_DELAY=y
556 CONFIG_GENERIC_BUG=y
557 @@ -37,17 +37,15 @@
558 CONFIG_BSD_PROCESS_ACCT=y
559 CONFIG_BSD_PROCESS_ACCT_V3=y
560 # CONFIG_TASKSTATS is not set
561 -# CONFIG_USER_NS is not set
562 -# CONFIG_PID_NS is not set
563 # CONFIG_AUDIT is not set
564 # CONFIG_IKCONFIG is not set
565 CONFIG_LOG_BUF_SHIFT=14
566 # CONFIG_CGROUPS is not set
567 -CONFIG_FAIR_GROUP_SCHED=y
568 -CONFIG_FAIR_USER_SCHED=y
569 -# CONFIG_FAIR_CGROUP_SCHED is not set
570 +# CONFIG_GROUP_SCHED is not set
571 CONFIG_SYSFS_DEPRECATED=y
572 +CONFIG_SYSFS_DEPRECATED_V2=y
573 # CONFIG_RELAY is not set
574 +# CONFIG_NAMESPACES is not set
575 CONFIG_BLK_DEV_INITRD=y
576 CONFIG_INITRAMFS_SOURCE=""
577 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
578 @@ -61,11 +59,13 @@
579 CONFIG_PRINTK=y
580 CONFIG_BUG=y
581 CONFIG_ELF_CORE=y
582 +# CONFIG_COMPAT_BRK is not set
583 # CONFIG_BASE_FULL is not set
584 CONFIG_FUTEX=y
585 CONFIG_ANON_INODES=y
586 CONFIG_EPOLL=y
587 CONFIG_SIGNALFD=y
588 +CONFIG_TIMERFD=y
589 CONFIG_EVENTFD=y
590 CONFIG_SHMEM=y
591 CONFIG_VM_EVENT_COUNTERS=y
592 @@ -73,6 +73,14 @@
593 # CONFIG_SLAB is not set
594 CONFIG_SLUB=y
595 # CONFIG_SLOB is not set
596 +CONFIG_PROFILING=y
597 +# CONFIG_MARKERS is not set
598 +CONFIG_OPROFILE=m
599 +CONFIG_HAVE_OPROFILE=y
600 +CONFIG_KPROBES=y
601 +CONFIG_HAVE_KPROBES=y
602 +# CONFIG_HAVE_KRETPROBES is not set
603 +CONFIG_PROC_PAGE_MONITOR=y
604 CONFIG_SLABINFO=y
605 CONFIG_RT_MUTEXES=y
606 # CONFIG_TINY_SHMEM is not set
607 @@ -101,10 +109,15 @@
608 CONFIG_DEFAULT_CFQ=y
609 # CONFIG_DEFAULT_NOOP is not set
610 CONFIG_DEFAULT_IOSCHED="cfq"
611 +CONFIG_CLASSIC_RCU=y
612
613 #
614 # System Type and features
615 #
616 +CONFIG_TICK_ONESHOT=y
617 +CONFIG_NO_HZ=y
618 +CONFIG_HIGH_RES_TIMERS=y
619 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
620 CONFIG_SUBARCH_AVR32B=y
621 CONFIG_MMU=y
622 CONFIG_PERFORMANCE_COUNTERS=y
623 @@ -113,6 +126,7 @@
624 CONFIG_CPU_AT32AP7000=y
625 # CONFIG_BOARD_ATSTK1000 is not set
626 CONFIG_BOARD_ATNGW100=y
627 +CONFIG_BOARD_ATNGW100_I2C_GPIO=y
628 CONFIG_LOADER_U_BOOT=y
629
630 #
631 @@ -121,6 +135,7 @@
632 # CONFIG_AP700X_32_BIT_SMC is not set
633 CONFIG_AP700X_16_BIT_SMC=y
634 # CONFIG_AP700X_8_BIT_SMC is not set
635 +CONFIG_GPIO_DEV=y
636 CONFIG_LOAD_ADDRESS=0x10000000
637 CONFIG_ENTRY_ADDRESS=0x90000000
638 CONFIG_PHYS_OFFSET=0x10000000
639 @@ -146,16 +161,26 @@
640 CONFIG_ZONE_DMA_FLAG=0
641 CONFIG_VIRT_TO_BUS=y
642 # CONFIG_OWNERSHIP_TRACE is not set
643 +CONFIG_NMI_DEBUGGING=y
644 +CONFIG_DW_DMAC=y
645 # CONFIG_HZ_100 is not set
646 CONFIG_HZ_250=y
647 # CONFIG_HZ_300 is not set
648 # CONFIG_HZ_1000 is not set
649 CONFIG_HZ=250
650 +# CONFIG_SCHED_HRTICK is not set
651 CONFIG_CMDLINE=""
652
653 #
654 # Power management options
655 #
656 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
657 +CONFIG_PM=y
658 +# CONFIG_PM_LEGACY is not set
659 +# CONFIG_PM_DEBUG is not set
660 +CONFIG_PM_SLEEP=y
661 +CONFIG_SUSPEND=y
662 +CONFIG_SUSPEND_FREEZER=y
663
664 #
665 # CPU Frequency scaling
666 @@ -164,9 +189,9 @@
667 CONFIG_CPU_FREQ_TABLE=y
668 # CONFIG_CPU_FREQ_DEBUG is not set
669 # CONFIG_CPU_FREQ_STAT is not set
670 -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
671 +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
672 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
673 -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
674 +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
675 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
676 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
677 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
678 @@ -202,6 +227,7 @@
679 CONFIG_XFRM_USER=y
680 # CONFIG_XFRM_SUB_POLICY is not set
681 # CONFIG_XFRM_MIGRATE is not set
682 +# CONFIG_XFRM_STATISTICS is not set
683 CONFIG_NET_KEY=y
684 # CONFIG_NET_KEY_MIGRATE is not set
685 CONFIG_INET=y
686 @@ -260,82 +286,33 @@
687 # CONFIG_NETWORK_SECMARK is not set
688 CONFIG_NETFILTER=y
689 # CONFIG_NETFILTER_DEBUG is not set
690 -CONFIG_BRIDGE_NETFILTER=y
691 +# CONFIG_NETFILTER_ADVANCED is not set
692
693 #
694 # Core Netfilter Configuration
695 #
696 -# CONFIG_NETFILTER_NETLINK is not set
697 -CONFIG_NF_CONNTRACK_ENABLED=m
698 +CONFIG_NETFILTER_NETLINK=m
699 +CONFIG_NETFILTER_NETLINK_LOG=m
700 CONFIG_NF_CONNTRACK=m
701 -CONFIG_NF_CT_ACCT=y
702 -CONFIG_NF_CONNTRACK_MARK=y
703 -# CONFIG_NF_CONNTRACK_EVENTS is not set
704 -CONFIG_NF_CT_PROTO_GRE=m
705 -# CONFIG_NF_CT_PROTO_SCTP is not set
706 -# CONFIG_NF_CT_PROTO_UDPLITE is not set
707 -CONFIG_NF_CONNTRACK_AMANDA=m
708 CONFIG_NF_CONNTRACK_FTP=m
709 -CONFIG_NF_CONNTRACK_H323=m
710 CONFIG_NF_CONNTRACK_IRC=m
711 -CONFIG_NF_CONNTRACK_NETBIOS_NS=m
712 -CONFIG_NF_CONNTRACK_PPTP=m
713 -CONFIG_NF_CONNTRACK_SANE=m
714 CONFIG_NF_CONNTRACK_SIP=m
715 -CONFIG_NF_CONNTRACK_TFTP=m
716 +CONFIG_NF_CT_NETLINK=m
717 CONFIG_NETFILTER_XTABLES=y
718 -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
719 -# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
720 -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
721 CONFIG_NETFILTER_XT_TARGET_MARK=m
722 -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
723 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
724 -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
725 -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
726 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
727 -CONFIG_NETFILTER_XT_MATCH_COMMENT=m
728 -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
729 -# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
730 -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
731 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
732 -# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
733 -# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
734 -CONFIG_NETFILTER_XT_MATCH_ESP=m
735 -CONFIG_NETFILTER_XT_MATCH_HELPER=m
736 -CONFIG_NETFILTER_XT_MATCH_LENGTH=m
737 -CONFIG_NETFILTER_XT_MATCH_LIMIT=m
738 -CONFIG_NETFILTER_XT_MATCH_MAC=m
739 CONFIG_NETFILTER_XT_MATCH_MARK=m
740 CONFIG_NETFILTER_XT_MATCH_POLICY=m
741 -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
742 -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
743 -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
744 -CONFIG_NETFILTER_XT_MATCH_QUOTA=m
745 -CONFIG_NETFILTER_XT_MATCH_REALM=m
746 -# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
747 CONFIG_NETFILTER_XT_MATCH_STATE=m
748 -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
749 -CONFIG_NETFILTER_XT_MATCH_STRING=m
750 -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
751 -# CONFIG_NETFILTER_XT_MATCH_TIME is not set
752 -# CONFIG_NETFILTER_XT_MATCH_U32 is not set
753 -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
754
755 #
756 # IP: Netfilter Configuration
757 #
758 CONFIG_NF_CONNTRACK_IPV4=m
759 CONFIG_NF_CONNTRACK_PROC_COMPAT=y
760 -# CONFIG_IP_NF_QUEUE is not set
761 CONFIG_IP_NF_IPTABLES=m
762 -CONFIG_IP_NF_MATCH_IPRANGE=m
763 -CONFIG_IP_NF_MATCH_TOS=m
764 -CONFIG_IP_NF_MATCH_RECENT=m
765 -CONFIG_IP_NF_MATCH_ECN=m
766 -CONFIG_IP_NF_MATCH_AH=m
767 -CONFIG_IP_NF_MATCH_TTL=m
768 -CONFIG_IP_NF_MATCH_OWNER=m
769 -CONFIG_IP_NF_MATCH_ADDRTYPE=m
770 CONFIG_IP_NF_FILTER=m
771 CONFIG_IP_NF_TARGET_REJECT=m
772 CONFIG_IP_NF_TARGET_LOG=m
773 @@ -343,54 +320,25 @@
774 CONFIG_NF_NAT=m
775 CONFIG_NF_NAT_NEEDED=y
776 CONFIG_IP_NF_TARGET_MASQUERADE=m
777 -CONFIG_IP_NF_TARGET_REDIRECT=m
778 -CONFIG_IP_NF_TARGET_NETMAP=m
779 -CONFIG_IP_NF_TARGET_SAME=m
780 -CONFIG_NF_NAT_SNMP_BASIC=m
781 -CONFIG_NF_NAT_PROTO_GRE=m
782 CONFIG_NF_NAT_FTP=m
783 CONFIG_NF_NAT_IRC=m
784 -CONFIG_NF_NAT_TFTP=m
785 -CONFIG_NF_NAT_AMANDA=m
786 -CONFIG_NF_NAT_PPTP=m
787 -CONFIG_NF_NAT_H323=m
788 +# CONFIG_NF_NAT_TFTP is not set
789 +# CONFIG_NF_NAT_AMANDA is not set
790 +# CONFIG_NF_NAT_PPTP is not set
791 +# CONFIG_NF_NAT_H323 is not set
792 CONFIG_NF_NAT_SIP=m
793 CONFIG_IP_NF_MANGLE=m
794 -CONFIG_IP_NF_TARGET_TOS=m
795 -CONFIG_IP_NF_TARGET_ECN=m
796 -CONFIG_IP_NF_TARGET_TTL=m
797 -CONFIG_IP_NF_TARGET_CLUSTERIP=m
798 -CONFIG_IP_NF_RAW=m
799 -CONFIG_IP_NF_ARPTABLES=m
800 -CONFIG_IP_NF_ARPFILTER=m
801 -CONFIG_IP_NF_ARP_MANGLE=m
802
803 #
804 -# IPv6: Netfilter Configuration (EXPERIMENTAL)
805 +# IPv6: Netfilter Configuration
806 #
807 CONFIG_NF_CONNTRACK_IPV6=m
808 -CONFIG_IP6_NF_QUEUE=m
809 CONFIG_IP6_NF_IPTABLES=m
810 -CONFIG_IP6_NF_MATCH_RT=m
811 -CONFIG_IP6_NF_MATCH_OPTS=m
812 -CONFIG_IP6_NF_MATCH_FRAG=m
813 -CONFIG_IP6_NF_MATCH_HL=m
814 -CONFIG_IP6_NF_MATCH_OWNER=m
815 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
816 -CONFIG_IP6_NF_MATCH_AH=m
817 -CONFIG_IP6_NF_MATCH_MH=m
818 -CONFIG_IP6_NF_MATCH_EUI64=m
819 CONFIG_IP6_NF_FILTER=m
820 CONFIG_IP6_NF_TARGET_LOG=m
821 CONFIG_IP6_NF_TARGET_REJECT=m
822 CONFIG_IP6_NF_MANGLE=m
823 -CONFIG_IP6_NF_TARGET_HL=m
824 -CONFIG_IP6_NF_RAW=m
825 -
826 -#
827 -# Bridge: Netfilter Configuration
828 -#
829 -# CONFIG_BRIDGE_NF_EBTABLES is not set
830 # CONFIG_IP_DCCP is not set
831 # CONFIG_IP_SCTP is not set
832 # CONFIG_TIPC is not set
833 @@ -407,7 +355,6 @@
834 # CONFIG_ECONET is not set
835 # CONFIG_WAN_ROUTER is not set
836 # CONFIG_NET_SCHED is not set
837 -CONFIG_NET_CLS_ROUTE=y
838
839 #
840 # Network testing
841 @@ -415,6 +362,7 @@
842 # CONFIG_NET_PKTGEN is not set
843 # CONFIG_NET_TCPPROBE is not set
844 # CONFIG_HAMRADIO is not set
845 +# CONFIG_CAN is not set
846 # CONFIG_IRDA is not set
847 # CONFIG_BT is not set
848 # CONFIG_AF_RXRPC is not set
849 @@ -531,11 +479,18 @@
850 CONFIG_BLK_DEV_RAM=m
851 CONFIG_BLK_DEV_RAM_COUNT=16
852 CONFIG_BLK_DEV_RAM_SIZE=4096
853 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
854 +# CONFIG_BLK_DEV_XIP is not set
855 # CONFIG_CDROM_PKTCDVD is not set
856 # CONFIG_ATA_OVER_ETH is not set
857 -# CONFIG_MISC_DEVICES is not set
858 -# CONFIG_IDE is not set
859 +CONFIG_MISC_DEVICES=y
860 +# CONFIG_ATMEL_PWM is not set
861 +CONFIG_ATMEL_TCLIB=y
862 +CONFIG_ATMEL_TCB_CLKSRC=y
863 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
864 +# CONFIG_EEPROM_93CX6 is not set
865 +# CONFIG_ATMEL_SSC is not set
866 +# CONFIG_ENCLOSURE_SERVICES is not set
867 +# CONFIG_HAVE_IDE is not set
868
869 #
870 # SCSI device support
871 @@ -568,11 +523,13 @@
872 # CONFIG_SMSC_PHY is not set
873 # CONFIG_BROADCOM_PHY is not set
874 # CONFIG_ICPLUS_PHY is not set
875 +# CONFIG_REALTEK_PHY is not set
876 # CONFIG_FIXED_PHY is not set
877 # CONFIG_MDIO_BITBANG is not set
878 CONFIG_NET_ETHERNET=y
879 # CONFIG_MII is not set
880 CONFIG_MACB=y
881 +# CONFIG_ENC28J60 is not set
882 # CONFIG_IBM_NEW_EMAC_ZMII is not set
883 # CONFIG_IBM_NEW_EMAC_RGMII is not set
884 # CONFIG_IBM_NEW_EMAC_TAH is not set
885 @@ -599,7 +556,6 @@
886 # CONFIG_PPPOL2TP is not set
887 # CONFIG_SLIP is not set
888 CONFIG_SLHC=m
889 -# CONFIG_SHAPER is not set
890 # CONFIG_NETCONSOLE is not set
891 # CONFIG_NETPOLL is not set
892 # CONFIG_NET_POLL_CONTROLLER is not set
893 @@ -633,6 +589,7 @@
894 #
895 CONFIG_SERIAL_ATMEL=y
896 CONFIG_SERIAL_ATMEL_CONSOLE=y
897 +CONFIG_SERIAL_ATMEL_PDC=y
898 # CONFIG_SERIAL_ATMEL_TTYAT is not set
899 CONFIG_SERIAL_CORE=y
900 CONFIG_SERIAL_CORE_CONSOLE=y
901 @@ -640,8 +597,6 @@
902 # CONFIG_LEGACY_PTYS is not set
903 # CONFIG_IPMI_HANDLER is not set
904 # CONFIG_HW_RANDOM is not set
905 -# CONFIG_RTC is not set
906 -# CONFIG_GEN_RTC is not set
907 # CONFIG_R3964 is not set
908 # CONFIG_RAW_DRIVER is not set
909 # CONFIG_TCG_TPM is not set
910 @@ -659,6 +614,7 @@
911 #
912 # I2C Hardware Bus support
913 #
914 +CONFIG_I2C_ATMELTWI=m
915 CONFIG_I2C_GPIO=m
916 # CONFIG_I2C_OCORES is not set
917 # CONFIG_I2C_PARPORT_LIGHT is not set
918 @@ -669,13 +625,12 @@
919 #
920 # Miscellaneous I2C Chip support
921 #
922 -# CONFIG_SENSORS_DS1337 is not set
923 -# CONFIG_SENSORS_DS1374 is not set
924 # CONFIG_DS1682 is not set
925 # CONFIG_SENSORS_EEPROM is not set
926 # CONFIG_SENSORS_PCF8574 is not set
927 -# CONFIG_SENSORS_PCA9539 is not set
928 +# CONFIG_PCF8575 is not set
929 # CONFIG_SENSORS_PCF8591 is not set
930 +# CONFIG_TPS65010 is not set
931 # CONFIG_SENSORS_MAX6875 is not set
932 # CONFIG_SENSORS_TSL2550 is not set
933 # CONFIG_I2C_DEBUG_CORE is not set
934 @@ -702,9 +657,27 @@
935 # CONFIG_SPI_AT25 is not set
936 CONFIG_SPI_SPIDEV=m
937 # CONFIG_SPI_TLE62X0 is not set
938 +CONFIG_HAVE_GPIO_LIB=y
939 +
940 +#
941 +# GPIO Support
942 +#
943 +# CONFIG_DEBUG_GPIO is not set
944 +
945 +#
946 +# I2C GPIO expanders:
947 +#
948 +# CONFIG_GPIO_PCA953X is not set
949 +# CONFIG_GPIO_PCF857X is not set
950 +
951 +#
952 +# SPI GPIO expanders:
953 +#
954 +# CONFIG_GPIO_MCP23S08 is not set
955 # CONFIG_W1 is not set
956 # CONFIG_POWER_SUPPLY is not set
957 # CONFIG_HWMON is not set
958 +# CONFIG_THERMAL is not set
959 CONFIG_WATCHDOG=y
960 # CONFIG_WATCHDOG_NOWAYOUT is not set
961
962 @@ -757,10 +730,6 @@
963 #
964 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
965 #
966 -
967 -#
968 -# USB Gadget Support
969 -#
970 CONFIG_USB_GADGET=y
971 # CONFIG_USB_GADGET_DEBUG is not set
972 # CONFIG_USB_GADGET_DEBUG_FILES is not set
973 @@ -787,21 +756,24 @@
974 # CONFIG_USB_FILE_STORAGE_TEST is not set
975 CONFIG_USB_G_SERIAL=m
976 # CONFIG_USB_MIDI_GADGET is not set
977 -CONFIG_MMC=m
978 +# CONFIG_USB_G_PRINTER is not set
979 +CONFIG_MMC=y
980 # CONFIG_MMC_DEBUG is not set
981 # CONFIG_MMC_UNSAFE_RESUME is not set
982
983 #
984 # MMC/SD Card Drivers
985 #
986 -CONFIG_MMC_BLOCK=m
987 +CONFIG_MMC_BLOCK=y
988 CONFIG_MMC_BLOCK_BOUNCE=y
989 # CONFIG_SDIO_UART is not set
990
991 #
992 # MMC/SD Host Controller Drivers
993 #
994 +CONFIG_MMC_ATMELMCI=y
995 CONFIG_MMC_SPI=m
996 +# CONFIG_MEMSTICK is not set
997 CONFIG_NEW_LEDS=y
998 CONFIG_LEDS_CLASS=y
999
1000 @@ -844,19 +816,22 @@
1001 # CONFIG_RTC_DRV_PCF8563 is not set
1002 # CONFIG_RTC_DRV_PCF8583 is not set
1003 # CONFIG_RTC_DRV_M41T80 is not set
1004 +# CONFIG_RTC_DRV_S35390A is not set
1005
1006 #
1007 # SPI RTC drivers
1008 #
1009 -# CONFIG_RTC_DRV_RS5C348 is not set
1010 # CONFIG_RTC_DRV_MAX6902 is not set
1011 +# CONFIG_RTC_DRV_R9701 is not set
1012 +# CONFIG_RTC_DRV_RS5C348 is not set
1013
1014 #
1015 # Platform RTC drivers
1016 #
1017 +# CONFIG_RTC_DRV_DS1511 is not set
1018 # CONFIG_RTC_DRV_DS1553 is not set
1019 -# CONFIG_RTC_DRV_STK17TA8 is not set
1020 # CONFIG_RTC_DRV_DS1742 is not set
1021 +# CONFIG_RTC_DRV_STK17TA8 is not set
1022 # CONFIG_RTC_DRV_M48T86 is not set
1023 # CONFIG_RTC_DRV_M48T59 is not set
1024 # CONFIG_RTC_DRV_V3020 is not set
1025 @@ -874,25 +849,23 @@
1026 #
1027 # File systems
1028 #
1029 -CONFIG_EXT2_FS=m
1030 +CONFIG_EXT2_FS=y
1031 # CONFIG_EXT2_FS_XATTR is not set
1032 # CONFIG_EXT2_FS_XIP is not set
1033 -CONFIG_EXT3_FS=m
1034 +CONFIG_EXT3_FS=y
1035 # CONFIG_EXT3_FS_XATTR is not set
1036 # CONFIG_EXT4DEV_FS is not set
1037 -CONFIG_JBD=m
1038 +CONFIG_JBD=y
1039 # CONFIG_REISERFS_FS is not set
1040 # CONFIG_JFS_FS is not set
1041 # CONFIG_FS_POSIX_ACL is not set
1042 # CONFIG_XFS_FS is not set
1043 # CONFIG_GFS2_FS is not set
1044 # CONFIG_OCFS2_FS is not set
1045 -# CONFIG_MINIX_FS is not set
1046 -# CONFIG_ROMFS_FS is not set
1047 +# CONFIG_DNOTIFY is not set
1048 CONFIG_INOTIFY=y
1049 CONFIG_INOTIFY_USER=y
1050 # CONFIG_QUOTA is not set
1051 -# CONFIG_DNOTIFY is not set
1052 # CONFIG_AUTOFS_FS is not set
1053 # CONFIG_AUTOFS4_FS is not set
1054 CONFIG_FUSE_FS=m
1055 @@ -923,7 +896,7 @@
1056 CONFIG_TMPFS=y
1057 # CONFIG_TMPFS_POSIX_ACL is not set
1058 # CONFIG_HUGETLB_PAGE is not set
1059 -CONFIG_CONFIGFS_FS=m
1060 +CONFIG_CONFIGFS_FS=y
1061
1062 #
1063 # Miscellaneous filesystems
1064 @@ -948,8 +921,10 @@
1065 # CONFIG_JFFS2_RUBIN is not set
1066 # CONFIG_CRAMFS is not set
1067 # CONFIG_VXFS_FS is not set
1068 +# CONFIG_MINIX_FS is not set
1069 # CONFIG_HPFS_FS is not set
1070 # CONFIG_QNX4FS_FS is not set
1071 +# CONFIG_ROMFS_FS is not set
1072 # CONFIG_SYSV_FS is not set
1073 # CONFIG_UFS_FS is not set
1074 CONFIG_NETWORK_FILESYSTEMS=y
1075 @@ -1030,11 +1005,6 @@
1076 # CONFIG_NLS_KOI8_U is not set
1077 CONFIG_NLS_UTF8=m
1078 # CONFIG_DLM is not set
1079 -CONFIG_INSTRUMENTATION=y
1080 -CONFIG_PROFILING=y
1081 -CONFIG_OPROFILE=m
1082 -CONFIG_KPROBES=y
1083 -# CONFIG_MARKERS is not set
1084
1085 #
1086 # Kernel hacking
1087 @@ -1053,6 +1023,7 @@
1088 # CONFIG_SCHEDSTATS is not set
1089 # CONFIG_TIMER_STATS is not set
1090 # CONFIG_SLUB_DEBUG_ON is not set
1091 +# CONFIG_SLUB_STATS is not set
1092 # CONFIG_DEBUG_RT_MUTEXES is not set
1093 # CONFIG_RT_MUTEX_TESTER is not set
1094 # CONFIG_DEBUG_SPINLOCK is not set
1095 @@ -1069,9 +1040,10 @@
1096 # CONFIG_DEBUG_LIST is not set
1097 # CONFIG_DEBUG_SG is not set
1098 CONFIG_FRAME_POINTER=y
1099 -# CONFIG_FORCED_INLINING is not set
1100 # CONFIG_BOOT_PRINTK_DELAY is not set
1101 # CONFIG_RCU_TORTURE_TEST is not set
1102 +# CONFIG_KPROBES_SANITY_TEST is not set
1103 +# CONFIG_BACKTRACE_SELF_TEST is not set
1104 # CONFIG_LKDTM is not set
1105 # CONFIG_FAULT_INJECTION is not set
1106 # CONFIG_SAMPLES is not set
1107 @@ -1084,7 +1056,9 @@
1108 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
1109 CONFIG_CRYPTO=y
1110 CONFIG_CRYPTO_ALGAPI=y
1111 +CONFIG_CRYPTO_AEAD=y
1112 CONFIG_CRYPTO_BLKCIPHER=y
1113 +# CONFIG_CRYPTO_SEQIV is not set
1114 CONFIG_CRYPTO_HASH=y
1115 CONFIG_CRYPTO_MANAGER=y
1116 CONFIG_CRYPTO_HMAC=y
1117 @@ -1103,6 +1077,9 @@
1118 CONFIG_CRYPTO_PCBC=m
1119 # CONFIG_CRYPTO_LRW is not set
1120 # CONFIG_CRYPTO_XTS is not set
1121 +# CONFIG_CRYPTO_CTR is not set
1122 +# CONFIG_CRYPTO_GCM is not set
1123 +# CONFIG_CRYPTO_CCM is not set
1124 # CONFIG_CRYPTO_CRYPTD is not set
1125 CONFIG_CRYPTO_DES=y
1126 # CONFIG_CRYPTO_FCRYPT is not set
1127 @@ -1117,12 +1094,14 @@
1128 # CONFIG_CRYPTO_KHAZAD is not set
1129 # CONFIG_CRYPTO_ANUBIS is not set
1130 # CONFIG_CRYPTO_SEED is not set
1131 +# CONFIG_CRYPTO_SALSA20 is not set
1132 CONFIG_CRYPTO_DEFLATE=y
1133 # CONFIG_CRYPTO_MICHAEL_MIC is not set
1134 # CONFIG_CRYPTO_CRC32C is not set
1135 # CONFIG_CRYPTO_CAMELLIA is not set
1136 # CONFIG_CRYPTO_TEST is not set
1137 -# CONFIG_CRYPTO_AUTHENC is not set
1138 +CONFIG_CRYPTO_AUTHENC=y
1139 +# CONFIG_CRYPTO_LZO is not set
1140 CONFIG_CRYPTO_HW=y
1141
1142 #
1143 @@ -1137,10 +1116,7 @@
1144 # CONFIG_LIBCRC32C is not set
1145 CONFIG_ZLIB_INFLATE=y
1146 CONFIG_ZLIB_DEFLATE=y
1147 -CONFIG_TEXTSEARCH=y
1148 -CONFIG_TEXTSEARCH_KMP=m
1149 -CONFIG_TEXTSEARCH_BM=m
1150 -CONFIG_TEXTSEARCH_FSM=m
1151 +CONFIG_GENERIC_ALLOCATOR=y
1152 CONFIG_PLIST=y
1153 CONFIG_HAS_IOMEM=y
1154 CONFIG_HAS_IOPORT=y
1155 --- a/arch/avr32/configs/atstk1002_defconfig
1156 +++ b/arch/avr32/configs/atstk1002_defconfig
1157 @@ -1,7 +1,7 @@
1158 #
1159 # Automatically generated make config: don't edit
1160 -# Linux kernel version: 2.6.24-rc7
1161 -# Wed Jan 9 23:07:43 2008
1162 +# Linux kernel version: 2.6.25.4
1163 +# Wed Jun 11 15:29:18 2008
1164 #
1165 CONFIG_AVR32=y
1166 CONFIG_GENERIC_GPIO=y
1167 @@ -13,10 +13,10 @@
1168 CONFIG_GENERIC_IRQ_PROBE=y
1169 CONFIG_RWSEM_GENERIC_SPINLOCK=y
1170 CONFIG_GENERIC_TIME=y
1171 +CONFIG_GENERIC_CLOCKEVENTS=y
1172 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
1173 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
1174 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
1175 -CONFIG_ARCH_SUPPORTS_OPROFILE=y
1176 CONFIG_GENERIC_HWEIGHT=y
1177 CONFIG_GENERIC_CALIBRATE_DELAY=y
1178 CONFIG_GENERIC_BUG=y
1179 @@ -36,15 +36,15 @@
1180 CONFIG_POSIX_MQUEUE=y
1181 # CONFIG_BSD_PROCESS_ACCT is not set
1182 # CONFIG_TASKSTATS is not set
1183 -# CONFIG_USER_NS is not set
1184 -# CONFIG_PID_NS is not set
1185 # CONFIG_AUDIT is not set
1186 # CONFIG_IKCONFIG is not set
1187 CONFIG_LOG_BUF_SHIFT=14
1188 # CONFIG_CGROUPS is not set
1189 -# CONFIG_FAIR_GROUP_SCHED is not set
1190 +# CONFIG_GROUP_SCHED is not set
1191 CONFIG_SYSFS_DEPRECATED=y
1192 +CONFIG_SYSFS_DEPRECATED_V2=y
1193 CONFIG_RELAY=y
1194 +# CONFIG_NAMESPACES is not set
1195 CONFIG_BLK_DEV_INITRD=y
1196 CONFIG_INITRAMFS_SOURCE=""
1197 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
1198 @@ -58,11 +58,13 @@
1199 CONFIG_PRINTK=y
1200 CONFIG_BUG=y
1201 CONFIG_ELF_CORE=y
1202 +# CONFIG_COMPAT_BRK is not set
1203 # CONFIG_BASE_FULL is not set
1204 CONFIG_FUTEX=y
1205 CONFIG_ANON_INODES=y
1206 CONFIG_EPOLL=y
1207 CONFIG_SIGNALFD=y
1208 +CONFIG_TIMERFD=y
1209 CONFIG_EVENTFD=y
1210 CONFIG_SHMEM=y
1211 CONFIG_VM_EVENT_COUNTERS=y
1212 @@ -70,6 +72,14 @@
1213 # CONFIG_SLAB is not set
1214 CONFIG_SLUB=y
1215 # CONFIG_SLOB is not set
1216 +CONFIG_PROFILING=y
1217 +# CONFIG_MARKERS is not set
1218 +CONFIG_OPROFILE=m
1219 +CONFIG_HAVE_OPROFILE=y
1220 +CONFIG_KPROBES=y
1221 +CONFIG_HAVE_KPROBES=y
1222 +# CONFIG_HAVE_KRETPROBES is not set
1223 +CONFIG_PROC_PAGE_MONITOR=y
1224 CONFIG_SLABINFO=y
1225 CONFIG_RT_MUTEXES=y
1226 # CONFIG_TINY_SHMEM is not set
1227 @@ -98,10 +108,15 @@
1228 CONFIG_DEFAULT_CFQ=y
1229 # CONFIG_DEFAULT_NOOP is not set
1230 CONFIG_DEFAULT_IOSCHED="cfq"
1231 +CONFIG_CLASSIC_RCU=y
1232
1233 #
1234 # System Type and features
1235 #
1236 +CONFIG_TICK_ONESHOT=y
1237 +CONFIG_NO_HZ=y
1238 +CONFIG_HIGH_RES_TIMERS=y
1239 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
1240 CONFIG_SUBARCH_AVR32B=y
1241 CONFIG_MMU=y
1242 CONFIG_PERFORMANCE_COUNTERS=y
1243 @@ -113,12 +128,16 @@
1244 CONFIG_BOARD_ATSTK1002=y
1245 # CONFIG_BOARD_ATSTK1003 is not set
1246 # CONFIG_BOARD_ATSTK1004 is not set
1247 +# CONFIG_BOARD_ATSTK1006 is not set
1248 # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
1249 # CONFIG_BOARD_ATSTK100X_SPI1 is not set
1250 # CONFIG_BOARD_ATSTK1000_J2_LED is not set
1251 # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
1252 # CONFIG_BOARD_ATSTK1000_J2_RGB is not set
1253 CONFIG_BOARD_ATSTK1000_EXTDAC=y
1254 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
1255 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
1256 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
1257 CONFIG_LOADER_U_BOOT=y
1258
1259 #
1260 @@ -127,6 +146,7 @@
1261 # CONFIG_AP700X_32_BIT_SMC is not set
1262 CONFIG_AP700X_16_BIT_SMC=y
1263 # CONFIG_AP700X_8_BIT_SMC is not set
1264 +CONFIG_GPIO_DEV=y
1265 CONFIG_LOAD_ADDRESS=0x10000000
1266 CONFIG_ENTRY_ADDRESS=0x90000000
1267 CONFIG_PHYS_OFFSET=0x10000000
1268 @@ -152,16 +172,26 @@
1269 CONFIG_ZONE_DMA_FLAG=0
1270 CONFIG_VIRT_TO_BUS=y
1271 # CONFIG_OWNERSHIP_TRACE is not set
1272 +CONFIG_NMI_DEBUGGING=y
1273 +CONFIG_DW_DMAC=y
1274 # CONFIG_HZ_100 is not set
1275 CONFIG_HZ_250=y
1276 # CONFIG_HZ_300 is not set
1277 # CONFIG_HZ_1000 is not set
1278 CONFIG_HZ=250
1279 +# CONFIG_SCHED_HRTICK is not set
1280 CONFIG_CMDLINE=""
1281
1282 #
1283 # Power management options
1284 #
1285 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
1286 +CONFIG_PM=y
1287 +# CONFIG_PM_LEGACY is not set
1288 +# CONFIG_PM_DEBUG is not set
1289 +CONFIG_PM_SLEEP=y
1290 +CONFIG_SUSPEND=y
1291 +CONFIG_SUSPEND_FREEZER=y
1292
1293 #
1294 # CPU Frequency scaling
1295 @@ -170,9 +200,9 @@
1296 CONFIG_CPU_FREQ_TABLE=y
1297 # CONFIG_CPU_FREQ_DEBUG is not set
1298 # CONFIG_CPU_FREQ_STAT is not set
1299 -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
1300 +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
1301 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
1302 -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
1303 +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
1304 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
1305 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
1306 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
1307 @@ -208,6 +238,7 @@
1308 CONFIG_XFRM_USER=m
1309 # CONFIG_XFRM_SUB_POLICY is not set
1310 # CONFIG_XFRM_MIGRATE is not set
1311 +# CONFIG_XFRM_STATISTICS is not set
1312 CONFIG_NET_KEY=m
1313 # CONFIG_NET_KEY_MIGRATE is not set
1314 CONFIG_INET=y
1315 @@ -279,6 +310,7 @@
1316 # CONFIG_NET_PKTGEN is not set
1317 # CONFIG_NET_TCPPROBE is not set
1318 # CONFIG_HAMRADIO is not set
1319 +# CONFIG_CAN is not set
1320 # CONFIG_IRDA is not set
1321 # CONFIG_BT is not set
1322 # CONFIG_AF_RXRPC is not set
1323 @@ -395,13 +427,18 @@
1324 CONFIG_BLK_DEV_RAM=m
1325 CONFIG_BLK_DEV_RAM_COUNT=16
1326 CONFIG_BLK_DEV_RAM_SIZE=4096
1327 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
1328 +# CONFIG_BLK_DEV_XIP is not set
1329 # CONFIG_CDROM_PKTCDVD is not set
1330 # CONFIG_ATA_OVER_ETH is not set
1331 CONFIG_MISC_DEVICES=y
1332 +CONFIG_ATMEL_PWM=m
1333 +CONFIG_ATMEL_TCLIB=y
1334 +CONFIG_ATMEL_TCB_CLKSRC=y
1335 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
1336 # CONFIG_EEPROM_93CX6 is not set
1337 CONFIG_ATMEL_SSC=m
1338 -# CONFIG_IDE is not set
1339 +# CONFIG_ENCLOSURE_SERVICES is not set
1340 +# CONFIG_HAVE_IDE is not set
1341
1342 #
1343 # SCSI device support
1344 @@ -444,6 +481,7 @@
1345 # CONFIG_SCSI_LOWLEVEL is not set
1346 CONFIG_ATA=m
1347 # CONFIG_ATA_NONSTANDARD is not set
1348 +# CONFIG_SATA_MV is not set
1349 CONFIG_PATA_AT32=m
1350 # CONFIG_PATA_PLATFORM is not set
1351 # CONFIG_MD is not set
1352 @@ -469,11 +507,13 @@
1353 # CONFIG_SMSC_PHY is not set
1354 # CONFIG_BROADCOM_PHY is not set
1355 # CONFIG_ICPLUS_PHY is not set
1356 +# CONFIG_REALTEK_PHY is not set
1357 # CONFIG_FIXED_PHY is not set
1358 # CONFIG_MDIO_BITBANG is not set
1359 CONFIG_NET_ETHERNET=y
1360 # CONFIG_MII is not set
1361 CONFIG_MACB=y
1362 +# CONFIG_ENC28J60 is not set
1363 # CONFIG_IBM_NEW_EMAC_ZMII is not set
1364 # CONFIG_IBM_NEW_EMAC_RGMII is not set
1365 # CONFIG_IBM_NEW_EMAC_TAH is not set
1366 @@ -500,7 +540,6 @@
1367 # CONFIG_PPPOL2TP is not set
1368 # CONFIG_SLIP is not set
1369 CONFIG_SLHC=m
1370 -# CONFIG_SHAPER is not set
1371 # CONFIG_NETCONSOLE is not set
1372 # CONFIG_NETPOLL is not set
1373 # CONFIG_NET_POLL_CONTROLLER is not set
1374 @@ -568,6 +607,7 @@
1375 #
1376 CONFIG_SERIAL_ATMEL=y
1377 CONFIG_SERIAL_ATMEL_CONSOLE=y
1378 +CONFIG_SERIAL_ATMEL_PDC=y
1379 # CONFIG_SERIAL_ATMEL_TTYAT is not set
1380 CONFIG_SERIAL_CORE=y
1381 CONFIG_SERIAL_CORE_CONSOLE=y
1382 @@ -575,8 +615,6 @@
1383 # CONFIG_LEGACY_PTYS is not set
1384 # CONFIG_IPMI_HANDLER is not set
1385 # CONFIG_HW_RANDOM is not set
1386 -# CONFIG_RTC is not set
1387 -# CONFIG_GEN_RTC is not set
1388 # CONFIG_R3964 is not set
1389 # CONFIG_RAW_DRIVER is not set
1390 # CONFIG_TCG_TPM is not set
1391 @@ -594,6 +632,7 @@
1392 #
1393 # I2C Hardware Bus support
1394 #
1395 +CONFIG_I2C_ATMELTWI=m
1396 CONFIG_I2C_GPIO=m
1397 # CONFIG_I2C_OCORES is not set
1398 # CONFIG_I2C_PARPORT_LIGHT is not set
1399 @@ -604,13 +643,12 @@
1400 #
1401 # Miscellaneous I2C Chip support
1402 #
1403 -# CONFIG_SENSORS_DS1337 is not set
1404 -# CONFIG_SENSORS_DS1374 is not set
1405 # CONFIG_DS1682 is not set
1406 # CONFIG_SENSORS_EEPROM is not set
1407 # CONFIG_SENSORS_PCF8574 is not set
1408 -# CONFIG_SENSORS_PCA9539 is not set
1409 +# CONFIG_PCF8575 is not set
1410 # CONFIG_SENSORS_PCF8591 is not set
1411 +# CONFIG_TPS65010 is not set
1412 # CONFIG_SENSORS_MAX6875 is not set
1413 # CONFIG_SENSORS_TSL2550 is not set
1414 # CONFIG_I2C_DEBUG_CORE is not set
1415 @@ -637,9 +675,27 @@
1416 # CONFIG_SPI_AT25 is not set
1417 CONFIG_SPI_SPIDEV=m
1418 # CONFIG_SPI_TLE62X0 is not set
1419 +CONFIG_HAVE_GPIO_LIB=y
1420 +
1421 +#
1422 +# GPIO Support
1423 +#
1424 +# CONFIG_DEBUG_GPIO is not set
1425 +
1426 +#
1427 +# I2C GPIO expanders:
1428 +#
1429 +# CONFIG_GPIO_PCA953X is not set
1430 +# CONFIG_GPIO_PCF857X is not set
1431 +
1432 +#
1433 +# SPI GPIO expanders:
1434 +#
1435 +# CONFIG_GPIO_MCP23S08 is not set
1436 # CONFIG_W1 is not set
1437 # CONFIG_POWER_SUPPLY is not set
1438 # CONFIG_HWMON is not set
1439 +# CONFIG_THERMAL is not set
1440 CONFIG_WATCHDOG=y
1441 # CONFIG_WATCHDOG_NOWAYOUT is not set
1442
1443 @@ -732,12 +788,18 @@
1444 #
1445 # Generic devices
1446 #
1447 +CONFIG_SND_AC97_CODEC=m
1448 # CONFIG_SND_DUMMY is not set
1449 # CONFIG_SND_MTPAV is not set
1450 # CONFIG_SND_SERIAL_U16550 is not set
1451 # CONFIG_SND_MPU401 is not set
1452
1453 #
1454 +# AVR32 devices
1455 +#
1456 +CONFIG_SND_ATMEL_AC97=m
1457 +
1458 +#
1459 # SPI devices
1460 #
1461 CONFIG_SND_AT73C213=m
1462 @@ -753,9 +815,14 @@
1463 #
1464
1465 #
1466 +# ALSA SoC audio for Freescale SOCs
1467 +#
1468 +
1469 +#
1470 # Open Sound System
1471 #
1472 # CONFIG_SOUND_PRIME is not set
1473 +CONFIG_AC97_BUS=m
1474 # CONFIG_HID_SUPPORT is not set
1475 CONFIG_USB_SUPPORT=y
1476 # CONFIG_USB_ARCH_HAS_HCD is not set
1477 @@ -765,10 +832,6 @@
1478 #
1479 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1480 #
1481 -
1482 -#
1483 -# USB Gadget Support
1484 -#
1485 CONFIG_USB_GADGET=y
1486 # CONFIG_USB_GADGET_DEBUG is not set
1487 # CONFIG_USB_GADGET_DEBUG_FILES is not set
1488 @@ -796,27 +859,31 @@
1489 # CONFIG_USB_FILE_STORAGE_TEST is not set
1490 CONFIG_USB_G_SERIAL=m
1491 # CONFIG_USB_MIDI_GADGET is not set
1492 -CONFIG_MMC=m
1493 +# CONFIG_USB_G_PRINTER is not set
1494 +CONFIG_MMC=y
1495 # CONFIG_MMC_DEBUG is not set
1496 # CONFIG_MMC_UNSAFE_RESUME is not set
1497
1498 #
1499 # MMC/SD Card Drivers
1500 #
1501 -CONFIG_MMC_BLOCK=m
1502 +CONFIG_MMC_BLOCK=y
1503 CONFIG_MMC_BLOCK_BOUNCE=y
1504 # CONFIG_SDIO_UART is not set
1505
1506 #
1507 # MMC/SD Host Controller Drivers
1508 #
1509 +CONFIG_MMC_ATMELMCI=y
1510 CONFIG_MMC_SPI=m
1511 +# CONFIG_MEMSTICK is not set
1512 CONFIG_NEW_LEDS=y
1513 CONFIG_LEDS_CLASS=m
1514
1515 #
1516 # LED drivers
1517 #
1518 +CONFIG_LEDS_ATMEL_PWM=m
1519 CONFIG_LEDS_GPIO=m
1520
1521 #
1522 @@ -853,19 +920,22 @@
1523 # CONFIG_RTC_DRV_PCF8563 is not set
1524 # CONFIG_RTC_DRV_PCF8583 is not set
1525 # CONFIG_RTC_DRV_M41T80 is not set
1526 +# CONFIG_RTC_DRV_S35390A is not set
1527
1528 #
1529 # SPI RTC drivers
1530 #
1531 -# CONFIG_RTC_DRV_RS5C348 is not set
1532 # CONFIG_RTC_DRV_MAX6902 is not set
1533 +# CONFIG_RTC_DRV_R9701 is not set
1534 +# CONFIG_RTC_DRV_RS5C348 is not set
1535
1536 #
1537 # Platform RTC drivers
1538 #
1539 +# CONFIG_RTC_DRV_DS1511 is not set
1540 # CONFIG_RTC_DRV_DS1553 is not set
1541 -# CONFIG_RTC_DRV_STK17TA8 is not set
1542 # CONFIG_RTC_DRV_DS1742 is not set
1543 +# CONFIG_RTC_DRV_STK17TA8 is not set
1544 # CONFIG_RTC_DRV_M48T86 is not set
1545 # CONFIG_RTC_DRV_M48T59 is not set
1546 # CONFIG_RTC_DRV_V3020 is not set
1547 @@ -883,13 +953,13 @@
1548 #
1549 # File systems
1550 #
1551 -CONFIG_EXT2_FS=m
1552 +CONFIG_EXT2_FS=y
1553 # CONFIG_EXT2_FS_XATTR is not set
1554 # CONFIG_EXT2_FS_XIP is not set
1555 -CONFIG_EXT3_FS=m
1556 +CONFIG_EXT3_FS=y
1557 # CONFIG_EXT3_FS_XATTR is not set
1558 # CONFIG_EXT4DEV_FS is not set
1559 -CONFIG_JBD=m
1560 +CONFIG_JBD=y
1561 # CONFIG_JBD_DEBUG is not set
1562 # CONFIG_REISERFS_FS is not set
1563 # CONFIG_JFS_FS is not set
1564 @@ -897,12 +967,10 @@
1565 # CONFIG_XFS_FS is not set
1566 # CONFIG_GFS2_FS is not set
1567 # CONFIG_OCFS2_FS is not set
1568 -CONFIG_MINIX_FS=m
1569 -# CONFIG_ROMFS_FS is not set
1570 +# CONFIG_DNOTIFY is not set
1571 CONFIG_INOTIFY=y
1572 CONFIG_INOTIFY_USER=y
1573 # CONFIG_QUOTA is not set
1574 -# CONFIG_DNOTIFY is not set
1575 # CONFIG_AUTOFS_FS is not set
1576 # CONFIG_AUTOFS4_FS is not set
1577 CONFIG_FUSE_FS=m
1578 @@ -933,7 +1001,7 @@
1579 CONFIG_TMPFS=y
1580 # CONFIG_TMPFS_POSIX_ACL is not set
1581 # CONFIG_HUGETLB_PAGE is not set
1582 -# CONFIG_CONFIGFS_FS is not set
1583 +CONFIG_CONFIGFS_FS=y
1584
1585 #
1586 # Miscellaneous filesystems
1587 @@ -957,8 +1025,10 @@
1588 # CONFIG_JFFS2_RUBIN is not set
1589 # CONFIG_CRAMFS is not set
1590 # CONFIG_VXFS_FS is not set
1591 +CONFIG_MINIX_FS=m
1592 # CONFIG_HPFS_FS is not set
1593 # CONFIG_QNX4FS_FS is not set
1594 +# CONFIG_ROMFS_FS is not set
1595 # CONFIG_SYSV_FS is not set
1596 # CONFIG_UFS_FS is not set
1597 CONFIG_NETWORK_FILESYSTEMS=y
1598 @@ -1028,11 +1098,6 @@
1599 # CONFIG_NLS_KOI8_U is not set
1600 CONFIG_NLS_UTF8=m
1601 # CONFIG_DLM is not set
1602 -CONFIG_INSTRUMENTATION=y
1603 -CONFIG_PROFILING=y
1604 -CONFIG_OPROFILE=m
1605 -CONFIG_KPROBES=y
1606 -# CONFIG_MARKERS is not set
1607
1608 #
1609 # Kernel hacking
1610 @@ -1051,6 +1116,7 @@
1611 # CONFIG_SCHEDSTATS is not set
1612 # CONFIG_TIMER_STATS is not set
1613 # CONFIG_SLUB_DEBUG_ON is not set
1614 +# CONFIG_SLUB_STATS is not set
1615 # CONFIG_DEBUG_RT_MUTEXES is not set
1616 # CONFIG_RT_MUTEX_TESTER is not set
1617 # CONFIG_DEBUG_SPINLOCK is not set
1618 @@ -1067,9 +1133,10 @@
1619 # CONFIG_DEBUG_LIST is not set
1620 # CONFIG_DEBUG_SG is not set
1621 CONFIG_FRAME_POINTER=y
1622 -CONFIG_FORCED_INLINING=y
1623 # CONFIG_BOOT_PRINTK_DELAY is not set
1624 # CONFIG_RCU_TORTURE_TEST is not set
1625 +# CONFIG_KPROBES_SANITY_TEST is not set
1626 +# CONFIG_BACKTRACE_SELF_TEST is not set
1627 # CONFIG_LKDTM is not set
1628 # CONFIG_FAULT_INJECTION is not set
1629 # CONFIG_SAMPLES is not set
1630 @@ -1082,7 +1149,9 @@
1631 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
1632 CONFIG_CRYPTO=y
1633 CONFIG_CRYPTO_ALGAPI=m
1634 +CONFIG_CRYPTO_AEAD=m
1635 CONFIG_CRYPTO_BLKCIPHER=m
1636 +# CONFIG_CRYPTO_SEQIV is not set
1637 CONFIG_CRYPTO_HASH=m
1638 CONFIG_CRYPTO_MANAGER=m
1639 CONFIG_CRYPTO_HMAC=m
1640 @@ -1101,6 +1170,9 @@
1641 # CONFIG_CRYPTO_PCBC is not set
1642 # CONFIG_CRYPTO_LRW is not set
1643 # CONFIG_CRYPTO_XTS is not set
1644 +# CONFIG_CRYPTO_CTR is not set
1645 +# CONFIG_CRYPTO_GCM is not set
1646 +# CONFIG_CRYPTO_CCM is not set
1647 # CONFIG_CRYPTO_CRYPTD is not set
1648 CONFIG_CRYPTO_DES=m
1649 # CONFIG_CRYPTO_FCRYPT is not set
1650 @@ -1115,12 +1187,14 @@
1651 # CONFIG_CRYPTO_KHAZAD is not set
1652 # CONFIG_CRYPTO_ANUBIS is not set
1653 # CONFIG_CRYPTO_SEED is not set
1654 +# CONFIG_CRYPTO_SALSA20 is not set
1655 CONFIG_CRYPTO_DEFLATE=m
1656 # CONFIG_CRYPTO_MICHAEL_MIC is not set
1657 # CONFIG_CRYPTO_CRC32C is not set
1658 # CONFIG_CRYPTO_CAMELLIA is not set
1659 # CONFIG_CRYPTO_TEST is not set
1660 -# CONFIG_CRYPTO_AUTHENC is not set
1661 +CONFIG_CRYPTO_AUTHENC=m
1662 +# CONFIG_CRYPTO_LZO is not set
1663 # CONFIG_CRYPTO_HW is not set
1664
1665 #
1666 @@ -1135,6 +1209,7 @@
1667 # CONFIG_LIBCRC32C is not set
1668 CONFIG_ZLIB_INFLATE=y
1669 CONFIG_ZLIB_DEFLATE=y
1670 +CONFIG_GENERIC_ALLOCATOR=y
1671 CONFIG_PLIST=y
1672 CONFIG_HAS_IOMEM=y
1673 CONFIG_HAS_IOPORT=y
1674 --- a/arch/avr32/configs/atstk1003_defconfig
1675 +++ b/arch/avr32/configs/atstk1003_defconfig
1676 @@ -1,7 +1,7 @@
1677 #
1678 # Automatically generated make config: don't edit
1679 -# Linux kernel version: 2.6.24-rc7
1680 -# Wed Jan 9 22:54:34 2008
1681 +# Linux kernel version: 2.6.25.4
1682 +# Wed Jun 11 15:33:36 2008
1683 #
1684 CONFIG_AVR32=y
1685 CONFIG_GENERIC_GPIO=y
1686 @@ -13,10 +13,10 @@
1687 CONFIG_GENERIC_IRQ_PROBE=y
1688 CONFIG_RWSEM_GENERIC_SPINLOCK=y
1689 CONFIG_GENERIC_TIME=y
1690 +CONFIG_GENERIC_CLOCKEVENTS=y
1691 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
1692 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
1693 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
1694 -CONFIG_ARCH_SUPPORTS_OPROFILE=y
1695 CONFIG_GENERIC_HWEIGHT=y
1696 CONFIG_GENERIC_CALIBRATE_DELAY=y
1697 CONFIG_GENERIC_BUG=y
1698 @@ -39,17 +39,15 @@
1699 CONFIG_TASKSTATS=y
1700 CONFIG_TASK_DELAY_ACCT=y
1701 # CONFIG_TASK_XACCT is not set
1702 -# CONFIG_USER_NS is not set
1703 -# CONFIG_PID_NS is not set
1704 CONFIG_AUDIT=y
1705 # CONFIG_IKCONFIG is not set
1706 CONFIG_LOG_BUF_SHIFT=14
1707 # CONFIG_CGROUPS is not set
1708 -CONFIG_FAIR_GROUP_SCHED=y
1709 -CONFIG_FAIR_USER_SCHED=y
1710 -# CONFIG_FAIR_CGROUP_SCHED is not set
1711 +# CONFIG_GROUP_SCHED is not set
1712 CONFIG_SYSFS_DEPRECATED=y
1713 +CONFIG_SYSFS_DEPRECATED_V2=y
1714 CONFIG_RELAY=y
1715 +# CONFIG_NAMESPACES is not set
1716 CONFIG_BLK_DEV_INITRD=y
1717 CONFIG_INITRAMFS_SOURCE=""
1718 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
1719 @@ -63,11 +61,13 @@
1720 CONFIG_PRINTK=y
1721 CONFIG_BUG=y
1722 CONFIG_ELF_CORE=y
1723 +# CONFIG_COMPAT_BRK is not set
1724 # CONFIG_BASE_FULL is not set
1725 CONFIG_FUTEX=y
1726 CONFIG_ANON_INODES=y
1727 CONFIG_EPOLL=y
1728 CONFIG_SIGNALFD=y
1729 +CONFIG_TIMERFD=y
1730 CONFIG_EVENTFD=y
1731 CONFIG_SHMEM=y
1732 CONFIG_VM_EVENT_COUNTERS=y
1733 @@ -75,6 +75,14 @@
1734 # CONFIG_SLAB is not set
1735 CONFIG_SLUB=y
1736 # CONFIG_SLOB is not set
1737 +CONFIG_PROFILING=y
1738 +# CONFIG_MARKERS is not set
1739 +CONFIG_OPROFILE=m
1740 +CONFIG_HAVE_OPROFILE=y
1741 +CONFIG_KPROBES=y
1742 +CONFIG_HAVE_KPROBES=y
1743 +# CONFIG_HAVE_KRETPROBES is not set
1744 +CONFIG_PROC_PAGE_MONITOR=y
1745 CONFIG_SLABINFO=y
1746 CONFIG_RT_MUTEXES=y
1747 # CONFIG_TINY_SHMEM is not set
1748 @@ -103,10 +111,15 @@
1749 CONFIG_DEFAULT_CFQ=y
1750 # CONFIG_DEFAULT_NOOP is not set
1751 CONFIG_DEFAULT_IOSCHED="cfq"
1752 +CONFIG_CLASSIC_RCU=y
1753
1754 #
1755 # System Type and features
1756 #
1757 +CONFIG_TICK_ONESHOT=y
1758 +CONFIG_NO_HZ=y
1759 +CONFIG_HIGH_RES_TIMERS=y
1760 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
1761 CONFIG_SUBARCH_AVR32B=y
1762 CONFIG_MMU=y
1763 CONFIG_PERFORMANCE_COUNTERS=y
1764 @@ -118,12 +131,16 @@
1765 # CONFIG_BOARD_ATSTK1002 is not set
1766 CONFIG_BOARD_ATSTK1003=y
1767 # CONFIG_BOARD_ATSTK1004 is not set
1768 +# CONFIG_BOARD_ATSTK1006 is not set
1769 # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
1770 # CONFIG_BOARD_ATSTK100X_SPI1 is not set
1771 # CONFIG_BOARD_ATSTK1000_J2_LED is not set
1772 # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
1773 # CONFIG_BOARD_ATSTK1000_J2_RGB is not set
1774 CONFIG_BOARD_ATSTK1000_EXTDAC=y
1775 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
1776 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
1777 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
1778 CONFIG_LOADER_U_BOOT=y
1779
1780 #
1781 @@ -132,6 +149,7 @@
1782 # CONFIG_AP700X_32_BIT_SMC is not set
1783 CONFIG_AP700X_16_BIT_SMC=y
1784 # CONFIG_AP700X_8_BIT_SMC is not set
1785 +CONFIG_GPIO_DEV=y
1786 CONFIG_LOAD_ADDRESS=0x10000000
1787 CONFIG_ENTRY_ADDRESS=0x90000000
1788 CONFIG_PHYS_OFFSET=0x10000000
1789 @@ -157,16 +175,26 @@
1790 CONFIG_ZONE_DMA_FLAG=0
1791 CONFIG_VIRT_TO_BUS=y
1792 # CONFIG_OWNERSHIP_TRACE is not set
1793 +CONFIG_NMI_DEBUGGING=y
1794 +CONFIG_DW_DMAC=y
1795 # CONFIG_HZ_100 is not set
1796 CONFIG_HZ_250=y
1797 # CONFIG_HZ_300 is not set
1798 # CONFIG_HZ_1000 is not set
1799 CONFIG_HZ=250
1800 +# CONFIG_SCHED_HRTICK is not set
1801 CONFIG_CMDLINE=""
1802
1803 #
1804 # Power management options
1805 #
1806 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
1807 +CONFIG_PM=y
1808 +# CONFIG_PM_LEGACY is not set
1809 +# CONFIG_PM_DEBUG is not set
1810 +CONFIG_PM_SLEEP=y
1811 +CONFIG_SUSPEND=y
1812 +CONFIG_SUSPEND_FREEZER=y
1813
1814 #
1815 # CPU Frequency scaling
1816 @@ -175,9 +203,9 @@
1817 CONFIG_CPU_FREQ_TABLE=y
1818 # CONFIG_CPU_FREQ_DEBUG is not set
1819 # CONFIG_CPU_FREQ_STAT is not set
1820 -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
1821 +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
1822 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
1823 -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
1824 +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
1825 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
1826 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
1827 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
1828 @@ -260,6 +288,7 @@
1829 # CONFIG_NET_PKTGEN is not set
1830 # CONFIG_NET_TCPPROBE is not set
1831 # CONFIG_HAMRADIO is not set
1832 +# CONFIG_CAN is not set
1833 # CONFIG_IRDA is not set
1834 # CONFIG_BT is not set
1835 # CONFIG_AF_RXRPC is not set
1836 @@ -376,13 +405,18 @@
1837 CONFIG_BLK_DEV_RAM=m
1838 CONFIG_BLK_DEV_RAM_COUNT=16
1839 CONFIG_BLK_DEV_RAM_SIZE=4096
1840 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
1841 +# CONFIG_BLK_DEV_XIP is not set
1842 # CONFIG_CDROM_PKTCDVD is not set
1843 # CONFIG_ATA_OVER_ETH is not set
1844 CONFIG_MISC_DEVICES=y
1845 +CONFIG_ATMEL_PWM=m
1846 +CONFIG_ATMEL_TCLIB=y
1847 +CONFIG_ATMEL_TCB_CLKSRC=y
1848 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
1849 # CONFIG_EEPROM_93CX6 is not set
1850 CONFIG_ATMEL_SSC=m
1851 -# CONFIG_IDE is not set
1852 +# CONFIG_ENCLOSURE_SERVICES is not set
1853 +# CONFIG_HAVE_IDE is not set
1854
1855 #
1856 # SCSI device support
1857 @@ -427,6 +461,7 @@
1858 # CONFIG_SCSI_DEBUG is not set
1859 CONFIG_ATA=m
1860 # CONFIG_ATA_NONSTANDARD is not set
1861 +# CONFIG_SATA_MV is not set
1862 CONFIG_PATA_AT32=m
1863 # CONFIG_PATA_PLATFORM is not set
1864 # CONFIG_MD is not set
1865 @@ -460,7 +495,6 @@
1866 # CONFIG_PPPOL2TP is not set
1867 # CONFIG_SLIP is not set
1868 CONFIG_SLHC=m
1869 -# CONFIG_SHAPER is not set
1870 # CONFIG_NETCONSOLE is not set
1871 # CONFIG_NETPOLL is not set
1872 # CONFIG_NET_POLL_CONTROLLER is not set
1873 @@ -528,6 +562,7 @@
1874 #
1875 CONFIG_SERIAL_ATMEL=y
1876 CONFIG_SERIAL_ATMEL_CONSOLE=y
1877 +CONFIG_SERIAL_ATMEL_PDC=y
1878 # CONFIG_SERIAL_ATMEL_TTYAT is not set
1879 CONFIG_SERIAL_CORE=y
1880 CONFIG_SERIAL_CORE_CONSOLE=y
1881 @@ -535,8 +570,6 @@
1882 # CONFIG_LEGACY_PTYS is not set
1883 # CONFIG_IPMI_HANDLER is not set
1884 # CONFIG_HW_RANDOM is not set
1885 -# CONFIG_RTC is not set
1886 -# CONFIG_GEN_RTC is not set
1887 # CONFIG_R3964 is not set
1888 # CONFIG_RAW_DRIVER is not set
1889 # CONFIG_TCG_TPM is not set
1890 @@ -554,6 +587,7 @@
1891 #
1892 # I2C Hardware Bus support
1893 #
1894 +CONFIG_I2C_ATMELTWI=m
1895 CONFIG_I2C_GPIO=m
1896 # CONFIG_I2C_OCORES is not set
1897 # CONFIG_I2C_PARPORT_LIGHT is not set
1898 @@ -564,13 +598,12 @@
1899 #
1900 # Miscellaneous I2C Chip support
1901 #
1902 -# CONFIG_SENSORS_DS1337 is not set
1903 -# CONFIG_SENSORS_DS1374 is not set
1904 # CONFIG_DS1682 is not set
1905 # CONFIG_SENSORS_EEPROM is not set
1906 # CONFIG_SENSORS_PCF8574 is not set
1907 -# CONFIG_SENSORS_PCA9539 is not set
1908 +# CONFIG_PCF8575 is not set
1909 # CONFIG_SENSORS_PCF8591 is not set
1910 +# CONFIG_TPS65010 is not set
1911 # CONFIG_SENSORS_MAX6875 is not set
1912 # CONFIG_SENSORS_TSL2550 is not set
1913 # CONFIG_I2C_DEBUG_CORE is not set
1914 @@ -597,9 +630,27 @@
1915 # CONFIG_SPI_AT25 is not set
1916 CONFIG_SPI_SPIDEV=m
1917 # CONFIG_SPI_TLE62X0 is not set
1918 +CONFIG_HAVE_GPIO_LIB=y
1919 +
1920 +#
1921 +# GPIO Support
1922 +#
1923 +# CONFIG_DEBUG_GPIO is not set
1924 +
1925 +#
1926 +# I2C GPIO expanders:
1927 +#
1928 +# CONFIG_GPIO_PCA953X is not set
1929 +# CONFIG_GPIO_PCF857X is not set
1930 +
1931 +#
1932 +# SPI GPIO expanders:
1933 +#
1934 +# CONFIG_GPIO_MCP23S08 is not set
1935 # CONFIG_W1 is not set
1936 # CONFIG_POWER_SUPPLY is not set
1937 # CONFIG_HWMON is not set
1938 +# CONFIG_THERMAL is not set
1939 CONFIG_WATCHDOG=y
1940 # CONFIG_WATCHDOG_NOWAYOUT is not set
1941
1942 @@ -665,12 +716,18 @@
1943 #
1944 # Generic devices
1945 #
1946 +CONFIG_SND_AC97_CODEC=m
1947 # CONFIG_SND_DUMMY is not set
1948 # CONFIG_SND_MTPAV is not set
1949 # CONFIG_SND_SERIAL_U16550 is not set
1950 # CONFIG_SND_MPU401 is not set
1951
1952 #
1953 +# AVR32 devices
1954 +#
1955 +CONFIG_SND_ATMEL_AC97=m
1956 +
1957 +#
1958 # SPI devices
1959 #
1960 CONFIG_SND_AT73C213=m
1961 @@ -686,9 +743,14 @@
1962 #
1963
1964 #
1965 +# ALSA SoC audio for Freescale SOCs
1966 +#
1967 +
1968 +#
1969 # Open Sound System
1970 #
1971 # CONFIG_SOUND_PRIME is not set
1972 +CONFIG_AC97_BUS=m
1973 # CONFIG_HID_SUPPORT is not set
1974 CONFIG_USB_SUPPORT=y
1975 # CONFIG_USB_ARCH_HAS_HCD is not set
1976 @@ -698,10 +760,6 @@
1977 #
1978 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1979 #
1980 -
1981 -#
1982 -# USB Gadget Support
1983 -#
1984 CONFIG_USB_GADGET=y
1985 # CONFIG_USB_GADGET_DEBUG is not set
1986 # CONFIG_USB_GADGET_DEBUG_FILES is not set
1987 @@ -729,27 +787,31 @@
1988 # CONFIG_USB_FILE_STORAGE_TEST is not set
1989 CONFIG_USB_G_SERIAL=m
1990 # CONFIG_USB_MIDI_GADGET is not set
1991 -CONFIG_MMC=m
1992 +# CONFIG_USB_G_PRINTER is not set
1993 +CONFIG_MMC=y
1994 # CONFIG_MMC_DEBUG is not set
1995 # CONFIG_MMC_UNSAFE_RESUME is not set
1996
1997 #
1998 # MMC/SD Card Drivers
1999 #
2000 -CONFIG_MMC_BLOCK=m
2001 +CONFIG_MMC_BLOCK=y
2002 # CONFIG_MMC_BLOCK_BOUNCE is not set
2003 # CONFIG_SDIO_UART is not set
2004
2005 #
2006 # MMC/SD Host Controller Drivers
2007 #
2008 +CONFIG_MMC_ATMELMCI=y
2009 CONFIG_MMC_SPI=m
2010 +# CONFIG_MEMSTICK is not set
2011 CONFIG_NEW_LEDS=y
2012 CONFIG_LEDS_CLASS=y
2013
2014 #
2015 # LED drivers
2016 #
2017 +CONFIG_LEDS_ATMEL_PWM=m
2018 CONFIG_LEDS_GPIO=y
2019
2020 #
2021 @@ -786,19 +848,22 @@
2022 # CONFIG_RTC_DRV_PCF8563 is not set
2023 # CONFIG_RTC_DRV_PCF8583 is not set
2024 # CONFIG_RTC_DRV_M41T80 is not set
2025 +# CONFIG_RTC_DRV_S35390A is not set
2026
2027 #
2028 # SPI RTC drivers
2029 #
2030 -# CONFIG_RTC_DRV_RS5C348 is not set
2031 # CONFIG_RTC_DRV_MAX6902 is not set
2032 +# CONFIG_RTC_DRV_R9701 is not set
2033 +# CONFIG_RTC_DRV_RS5C348 is not set
2034
2035 #
2036 # Platform RTC drivers
2037 #
2038 +# CONFIG_RTC_DRV_DS1511 is not set
2039 # CONFIG_RTC_DRV_DS1553 is not set
2040 -# CONFIG_RTC_DRV_STK17TA8 is not set
2041 # CONFIG_RTC_DRV_DS1742 is not set
2042 +# CONFIG_RTC_DRV_STK17TA8 is not set
2043 # CONFIG_RTC_DRV_M48T86 is not set
2044 # CONFIG_RTC_DRV_M48T59 is not set
2045 # CONFIG_RTC_DRV_V3020 is not set
2046 @@ -816,13 +881,13 @@
2047 #
2048 # File systems
2049 #
2050 -CONFIG_EXT2_FS=m
2051 +CONFIG_EXT2_FS=y
2052 # CONFIG_EXT2_FS_XATTR is not set
2053 # CONFIG_EXT2_FS_XIP is not set
2054 -CONFIG_EXT3_FS=m
2055 +CONFIG_EXT3_FS=y
2056 # CONFIG_EXT3_FS_XATTR is not set
2057 # CONFIG_EXT4DEV_FS is not set
2058 -CONFIG_JBD=m
2059 +CONFIG_JBD=y
2060 # CONFIG_JBD_DEBUG is not set
2061 # CONFIG_REISERFS_FS is not set
2062 # CONFIG_JFS_FS is not set
2063 @@ -830,12 +895,10 @@
2064 # CONFIG_XFS_FS is not set
2065 # CONFIG_GFS2_FS is not set
2066 # CONFIG_OCFS2_FS is not set
2067 -# CONFIG_MINIX_FS is not set
2068 -# CONFIG_ROMFS_FS is not set
2069 +# CONFIG_DNOTIFY is not set
2070 CONFIG_INOTIFY=y
2071 CONFIG_INOTIFY_USER=y
2072 # CONFIG_QUOTA is not set
2073 -# CONFIG_DNOTIFY is not set
2074 # CONFIG_AUTOFS_FS is not set
2075 # CONFIG_AUTOFS4_FS is not set
2076 CONFIG_FUSE_FS=m
2077 @@ -866,7 +929,7 @@
2078 CONFIG_TMPFS=y
2079 # CONFIG_TMPFS_POSIX_ACL is not set
2080 # CONFIG_HUGETLB_PAGE is not set
2081 -CONFIG_CONFIGFS_FS=m
2082 +CONFIG_CONFIGFS_FS=y
2083
2084 #
2085 # Miscellaneous filesystems
2086 @@ -891,8 +954,10 @@
2087 # CONFIG_JFFS2_RUBIN is not set
2088 # CONFIG_CRAMFS is not set
2089 # CONFIG_VXFS_FS is not set
2090 +# CONFIG_MINIX_FS is not set
2091 # CONFIG_HPFS_FS is not set
2092 # CONFIG_QNX4FS_FS is not set
2093 +# CONFIG_ROMFS_FS is not set
2094 # CONFIG_SYSV_FS is not set
2095 # CONFIG_UFS_FS is not set
2096 # CONFIG_NETWORK_FILESYSTEMS is not set
2097 @@ -943,11 +1008,6 @@
2098 # CONFIG_NLS_KOI8_U is not set
2099 CONFIG_NLS_UTF8=m
2100 # CONFIG_DLM is not set
2101 -CONFIG_INSTRUMENTATION=y
2102 -CONFIG_PROFILING=y
2103 -CONFIG_OPROFILE=m
2104 -CONFIG_KPROBES=y
2105 -# CONFIG_MARKERS is not set
2106
2107 #
2108 # Kernel hacking
2109 @@ -965,6 +1025,7 @@
2110 CONFIG_SCHED_DEBUG=y
2111 # CONFIG_SCHEDSTATS is not set
2112 # CONFIG_TIMER_STATS is not set
2113 +# CONFIG_SLUB_STATS is not set
2114 # CONFIG_DEBUG_RT_MUTEXES is not set
2115 # CONFIG_RT_MUTEX_TESTER is not set
2116 # CONFIG_DEBUG_SPINLOCK is not set
2117 @@ -981,9 +1042,10 @@
2118 # CONFIG_DEBUG_LIST is not set
2119 # CONFIG_DEBUG_SG is not set
2120 CONFIG_FRAME_POINTER=y
2121 -CONFIG_FORCED_INLINING=y
2122 # CONFIG_BOOT_PRINTK_DELAY is not set
2123 # CONFIG_RCU_TORTURE_TEST is not set
2124 +# CONFIG_KPROBES_SANITY_TEST is not set
2125 +# CONFIG_BACKTRACE_SELF_TEST is not set
2126 # CONFIG_LKDTM is not set
2127 # CONFIG_FAULT_INJECTION is not set
2128 # CONFIG_SAMPLES is not set
2129 @@ -1009,6 +1071,7 @@
2130 CONFIG_AUDIT_GENERIC=y
2131 CONFIG_ZLIB_INFLATE=y
2132 CONFIG_ZLIB_DEFLATE=y
2133 +CONFIG_GENERIC_ALLOCATOR=y
2134 CONFIG_PLIST=y
2135 CONFIG_HAS_IOMEM=y
2136 CONFIG_HAS_IOPORT=y
2137 --- a/arch/avr32/configs/atstk1004_defconfig
2138 +++ b/arch/avr32/configs/atstk1004_defconfig
2139 @@ -1,7 +1,7 @@
2140 #
2141 # Automatically generated make config: don't edit
2142 -# Linux kernel version: 2.6.24-rc7
2143 -# Wed Jan 9 23:04:20 2008
2144 +# Linux kernel version: 2.6.25.4
2145 +# Wed Jun 11 15:37:49 2008
2146 #
2147 CONFIG_AVR32=y
2148 CONFIG_GENERIC_GPIO=y
2149 @@ -13,10 +13,10 @@
2150 CONFIG_GENERIC_IRQ_PROBE=y
2151 CONFIG_RWSEM_GENERIC_SPINLOCK=y
2152 CONFIG_GENERIC_TIME=y
2153 +CONFIG_GENERIC_CLOCKEVENTS=y
2154 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
2155 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
2156 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
2157 -CONFIG_ARCH_SUPPORTS_OPROFILE=y
2158 CONFIG_GENERIC_HWEIGHT=y
2159 CONFIG_GENERIC_CALIBRATE_DELAY=y
2160 CONFIG_GENERIC_BUG=y
2161 @@ -34,15 +34,15 @@
2162 # CONFIG_POSIX_MQUEUE is not set
2163 # CONFIG_BSD_PROCESS_ACCT is not set
2164 # CONFIG_TASKSTATS is not set
2165 -# CONFIG_USER_NS is not set
2166 -# CONFIG_PID_NS is not set
2167 # CONFIG_AUDIT is not set
2168 # CONFIG_IKCONFIG is not set
2169 CONFIG_LOG_BUF_SHIFT=14
2170 # CONFIG_CGROUPS is not set
2171 -# CONFIG_FAIR_GROUP_SCHED is not set
2172 +# CONFIG_GROUP_SCHED is not set
2173 CONFIG_SYSFS_DEPRECATED=y
2174 +CONFIG_SYSFS_DEPRECATED_V2=y
2175 # CONFIG_RELAY is not set
2176 +# CONFIG_NAMESPACES is not set
2177 # CONFIG_BLK_DEV_INITRD is not set
2178 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
2179 CONFIG_SYSCTL=y
2180 @@ -54,24 +54,37 @@
2181 CONFIG_PRINTK=y
2182 CONFIG_BUG=y
2183 CONFIG_ELF_CORE=y
2184 +# CONFIG_COMPAT_BRK is not set
2185 # CONFIG_BASE_FULL is not set
2186 # CONFIG_FUTEX is not set
2187 # CONFIG_EPOLL is not set
2188 # CONFIG_SIGNALFD is not set
2189 +# CONFIG_TIMERFD is not set
2190 # CONFIG_EVENTFD is not set
2191 CONFIG_SHMEM=y
2192 CONFIG_VM_EVENT_COUNTERS=y
2193 # CONFIG_SLAB is not set
2194 # CONFIG_SLUB is not set
2195 CONFIG_SLOB=y
2196 +# CONFIG_PROFILING is not set
2197 +# CONFIG_MARKERS is not set
2198 +CONFIG_HAVE_OPROFILE=y
2199 +CONFIG_HAVE_KPROBES=y
2200 +# CONFIG_HAVE_KRETPROBES is not set
2201 +# CONFIG_PROC_PAGE_MONITOR is not set
2202 # CONFIG_TINY_SHMEM is not set
2203 CONFIG_BASE_SMALL=1
2204 # CONFIG_MODULES is not set
2205 # CONFIG_BLOCK is not set
2206 +CONFIG_CLASSIC_RCU=y
2207
2208 #
2209 # System Type and features
2210 #
2211 +# CONFIG_TICK_ONESHOT is not set
2212 +# CONFIG_NO_HZ is not set
2213 +# CONFIG_HIGH_RES_TIMERS is not set
2214 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
2215 CONFIG_SUBARCH_AVR32B=y
2216 CONFIG_MMU=y
2217 CONFIG_PERFORMANCE_COUNTERS=y
2218 @@ -83,10 +96,14 @@
2219 # CONFIG_BOARD_ATSTK1002 is not set
2220 # CONFIG_BOARD_ATSTK1003 is not set
2221 CONFIG_BOARD_ATSTK1004=y
2222 +# CONFIG_BOARD_ATSTK1006 is not set
2223 # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
2224 # CONFIG_BOARD_ATSTK100X_SPI1 is not set
2225 # CONFIG_BOARD_ATSTK1000_J2_LED is not set
2226 CONFIG_BOARD_ATSTK1000_EXTDAC=y
2227 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
2228 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
2229 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
2230 CONFIG_LOADER_U_BOOT=y
2231
2232 #
2233 @@ -95,6 +112,7 @@
2234 # CONFIG_AP700X_32_BIT_SMC is not set
2235 CONFIG_AP700X_16_BIT_SMC=y
2236 # CONFIG_AP700X_8_BIT_SMC is not set
2237 +# CONFIG_GPIO_DEV is not set
2238 CONFIG_LOAD_ADDRESS=0x10000000
2239 CONFIG_ENTRY_ADDRESS=0x90000000
2240 CONFIG_PHYS_OFFSET=0x10000000
2241 @@ -120,34 +138,26 @@
2242 CONFIG_ZONE_DMA_FLAG=0
2243 CONFIG_VIRT_TO_BUS=y
2244 # CONFIG_OWNERSHIP_TRACE is not set
2245 +# CONFIG_NMI_DEBUGGING is not set
2246 +CONFIG_DW_DMAC=y
2247 # CONFIG_HZ_100 is not set
2248 CONFIG_HZ_250=y
2249 # CONFIG_HZ_300 is not set
2250 # CONFIG_HZ_1000 is not set
2251 CONFIG_HZ=250
2252 +# CONFIG_SCHED_HRTICK is not set
2253 CONFIG_CMDLINE=""
2254
2255 #
2256 # Power management options
2257 #
2258 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
2259 +# CONFIG_PM is not set
2260
2261 #
2262 # CPU Frequency scaling
2263 #
2264 -CONFIG_CPU_FREQ=y
2265 -CONFIG_CPU_FREQ_TABLE=y
2266 -# CONFIG_CPU_FREQ_DEBUG is not set
2267 -# CONFIG_CPU_FREQ_STAT is not set
2268 -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
2269 -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
2270 -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
2271 -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
2272 -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
2273 -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
2274 -CONFIG_CPU_FREQ_GOV_USERSPACE=y
2275 -CONFIG_CPU_FREQ_GOV_ONDEMAND=y
2276 -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
2277 -CONFIG_CPU_FREQ_AT32AP=y
2278 +# CONFIG_CPU_FREQ is not set
2279
2280 #
2281 # Bus options
2282 @@ -222,6 +232,7 @@
2283 #
2284 # CONFIG_NET_PKTGEN is not set
2285 # CONFIG_HAMRADIO is not set
2286 +# CONFIG_CAN is not set
2287 # CONFIG_IRDA is not set
2288 # CONFIG_BT is not set
2289 # CONFIG_AF_RXRPC is not set
2290 @@ -321,6 +332,7 @@
2291 # CONFIG_MTD_UBI is not set
2292 # CONFIG_PARPORT is not set
2293 # CONFIG_MISC_DEVICES is not set
2294 +# CONFIG_HAVE_IDE is not set
2295
2296 #
2297 # SCSI device support
2298 @@ -358,6 +370,7 @@
2299 #
2300 CONFIG_SERIAL_ATMEL=y
2301 CONFIG_SERIAL_ATMEL_CONSOLE=y
2302 +# CONFIG_SERIAL_ATMEL_PDC is not set
2303 # CONFIG_SERIAL_ATMEL_TTYAT is not set
2304 CONFIG_SERIAL_CORE=y
2305 CONFIG_SERIAL_CORE_CONSOLE=y
2306 @@ -365,8 +378,6 @@
2307 # CONFIG_LEGACY_PTYS is not set
2308 # CONFIG_IPMI_HANDLER is not set
2309 # CONFIG_HW_RANDOM is not set
2310 -# CONFIG_RTC is not set
2311 -# CONFIG_GEN_RTC is not set
2312 # CONFIG_R3964 is not set
2313 # CONFIG_TCG_TPM is not set
2314 # CONFIG_I2C is not set
2315 @@ -389,9 +400,24 @@
2316 # CONFIG_SPI_AT25 is not set
2317 # CONFIG_SPI_SPIDEV is not set
2318 # CONFIG_SPI_TLE62X0 is not set
2319 +CONFIG_HAVE_GPIO_LIB=y
2320 +
2321 +#
2322 +# GPIO Support
2323 +#
2324 +
2325 +#
2326 +# I2C GPIO expanders:
2327 +#
2328 +
2329 +#
2330 +# SPI GPIO expanders:
2331 +#
2332 +# CONFIG_GPIO_MCP23S08 is not set
2333 # CONFIG_W1 is not set
2334 # CONFIG_POWER_SUPPLY is not set
2335 # CONFIG_HWMON is not set
2336 +# CONFIG_THERMAL is not set
2337 CONFIG_WATCHDOG=y
2338 # CONFIG_WATCHDOG_NOWAYOUT is not set
2339
2340 @@ -471,10 +497,6 @@
2341 #
2342 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
2343 #
2344 -
2345 -#
2346 -# USB Gadget Support
2347 -#
2348 CONFIG_USB_GADGET=y
2349 # CONFIG_USB_GADGET_DEBUG_FILES is not set
2350 CONFIG_USB_GADGET_SELECTED=y
2351 @@ -499,7 +521,9 @@
2352 # CONFIG_USB_FILE_STORAGE is not set
2353 # CONFIG_USB_G_SERIAL is not set
2354 # CONFIG_USB_MIDI_GADGET is not set
2355 +# CONFIG_USB_G_PRINTER is not set
2356 # CONFIG_MMC is not set
2357 +# CONFIG_MEMSTICK is not set
2358 # CONFIG_NEW_LEDS is not set
2359 CONFIG_RTC_LIB=y
2360 CONFIG_RTC_CLASS=y
2361 @@ -519,15 +543,17 @@
2362 #
2363 # SPI RTC drivers
2364 #
2365 -# CONFIG_RTC_DRV_RS5C348 is not set
2366 # CONFIG_RTC_DRV_MAX6902 is not set
2367 +# CONFIG_RTC_DRV_R9701 is not set
2368 +# CONFIG_RTC_DRV_RS5C348 is not set
2369
2370 #
2371 # Platform RTC drivers
2372 #
2373 +# CONFIG_RTC_DRV_DS1511 is not set
2374 # CONFIG_RTC_DRV_DS1553 is not set
2375 -# CONFIG_RTC_DRV_STK17TA8 is not set
2376 # CONFIG_RTC_DRV_DS1742 is not set
2377 +# CONFIG_RTC_DRV_STK17TA8 is not set
2378 # CONFIG_RTC_DRV_M48T86 is not set
2379 # CONFIG_RTC_DRV_M48T59 is not set
2380 # CONFIG_RTC_DRV_V3020 is not set
2381 @@ -545,9 +571,9 @@
2382 #
2383 # File systems
2384 #
2385 +# CONFIG_DNOTIFY is not set
2386 # CONFIG_INOTIFY is not set
2387 # CONFIG_QUOTA is not set
2388 -# CONFIG_DNOTIFY is not set
2389 # CONFIG_AUTOFS_FS is not set
2390 # CONFIG_AUTOFS4_FS is not set
2391 # CONFIG_FUSE_FS is not set
2392 @@ -580,7 +606,6 @@
2393 # CONFIG_NETWORK_FILESYSTEMS is not set
2394 # CONFIG_NLS is not set
2395 # CONFIG_DLM is not set
2396 -# CONFIG_INSTRUMENTATION is not set
2397
2398 #
2399 # Kernel hacking
2400 @@ -616,6 +641,7 @@
2401 # CONFIG_LIBCRC32C is not set
2402 CONFIG_ZLIB_INFLATE=y
2403 CONFIG_ZLIB_DEFLATE=y
2404 +CONFIG_GENERIC_ALLOCATOR=y
2405 CONFIG_HAS_IOMEM=y
2406 CONFIG_HAS_IOPORT=y
2407 CONFIG_HAS_DMA=y
2408 --- /dev/null
2409 +++ b/arch/avr32/configs/atstk1006_defconfig
2410 @@ -0,0 +1,1235 @@
2411 +#
2412 +# Automatically generated make config: don't edit
2413 +# Linux kernel version: 2.6.25.4
2414 +# Wed Jun 11 15:40:45 2008
2415 +#
2416 +CONFIG_AVR32=y
2417 +CONFIG_GENERIC_GPIO=y
2418 +CONFIG_GENERIC_HARDIRQS=y
2419 +CONFIG_STACKTRACE_SUPPORT=y
2420 +CONFIG_LOCKDEP_SUPPORT=y
2421 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
2422 +CONFIG_HARDIRQS_SW_RESEND=y
2423 +CONFIG_GENERIC_IRQ_PROBE=y
2424 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
2425 +CONFIG_GENERIC_TIME=y
2426 +CONFIG_GENERIC_CLOCKEVENTS=y
2427 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
2428 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
2429 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
2430 +CONFIG_GENERIC_HWEIGHT=y
2431 +CONFIG_GENERIC_CALIBRATE_DELAY=y
2432 +CONFIG_GENERIC_BUG=y
2433 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
2434 +
2435 +#
2436 +# General setup
2437 +#
2438 +CONFIG_EXPERIMENTAL=y
2439 +CONFIG_BROKEN_ON_SMP=y
2440 +CONFIG_INIT_ENV_ARG_LIMIT=32
2441 +CONFIG_LOCALVERSION=""
2442 +# CONFIG_LOCALVERSION_AUTO is not set
2443 +CONFIG_SWAP=y
2444 +CONFIG_SYSVIPC=y
2445 +CONFIG_SYSVIPC_SYSCTL=y
2446 +CONFIG_POSIX_MQUEUE=y
2447 +# CONFIG_BSD_PROCESS_ACCT is not set
2448 +# CONFIG_TASKSTATS is not set
2449 +# CONFIG_AUDIT is not set
2450 +# CONFIG_IKCONFIG is not set
2451 +CONFIG_LOG_BUF_SHIFT=14
2452 +# CONFIG_CGROUPS is not set
2453 +# CONFIG_GROUP_SCHED is not set
2454 +CONFIG_SYSFS_DEPRECATED=y
2455 +CONFIG_SYSFS_DEPRECATED_V2=y
2456 +CONFIG_RELAY=y
2457 +# CONFIG_NAMESPACES is not set
2458 +CONFIG_BLK_DEV_INITRD=y
2459 +CONFIG_INITRAMFS_SOURCE=""
2460 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
2461 +CONFIG_SYSCTL=y
2462 +CONFIG_EMBEDDED=y
2463 +# CONFIG_SYSCTL_SYSCALL is not set
2464 +CONFIG_KALLSYMS=y
2465 +# CONFIG_KALLSYMS_ALL is not set
2466 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
2467 +CONFIG_HOTPLUG=y
2468 +CONFIG_PRINTK=y
2469 +CONFIG_BUG=y
2470 +CONFIG_ELF_CORE=y
2471 +# CONFIG_COMPAT_BRK is not set
2472 +# CONFIG_BASE_FULL is not set
2473 +CONFIG_FUTEX=y
2474 +CONFIG_ANON_INODES=y
2475 +CONFIG_EPOLL=y
2476 +CONFIG_SIGNALFD=y
2477 +CONFIG_TIMERFD=y
2478 +CONFIG_EVENTFD=y
2479 +CONFIG_SHMEM=y
2480 +CONFIG_VM_EVENT_COUNTERS=y
2481 +CONFIG_SLUB_DEBUG=y
2482 +# CONFIG_SLAB is not set
2483 +CONFIG_SLUB=y
2484 +# CONFIG_SLOB is not set
2485 +CONFIG_PROFILING=y
2486 +# CONFIG_MARKERS is not set
2487 +CONFIG_OPROFILE=m
2488 +CONFIG_HAVE_OPROFILE=y
2489 +CONFIG_KPROBES=y
2490 +CONFIG_HAVE_KPROBES=y
2491 +# CONFIG_HAVE_KRETPROBES is not set
2492 +CONFIG_PROC_PAGE_MONITOR=y
2493 +CONFIG_SLABINFO=y
2494 +CONFIG_RT_MUTEXES=y
2495 +# CONFIG_TINY_SHMEM is not set
2496 +CONFIG_BASE_SMALL=1
2497 +CONFIG_MODULES=y
2498 +CONFIG_MODULE_UNLOAD=y
2499 +# CONFIG_MODULE_FORCE_UNLOAD is not set
2500 +# CONFIG_MODVERSIONS is not set
2501 +# CONFIG_MODULE_SRCVERSION_ALL is not set
2502 +# CONFIG_KMOD is not set
2503 +CONFIG_BLOCK=y
2504 +# CONFIG_LBD is not set
2505 +# CONFIG_BLK_DEV_IO_TRACE is not set
2506 +# CONFIG_LSF is not set
2507 +# CONFIG_BLK_DEV_BSG is not set
2508 +
2509 +#
2510 +# IO Schedulers
2511 +#
2512 +CONFIG_IOSCHED_NOOP=y
2513 +# CONFIG_IOSCHED_AS is not set
2514 +# CONFIG_IOSCHED_DEADLINE is not set
2515 +CONFIG_IOSCHED_CFQ=y
2516 +# CONFIG_DEFAULT_AS is not set
2517 +# CONFIG_DEFAULT_DEADLINE is not set
2518 +CONFIG_DEFAULT_CFQ=y
2519 +# CONFIG_DEFAULT_NOOP is not set
2520 +CONFIG_DEFAULT_IOSCHED="cfq"
2521 +CONFIG_CLASSIC_RCU=y
2522 +
2523 +#
2524 +# System Type and features
2525 +#
2526 +CONFIG_TICK_ONESHOT=y
2527 +CONFIG_NO_HZ=y
2528 +CONFIG_HIGH_RES_TIMERS=y
2529 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
2530 +CONFIG_SUBARCH_AVR32B=y
2531 +CONFIG_MMU=y
2532 +CONFIG_PERFORMANCE_COUNTERS=y
2533 +CONFIG_PLATFORM_AT32AP=y
2534 +CONFIG_CPU_AT32AP700X=y
2535 +CONFIG_CPU_AT32AP7000=y
2536 +CONFIG_BOARD_ATSTK1000=y
2537 +# CONFIG_BOARD_ATNGW100 is not set
2538 +# CONFIG_BOARD_ATSTK1002 is not set
2539 +# CONFIG_BOARD_ATSTK1003 is not set
2540 +# CONFIG_BOARD_ATSTK1004 is not set
2541 +CONFIG_BOARD_ATSTK1006=y
2542 +# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
2543 +# CONFIG_BOARD_ATSTK100X_SPI1 is not set
2544 +# CONFIG_BOARD_ATSTK1000_J2_LED is not set
2545 +# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
2546 +# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
2547 +CONFIG_BOARD_ATSTK1000_EXTDAC=y
2548 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
2549 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
2550 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
2551 +CONFIG_LOADER_U_BOOT=y
2552 +
2553 +#
2554 +# Atmel AVR32 AP options
2555 +#
2556 +# CONFIG_AP700X_32_BIT_SMC is not set
2557 +CONFIG_AP700X_16_BIT_SMC=y
2558 +# CONFIG_AP700X_8_BIT_SMC is not set
2559 +CONFIG_GPIO_DEV=y
2560 +CONFIG_LOAD_ADDRESS=0x10000000
2561 +CONFIG_ENTRY_ADDRESS=0x90000000
2562 +CONFIG_PHYS_OFFSET=0x10000000
2563 +CONFIG_PREEMPT_NONE=y
2564 +# CONFIG_PREEMPT_VOLUNTARY is not set
2565 +# CONFIG_PREEMPT is not set
2566 +# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
2567 +# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
2568 +# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
2569 +CONFIG_ARCH_FLATMEM_ENABLE=y
2570 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
2571 +# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
2572 +CONFIG_SELECT_MEMORY_MODEL=y
2573 +CONFIG_FLATMEM_MANUAL=y
2574 +# CONFIG_DISCONTIGMEM_MANUAL is not set
2575 +# CONFIG_SPARSEMEM_MANUAL is not set
2576 +CONFIG_FLATMEM=y
2577 +CONFIG_FLAT_NODE_MEM_MAP=y
2578 +# CONFIG_SPARSEMEM_STATIC is not set
2579 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
2580 +CONFIG_SPLIT_PTLOCK_CPUS=4
2581 +# CONFIG_RESOURCES_64BIT is not set
2582 +CONFIG_ZONE_DMA_FLAG=0
2583 +CONFIG_VIRT_TO_BUS=y
2584 +# CONFIG_OWNERSHIP_TRACE is not set
2585 +CONFIG_NMI_DEBUGGING=y
2586 +CONFIG_DW_DMAC=y
2587 +# CONFIG_HZ_100 is not set
2588 +CONFIG_HZ_250=y
2589 +# CONFIG_HZ_300 is not set
2590 +# CONFIG_HZ_1000 is not set
2591 +CONFIG_HZ=250
2592 +# CONFIG_SCHED_HRTICK is not set
2593 +CONFIG_CMDLINE=""
2594 +
2595 +#
2596 +# Power management options
2597 +#
2598 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
2599 +CONFIG_PM=y
2600 +# CONFIG_PM_LEGACY is not set
2601 +# CONFIG_PM_DEBUG is not set
2602 +CONFIG_PM_SLEEP=y
2603 +CONFIG_SUSPEND=y
2604 +CONFIG_SUSPEND_FREEZER=y
2605 +
2606 +#
2607 +# CPU Frequency scaling
2608 +#
2609 +CONFIG_CPU_FREQ=y
2610 +CONFIG_CPU_FREQ_TABLE=y
2611 +# CONFIG_CPU_FREQ_DEBUG is not set
2612 +# CONFIG_CPU_FREQ_STAT is not set
2613 +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
2614 +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
2615 +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
2616 +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
2617 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
2618 +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
2619 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
2620 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
2621 +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
2622 +CONFIG_CPU_FREQ_AT32AP=y
2623 +
2624 +#
2625 +# Bus options
2626 +#
2627 +# CONFIG_ARCH_SUPPORTS_MSI is not set
2628 +# CONFIG_PCCARD is not set
2629 +
2630 +#
2631 +# Executable file formats
2632 +#
2633 +CONFIG_BINFMT_ELF=y
2634 +# CONFIG_BINFMT_MISC is not set
2635 +
2636 +#
2637 +# Networking
2638 +#
2639 +CONFIG_NET=y
2640 +
2641 +#
2642 +# Networking options
2643 +#
2644 +CONFIG_PACKET=y
2645 +CONFIG_PACKET_MMAP=y
2646 +CONFIG_UNIX=y
2647 +CONFIG_XFRM=y
2648 +CONFIG_XFRM_USER=m
2649 +# CONFIG_XFRM_SUB_POLICY is not set
2650 +# CONFIG_XFRM_MIGRATE is not set
2651 +# CONFIG_XFRM_STATISTICS is not set
2652 +CONFIG_NET_KEY=m
2653 +# CONFIG_NET_KEY_MIGRATE is not set
2654 +CONFIG_INET=y
2655 +# CONFIG_IP_MULTICAST is not set
2656 +# CONFIG_IP_ADVANCED_ROUTER is not set
2657 +CONFIG_IP_FIB_HASH=y
2658 +CONFIG_IP_PNP=y
2659 +CONFIG_IP_PNP_DHCP=y
2660 +# CONFIG_IP_PNP_BOOTP is not set
2661 +# CONFIG_IP_PNP_RARP is not set
2662 +CONFIG_NET_IPIP=m
2663 +CONFIG_NET_IPGRE=m
2664 +# CONFIG_ARPD is not set
2665 +# CONFIG_SYN_COOKIES is not set
2666 +CONFIG_INET_AH=m
2667 +CONFIG_INET_ESP=m
2668 +# CONFIG_INET_IPCOMP is not set
2669 +# CONFIG_INET_XFRM_TUNNEL is not set
2670 +CONFIG_INET_TUNNEL=m
2671 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
2672 +CONFIG_INET_XFRM_MODE_TUNNEL=m
2673 +CONFIG_INET_XFRM_MODE_BEET=m
2674 +# CONFIG_INET_LRO is not set
2675 +CONFIG_INET_DIAG=y
2676 +CONFIG_INET_TCP_DIAG=y
2677 +# CONFIG_TCP_CONG_ADVANCED is not set
2678 +CONFIG_TCP_CONG_CUBIC=y
2679 +CONFIG_DEFAULT_TCP_CONG="cubic"
2680 +# CONFIG_TCP_MD5SIG is not set
2681 +CONFIG_IPV6=m
2682 +# CONFIG_IPV6_PRIVACY is not set
2683 +# CONFIG_IPV6_ROUTER_PREF is not set
2684 +# CONFIG_IPV6_OPTIMISTIC_DAD is not set
2685 +CONFIG_INET6_AH=m
2686 +CONFIG_INET6_ESP=m
2687 +CONFIG_INET6_IPCOMP=m
2688 +# CONFIG_IPV6_MIP6 is not set
2689 +CONFIG_INET6_XFRM_TUNNEL=m
2690 +CONFIG_INET6_TUNNEL=m
2691 +CONFIG_INET6_XFRM_MODE_TRANSPORT=m
2692 +CONFIG_INET6_XFRM_MODE_TUNNEL=m
2693 +CONFIG_INET6_XFRM_MODE_BEET=m
2694 +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
2695 +CONFIG_IPV6_SIT=m
2696 +CONFIG_IPV6_TUNNEL=m
2697 +# CONFIG_IPV6_MULTIPLE_TABLES is not set
2698 +# CONFIG_NETWORK_SECMARK is not set
2699 +# CONFIG_NETFILTER is not set
2700 +# CONFIG_IP_DCCP is not set
2701 +# CONFIG_IP_SCTP is not set
2702 +# CONFIG_TIPC is not set
2703 +# CONFIG_ATM is not set
2704 +CONFIG_BRIDGE=m
2705 +# CONFIG_VLAN_8021Q is not set
2706 +# CONFIG_DECNET is not set
2707 +CONFIG_LLC=m
2708 +# CONFIG_LLC2 is not set
2709 +# CONFIG_IPX is not set
2710 +# CONFIG_ATALK is not set
2711 +# CONFIG_X25 is not set
2712 +# CONFIG_LAPB is not set
2713 +# CONFIG_ECONET is not set
2714 +# CONFIG_WAN_ROUTER is not set
2715 +# CONFIG_NET_SCHED is not set
2716 +
2717 +#
2718 +# Network testing
2719 +#
2720 +# CONFIG_NET_PKTGEN is not set
2721 +# CONFIG_NET_TCPPROBE is not set
2722 +# CONFIG_HAMRADIO is not set
2723 +# CONFIG_CAN is not set
2724 +# CONFIG_IRDA is not set
2725 +# CONFIG_BT is not set
2726 +# CONFIG_AF_RXRPC is not set
2727 +
2728 +#
2729 +# Wireless
2730 +#
2731 +# CONFIG_CFG80211 is not set
2732 +# CONFIG_WIRELESS_EXT is not set
2733 +# CONFIG_MAC80211 is not set
2734 +# CONFIG_IEEE80211 is not set
2735 +# CONFIG_RFKILL is not set
2736 +# CONFIG_NET_9P is not set
2737 +
2738 +#
2739 +# Device Drivers
2740 +#
2741 +
2742 +#
2743 +# Generic Driver Options
2744 +#
2745 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
2746 +CONFIG_STANDALONE=y
2747 +# CONFIG_PREVENT_FIRMWARE_BUILD is not set
2748 +# CONFIG_FW_LOADER is not set
2749 +# CONFIG_DEBUG_DRIVER is not set
2750 +# CONFIG_DEBUG_DEVRES is not set
2751 +# CONFIG_SYS_HYPERVISOR is not set
2752 +# CONFIG_CONNECTOR is not set
2753 +CONFIG_MTD=y
2754 +# CONFIG_MTD_DEBUG is not set
2755 +# CONFIG_MTD_CONCAT is not set
2756 +CONFIG_MTD_PARTITIONS=y
2757 +# CONFIG_MTD_REDBOOT_PARTS is not set
2758 +CONFIG_MTD_CMDLINE_PARTS=y
2759 +
2760 +#
2761 +# User Modules And Translation Layers
2762 +#
2763 +CONFIG_MTD_CHAR=y
2764 +CONFIG_MTD_BLKDEVS=y
2765 +CONFIG_MTD_BLOCK=y
2766 +# CONFIG_FTL is not set
2767 +# CONFIG_NFTL is not set
2768 +# CONFIG_INFTL is not set
2769 +# CONFIG_RFD_FTL is not set
2770 +# CONFIG_SSFDC is not set
2771 +# CONFIG_MTD_OOPS is not set
2772 +
2773 +#
2774 +# RAM/ROM/Flash chip drivers
2775 +#
2776 +CONFIG_MTD_CFI=y
2777 +# CONFIG_MTD_JEDECPROBE is not set
2778 +CONFIG_MTD_GEN_PROBE=y
2779 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
2780 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
2781 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
2782 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
2783 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
2784 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
2785 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
2786 +CONFIG_MTD_CFI_I1=y
2787 +CONFIG_MTD_CFI_I2=y
2788 +# CONFIG_MTD_CFI_I4 is not set
2789 +# CONFIG_MTD_CFI_I8 is not set
2790 +# CONFIG_MTD_CFI_INTELEXT is not set
2791 +CONFIG_MTD_CFI_AMDSTD=y
2792 +# CONFIG_MTD_CFI_STAA is not set
2793 +CONFIG_MTD_CFI_UTIL=y
2794 +# CONFIG_MTD_RAM is not set
2795 +# CONFIG_MTD_ROM is not set
2796 +# CONFIG_MTD_ABSENT is not set
2797 +
2798 +#
2799 +# Mapping drivers for chip access
2800 +#
2801 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
2802 +CONFIG_MTD_PHYSMAP=y
2803 +CONFIG_MTD_PHYSMAP_START=0x8000000
2804 +CONFIG_MTD_PHYSMAP_LEN=0x0
2805 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2
2806 +# CONFIG_MTD_PLATRAM is not set
2807 +
2808 +#
2809 +# Self-contained MTD device drivers
2810 +#
2811 +CONFIG_MTD_DATAFLASH=m
2812 +CONFIG_MTD_M25P80=m
2813 +# CONFIG_MTD_SLRAM is not set
2814 +# CONFIG_MTD_PHRAM is not set
2815 +# CONFIG_MTD_MTDRAM is not set
2816 +# CONFIG_MTD_BLOCK2MTD is not set
2817 +
2818 +#
2819 +# Disk-On-Chip Device Drivers
2820 +#
2821 +# CONFIG_MTD_DOC2000 is not set
2822 +# CONFIG_MTD_DOC2001 is not set
2823 +# CONFIG_MTD_DOC2001PLUS is not set
2824 +CONFIG_MTD_NAND=y
2825 +# CONFIG_MTD_NAND_VERIFY_WRITE is not set
2826 +# CONFIG_MTD_NAND_ECC_SMC is not set
2827 +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
2828 +CONFIG_MTD_NAND_IDS=y
2829 +# CONFIG_MTD_NAND_DISKONCHIP is not set
2830 +CONFIG_MTD_NAND_ATMEL=y
2831 +CONFIG_MTD_NAND_ATMEL_ECC_HW=y
2832 +# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
2833 +# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
2834 +# CONFIG_MTD_NAND_NANDSIM is not set
2835 +# CONFIG_MTD_NAND_PLATFORM is not set
2836 +# CONFIG_MTD_ONENAND is not set
2837 +
2838 +#
2839 +# UBI - Unsorted block images
2840 +#
2841 +CONFIG_MTD_UBI=m
2842 +CONFIG_MTD_UBI_WL_THRESHOLD=4096
2843 +CONFIG_MTD_UBI_BEB_RESERVE=1
2844 +CONFIG_MTD_UBI_GLUEBI=y
2845 +
2846 +#
2847 +# UBI debugging options
2848 +#
2849 +# CONFIG_MTD_UBI_DEBUG is not set
2850 +# CONFIG_PARPORT is not set
2851 +CONFIG_BLK_DEV=y
2852 +# CONFIG_BLK_DEV_COW_COMMON is not set
2853 +CONFIG_BLK_DEV_LOOP=m
2854 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
2855 +CONFIG_BLK_DEV_NBD=m
2856 +CONFIG_BLK_DEV_RAM=m
2857 +CONFIG_BLK_DEV_RAM_COUNT=16
2858 +CONFIG_BLK_DEV_RAM_SIZE=4096
2859 +# CONFIG_BLK_DEV_XIP is not set
2860 +# CONFIG_CDROM_PKTCDVD is not set
2861 +# CONFIG_ATA_OVER_ETH is not set
2862 +CONFIG_MISC_DEVICES=y
2863 +CONFIG_ATMEL_PWM=m
2864 +CONFIG_ATMEL_TCLIB=y
2865 +CONFIG_ATMEL_TCB_CLKSRC=y
2866 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
2867 +# CONFIG_EEPROM_93CX6 is not set
2868 +CONFIG_ATMEL_SSC=m
2869 +# CONFIG_ENCLOSURE_SERVICES is not set
2870 +# CONFIG_HAVE_IDE is not set
2871 +
2872 +#
2873 +# SCSI device support
2874 +#
2875 +# CONFIG_RAID_ATTRS is not set
2876 +CONFIG_SCSI=m
2877 +CONFIG_SCSI_DMA=y
2878 +# CONFIG_SCSI_TGT is not set
2879 +# CONFIG_SCSI_NETLINK is not set
2880 +# CONFIG_SCSI_PROC_FS is not set
2881 +
2882 +#
2883 +# SCSI support type (disk, tape, CD-ROM)
2884 +#
2885 +CONFIG_BLK_DEV_SD=m
2886 +# CONFIG_CHR_DEV_ST is not set
2887 +# CONFIG_CHR_DEV_OSST is not set
2888 +CONFIG_BLK_DEV_SR=m
2889 +# CONFIG_BLK_DEV_SR_VENDOR is not set
2890 +# CONFIG_CHR_DEV_SG is not set
2891 +# CONFIG_CHR_DEV_SCH is not set
2892 +
2893 +#
2894 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
2895 +#
2896 +# CONFIG_SCSI_MULTI_LUN is not set
2897 +# CONFIG_SCSI_CONSTANTS is not set
2898 +# CONFIG_SCSI_LOGGING is not set
2899 +# CONFIG_SCSI_SCAN_ASYNC is not set
2900 +CONFIG_SCSI_WAIT_SCAN=m
2901 +
2902 +#
2903 +# SCSI Transports
2904 +#
2905 +# CONFIG_SCSI_SPI_ATTRS is not set
2906 +# CONFIG_SCSI_FC_ATTRS is not set
2907 +# CONFIG_SCSI_ISCSI_ATTRS is not set
2908 +# CONFIG_SCSI_SAS_LIBSAS is not set
2909 +# CONFIG_SCSI_SRP_ATTRS is not set
2910 +# CONFIG_SCSI_LOWLEVEL is not set
2911 +CONFIG_ATA=m
2912 +# CONFIG_ATA_NONSTANDARD is not set
2913 +# CONFIG_SATA_MV is not set
2914 +CONFIG_PATA_AT32=m
2915 +# CONFIG_PATA_PLATFORM is not set
2916 +# CONFIG_MD is not set
2917 +CONFIG_NETDEVICES=y
2918 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
2919 +# CONFIG_DUMMY is not set
2920 +# CONFIG_BONDING is not set
2921 +# CONFIG_MACVLAN is not set
2922 +# CONFIG_EQUALIZER is not set
2923 +CONFIG_TUN=m
2924 +# CONFIG_VETH is not set
2925 +CONFIG_PHYLIB=y
2926 +
2927 +#
2928 +# MII PHY device drivers
2929 +#
2930 +# CONFIG_MARVELL_PHY is not set
2931 +# CONFIG_DAVICOM_PHY is not set
2932 +# CONFIG_QSEMI_PHY is not set
2933 +# CONFIG_LXT_PHY is not set
2934 +# CONFIG_CICADA_PHY is not set
2935 +# CONFIG_VITESSE_PHY is not set
2936 +# CONFIG_SMSC_PHY is not set
2937 +# CONFIG_BROADCOM_PHY is not set
2938 +# CONFIG_ICPLUS_PHY is not set
2939 +# CONFIG_REALTEK_PHY is not set
2940 +# CONFIG_FIXED_PHY is not set
2941 +# CONFIG_MDIO_BITBANG is not set
2942 +CONFIG_NET_ETHERNET=y
2943 +# CONFIG_MII is not set
2944 +CONFIG_MACB=y
2945 +# CONFIG_ENC28J60 is not set
2946 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
2947 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
2948 +# CONFIG_IBM_NEW_EMAC_TAH is not set
2949 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
2950 +# CONFIG_B44 is not set
2951 +# CONFIG_NETDEV_1000 is not set
2952 +# CONFIG_NETDEV_10000 is not set
2953 +
2954 +#
2955 +# Wireless LAN
2956 +#
2957 +# CONFIG_WLAN_PRE80211 is not set
2958 +# CONFIG_WLAN_80211 is not set
2959 +# CONFIG_WAN is not set
2960 +CONFIG_PPP=m
2961 +# CONFIG_PPP_MULTILINK is not set
2962 +# CONFIG_PPP_FILTER is not set
2963 +CONFIG_PPP_ASYNC=m
2964 +# CONFIG_PPP_SYNC_TTY is not set
2965 +CONFIG_PPP_DEFLATE=m
2966 +CONFIG_PPP_BSDCOMP=m
2967 +# CONFIG_PPP_MPPE is not set
2968 +# CONFIG_PPPOE is not set
2969 +# CONFIG_PPPOL2TP is not set
2970 +# CONFIG_SLIP is not set
2971 +CONFIG_SLHC=m
2972 +# CONFIG_NETCONSOLE is not set
2973 +# CONFIG_NETPOLL is not set
2974 +# CONFIG_NET_POLL_CONTROLLER is not set
2975 +# CONFIG_ISDN is not set
2976 +# CONFIG_PHONE is not set
2977 +
2978 +#
2979 +# Input device support
2980 +#
2981 +CONFIG_INPUT=m
2982 +# CONFIG_INPUT_FF_MEMLESS is not set
2983 +CONFIG_INPUT_POLLDEV=m
2984 +
2985 +#
2986 +# Userland interfaces
2987 +#
2988 +CONFIG_INPUT_MOUSEDEV=m
2989 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
2990 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
2991 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
2992 +# CONFIG_INPUT_JOYDEV is not set
2993 +CONFIG_INPUT_EVDEV=m
2994 +# CONFIG_INPUT_EVBUG is not set
2995 +
2996 +#
2997 +# Input Device Drivers
2998 +#
2999 +CONFIG_INPUT_KEYBOARD=y
3000 +# CONFIG_KEYBOARD_ATKBD is not set
3001 +# CONFIG_KEYBOARD_SUNKBD is not set
3002 +# CONFIG_KEYBOARD_LKKBD is not set
3003 +# CONFIG_KEYBOARD_XTKBD is not set
3004 +# CONFIG_KEYBOARD_NEWTON is not set
3005 +# CONFIG_KEYBOARD_STOWAWAY is not set
3006 +CONFIG_KEYBOARD_GPIO=m
3007 +CONFIG_INPUT_MOUSE=y
3008 +# CONFIG_MOUSE_PS2 is not set
3009 +# CONFIG_MOUSE_SERIAL is not set
3010 +# CONFIG_MOUSE_VSXXXAA is not set
3011 +CONFIG_MOUSE_GPIO=m
3012 +# CONFIG_INPUT_JOYSTICK is not set
3013 +# CONFIG_INPUT_TABLET is not set
3014 +# CONFIG_INPUT_TOUCHSCREEN is not set
3015 +# CONFIG_INPUT_MISC is not set
3016 +
3017 +#
3018 +# Hardware I/O ports
3019 +#
3020 +# CONFIG_SERIO is not set
3021 +# CONFIG_GAMEPORT is not set
3022 +
3023 +#
3024 +# Character devices
3025 +#
3026 +# CONFIG_VT is not set
3027 +# CONFIG_SERIAL_NONSTANDARD is not set
3028 +
3029 +#
3030 +# Serial drivers
3031 +#
3032 +# CONFIG_SERIAL_8250 is not set
3033 +
3034 +#
3035 +# Non-8250 serial port support
3036 +#
3037 +CONFIG_SERIAL_ATMEL=y
3038 +CONFIG_SERIAL_ATMEL_CONSOLE=y
3039 +CONFIG_SERIAL_ATMEL_PDC=y
3040 +# CONFIG_SERIAL_ATMEL_TTYAT is not set
3041 +CONFIG_SERIAL_CORE=y
3042 +CONFIG_SERIAL_CORE_CONSOLE=y
3043 +CONFIG_UNIX98_PTYS=y
3044 +# CONFIG_LEGACY_PTYS is not set
3045 +# CONFIG_IPMI_HANDLER is not set
3046 +# CONFIG_HW_RANDOM is not set
3047 +# CONFIG_R3964 is not set
3048 +# CONFIG_RAW_DRIVER is not set
3049 +# CONFIG_TCG_TPM is not set
3050 +CONFIG_I2C=m
3051 +CONFIG_I2C_BOARDINFO=y
3052 +CONFIG_I2C_CHARDEV=m
3053 +
3054 +#
3055 +# I2C Algorithms
3056 +#
3057 +CONFIG_I2C_ALGOBIT=m
3058 +# CONFIG_I2C_ALGOPCF is not set
3059 +# CONFIG_I2C_ALGOPCA is not set
3060 +
3061 +#
3062 +# I2C Hardware Bus support
3063 +#
3064 +CONFIG_I2C_ATMELTWI=m
3065 +CONFIG_I2C_GPIO=m
3066 +# CONFIG_I2C_OCORES is not set
3067 +# CONFIG_I2C_PARPORT_LIGHT is not set
3068 +# CONFIG_I2C_SIMTEC is not set
3069 +# CONFIG_I2C_TAOS_EVM is not set
3070 +# CONFIG_I2C_STUB is not set
3071 +
3072 +#
3073 +# Miscellaneous I2C Chip support
3074 +#
3075 +# CONFIG_DS1682 is not set
3076 +# CONFIG_SENSORS_EEPROM is not set
3077 +# CONFIG_SENSORS_PCF8574 is not set
3078 +# CONFIG_PCF8575 is not set
3079 +# CONFIG_SENSORS_PCF8591 is not set
3080 +# CONFIG_TPS65010 is not set
3081 +# CONFIG_SENSORS_MAX6875 is not set
3082 +# CONFIG_SENSORS_TSL2550 is not set
3083 +# CONFIG_I2C_DEBUG_CORE is not set
3084 +# CONFIG_I2C_DEBUG_ALGO is not set
3085 +# CONFIG_I2C_DEBUG_BUS is not set
3086 +# CONFIG_I2C_DEBUG_CHIP is not set
3087 +
3088 +#
3089 +# SPI support
3090 +#
3091 +CONFIG_SPI=y
3092 +# CONFIG_SPI_DEBUG is not set
3093 +CONFIG_SPI_MASTER=y
3094 +
3095 +#
3096 +# SPI Master Controller Drivers
3097 +#
3098 +CONFIG_SPI_ATMEL=y
3099 +# CONFIG_SPI_BITBANG is not set
3100 +
3101 +#
3102 +# SPI Protocol Masters
3103 +#
3104 +# CONFIG_SPI_AT25 is not set
3105 +CONFIG_SPI_SPIDEV=m
3106 +# CONFIG_SPI_TLE62X0 is not set
3107 +CONFIG_HAVE_GPIO_LIB=y
3108 +
3109 +#
3110 +# GPIO Support
3111 +#
3112 +# CONFIG_DEBUG_GPIO is not set
3113 +
3114 +#
3115 +# I2C GPIO expanders:
3116 +#
3117 +# CONFIG_GPIO_PCA953X is not set
3118 +# CONFIG_GPIO_PCF857X is not set
3119 +
3120 +#
3121 +# SPI GPIO expanders:
3122 +#
3123 +# CONFIG_GPIO_MCP23S08 is not set
3124 +# CONFIG_W1 is not set
3125 +# CONFIG_POWER_SUPPLY is not set
3126 +# CONFIG_HWMON is not set
3127 +# CONFIG_THERMAL is not set
3128 +CONFIG_WATCHDOG=y
3129 +# CONFIG_WATCHDOG_NOWAYOUT is not set
3130 +
3131 +#
3132 +# Watchdog Device Drivers
3133 +#
3134 +# CONFIG_SOFT_WATCHDOG is not set
3135 +CONFIG_AT32AP700X_WDT=y
3136 +
3137 +#
3138 +# Sonics Silicon Backplane
3139 +#
3140 +CONFIG_SSB_POSSIBLE=y
3141 +# CONFIG_SSB is not set
3142 +
3143 +#
3144 +# Multifunction device drivers
3145 +#
3146 +# CONFIG_MFD_SM501 is not set
3147 +
3148 +#
3149 +# Multimedia devices
3150 +#
3151 +# CONFIG_VIDEO_DEV is not set
3152 +# CONFIG_DVB_CORE is not set
3153 +# CONFIG_DAB is not set
3154 +
3155 +#
3156 +# Graphics support
3157 +#
3158 +# CONFIG_VGASTATE is not set
3159 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
3160 +CONFIG_FB=y
3161 +# CONFIG_FIRMWARE_EDID is not set
3162 +# CONFIG_FB_DDC is not set
3163 +CONFIG_FB_CFB_FILLRECT=y
3164 +CONFIG_FB_CFB_COPYAREA=y
3165 +CONFIG_FB_CFB_IMAGEBLIT=y
3166 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
3167 +# CONFIG_FB_SYS_FILLRECT is not set
3168 +# CONFIG_FB_SYS_COPYAREA is not set
3169 +# CONFIG_FB_SYS_IMAGEBLIT is not set
3170 +# CONFIG_FB_SYS_FOPS is not set
3171 +CONFIG_FB_DEFERRED_IO=y
3172 +# CONFIG_FB_SVGALIB is not set
3173 +# CONFIG_FB_MACMODES is not set
3174 +# CONFIG_FB_BACKLIGHT is not set
3175 +# CONFIG_FB_MODE_HELPERS is not set
3176 +# CONFIG_FB_TILEBLITTING is not set
3177 +
3178 +#
3179 +# Frame buffer hardware drivers
3180 +#
3181 +# CONFIG_FB_S1D13XXX is not set
3182 +CONFIG_FB_ATMEL=y
3183 +# CONFIG_FB_VIRTUAL is not set
3184 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
3185 +CONFIG_LCD_CLASS_DEVICE=y
3186 +CONFIG_LCD_LTV350QV=y
3187 +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
3188 +
3189 +#
3190 +# Display device support
3191 +#
3192 +# CONFIG_DISPLAY_SUPPORT is not set
3193 +# CONFIG_LOGO is not set
3194 +
3195 +#
3196 +# Sound
3197 +#
3198 +CONFIG_SOUND=m
3199 +
3200 +#
3201 +# Advanced Linux Sound Architecture
3202 +#
3203 +CONFIG_SND=m
3204 +CONFIG_SND_TIMER=m
3205 +CONFIG_SND_PCM=m
3206 +# CONFIG_SND_SEQUENCER is not set
3207 +CONFIG_SND_OSSEMUL=y
3208 +CONFIG_SND_MIXER_OSS=m
3209 +CONFIG_SND_PCM_OSS=m
3210 +CONFIG_SND_PCM_OSS_PLUGINS=y
3211 +# CONFIG_SND_DYNAMIC_MINORS is not set
3212 +# CONFIG_SND_SUPPORT_OLD_API is not set
3213 +# CONFIG_SND_VERBOSE_PROCFS is not set
3214 +# CONFIG_SND_VERBOSE_PRINTK is not set
3215 +# CONFIG_SND_DEBUG is not set
3216 +
3217 +#
3218 +# Generic devices
3219 +#
3220 +CONFIG_SND_AC97_CODEC=m
3221 +# CONFIG_SND_DUMMY is not set
3222 +# CONFIG_SND_MTPAV is not set
3223 +# CONFIG_SND_SERIAL_U16550 is not set
3224 +# CONFIG_SND_MPU401 is not set
3225 +
3226 +#
3227 +# AVR32 devices
3228 +#
3229 +CONFIG_SND_ATMEL_AC97=m
3230 +
3231 +#
3232 +# SPI devices
3233 +#
3234 +CONFIG_SND_AT73C213=m
3235 +CONFIG_SND_AT73C213_TARGET_BITRATE=48000
3236 +
3237 +#
3238 +# System on Chip audio support
3239 +#
3240 +# CONFIG_SND_SOC is not set
3241 +
3242 +#
3243 +# SoC Audio support for SuperH
3244 +#
3245 +
3246 +#
3247 +# ALSA SoC audio for Freescale SOCs
3248 +#
3249 +
3250 +#
3251 +# Open Sound System
3252 +#
3253 +# CONFIG_SOUND_PRIME is not set
3254 +CONFIG_AC97_BUS=m
3255 +# CONFIG_HID_SUPPORT is not set
3256 +CONFIG_USB_SUPPORT=y
3257 +# CONFIG_USB_ARCH_HAS_HCD is not set
3258 +# CONFIG_USB_ARCH_HAS_OHCI is not set
3259 +# CONFIG_USB_ARCH_HAS_EHCI is not set
3260 +
3261 +#
3262 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
3263 +#
3264 +CONFIG_USB_GADGET=y
3265 +# CONFIG_USB_GADGET_DEBUG is not set
3266 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
3267 +# CONFIG_USB_GADGET_DEBUG_FS is not set
3268 +CONFIG_USB_GADGET_SELECTED=y
3269 +# CONFIG_USB_GADGET_AMD5536UDC is not set
3270 +CONFIG_USB_GADGET_ATMEL_USBA=y
3271 +CONFIG_USB_ATMEL_USBA=y
3272 +# CONFIG_USB_GADGET_FSL_USB2 is not set
3273 +# CONFIG_USB_GADGET_NET2280 is not set
3274 +# CONFIG_USB_GADGET_PXA2XX is not set
3275 +# CONFIG_USB_GADGET_M66592 is not set
3276 +# CONFIG_USB_GADGET_GOKU is not set
3277 +# CONFIG_USB_GADGET_LH7A40X is not set
3278 +# CONFIG_USB_GADGET_OMAP is not set
3279 +# CONFIG_USB_GADGET_S3C2410 is not set
3280 +# CONFIG_USB_GADGET_AT91 is not set
3281 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
3282 +CONFIG_USB_GADGET_DUALSPEED=y
3283 +CONFIG_USB_ZERO=m
3284 +CONFIG_USB_ETH=m
3285 +CONFIG_USB_ETH_RNDIS=y
3286 +CONFIG_USB_GADGETFS=m
3287 +CONFIG_USB_FILE_STORAGE=m
3288 +# CONFIG_USB_FILE_STORAGE_TEST is not set
3289 +CONFIG_USB_G_SERIAL=m
3290 +# CONFIG_USB_MIDI_GADGET is not set
3291 +# CONFIG_USB_G_PRINTER is not set
3292 +CONFIG_MMC=y
3293 +# CONFIG_MMC_DEBUG is not set
3294 +# CONFIG_MMC_UNSAFE_RESUME is not set
3295 +
3296 +#
3297 +# MMC/SD Card Drivers
3298 +#
3299 +CONFIG_MMC_BLOCK=y
3300 +CONFIG_MMC_BLOCK_BOUNCE=y
3301 +# CONFIG_SDIO_UART is not set
3302 +
3303 +#
3304 +# MMC/SD Host Controller Drivers
3305 +#
3306 +CONFIG_MMC_ATMELMCI=y
3307 +CONFIG_MMC_SPI=m
3308 +# CONFIG_MEMSTICK is not set
3309 +CONFIG_NEW_LEDS=y
3310 +CONFIG_LEDS_CLASS=m
3311 +
3312 +#
3313 +# LED drivers
3314 +#
3315 +CONFIG_LEDS_ATMEL_PWM=m
3316 +CONFIG_LEDS_GPIO=m
3317 +
3318 +#
3319 +# LED Triggers
3320 +#
3321 +CONFIG_LEDS_TRIGGERS=y
3322 +CONFIG_LEDS_TRIGGER_TIMER=m
3323 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
3324 +CONFIG_RTC_LIB=y
3325 +CONFIG_RTC_CLASS=y
3326 +CONFIG_RTC_HCTOSYS=y
3327 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
3328 +# CONFIG_RTC_DEBUG is not set
3329 +
3330 +#
3331 +# RTC interfaces
3332 +#
3333 +CONFIG_RTC_INTF_SYSFS=y
3334 +CONFIG_RTC_INTF_PROC=y
3335 +CONFIG_RTC_INTF_DEV=y
3336 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
3337 +# CONFIG_RTC_DRV_TEST is not set
3338 +
3339 +#
3340 +# I2C RTC drivers
3341 +#
3342 +# CONFIG_RTC_DRV_DS1307 is not set
3343 +# CONFIG_RTC_DRV_DS1374 is not set
3344 +# CONFIG_RTC_DRV_DS1672 is not set
3345 +# CONFIG_RTC_DRV_MAX6900 is not set
3346 +# CONFIG_RTC_DRV_RS5C372 is not set
3347 +# CONFIG_RTC_DRV_ISL1208 is not set
3348 +# CONFIG_RTC_DRV_X1205 is not set
3349 +# CONFIG_RTC_DRV_PCF8563 is not set
3350 +# CONFIG_RTC_DRV_PCF8583 is not set
3351 +# CONFIG_RTC_DRV_M41T80 is not set
3352 +# CONFIG_RTC_DRV_S35390A is not set
3353 +
3354 +#
3355 +# SPI RTC drivers
3356 +#
3357 +# CONFIG_RTC_DRV_MAX6902 is not set
3358 +# CONFIG_RTC_DRV_R9701 is not set
3359 +# CONFIG_RTC_DRV_RS5C348 is not set
3360 +
3361 +#
3362 +# Platform RTC drivers
3363 +#
3364 +# CONFIG_RTC_DRV_DS1511 is not set
3365 +# CONFIG_RTC_DRV_DS1553 is not set
3366 +# CONFIG_RTC_DRV_DS1742 is not set
3367 +# CONFIG_RTC_DRV_STK17TA8 is not set
3368 +# CONFIG_RTC_DRV_M48T86 is not set
3369 +# CONFIG_RTC_DRV_M48T59 is not set
3370 +# CONFIG_RTC_DRV_V3020 is not set
3371 +
3372 +#
3373 +# on-CPU RTC drivers
3374 +#
3375 +CONFIG_RTC_DRV_AT32AP700X=y
3376 +
3377 +#
3378 +# Userspace I/O
3379 +#
3380 +# CONFIG_UIO is not set
3381 +
3382 +#
3383 +# File systems
3384 +#
3385 +CONFIG_EXT2_FS=y
3386 +# CONFIG_EXT2_FS_XATTR is not set
3387 +# CONFIG_EXT2_FS_XIP is not set
3388 +CONFIG_EXT3_FS=y
3389 +# CONFIG_EXT3_FS_XATTR is not set
3390 +# CONFIG_EXT4DEV_FS is not set
3391 +CONFIG_JBD=y
3392 +# CONFIG_JBD_DEBUG is not set
3393 +# CONFIG_REISERFS_FS is not set
3394 +# CONFIG_JFS_FS is not set
3395 +# CONFIG_FS_POSIX_ACL is not set
3396 +# CONFIG_XFS_FS is not set
3397 +# CONFIG_GFS2_FS is not set
3398 +# CONFIG_OCFS2_FS is not set
3399 +# CONFIG_DNOTIFY is not set
3400 +CONFIG_INOTIFY=y
3401 +CONFIG_INOTIFY_USER=y
3402 +# CONFIG_QUOTA is not set
3403 +# CONFIG_AUTOFS_FS is not set
3404 +# CONFIG_AUTOFS4_FS is not set
3405 +CONFIG_FUSE_FS=m
3406 +
3407 +#
3408 +# CD-ROM/DVD Filesystems
3409 +#
3410 +# CONFIG_ISO9660_FS is not set
3411 +# CONFIG_UDF_FS is not set
3412 +
3413 +#
3414 +# DOS/FAT/NT Filesystems
3415 +#
3416 +CONFIG_FAT_FS=m
3417 +CONFIG_MSDOS_FS=m
3418 +CONFIG_VFAT_FS=m
3419 +CONFIG_FAT_DEFAULT_CODEPAGE=437
3420 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
3421 +# CONFIG_NTFS_FS is not set
3422 +
3423 +#
3424 +# Pseudo filesystems
3425 +#
3426 +CONFIG_PROC_FS=y
3427 +CONFIG_PROC_KCORE=y
3428 +CONFIG_PROC_SYSCTL=y
3429 +CONFIG_SYSFS=y
3430 +CONFIG_TMPFS=y
3431 +# CONFIG_TMPFS_POSIX_ACL is not set
3432 +# CONFIG_HUGETLB_PAGE is not set
3433 +CONFIG_CONFIGFS_FS=y
3434 +
3435 +#
3436 +# Miscellaneous filesystems
3437 +#
3438 +# CONFIG_ADFS_FS is not set
3439 +# CONFIG_AFFS_FS is not set
3440 +# CONFIG_HFS_FS is not set
3441 +# CONFIG_HFSPLUS_FS is not set
3442 +# CONFIG_BEFS_FS is not set
3443 +# CONFIG_BFS_FS is not set
3444 +# CONFIG_EFS_FS is not set
3445 +CONFIG_JFFS2_FS=y
3446 +CONFIG_JFFS2_FS_DEBUG=0
3447 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set
3448 +# CONFIG_JFFS2_SUMMARY is not set
3449 +# CONFIG_JFFS2_FS_XATTR is not set
3450 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
3451 +CONFIG_JFFS2_ZLIB=y
3452 +# CONFIG_JFFS2_LZO is not set
3453 +CONFIG_JFFS2_RTIME=y
3454 +# CONFIG_JFFS2_RUBIN is not set
3455 +# CONFIG_CRAMFS is not set
3456 +# CONFIG_VXFS_FS is not set
3457 +CONFIG_MINIX_FS=m
3458 +# CONFIG_HPFS_FS is not set
3459 +# CONFIG_QNX4FS_FS is not set
3460 +# CONFIG_ROMFS_FS is not set
3461 +# CONFIG_SYSV_FS is not set
3462 +# CONFIG_UFS_FS is not set
3463 +CONFIG_NETWORK_FILESYSTEMS=y
3464 +CONFIG_NFS_FS=y
3465 +CONFIG_NFS_V3=y
3466 +# CONFIG_NFS_V3_ACL is not set
3467 +# CONFIG_NFS_V4 is not set
3468 +# CONFIG_NFS_DIRECTIO is not set
3469 +# CONFIG_NFSD is not set
3470 +CONFIG_ROOT_NFS=y
3471 +CONFIG_LOCKD=y
3472 +CONFIG_LOCKD_V4=y
3473 +CONFIG_NFS_COMMON=y
3474 +CONFIG_SUNRPC=y
3475 +# CONFIG_SUNRPC_BIND34 is not set
3476 +# CONFIG_RPCSEC_GSS_KRB5 is not set
3477 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
3478 +# CONFIG_SMB_FS is not set
3479 +# CONFIG_CIFS is not set
3480 +# CONFIG_NCP_FS is not set
3481 +# CONFIG_CODA_FS is not set
3482 +# CONFIG_AFS_FS is not set
3483 +
3484 +#
3485 +# Partition Types
3486 +#
3487 +# CONFIG_PARTITION_ADVANCED is not set
3488 +CONFIG_MSDOS_PARTITION=y
3489 +CONFIG_NLS=m
3490 +CONFIG_NLS_DEFAULT="iso8859-1"
3491 +CONFIG_NLS_CODEPAGE_437=m
3492 +# CONFIG_NLS_CODEPAGE_737 is not set
3493 +# CONFIG_NLS_CODEPAGE_775 is not set
3494 +# CONFIG_NLS_CODEPAGE_850 is not set
3495 +# CONFIG_NLS_CODEPAGE_852 is not set
3496 +# CONFIG_NLS_CODEPAGE_855 is not set
3497 +# CONFIG_NLS_CODEPAGE_857 is not set
3498 +# CONFIG_NLS_CODEPAGE_860 is not set
3499 +# CONFIG_NLS_CODEPAGE_861 is not set
3500 +# CONFIG_NLS_CODEPAGE_862 is not set
3501 +# CONFIG_NLS_CODEPAGE_863 is not set
3502 +# CONFIG_NLS_CODEPAGE_864 is not set
3503 +# CONFIG_NLS_CODEPAGE_865 is not set
3504 +# CONFIG_NLS_CODEPAGE_866 is not set
3505 +# CONFIG_NLS_CODEPAGE_869 is not set
3506 +# CONFIG_NLS_CODEPAGE_936 is not set
3507 +# CONFIG_NLS_CODEPAGE_950 is not set
3508 +# CONFIG_NLS_CODEPAGE_932 is not set
3509 +# CONFIG_NLS_CODEPAGE_949 is not set
3510 +# CONFIG_NLS_CODEPAGE_874 is not set
3511 +# CONFIG_NLS_ISO8859_8 is not set
3512 +# CONFIG_NLS_CODEPAGE_1250 is not set
3513 +# CONFIG_NLS_CODEPAGE_1251 is not set
3514 +# CONFIG_NLS_ASCII is not set
3515 +CONFIG_NLS_ISO8859_1=m
3516 +# CONFIG_NLS_ISO8859_2 is not set
3517 +# CONFIG_NLS_ISO8859_3 is not set
3518 +# CONFIG_NLS_ISO8859_4 is not set
3519 +# CONFIG_NLS_ISO8859_5 is not set
3520 +# CONFIG_NLS_ISO8859_6 is not set
3521 +# CONFIG_NLS_ISO8859_7 is not set
3522 +# CONFIG_NLS_ISO8859_9 is not set
3523 +# CONFIG_NLS_ISO8859_13 is not set
3524 +# CONFIG_NLS_ISO8859_14 is not set
3525 +# CONFIG_NLS_ISO8859_15 is not set
3526 +# CONFIG_NLS_KOI8_R is not set
3527 +# CONFIG_NLS_KOI8_U is not set
3528 +CONFIG_NLS_UTF8=m
3529 +# CONFIG_DLM is not set
3530 +
3531 +#
3532 +# Kernel hacking
3533 +#
3534 +# CONFIG_PRINTK_TIME is not set
3535 +CONFIG_ENABLE_WARN_DEPRECATED=y
3536 +CONFIG_ENABLE_MUST_CHECK=y
3537 +CONFIG_MAGIC_SYSRQ=y
3538 +# CONFIG_UNUSED_SYMBOLS is not set
3539 +CONFIG_DEBUG_FS=y
3540 +# CONFIG_HEADERS_CHECK is not set
3541 +CONFIG_DEBUG_KERNEL=y
3542 +# CONFIG_DEBUG_SHIRQ is not set
3543 +CONFIG_DETECT_SOFTLOCKUP=y
3544 +CONFIG_SCHED_DEBUG=y
3545 +# CONFIG_SCHEDSTATS is not set
3546 +# CONFIG_TIMER_STATS is not set
3547 +# CONFIG_SLUB_DEBUG_ON is not set
3548 +# CONFIG_SLUB_STATS is not set
3549 +# CONFIG_DEBUG_RT_MUTEXES is not set
3550 +# CONFIG_RT_MUTEX_TESTER is not set
3551 +# CONFIG_DEBUG_SPINLOCK is not set
3552 +# CONFIG_DEBUG_MUTEXES is not set
3553 +# CONFIG_DEBUG_LOCK_ALLOC is not set
3554 +# CONFIG_PROVE_LOCKING is not set
3555 +# CONFIG_LOCK_STAT is not set
3556 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
3557 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
3558 +# CONFIG_DEBUG_KOBJECT is not set
3559 +CONFIG_DEBUG_BUGVERBOSE=y
3560 +# CONFIG_DEBUG_INFO is not set
3561 +# CONFIG_DEBUG_VM is not set
3562 +# CONFIG_DEBUG_LIST is not set
3563 +# CONFIG_DEBUG_SG is not set
3564 +CONFIG_FRAME_POINTER=y
3565 +# CONFIG_BOOT_PRINTK_DELAY is not set
3566 +# CONFIG_RCU_TORTURE_TEST is not set
3567 +# CONFIG_KPROBES_SANITY_TEST is not set
3568 +# CONFIG_BACKTRACE_SELF_TEST is not set
3569 +# CONFIG_LKDTM is not set
3570 +# CONFIG_FAULT_INJECTION is not set
3571 +# CONFIG_SAMPLES is not set
3572 +
3573 +#
3574 +# Security options
3575 +#
3576 +# CONFIG_KEYS is not set
3577 +# CONFIG_SECURITY is not set
3578 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
3579 +CONFIG_CRYPTO=y
3580 +CONFIG_CRYPTO_ALGAPI=m
3581 +CONFIG_CRYPTO_AEAD=m
3582 +CONFIG_CRYPTO_BLKCIPHER=m
3583 +# CONFIG_CRYPTO_SEQIV is not set
3584 +CONFIG_CRYPTO_HASH=m
3585 +CONFIG_CRYPTO_MANAGER=m
3586 +CONFIG_CRYPTO_HMAC=m
3587 +# CONFIG_CRYPTO_XCBC is not set
3588 +# CONFIG_CRYPTO_NULL is not set
3589 +# CONFIG_CRYPTO_MD4 is not set
3590 +CONFIG_CRYPTO_MD5=m
3591 +CONFIG_CRYPTO_SHA1=m
3592 +# CONFIG_CRYPTO_SHA256 is not set
3593 +# CONFIG_CRYPTO_SHA512 is not set
3594 +# CONFIG_CRYPTO_WP512 is not set
3595 +# CONFIG_CRYPTO_TGR192 is not set
3596 +# CONFIG_CRYPTO_GF128MUL is not set
3597 +# CONFIG_CRYPTO_ECB is not set
3598 +CONFIG_CRYPTO_CBC=m
3599 +# CONFIG_CRYPTO_PCBC is not set
3600 +# CONFIG_CRYPTO_LRW is not set
3601 +# CONFIG_CRYPTO_XTS is not set
3602 +# CONFIG_CRYPTO_CTR is not set
3603 +# CONFIG_CRYPTO_GCM is not set
3604 +# CONFIG_CRYPTO_CCM is not set
3605 +# CONFIG_CRYPTO_CRYPTD is not set
3606 +CONFIG_CRYPTO_DES=m
3607 +# CONFIG_CRYPTO_FCRYPT is not set
3608 +# CONFIG_CRYPTO_BLOWFISH is not set
3609 +# CONFIG_CRYPTO_TWOFISH is not set
3610 +# CONFIG_CRYPTO_SERPENT is not set
3611 +# CONFIG_CRYPTO_AES is not set
3612 +# CONFIG_CRYPTO_CAST5 is not set
3613 +# CONFIG_CRYPTO_CAST6 is not set
3614 +# CONFIG_CRYPTO_TEA is not set
3615 +# CONFIG_CRYPTO_ARC4 is not set
3616 +# CONFIG_CRYPTO_KHAZAD is not set
3617 +# CONFIG_CRYPTO_ANUBIS is not set
3618 +# CONFIG_CRYPTO_SEED is not set
3619 +# CONFIG_CRYPTO_SALSA20 is not set
3620 +CONFIG_CRYPTO_DEFLATE=m
3621 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
3622 +# CONFIG_CRYPTO_CRC32C is not set
3623 +# CONFIG_CRYPTO_CAMELLIA is not set
3624 +# CONFIG_CRYPTO_TEST is not set
3625 +CONFIG_CRYPTO_AUTHENC=m
3626 +# CONFIG_CRYPTO_LZO is not set
3627 +# CONFIG_CRYPTO_HW is not set
3628 +
3629 +#
3630 +# Library routines
3631 +#
3632 +CONFIG_BITREVERSE=y
3633 +CONFIG_CRC_CCITT=m
3634 +# CONFIG_CRC16 is not set
3635 +CONFIG_CRC_ITU_T=m
3636 +CONFIG_CRC32=y
3637 +CONFIG_CRC7=m
3638 +# CONFIG_LIBCRC32C is not set
3639 +CONFIG_ZLIB_INFLATE=y
3640 +CONFIG_ZLIB_DEFLATE=y
3641 +CONFIG_GENERIC_ALLOCATOR=y
3642 +CONFIG_PLIST=y
3643 +CONFIG_HAS_IOMEM=y
3644 +CONFIG_HAS_IOPORT=y
3645 +CONFIG_HAS_DMA=y
3646 --- /dev/null
3647 +++ b/arch/avr32/drivers/Makefile
3648 @@ -0,0 +1 @@
3649 +obj-$(CONFIG_DW_DMAC) += dw-dmac.o
3650 --- /dev/null
3651 +++ b/arch/avr32/drivers/dw-dmac.c
3652 @@ -0,0 +1,761 @@
3653 +/*
3654 + * Driver for the Synopsys DesignWare DMA Controller
3655 + *
3656 + * Copyright (C) 2005-2006 Atmel Corporation
3657 + *
3658 + * This program is free software; you can redistribute it and/or modify
3659 + * it under the terms of the GNU General Public License version 2 as
3660 + * published by the Free Software Foundation.
3661 + */
3662 +#include <linux/clk.h>
3663 +#include <linux/device.h>
3664 +#include <linux/dma-mapping.h>
3665 +#include <linux/dmapool.h>
3666 +#include <linux/init.h>
3667 +#include <linux/interrupt.h>
3668 +#include <linux/module.h>
3669 +#include <linux/platform_device.h>
3670 +
3671 +#include <asm/dma-controller.h>
3672 +#include <asm/io.h>
3673 +
3674 +#include "dw-dmac.h"
3675 +
3676 +#define DMAC_NR_CHANNELS 3
3677 +#define DMAC_MAX_BLOCKSIZE 4095
3678 +
3679 +enum {
3680 + CH_STATE_FREE = 0,
3681 + CH_STATE_ALLOCATED,
3682 + CH_STATE_BUSY,
3683 +};
3684 +
3685 +struct dw_dma_lli {
3686 + dma_addr_t sar;
3687 + dma_addr_t dar;
3688 + dma_addr_t llp;
3689 + u32 ctllo;
3690 + u32 ctlhi;
3691 + u32 sstat;
3692 + u32 dstat;
3693 +};
3694 +
3695 +struct dw_dma_block {
3696 + struct dw_dma_lli *lli_vaddr;
3697 + dma_addr_t lli_dma_addr;
3698 +};
3699 +
3700 +struct dw_dma_channel {
3701 + unsigned int state;
3702 + int is_cyclic;
3703 + struct dma_request_sg *req_sg;
3704 + struct dma_request_cyclic *req_cyclic;
3705 + unsigned int nr_blocks;
3706 + int direction;
3707 + struct dw_dma_block *block;
3708 +};
3709 +
3710 +struct dw_dma_controller {
3711 + spinlock_t lock;
3712 + void * __iomem regs;
3713 + struct dma_pool *lli_pool;
3714 + struct clk *hclk;
3715 + struct dma_controller dma;
3716 + struct dw_dma_channel channel[DMAC_NR_CHANNELS];
3717 +};
3718 +#define to_dw_dmac(dmac) container_of(dmac, struct dw_dma_controller, dma)
3719 +
3720 +#define dmac_writel_hi(dmac, reg, value) \
3721 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg + 4)
3722 +#define dmac_readl_hi(dmac, reg) \
3723 + __raw_readl((dmac)->regs + DW_DMAC_##reg + 4)
3724 +#define dmac_writel_lo(dmac, reg, value) \
3725 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg)
3726 +#define dmac_readl_lo(dmac, reg) \
3727 + __raw_readl((dmac)->regs + DW_DMAC_##reg)
3728 +#define dmac_chan_writel_hi(dmac, chan, reg, value) \
3729 + __raw_writel((value), ((dmac)->regs + 0x58 * (chan) \
3730 + + DW_DMAC_CHAN_##reg + 4))
3731 +#define dmac_chan_readl_hi(dmac, chan, reg) \
3732 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg + 4)
3733 +#define dmac_chan_writel_lo(dmac, chan, reg, value) \
3734 + __raw_writel((value), (dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
3735 +#define dmac_chan_readl_lo(dmac, chan, reg) \
3736 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
3737 +#define set_channel_bit(dmac, reg, chan) \
3738 + dmac_writel_lo(dmac, reg, (1 << (chan)) | (1 << ((chan) + 8)))
3739 +#define clear_channel_bit(dmac, reg, chan) \
3740 + dmac_writel_lo(dmac, reg, (0 << (chan)) | (1 << ((chan) + 8)))
3741 +
3742 +static int dmac_alloc_channel(struct dma_controller *_dmac)
3743 +{
3744 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
3745 + struct dw_dma_channel *chan;
3746 + unsigned long flags;
3747 + int i;
3748 +
3749 + spin_lock_irqsave(&dmac->lock, flags);
3750 + for (i = 0; i < DMAC_NR_CHANNELS; i++)
3751 + if (dmac->channel[i].state == CH_STATE_FREE)
3752 + break;
3753 +
3754 + if (i < DMAC_NR_CHANNELS) {
3755 + chan = &dmac->channel[i];
3756 + chan->state = CH_STATE_ALLOCATED;
3757 + } else {
3758 + i = -EBUSY;
3759 + }
3760 +
3761 + spin_unlock_irqrestore(&dmac->lock, flags);
3762 +
3763 + return i;
3764 +}
3765 +
3766 +static void dmac_release_channel(struct dma_controller *_dmac, int channel)
3767 +{
3768 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
3769 +
3770 + BUG_ON(channel >= DMAC_NR_CHANNELS
3771 + || dmac->channel[channel].state != CH_STATE_ALLOCATED);
3772 +
3773 + dmac->channel[channel].state = CH_STATE_FREE;
3774 +}
3775 +
3776 +static struct dw_dma_block *allocate_blocks(struct dw_dma_controller *dmac,
3777 + unsigned int nr_blocks)
3778 +{
3779 + struct dw_dma_block *block;
3780 + void *p;
3781 + unsigned int i;
3782 +
3783 + block = kmalloc(nr_blocks * sizeof(*block),
3784 + GFP_KERNEL);
3785 + if (unlikely(!block))
3786 + return NULL;
3787 +
3788 + for (i = 0; i < nr_blocks; i++) {
3789 + p = dma_pool_alloc(dmac->lli_pool, GFP_KERNEL,
3790 + &block[i].lli_dma_addr);
3791 + block[i].lli_vaddr = p;
3792 + if (unlikely(!p))
3793 + goto fail;
3794 + }
3795 +
3796 + return block;
3797 +
3798 +fail:
3799 + for (i = 0; i < nr_blocks; i++) {
3800 + if (!block[i].lli_vaddr)
3801 + break;
3802 + dma_pool_free(dmac->lli_pool, block[i].lli_vaddr,
3803 + block[i].lli_dma_addr);
3804 + }
3805 + kfree(block);
3806 + return NULL;
3807 +}
3808 +
3809 +static void cleanup_channel(struct dw_dma_controller *dmac,
3810 + struct dw_dma_channel *chan)
3811 +{
3812 + unsigned int i;
3813 +
3814 + if (chan->nr_blocks > 1) {
3815 + for (i = 0; i < chan->nr_blocks; i++)
3816 + dma_pool_free(dmac->lli_pool, chan->block[i].lli_vaddr,
3817 + chan->block[i].lli_dma_addr);
3818 + kfree(chan->block);
3819 + }
3820 +
3821 + chan->state = CH_STATE_ALLOCATED;
3822 +}
3823 +
3824 +static int dmac_prepare_request_sg(struct dma_controller *_dmac,
3825 + struct dma_request_sg *req)
3826 +{
3827 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
3828 + struct dw_dma_channel *chan;
3829 + unsigned long ctlhi, ctllo, cfghi, cfglo;
3830 + unsigned long block_size;
3831 + unsigned int nr_blocks;
3832 + int ret, i, direction;
3833 + unsigned long flags;
3834 +
3835 + spin_lock_irqsave(&dmac->lock, flags);
3836 +
3837 + ret = -EINVAL;
3838 + if (req->req.channel >= DMAC_NR_CHANNELS
3839 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
3840 + || req->block_size > DMAC_MAX_BLOCKSIZE) {
3841 + spin_unlock_irqrestore(&dmac->lock, flags);
3842 + return -EINVAL;
3843 + }
3844 +
3845 + chan = &dmac->channel[req->req.channel];
3846 + chan->state = CH_STATE_BUSY;
3847 + chan->req_sg = req;
3848 + chan->is_cyclic = 0;
3849 +
3850 + /*
3851 + * We have marked the channel as busy, so no need to keep the
3852 + * lock as long as we only touch the channel-specific
3853 + * registers
3854 + */
3855 + spin_unlock_irqrestore(&dmac->lock, flags);
3856 +
3857 + /*
3858 + * There may be limitations in the driver and/or the DMA
3859 + * controller that prevents us from sending a whole
3860 + * scatterlist item in one go. Taking this into account,
3861 + * calculate the number of block transfers we need to set up.
3862 + *
3863 + * FIXME: Let the peripheral driver know about the maximum
3864 + * block size we support. We really don't want to use a
3865 + * different block size than what was suggested by the
3866 + * peripheral.
3867 + *
3868 + * Each block will get its own Linked List Item (LLI) below.
3869 + */
3870 + block_size = req->block_size;
3871 + nr_blocks = req->nr_blocks;
3872 + pr_debug("block_size %lu, nr_blocks %u nr_sg = %u\n",
3873 + block_size, nr_blocks, req->nr_sg);
3874 +
3875 + BUG_ON(nr_blocks == 0);
3876 + chan->nr_blocks = nr_blocks;
3877 +
3878 + ret = -EINVAL;
3879 + cfglo = cfghi = 0;
3880 + switch (req->direction) {
3881 + case DMA_DIR_MEM_TO_PERIPH:
3882 + direction = DMA_TO_DEVICE;
3883 + cfghi = req->periph_id << (43 - 32);
3884 + break;
3885 +
3886 + case DMA_DIR_PERIPH_TO_MEM:
3887 + direction = DMA_FROM_DEVICE;
3888 + cfghi = req->periph_id << (39 - 32);
3889 + break;
3890 + default:
3891 + goto out_unclaim_channel;
3892 + }
3893 +
3894 + chan->direction = direction;
3895 +
3896 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
3897 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
3898 +
3899 + ctlhi = block_size >> req->width;
3900 + ctllo = ((req->direction << 20)
3901 + // | (1 << 14) | (1 << 11) // source/dest burst trans len
3902 + | (req->width << 4) | (req->width << 1)
3903 + | (1 << 0)); // interrupt enable
3904 +
3905 + if (nr_blocks == 1) {
3906 + /* Only one block: No need to use block chaining */
3907 + if (direction == DMA_TO_DEVICE) {
3908 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
3909 + req->sg->dma_address);
3910 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
3911 + req->data_reg);
3912 + ctllo |= 2 << 7; // no dst increment
3913 + } else {
3914 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
3915 + req->data_reg);
3916 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
3917 + req->sg->dma_address);
3918 + ctllo |= 2 << 9; // no src increment
3919 + }
3920 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, ctllo);
3921 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, ctlhi);
3922 + pr_debug("ctl hi:lo 0x%lx:%lx\n", ctlhi, ctllo);
3923 + } else {
3924 + struct dw_dma_lli *lli, *lli_prev = NULL;
3925 + int j = 0, offset = 0;
3926 +
3927 + ret = -ENOMEM;
3928 + chan->block = allocate_blocks(dmac, nr_blocks);
3929 + if (!chan->block)
3930 + goto out_unclaim_channel;
3931 +
3932 + if (direction == DMA_TO_DEVICE)
3933 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
3934 + else
3935 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
3936 +
3937 + /*
3938 + * Map scatterlist items to blocks. One scatterlist
3939 + * item may need more than one block for the reasons
3940 + * mentioned above.
3941 + */
3942 + for (i = 0; i < nr_blocks; i++) {
3943 + lli = chan->block[i].lli_vaddr;
3944 + if (lli_prev) {
3945 + lli_prev->llp = chan->block[i].lli_dma_addr;
3946 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3947 + i - 1, chan->block[i - 1].lli_vaddr,
3948 + chan->block[i - 1].lli_dma_addr,
3949 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
3950 + lli_prev->ctllo, lli_prev->ctlhi);
3951 + }
3952 + lli->llp = 0;
3953 + lli->ctllo = ctllo;
3954 + lli->ctlhi = ctlhi;
3955 + if (direction == DMA_TO_DEVICE) {
3956 + lli->sar = req->sg[j].dma_address + offset;
3957 + lli->dar = req->data_reg;
3958 + } else {
3959 + lli->sar = req->data_reg;
3960 + lli->dar = req->sg[j].dma_address + offset;
3961 + }
3962 + lli_prev = lli;
3963 +
3964 + offset += block_size;
3965 + if (offset > req->sg[j].length) {
3966 + j++;
3967 + offset = 0;
3968 + }
3969 + }
3970 +
3971 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3972 + i - 1, chan->block[i - 1].lli_vaddr,
3973 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
3974 + lli_prev->dar, lli_prev->llp,
3975 + lli_prev->ctllo, lli_prev->ctlhi);
3976 +
3977 + /*
3978 + * SAR, DAR and CTL are initialized from the LLI. We
3979 + * only have to enable the LLI bits in CTL.
3980 + */
3981 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, 0);
3982 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
3983 + chan->block[0].lli_dma_addr);
3984 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
3985 + }
3986 +
3987 + set_channel_bit(dmac, MASK_XFER, req->req.channel);
3988 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
3989 + if (req->req.block_complete)
3990 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
3991 + else
3992 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
3993 +
3994 + return 0;
3995 +
3996 +out_unclaim_channel:
3997 + chan->state = CH_STATE_ALLOCATED;
3998 + return ret;
3999 +}
4000 +
4001 +static int dmac_prepare_request_cyclic(struct dma_controller *_dmac,
4002 + struct dma_request_cyclic *req)
4003 +{
4004 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4005 + struct dw_dma_channel *chan;
4006 + unsigned long ctlhi, ctllo, cfghi, cfglo;
4007 + unsigned long block_size;
4008 + int ret, i, direction;
4009 + unsigned long flags;
4010 +
4011 + spin_lock_irqsave(&dmac->lock, flags);
4012 +
4013 + block_size = (req->buffer_size/req->periods) >> req->width;
4014 +
4015 + ret = -EINVAL;
4016 + if (req->req.channel >= DMAC_NR_CHANNELS
4017 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
4018 + || (req->periods == 0)
4019 + || block_size > DMAC_MAX_BLOCKSIZE) {
4020 + spin_unlock_irqrestore(&dmac->lock, flags);
4021 + return -EINVAL;
4022 + }
4023 +
4024 + chan = &dmac->channel[req->req.channel];
4025 + chan->state = CH_STATE_BUSY;
4026 + chan->is_cyclic = 1;
4027 + chan->req_cyclic = req;
4028 +
4029 + /*
4030 + * We have marked the channel as busy, so no need to keep the
4031 + * lock as long as we only touch the channel-specific
4032 + * registers
4033 + */
4034 + spin_unlock_irqrestore(&dmac->lock, flags);
4035 +
4036 + /*
4037 + Setup
4038 + */
4039 + BUG_ON(req->buffer_size % req->periods);
4040 + /* printk(KERN_INFO "block_size = %lu, periods = %u\n", block_size, req->periods); */
4041 +
4042 + chan->nr_blocks = req->periods;
4043 +
4044 + ret = -EINVAL;
4045 + cfglo = cfghi = 0;
4046 + switch (req->direction) {
4047 + case DMA_DIR_MEM_TO_PERIPH:
4048 + direction = DMA_TO_DEVICE;
4049 + cfghi = req->periph_id << (43 - 32);
4050 + break;
4051 +
4052 + case DMA_DIR_PERIPH_TO_MEM:
4053 + direction = DMA_FROM_DEVICE;
4054 + cfghi = req->periph_id << (39 - 32);
4055 + break;
4056 + default:
4057 + goto out_unclaim_channel;
4058 + }
4059 +
4060 + chan->direction = direction;
4061 +
4062 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
4063 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
4064 +
4065 + ctlhi = block_size;
4066 + ctllo = ((req->direction << 20)
4067 + | (req->width << 4) | (req->width << 1)
4068 + | (1 << 0)); // interrupt enable
4069 +
4070 + {
4071 + struct dw_dma_lli *lli = NULL, *lli_prev = NULL;
4072 +
4073 + ret = -ENOMEM;
4074 + chan->block = allocate_blocks(dmac, req->periods);
4075 + if (!chan->block)
4076 + goto out_unclaim_channel;
4077 +
4078 + if (direction == DMA_TO_DEVICE)
4079 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
4080 + else
4081 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
4082 +
4083 + /*
4084 + * Set up a linked list items where each period gets
4085 + * an item. The linked list item for the last period
4086 + * points back to the star of the buffer making a
4087 + * cyclic buffer.
4088 + */
4089 + for (i = 0; i < req->periods; i++) {
4090 + lli = chan->block[i].lli_vaddr;
4091 + if (lli_prev) {
4092 + lli_prev->llp = chan->block[i].lli_dma_addr;
4093 + /* printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
4094 + i - 1, chan->block[i - 1].lli_vaddr,
4095 + chan->block[i - 1].lli_dma_addr,
4096 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
4097 + lli_prev->ctllo, lli_prev->ctlhi);*/
4098 + }
4099 + lli->llp = 0;
4100 + lli->ctllo = ctllo;
4101 + lli->ctlhi = ctlhi;
4102 + if (direction == DMA_TO_DEVICE) {
4103 + lli->sar = req->buffer_start + i*(block_size << req->width);
4104 + lli->dar = req->data_reg;
4105 + } else {
4106 + lli->sar = req->data_reg;
4107 + lli->dar = req->buffer_start + i*(block_size << req->width);
4108 + }
4109 + lli_prev = lli;
4110 + }
4111 + lli->llp = chan->block[0].lli_dma_addr;
4112 +
4113 + /*printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
4114 + i - 1, chan->block[i - 1].lli_vaddr,
4115 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
4116 + lli_prev->dar, lli_prev->llp,
4117 + lli_prev->ctllo, lli_prev->ctlhi); */
4118 +
4119 + /*
4120 + * SAR, DAR and CTL are initialized from the LLI. We
4121 + * only have to enable the LLI bits in CTL.
4122 + */
4123 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
4124 + chan->block[0].lli_dma_addr);
4125 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
4126 + }
4127 +
4128 + clear_channel_bit(dmac, MASK_XFER, req->req.channel);
4129 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
4130 + if (req->req.block_complete)
4131 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
4132 + else
4133 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
4134 +
4135 + return 0;
4136 +
4137 +out_unclaim_channel:
4138 + chan->state = CH_STATE_ALLOCATED;
4139 + return ret;
4140 +}
4141 +
4142 +static int dmac_start_request(struct dma_controller *_dmac,
4143 + unsigned int channel)
4144 +{
4145 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4146 +
4147 + BUG_ON(channel >= DMAC_NR_CHANNELS);
4148 +
4149 + set_channel_bit(dmac, CH_EN, channel);
4150 +
4151 + return 0;
4152 +}
4153 +
4154 +static dma_addr_t dmac_get_current_pos(struct dma_controller *_dmac,
4155 + unsigned int channel)
4156 +{
4157 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4158 + struct dw_dma_channel *chan;
4159 + dma_addr_t current_pos;
4160 +
4161 + BUG_ON(channel >= DMAC_NR_CHANNELS);
4162 +
4163 + chan = &dmac->channel[channel];
4164 +
4165 + switch (chan->direction) {
4166 + case DMA_TO_DEVICE:
4167 + current_pos = dmac_chan_readl_lo(dmac, channel, SAR);
4168 + break;
4169 + case DMA_FROM_DEVICE:
4170 + current_pos = dmac_chan_readl_lo(dmac, channel, DAR);
4171 + break;
4172 + default:
4173 + return 0;
4174 + }
4175 +
4176 +
4177 + if (!current_pos) {
4178 + if (chan->is_cyclic) {
4179 + current_pos = chan->req_cyclic->buffer_start;
4180 + } else {
4181 + current_pos = chan->req_sg->sg->dma_address;
4182 + }
4183 + }
4184 +
4185 + return current_pos;
4186 +}
4187 +
4188 +
4189 +static int dmac_stop_request(struct dma_controller *_dmac,
4190 + unsigned int channel)
4191 +{
4192 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4193 + struct dw_dma_channel *chan;
4194 +
4195 + BUG_ON(channel >= DMAC_NR_CHANNELS);
4196 +
4197 + chan = &dmac->channel[channel];
4198 + pr_debug("stop: st%u s%08x d%08x l%08x ctl0x%08x:0x%08x\n",
4199 + chan->state, dmac_chan_readl_lo(dmac, channel, SAR),
4200 + dmac_chan_readl_lo(dmac, channel, DAR),
4201 + dmac_chan_readl_lo(dmac, channel, LLP),
4202 + dmac_chan_readl_hi(dmac, channel, CTL),
4203 + dmac_chan_readl_lo(dmac, channel, CTL));
4204 +
4205 + if (chan->state == CH_STATE_BUSY) {
4206 + clear_channel_bit(dmac, CH_EN, channel);
4207 + cleanup_channel(dmac, &dmac->channel[channel]);
4208 + }
4209 +
4210 + return 0;
4211 +}
4212 +
4213 +
4214 +static void dmac_block_complete(struct dw_dma_controller *dmac)
4215 +{
4216 + struct dw_dma_channel *chan;
4217 + unsigned long status, chanid;
4218 +
4219 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
4220 +
4221 + while (status) {
4222 + struct dma_request *req;
4223 + chanid = __ffs(status);
4224 + chan = &dmac->channel[chanid];
4225 +
4226 + if (chan->is_cyclic) {
4227 + BUG_ON(!chan->req_cyclic
4228 + || !chan->req_cyclic->req.block_complete);
4229 + req = &chan->req_cyclic->req;
4230 + } else {
4231 + BUG_ON(!chan->req_sg || !chan->req_sg->req.block_complete);
4232 + req = &chan->req_sg->req;
4233 + }
4234 + dmac_writel_lo(dmac, CLEAR_BLOCK, 1 << chanid);
4235 + req->block_complete(req);
4236 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
4237 + }
4238 +}
4239 +
4240 +static void dmac_xfer_complete(struct dw_dma_controller *dmac)
4241 +{
4242 + struct dw_dma_channel *chan;
4243 + struct dma_request *req;
4244 + unsigned long status, chanid;
4245 +
4246 + status = dmac_readl_lo(dmac, STATUS_XFER);
4247 +
4248 + while (status) {
4249 + chanid = __ffs(status);
4250 + chan = &dmac->channel[chanid];
4251 +
4252 + dmac_writel_lo(dmac, CLEAR_XFER, 1 << chanid);
4253 +
4254 + req = &chan->req_sg->req;
4255 + BUG_ON(!req);
4256 + cleanup_channel(dmac, chan);
4257 + if (req->xfer_complete)
4258 + req->xfer_complete(req);
4259 +
4260 + status = dmac_readl_lo(dmac, STATUS_XFER);
4261 + }
4262 +}
4263 +
4264 +static void dmac_error(struct dw_dma_controller *dmac)
4265 +{
4266 + struct dw_dma_channel *chan;
4267 + unsigned long status, chanid;
4268 +
4269 + status = dmac_readl_lo(dmac, STATUS_ERROR);
4270 +
4271 + while (status) {
4272 + struct dma_request *req;
4273 +
4274 + chanid = __ffs(status);
4275 + chan = &dmac->channel[chanid];
4276 +
4277 + dmac_writel_lo(dmac, CLEAR_ERROR, 1 << chanid);
4278 + clear_channel_bit(dmac, CH_EN, chanid);
4279 +
4280 + if (chan->is_cyclic) {
4281 + BUG_ON(!chan->req_cyclic);
4282 + req = &chan->req_cyclic->req;
4283 + } else {
4284 + BUG_ON(!chan->req_sg);
4285 + req = &chan->req_sg->req;
4286 + }
4287 +
4288 + cleanup_channel(dmac, chan);
4289 + if (req->error)
4290 + req->error(req);
4291 +
4292 + status = dmac_readl_lo(dmac, STATUS_XFER);
4293 + }
4294 +}
4295 +
4296 +static irqreturn_t dmac_interrupt(int irq, void *dev_id)
4297 +{
4298 + struct dw_dma_controller *dmac = dev_id;
4299 + unsigned long status;
4300 + int ret = IRQ_NONE;
4301 +
4302 + spin_lock(&dmac->lock);
4303 +
4304 + status = dmac_readl_lo(dmac, STATUS_INT);
4305 +
4306 + while (status) {
4307 + ret = IRQ_HANDLED;
4308 + if (status & 0x10)
4309 + dmac_error(dmac);
4310 + if (status & 0x02)
4311 + dmac_block_complete(dmac);
4312 + if (status & 0x01)
4313 + dmac_xfer_complete(dmac);
4314 +
4315 + status = dmac_readl_lo(dmac, STATUS_INT);
4316 + }
4317 +
4318 + spin_unlock(&dmac->lock);
4319 + return ret;
4320 +}
4321 +
4322 +static int __devinit dmac_probe(struct platform_device *pdev)
4323 +{
4324 + struct dw_dma_controller *dmac;
4325 + struct resource *regs;
4326 + int ret;
4327 +
4328 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4329 + if (!regs)
4330 + return -ENXIO;
4331 +
4332 + dmac = kmalloc(sizeof(*dmac), GFP_KERNEL);
4333 + if (!dmac)
4334 + return -ENOMEM;
4335 + memset(dmac, 0, sizeof(*dmac));
4336 +
4337 + dmac->hclk = clk_get(&pdev->dev, "hclk");
4338 + if (IS_ERR(dmac->hclk)) {
4339 + ret = PTR_ERR(dmac->hclk);
4340 + goto out_free_dmac;
4341 + }
4342 + clk_enable(dmac->hclk);
4343 +
4344 + ret = -ENOMEM;
4345 + dmac->lli_pool = dma_pool_create("dmac", &pdev->dev,
4346 + sizeof(struct dw_dma_lli), 4, 0);
4347 + if (!dmac->lli_pool)
4348 + goto out_disable_clk;
4349 +
4350 + spin_lock_init(&dmac->lock);
4351 + dmac->dma.dev = &pdev->dev;
4352 + dmac->dma.alloc_channel = dmac_alloc_channel;
4353 + dmac->dma.release_channel = dmac_release_channel;
4354 + dmac->dma.prepare_request_sg = dmac_prepare_request_sg;
4355 + dmac->dma.prepare_request_cyclic = dmac_prepare_request_cyclic;
4356 + dmac->dma.start_request = dmac_start_request;
4357 + dmac->dma.stop_request = dmac_stop_request;
4358 + dmac->dma.get_current_pos = dmac_get_current_pos;
4359 +
4360 + dmac->regs = ioremap(regs->start, regs->end - regs->start + 1);
4361 + if (!dmac->regs)
4362 + goto out_free_pool;
4363 +
4364 + ret = request_irq(platform_get_irq(pdev, 0), dmac_interrupt,
4365 + IRQF_SAMPLE_RANDOM, pdev->name, dmac);
4366 + if (ret)
4367 + goto out_unmap_regs;
4368 +
4369 + /* Enable the DMA controller */
4370 + dmac_writel_lo(dmac, CFG, 1);
4371 +
4372 + register_dma_controller(&dmac->dma);
4373 +
4374 + printk(KERN_INFO
4375 + "dmac%d: DesignWare DMA controller at 0x%p irq %d\n",
4376 + dmac->dma.id, dmac->regs, platform_get_irq(pdev, 0));
4377 +
4378 + return 0;
4379 +
4380 +out_unmap_regs:
4381 + iounmap(dmac->regs);
4382 +out_free_pool:
4383 + dma_pool_destroy(dmac->lli_pool);
4384 +out_disable_clk:
4385 + clk_disable(dmac->hclk);
4386 + clk_put(dmac->hclk);
4387 +out_free_dmac:
4388 + kfree(dmac);
4389 + return ret;
4390 +}
4391 +
4392 +static struct platform_driver dmac_driver = {
4393 + .probe = dmac_probe,
4394 + .driver = {
4395 + .name = "dmaca",
4396 + },
4397 +};
4398 +
4399 +static int __init dmac_init(void)
4400 +{
4401 + return platform_driver_register(&dmac_driver);
4402 +}
4403 +subsys_initcall(dmac_init);
4404 +
4405 +static void __exit dmac_exit(void)
4406 +{
4407 + platform_driver_unregister(&dmac_driver);
4408 +}
4409 +module_exit(dmac_exit);
4410 +
4411 +MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
4412 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
4413 +MODULE_LICENSE("GPL");
4414 --- /dev/null
4415 +++ b/arch/avr32/drivers/dw-dmac.h
4416 @@ -0,0 +1,42 @@
4417 +/*
4418 + * Driver for the Synopsys DesignWare DMA Controller
4419 + *
4420 + * Copyright (C) 2005-2006 Atmel Corporation
4421 + *
4422 + * This program is free software; you can redistribute it and/or modify
4423 + * it under the terms of the GNU General Public License version 2 as
4424 + * published by the Free Software Foundation.
4425 + */
4426 +#ifndef __AVR32_DW_DMAC_H__
4427 +#define __AVR32_DW_DMAC_H__
4428 +
4429 +#define DW_DMAC_CFG 0x398
4430 +#define DW_DMAC_CH_EN 0x3a0
4431 +
4432 +#define DW_DMAC_STATUS_XFER 0x2e8
4433 +#define DW_DMAC_STATUS_BLOCK 0x2f0
4434 +#define DW_DMAC_STATUS_ERROR 0x308
4435 +
4436 +#define DW_DMAC_MASK_XFER 0x310
4437 +#define DW_DMAC_MASK_BLOCK 0x318
4438 +#define DW_DMAC_MASK_ERROR 0x330
4439 +
4440 +#define DW_DMAC_CLEAR_XFER 0x338
4441 +#define DW_DMAC_CLEAR_BLOCK 0x340
4442 +#define DW_DMAC_CLEAR_ERROR 0x358
4443 +
4444 +#define DW_DMAC_STATUS_INT 0x360
4445 +
4446 +#define DW_DMAC_CHAN_SAR 0x000
4447 +#define DW_DMAC_CHAN_DAR 0x008
4448 +#define DW_DMAC_CHAN_LLP 0x010
4449 +#define DW_DMAC_CHAN_CTL 0x018
4450 +#define DW_DMAC_CHAN_SSTAT 0x020
4451 +#define DW_DMAC_CHAN_DSTAT 0x028
4452 +#define DW_DMAC_CHAN_SSTATAR 0x030
4453 +#define DW_DMAC_CHAN_DSTATAR 0x038
4454 +#define DW_DMAC_CHAN_CFG 0x040
4455 +#define DW_DMAC_CHAN_SGR 0x048
4456 +#define DW_DMAC_CHAN_DSR 0x050
4457 +
4458 +#endif /* __AVR32_DW_DMAC_H__ */
4459 --- a/arch/avr32/kernel/Makefile
4460 +++ b/arch/avr32/kernel/Makefile
4461 @@ -9,6 +9,7 @@
4462 obj-y += setup.o traps.o semaphore.o ocd.o ptrace.o
4463 obj-y += signal.o sys_avr32.o process.o time.o
4464 obj-y += init_task.o switch_to.o cpu.o
4465 +obj-y += dma-controller.o
4466 obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o
4467 obj-$(CONFIG_KPROBES) += kprobes.o
4468 obj-$(CONFIG_STACKTRACE) += stacktrace.o
4469 --- a/arch/avr32/kernel/avr32_ksyms.c
4470 +++ b/arch/avr32/kernel/avr32_ksyms.c
4471 @@ -29,7 +29,9 @@
4472 */
4473 EXPORT_SYMBOL(memset);
4474 EXPORT_SYMBOL(memcpy);
4475 +
4476 EXPORT_SYMBOL(clear_page);
4477 +EXPORT_SYMBOL(copy_page);
4478
4479 /*
4480 * Userspace access stuff.
4481 @@ -41,6 +43,8 @@
4482 EXPORT_SYMBOL(__strncpy_from_user);
4483 EXPORT_SYMBOL(clear_user);
4484 EXPORT_SYMBOL(__clear_user);
4485 +EXPORT_SYMBOL(strnlen_user);
4486 +
4487 EXPORT_SYMBOL(csum_partial);
4488 EXPORT_SYMBOL(csum_partial_copy_generic);
4489
4490 --- /dev/null
4491 +++ b/arch/avr32/kernel/dma-controller.c
4492 @@ -0,0 +1,34 @@
4493 +/*
4494 + * Preliminary DMA controller framework for AVR32
4495 + *
4496 + * Copyright (C) 2005-2006 Atmel Corporation
4497 + *
4498 + * This program is free software; you can redistribute it and/or modify
4499 + * it under the terms of the GNU General Public License version 2 as
4500 + * published by the Free Software Foundation.
4501 + */
4502 +#include <asm/dma-controller.h>
4503 +
4504 +static LIST_HEAD(controllers);
4505 +
4506 +int register_dma_controller(struct dma_controller *dmac)
4507 +{
4508 + static int next_id;
4509 +
4510 + dmac->id = next_id++;
4511 + list_add_tail(&dmac->list, &controllers);
4512 +
4513 + return 0;
4514 +}
4515 +EXPORT_SYMBOL(register_dma_controller);
4516 +
4517 +struct dma_controller *find_dma_controller(int id)
4518 +{
4519 + struct dma_controller *dmac;
4520 +
4521 + list_for_each_entry(dmac, &controllers, list)
4522 + if (dmac->id == id)
4523 + return dmac;
4524 + return NULL;
4525 +}
4526 +EXPORT_SYMBOL(find_dma_controller);
4527 --- a/arch/avr32/kernel/entry-avr32b.S
4528 +++ b/arch/avr32/kernel/entry-avr32b.S
4529 @@ -74,50 +74,41 @@
4530 .align 2
4531 bral do_dtlb_modified
4532
4533 - /*
4534 - * r0 : PGD/PT/PTE
4535 - * r1 : Offending address
4536 - * r2 : Scratch register
4537 - * r3 : Cause (5, 12 or 13)
4538 - */
4539 #define tlbmiss_save pushm r0-r3
4540 #define tlbmiss_restore popm r0-r3
4541
4542 - .section .tlbx.ex.text,"ax",@progbits
4543 + .org 0x50
4544 .global itlb_miss
4545 itlb_miss:
4546 tlbmiss_save
4547 rjmp tlb_miss_common
4548
4549 - .section .tlbr.ex.text,"ax",@progbits
4550 + .org 0x60
4551 dtlb_miss_read:
4552 tlbmiss_save
4553 rjmp tlb_miss_common
4554
4555 - .section .tlbw.ex.text,"ax",@progbits
4556 + .org 0x70
4557 dtlb_miss_write:
4558 tlbmiss_save
4559
4560 .global tlb_miss_common
4561 + .align 2
4562 tlb_miss_common:
4563 mfsr r0, SYSREG_TLBEAR
4564 mfsr r1, SYSREG_PTBR
4565
4566 - /* Is it the vmalloc space? */
4567 - bld r0, 31
4568 - brcs handle_vmalloc_miss
4569 -
4570 - /* First level lookup */
4571 + /*
4572 + * First level lookup: The PGD contains virtual pointers to
4573 + * the second-level page tables, but they may be NULL if not
4574 + * present.
4575 + */
4576 pgtbl_lookup:
4577 lsr r2, r0, PGDIR_SHIFT
4578 ld.w r3, r1[r2 << 2]
4579 bfextu r1, r0, PAGE_SHIFT, PGDIR_SHIFT - PAGE_SHIFT
4580 - bld r3, _PAGE_BIT_PRESENT
4581 - brcc page_table_not_present
4582 -
4583 - /* Translate to virtual address in P1. */
4584 - andl r3, 0xf000
4585 - sbr r3, 31
4586 + cp.w r3, 0
4587 + breq page_table_not_present
4588
4589 /* Second level lookup */
4590 ld.w r2, r3[r1 << 2]
4591 @@ -148,16 +139,55 @@
4592 tlbmiss_restore
4593 rete
4594
4595 -handle_vmalloc_miss:
4596 - /* Simply do the lookup in init's page table */
4597 + /* The slow path of the TLB miss handler */
4598 + .align 2
4599 +page_table_not_present:
4600 + /* Do we need to synchronize with swapper_pg_dir? */
4601 + bld r0, 31
4602 + brcs sync_with_swapper_pg_dir
4603 +
4604 +page_not_present:
4605 + tlbmiss_restore
4606 + sub sp, 4
4607 + stmts --sp, r0-lr
4608 + rcall save_full_context_ex
4609 + mfsr r12, SYSREG_ECR
4610 + mov r11, sp
4611 + rcall do_page_fault
4612 + rjmp ret_from_exception
4613 +
4614 + .align 2
4615 +sync_with_swapper_pg_dir:
4616 + /*
4617 + * If swapper_pg_dir contains a non-NULL second-level page
4618 + * table pointer, copy it into the current PGD. If not, we
4619 + * must handle it as a full-blown page fault.
4620 + *
4621 + * Jumping back to pgtbl_lookup causes an unnecessary lookup,
4622 + * but it is guaranteed to be a cache hit, it won't happen
4623 + * very often, and we absolutely do not want to sacrifice any
4624 + * performance in the fast path in order to improve this.
4625 + */
4626 mov r1, lo(swapper_pg_dir)
4627 orh r1, hi(swapper_pg_dir)
4628 + ld.w r3, r1[r2 << 2]
4629 + cp.w r3, 0
4630 + breq page_not_present
4631 + mfsr r1, SYSREG_PTBR
4632 + st.w r1[r2 << 2], r3
4633 rjmp pgtbl_lookup
4634
4635 + /*
4636 + * We currently have two bytes left at this point until we
4637 + * crash into the system call handler...
4638 + *
4639 + * Don't worry, the assembler will let us know.
4640 + */
4641 +
4642
4643 /* --- System Call --- */
4644
4645 - .section .scall.text,"ax",@progbits
4646 + .org 0x100
4647 system_call:
4648 #ifdef CONFIG_PREEMPT
4649 mask_interrupts
4650 @@ -266,18 +296,6 @@
4651 brcc syscall_exit_cont
4652 rjmp enter_monitor_mode
4653
4654 - /* The slow path of the TLB miss handler */
4655 -page_table_not_present:
4656 -page_not_present:
4657 - tlbmiss_restore
4658 - sub sp, 4
4659 - stmts --sp, r0-lr
4660 - rcall save_full_context_ex
4661 - mfsr r12, SYSREG_ECR
4662 - mov r11, sp
4663 - rcall do_page_fault
4664 - rjmp ret_from_exception
4665 -
4666 /* This function expects to find offending PC in SYSREG_RAR_EX */
4667 .type save_full_context_ex, @function
4668 .align 2
4669 @@ -741,26 +759,6 @@
4670
4671 .section .irq.text,"ax",@progbits
4672
4673 -.global cpu_idle_sleep
4674 -cpu_idle_sleep:
4675 - mask_interrupts
4676 - get_thread_info r8
4677 - ld.w r9, r8[TI_flags]
4678 - bld r9, TIF_NEED_RESCHED
4679 - brcs cpu_idle_enable_int_and_exit
4680 - sbr r9, TIF_CPU_GOING_TO_SLEEP
4681 - st.w r8[TI_flags], r9
4682 - unmask_interrupts
4683 - sleep 0
4684 -cpu_idle_skip_sleep:
4685 - mask_interrupts
4686 - ld.w r9, r8[TI_flags]
4687 - cbr r9, TIF_CPU_GOING_TO_SLEEP
4688 - st.w r8[TI_flags], r9
4689 -cpu_idle_enable_int_and_exit:
4690 - unmask_interrupts
4691 - retal r12
4692 -
4693 .global irq_level0
4694 .global irq_level1
4695 .global irq_level2
4696 --- a/arch/avr32/kernel/process.c
4697 +++ b/arch/avr32/kernel/process.c
4698 @@ -18,11 +18,11 @@
4699 #include <asm/sysreg.h>
4700 #include <asm/ocd.h>
4701
4702 +#include <asm/arch/pm.h>
4703 +
4704 void (*pm_power_off)(void) = NULL;
4705 EXPORT_SYMBOL(pm_power_off);
4706
4707 -extern void cpu_idle_sleep(void);
4708 -
4709 /*
4710 * This file handles the architecture-dependent parts of process handling..
4711 */
4712 @@ -54,6 +54,8 @@
4713
4714 void machine_power_off(void)
4715 {
4716 + if (pm_power_off)
4717 + pm_power_off();
4718 }
4719
4720 void machine_restart(char *cmd)
4721 --- a/arch/avr32/kernel/setup.c
4722 +++ b/arch/avr32/kernel/setup.c
4723 @@ -274,6 +274,8 @@
4724 printk(KERN_WARNING
4725 "Failed to allocate framebuffer memory\n");
4726 fbmem_size = 0;
4727 + } else {
4728 + memset(__va(fbmem_start), 0, fbmem_size);
4729 }
4730 }
4731
4732 --- a/arch/avr32/kernel/signal.c
4733 +++ b/arch/avr32/kernel/signal.c
4734 @@ -93,6 +93,9 @@
4735 if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
4736 goto badframe;
4737
4738 + if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT)
4739 + goto badframe;
4740 +
4741 pr_debug("Context restored: pc = %08lx, lr = %08lx, sp = %08lx\n",
4742 regs->pc, regs->lr, regs->sp);
4743
4744 --- a/arch/avr32/kernel/time.c
4745 +++ b/arch/avr32/kernel/time.c
4746 @@ -1,233 +1,147 @@
4747 /*
4748 * Copyright (C) 2004-2007 Atmel Corporation
4749 *
4750 - * Based on MIPS implementation arch/mips/kernel/time.c
4751 - * Copyright 2001 MontaVista Software Inc.
4752 - *
4753 * This program is free software; you can redistribute it and/or modify
4754 * it under the terms of the GNU General Public License version 2 as
4755 * published by the Free Software Foundation.
4756 */
4757 -
4758 #include <linux/clk.h>
4759 -#include <linux/clocksource.h>
4760 -#include <linux/time.h>
4761 -#include <linux/module.h>
4762 +#include <linux/clockchips.h>
4763 +#include <linux/init.h>
4764 #include <linux/interrupt.h>
4765 #include <linux/irq.h>
4766 -#include <linux/kernel_stat.h>
4767 -#include <linux/errno.h>
4768 -#include <linux/init.h>
4769 -#include <linux/profile.h>
4770 -#include <linux/sysdev.h>
4771 -#include <linux/err.h>
4772 +#include <linux/kernel.h>
4773 +#include <linux/time.h>
4774
4775 -#include <asm/div64.h>
4776 #include <asm/sysreg.h>
4777 -#include <asm/io.h>
4778 -#include <asm/sections.h>
4779
4780 -/* how many counter cycles in a jiffy? */
4781 -static u32 cycles_per_jiffy;
4782 +#include <asm/arch/pm.h>
4783
4784 -/* the count value for the next timer interrupt */
4785 -static u32 expirelo;
4786
4787 -cycle_t __weak read_cycle_count(void)
4788 +static cycle_t read_cycle_count(void)
4789 {
4790 return (cycle_t)sysreg_read(COUNT);
4791 }
4792
4793 -struct clocksource __weak clocksource_avr32 = {
4794 - .name = "avr32",
4795 - .rating = 350,
4796 +/*
4797 + * The architectural cycle count registers are a fine clocksource unless
4798 + * the system idle loop use sleep states like "idle": the CPU cycles
4799 + * measured by COUNT (and COMPARE) don't happen during sleep states.
4800 + * Their duration also changes if cpufreq changes the CPU clock rate.
4801 + * So we rate the clocksource using COUNT as very low quality.
4802 + */
4803 +static struct clocksource counter = {
4804 + .name = "avr32_counter",
4805 + .rating = 50,
4806 .read = read_cycle_count,
4807 .mask = CLOCKSOURCE_MASK(32),
4808 .shift = 16,
4809 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
4810 };
4811
4812 -irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
4813 -
4814 -struct irqaction timer_irqaction = {
4815 - .handler = timer_interrupt,
4816 - .flags = IRQF_DISABLED,
4817 - .name = "timer",
4818 -};
4819 -
4820 -/*
4821 - * By default we provide the null RTC ops
4822 - */
4823 -static unsigned long null_rtc_get_time(void)
4824 -{
4825 - return mktime(2007, 1, 1, 0, 0, 0);
4826 -}
4827 -
4828 -static int null_rtc_set_time(unsigned long sec)
4829 +static irqreturn_t timer_interrupt(int irq, void *dev_id)
4830 {
4831 - return 0;
4832 -}
4833 -
4834 -static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
4835 -static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
4836 + struct clock_event_device *evdev = dev_id;
4837
4838 -static void avr32_timer_ack(void)
4839 -{
4840 - u32 count;
4841 -
4842 - /* Ack this timer interrupt and set the next one */
4843 - expirelo += cycles_per_jiffy;
4844 - /* setting COMPARE to 0 stops the COUNT-COMPARE */
4845 - if (expirelo == 0) {
4846 - sysreg_write(COMPARE, expirelo + 1);
4847 - } else {
4848 - sysreg_write(COMPARE, expirelo);
4849 - }
4850 + /*
4851 + * Disable the interrupt until the clockevent subsystem
4852 + * reprograms it.
4853 + */
4854 + sysreg_write(COMPARE, 0);
4855
4856 - /* Check to see if we have missed any timer interrupts */
4857 - count = sysreg_read(COUNT);
4858 - if ((count - expirelo) < 0x7fffffff) {
4859 - expirelo = count + cycles_per_jiffy;
4860 - sysreg_write(COMPARE, expirelo);
4861 - }
4862 + evdev->event_handler(evdev);
4863 + return IRQ_HANDLED;
4864 }
4865
4866 -int __weak avr32_hpt_init(void)
4867 -{
4868 - int ret;
4869 - unsigned long mult, shift, count_hz;
4870 -
4871 - count_hz = clk_get_rate(boot_cpu_data.clk);
4872 - shift = clocksource_avr32.shift;
4873 - mult = clocksource_hz2mult(count_hz, shift);
4874 - clocksource_avr32.mult = mult;
4875 -
4876 - {
4877 - u64 tmp;
4878 -
4879 - tmp = TICK_NSEC;
4880 - tmp <<= shift;
4881 - tmp += mult / 2;
4882 - do_div(tmp, mult);
4883 -
4884 - cycles_per_jiffy = tmp;
4885 - }
4886 +static struct irqaction timer_irqaction = {
4887 + .handler = timer_interrupt,
4888 + .flags = IRQF_TIMER | IRQF_DISABLED,
4889 + .name = "avr32_comparator",
4890 +};
4891
4892 - ret = setup_irq(0, &timer_irqaction);
4893 - if (ret) {
4894 - pr_debug("timer: could not request IRQ 0: %d\n", ret);
4895 - return -ENODEV;
4896 - }
4897 +static int comparator_next_event(unsigned long delta,
4898 + struct clock_event_device *evdev)
4899 +{
4900 + unsigned long flags;
4901
4902 - printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
4903 - "%lu.%03lu MHz\n",
4904 - ((count_hz + 500) / 1000) / 1000,
4905 - ((count_hz + 500) / 1000) % 1000);
4906 + raw_local_irq_save(flags);
4907
4908 - return 0;
4909 -}
4910 + /* The time to read COUNT then update COMPARE must be less
4911 + * than the min_delta_ns value for this clockevent source.
4912 + */
4913 + sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
4914
4915 -/*
4916 - * Taken from MIPS c0_hpt_timer_init().
4917 - *
4918 - * The reason COUNT is written twice is probably to make sure we don't get any
4919 - * timer interrupts while we are messing with the counter.
4920 - */
4921 -int __weak avr32_hpt_start(void)
4922 -{
4923 - u32 count = sysreg_read(COUNT);
4924 - expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
4925 - sysreg_write(COUNT, expirelo - cycles_per_jiffy);
4926 - sysreg_write(COMPARE, expirelo);
4927 - sysreg_write(COUNT, count);
4928 + raw_local_irq_restore(flags);
4929
4930 return 0;
4931 }
4932
4933 -/*
4934 - * local_timer_interrupt() does profiling and process accounting on a
4935 - * per-CPU basis.
4936 - *
4937 - * In UP mode, it is invoked from the (global) timer_interrupt.
4938 - */
4939 -void local_timer_interrupt(int irq, void *dev_id)
4940 +static void comparator_mode(enum clock_event_mode mode,
4941 + struct clock_event_device *evdev)
4942 {
4943 - if (current->pid)
4944 - profile_tick(CPU_PROFILING);
4945 - update_process_times(user_mode(get_irq_regs()));
4946 + switch (mode) {
4947 + case CLOCK_EVT_MODE_ONESHOT:
4948 + pr_debug("%s: start\n", evdev->name);
4949 + /* FALLTHROUGH */
4950 + case CLOCK_EVT_MODE_RESUME:
4951 + cpu_disable_idle_sleep();
4952 + break;
4953 + case CLOCK_EVT_MODE_UNUSED:
4954 + case CLOCK_EVT_MODE_SHUTDOWN:
4955 + sysreg_write(COMPARE, 0);
4956 + pr_debug("%s: stop\n", evdev->name);
4957 + cpu_enable_idle_sleep();
4958 + break;
4959 + default:
4960 + BUG();
4961 + }
4962 }
4963
4964 -irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
4965 -{
4966 - /* ack timer interrupt and try to set next interrupt */
4967 - avr32_timer_ack();
4968 -
4969 - /*
4970 - * Call the generic timer interrupt handler
4971 - */
4972 - write_seqlock(&xtime_lock);
4973 - do_timer(1);
4974 - write_sequnlock(&xtime_lock);
4975 -
4976 - /*
4977 - * In UP mode, we call local_timer_interrupt() to do profiling
4978 - * and process accounting.
4979 - *
4980 - * SMP is not supported yet.
4981 - */
4982 - local_timer_interrupt(irq, dev_id);
4983 -
4984 - return IRQ_HANDLED;
4985 -}
4986 +static struct clock_event_device comparator = {
4987 + .name = "avr32_comparator",
4988 + .features = CLOCK_EVT_FEAT_ONESHOT,
4989 + .shift = 16,
4990 + .rating = 50,
4991 + .cpumask = CPU_MASK_CPU0,
4992 + .set_next_event = comparator_next_event,
4993 + .set_mode = comparator_mode,
4994 +};
4995
4996 void __init time_init(void)
4997 {
4998 + unsigned long counter_hz;
4999 int ret;
5000
5001 - /*
5002 - * Make sure we don't get any COMPARE interrupts before we can
5003 - * handle them.
5004 - */
5005 - sysreg_write(COMPARE, 0);
5006 -
5007 - xtime.tv_sec = rtc_get_time();
5008 + xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
5009 xtime.tv_nsec = 0;
5010
5011 set_normalized_timespec(&wall_to_monotonic,
5012 -xtime.tv_sec, -xtime.tv_nsec);
5013
5014 - ret = avr32_hpt_init();
5015 - if (ret) {
5016 - pr_debug("timer: failed setup: %d\n", ret);
5017 - return;
5018 - }
5019 + /* figure rate for counter */
5020 + counter_hz = clk_get_rate(boot_cpu_data.clk);
5021 + counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
5022
5023 - ret = clocksource_register(&clocksource_avr32);
5024 + ret = clocksource_register(&counter);
5025 if (ret)
5026 pr_debug("timer: could not register clocksource: %d\n", ret);
5027
5028 - ret = avr32_hpt_start();
5029 - if (ret) {
5030 - pr_debug("timer: failed starting: %d\n", ret);
5031 - return;
5032 - }
5033 -}
5034 + /* setup COMPARE clockevent */
5035 + comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
5036 + comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
5037 + comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
5038
5039 -static struct sysdev_class timer_class = {
5040 - .name = "timer",
5041 -};
5042 + sysreg_write(COMPARE, 0);
5043 + timer_irqaction.dev_id = &comparator;
5044
5045 -static struct sys_device timer_device = {
5046 - .id = 0,
5047 - .cls = &timer_class,
5048 -};
5049 + ret = setup_irq(0, &timer_irqaction);
5050 + if (ret)
5051 + pr_debug("timer: could not request IRQ 0: %d\n", ret);
5052 + else {
5053 + clockevents_register_device(&comparator);
5054
5055 -static int __init init_timer_sysfs(void)
5056 -{
5057 - int err = sysdev_class_register(&timer_class);
5058 - if (!err)
5059 - err = sysdev_register(&timer_device);
5060 - return err;
5061 + pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
5062 + ((counter_hz + 500) / 1000) / 1000,
5063 + ((counter_hz + 500) / 1000) % 1000);
5064 + }
5065 }
5066 -
5067 -device_initcall(init_timer_sysfs);
5068 --- a/arch/avr32/kernel/vmlinux.lds.S
5069 +++ b/arch/avr32/kernel/vmlinux.lds.S
5070 @@ -68,14 +68,6 @@
5071 _evba = .;
5072 _text = .;
5073 *(.ex.text)
5074 - . = 0x50;
5075 - *(.tlbx.ex.text)
5076 - . = 0x60;
5077 - *(.tlbr.ex.text)
5078 - . = 0x70;
5079 - *(.tlbw.ex.text)
5080 - . = 0x100;
5081 - *(.scall.text)
5082 *(.irq.text)
5083 KPROBES_TEXT
5084 TEXT_TEXT
5085 @@ -107,6 +99,10 @@
5086 */
5087 *(.data.init_task)
5088
5089 + /* Then, the page-aligned data */
5090 + . = ALIGN(PAGE_SIZE);
5091 + *(.data.page_aligned)
5092 +
5093 /* Then, the cacheline aligned data */
5094 . = ALIGN(L1_CACHE_BYTES);
5095 *(.data.cacheline_aligned)
5096 --- a/arch/avr32/lib/io-readsb.S
5097 +++ b/arch/avr32/lib/io-readsb.S
5098 @@ -41,7 +41,7 @@
5099 2: sub r10, -4
5100 reteq r12
5101
5102 -3: ld.uh r8, r12[0]
5103 +3: ld.ub r8, r12[0]
5104 sub r10, 1
5105 st.b r11++, r8
5106 brne 3b
5107 --- a/arch/avr32/mach-at32ap/Kconfig
5108 +++ b/arch/avr32/mach-at32ap/Kconfig
5109 @@ -26,6 +26,13 @@
5110
5111 endchoice
5112
5113 +config GPIO_DEV
5114 + bool "GPIO /dev interface"
5115 + select CONFIGFS_FS
5116 + default n
5117 + help
5118 + Say `Y' to enable a /dev interface to the GPIO pins.
5119 +
5120 endmenu
5121
5122 endif # PLATFORM_AT32AP
5123 --- a/arch/avr32/mach-at32ap/Makefile
5124 +++ b/arch/avr32/mach-at32ap/Makefile
5125 @@ -1,4 +1,9 @@
5126 -obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
5127 -obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o
5128 -obj-$(CONFIG_CPU_AT32AP700X) += time-tc.o
5129 +obj-y += pdc.o clock.o intc.o extint.o pio.o hsmc.o
5130 +obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
5131 obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
5132 +obj-$(CONFIG_GPIO_DEV) += gpio-dev.o
5133 +obj-$(CONFIG_PM) += pm.o
5134 +
5135 +ifeq ($(CONFIG_PM_DEBUG),y)
5136 +CFLAGS_pm.o += -DDEBUG
5137 +endif
5138 --- a/arch/avr32/mach-at32ap/at32ap.c
5139 +++ /dev/null
5140 @@ -1,56 +0,0 @@
5141 -/*
5142 - * Copyright (C) 2006 Atmel Corporation
5143 - *
5144 - * This program is free software; you can redistribute it and/or modify
5145 - * it under the terms of the GNU General Public License version 2 as
5146 - * published by the Free Software Foundation.
5147 - */
5148 -
5149 -#include <linux/clk.h>
5150 -#include <linux/err.h>
5151 -#include <linux/init.h>
5152 -#include <linux/platform_device.h>
5153 -
5154 -#include <asm/arch/init.h>
5155 -
5156 -void __init setup_platform(void)
5157 -{
5158 - at32_clock_init();
5159 - at32_portmux_init();
5160 -}
5161 -
5162 -static int __init pdc_probe(struct platform_device *pdev)
5163 -{
5164 - struct clk *pclk, *hclk;
5165 -
5166 - pclk = clk_get(&pdev->dev, "pclk");
5167 - if (IS_ERR(pclk)) {
5168 - dev_err(&pdev->dev, "no pclk defined\n");
5169 - return PTR_ERR(pclk);
5170 - }
5171 - hclk = clk_get(&pdev->dev, "hclk");
5172 - if (IS_ERR(hclk)) {
5173 - dev_err(&pdev->dev, "no hclk defined\n");
5174 - clk_put(pclk);
5175 - return PTR_ERR(hclk);
5176 - }
5177 -
5178 - clk_enable(pclk);
5179 - clk_enable(hclk);
5180 -
5181 - dev_info(&pdev->dev, "Atmel Peripheral DMA Controller enabled\n");
5182 - return 0;
5183 -}
5184 -
5185 -static struct platform_driver pdc_driver = {
5186 - .probe = pdc_probe,
5187 - .driver = {
5188 - .name = "pdc",
5189 - },
5190 -};
5191 -
5192 -static int __init pdc_init(void)
5193 -{
5194 - return platform_driver_register(&pdc_driver);
5195 -}
5196 -arch_initcall(pdc_init);
5197 --- a/arch/avr32/mach-at32ap/at32ap700x.c
5198 +++ b/arch/avr32/mach-at32ap/at32ap700x.c
5199 @@ -6,11 +6,13 @@
5200 * published by the Free Software Foundation.
5201 */
5202 #include <linux/clk.h>
5203 +#include <linux/delay.h>
5204 #include <linux/fb.h>
5205 #include <linux/init.h>
5206 #include <linux/platform_device.h>
5207 #include <linux/dma-mapping.h>
5208 #include <linux/spi/spi.h>
5209 +#include <linux/usb/atmel_usba_udc.h>
5210
5211 #include <asm/io.h>
5212 #include <asm/irq.h>
5213 @@ -18,6 +20,7 @@
5214 #include <asm/arch/at32ap700x.h>
5215 #include <asm/arch/board.h>
5216 #include <asm/arch/portmux.h>
5217 +#include <asm/arch/sram.h>
5218
5219 #include <video/atmel_lcdc.h>
5220
5221 @@ -91,25 +94,18 @@
5222
5223 static DEFINE_SPINLOCK(pm_lock);
5224
5225 -unsigned long at32ap7000_osc_rates[3] = {
5226 - [0] = 32768,
5227 - /* FIXME: these are ATSTK1002-specific */
5228 - [1] = 20000000,
5229 - [2] = 12000000,
5230 -};
5231 +static struct clk osc0;
5232 +static struct clk osc1;
5233
5234 static unsigned long osc_get_rate(struct clk *clk)
5235 {
5236 - return at32ap7000_osc_rates[clk->index];
5237 + return at32_board_osc_rates[clk->index];
5238 }
5239
5240 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
5241 {
5242 unsigned long div, mul, rate;
5243
5244 - if (!(control & PM_BIT(PLLEN)))
5245 - return 0;
5246 -
5247 div = PM_BFEXT(PLLDIV, control) + 1;
5248 mul = PM_BFEXT(PLLMUL, control) + 1;
5249
5250 @@ -120,6 +116,71 @@
5251 return rate;
5252 }
5253
5254 +static long pll_set_rate(struct clk *clk, unsigned long rate,
5255 + u32 *pll_ctrl)
5256 +{
5257 + unsigned long mul;
5258 + unsigned long mul_best_fit = 0;
5259 + unsigned long div;
5260 + unsigned long div_min;
5261 + unsigned long div_max;
5262 + unsigned long div_best_fit = 0;
5263 + unsigned long base;
5264 + unsigned long pll_in;
5265 + unsigned long actual = 0;
5266 + unsigned long rate_error;
5267 + unsigned long rate_error_prev = ~0UL;
5268 + u32 ctrl;
5269 +
5270 + /* Rate must be between 80 MHz and 200 Mhz. */
5271 + if (rate < 80000000UL || rate > 200000000UL)
5272 + return -EINVAL;
5273 +
5274 + ctrl = PM_BF(PLLOPT, 4);
5275 + base = clk->parent->get_rate(clk->parent);
5276 +
5277 + /* PLL input frequency must be between 6 MHz and 32 MHz. */
5278 + div_min = DIV_ROUND_UP(base, 32000000UL);
5279 + div_max = base / 6000000UL;
5280 +
5281 + if (div_max < div_min)
5282 + return -EINVAL;
5283 +
5284 + for (div = div_min; div <= div_max; div++) {
5285 + pll_in = (base + div / 2) / div;
5286 + mul = (rate + pll_in / 2) / pll_in;
5287 +
5288 + if (mul == 0)
5289 + continue;
5290 +
5291 + actual = pll_in * mul;
5292 + rate_error = abs(actual - rate);
5293 +
5294 + if (rate_error < rate_error_prev) {
5295 + mul_best_fit = mul;
5296 + div_best_fit = div;
5297 + rate_error_prev = rate_error;
5298 + }
5299 +
5300 + if (rate_error == 0)
5301 + break;
5302 + }
5303 +
5304 + if (div_best_fit == 0)
5305 + return -EINVAL;
5306 +
5307 + ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
5308 + ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
5309 + ctrl |= PM_BF(PLLCOUNT, 16);
5310 +
5311 + if (clk->parent == &osc1)
5312 + ctrl |= PM_BIT(PLLOSC);
5313 +
5314 + *pll_ctrl = ctrl;
5315 +
5316 + return actual;
5317 +}
5318 +
5319 static unsigned long pll0_get_rate(struct clk *clk)
5320 {
5321 u32 control;
5322 @@ -129,6 +190,41 @@
5323 return pll_get_rate(clk, control);
5324 }
5325
5326 +static void pll1_mode(struct clk *clk, int enabled)
5327 +{
5328 + unsigned long timeout;
5329 + u32 status;
5330 + u32 ctrl;
5331 +
5332 + ctrl = pm_readl(PLL1);
5333 +
5334 + if (enabled) {
5335 + if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
5336 + pr_debug("clk %s: failed to enable, rate not set\n",
5337 + clk->name);
5338 + return;
5339 + }
5340 +
5341 + ctrl |= PM_BIT(PLLEN);
5342 + pm_writel(PLL1, ctrl);
5343 +
5344 + /* Wait for PLL lock. */
5345 + for (timeout = 10000; timeout; timeout--) {
5346 + status = pm_readl(ISR);
5347 + if (status & PM_BIT(LOCK1))
5348 + break;
5349 + udelay(10);
5350 + }
5351 +
5352 + if (!(status & PM_BIT(LOCK1)))
5353 + printk(KERN_ERR "clk %s: timeout waiting for lock\n",
5354 + clk->name);
5355 + } else {
5356 + ctrl &= ~PM_BIT(PLLEN);
5357 + pm_writel(PLL1, ctrl);
5358 + }
5359 +}
5360 +
5361 static unsigned long pll1_get_rate(struct clk *clk)
5362 {
5363 u32 control;
5364 @@ -138,6 +234,49 @@
5365 return pll_get_rate(clk, control);
5366 }
5367
5368 +static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
5369 +{
5370 + u32 ctrl = 0;
5371 + unsigned long actual_rate;
5372 +
5373 + actual_rate = pll_set_rate(clk, rate, &ctrl);
5374 +
5375 + if (apply) {
5376 + if (actual_rate != rate)
5377 + return -EINVAL;
5378 + if (clk->users > 0)
5379 + return -EBUSY;
5380 + pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
5381 + clk->name, rate, actual_rate);
5382 + pm_writel(PLL1, ctrl);
5383 + }
5384 +
5385 + return actual_rate;
5386 +}
5387 +
5388 +static int pll1_set_parent(struct clk *clk, struct clk *parent)
5389 +{
5390 + u32 ctrl;
5391 +
5392 + if (clk->users > 0)
5393 + return -EBUSY;
5394 +
5395 + ctrl = pm_readl(PLL1);
5396 + WARN_ON(ctrl & PM_BIT(PLLEN));
5397 +
5398 + if (parent == &osc0)
5399 + ctrl &= ~PM_BIT(PLLOSC);
5400 + else if (parent == &osc1)
5401 + ctrl |= PM_BIT(PLLOSC);
5402 + else
5403 + return -EINVAL;
5404 +
5405 + pm_writel(PLL1, ctrl);
5406 + clk->parent = parent;
5407 +
5408 + return 0;
5409 +}
5410 +
5411 /*
5412 * The AT32AP7000 has five primary clock sources: One 32kHz
5413 * oscillator, two crystal oscillators and two PLLs.
5414 @@ -166,7 +305,10 @@
5415 };
5416 static struct clk pll1 = {
5417 .name = "pll1",
5418 + .mode = pll1_mode,
5419 .get_rate = pll1_get_rate,
5420 + .set_rate = pll1_set_rate,
5421 + .set_parent = pll1_set_parent,
5422 .parent = &osc0,
5423 };
5424
5425 @@ -534,6 +676,14 @@
5426 .users = 1,
5427 .index = 3,
5428 };
5429 +static struct clk sdramc_clk = {
5430 + .name = "sdramc_clk",
5431 + .parent = &pbb_clk,
5432 + .mode = pbb_clk_mode,
5433 + .get_rate = pbb_clk_get_rate,
5434 + .users = 1,
5435 + .index = 14,
5436 +};
5437
5438 static struct resource smc0_resource[] = {
5439 PBMEM(0xfff03400),
5440 @@ -605,19 +755,32 @@
5441 }
5442
5443 /* --------------------------------------------------------------------
5444 - * System Timer/Counter (TC)
5445 + * Timer/Counter (TC)
5446 * -------------------------------------------------------------------- */
5447 -static struct resource at32_systc0_resource[] = {
5448 +
5449 +static struct resource at32_tcb0_resource[] = {
5450 PBMEM(0xfff00c00),
5451 IRQ(22),
5452 };
5453 -struct platform_device at32_systc0_device = {
5454 - .name = "systc",
5455 +static struct platform_device at32_tcb0_device = {
5456 + .name = "atmel_tcb",
5457 .id = 0,
5458 - .resource = at32_systc0_resource,
5459 - .num_resources = ARRAY_SIZE(at32_systc0_resource),
5460 + .resource = at32_tcb0_resource,
5461 + .num_resources = ARRAY_SIZE(at32_tcb0_resource),
5462 +};
5463 +DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
5464 +
5465 +static struct resource at32_tcb1_resource[] = {
5466 + PBMEM(0xfff01000),
5467 + IRQ(23),
5468 +};
5469 +static struct platform_device at32_tcb1_device = {
5470 + .name = "atmel_tcb",
5471 + .id = 1,
5472 + .resource = at32_tcb1_resource,
5473 + .num_resources = ARRAY_SIZE(at32_tcb1_resource),
5474 };
5475 -DEV_CLK(pclk, at32_systc0, pbb, 3);
5476 +DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
5477
5478 /* --------------------------------------------------------------------
5479 * PIO
5480 @@ -669,7 +832,8 @@
5481 platform_device_register(&pdc_device);
5482 platform_device_register(&dmaca0_device);
5483
5484 - platform_device_register(&at32_systc0_device);
5485 + platform_device_register(&at32_tcb0_device);
5486 + platform_device_register(&at32_tcb1_device);
5487
5488 platform_device_register(&pio0_device);
5489 platform_device_register(&pio1_device);
5490 @@ -679,6 +843,81 @@
5491 }
5492
5493 /* --------------------------------------------------------------------
5494 + * PSIF
5495 + * -------------------------------------------------------------------- */
5496 +static struct resource atmel_psif0_resource[] __initdata = {
5497 + {
5498 + .start = 0xffe03c00,
5499 + .end = 0xffe03cff,
5500 + .flags = IORESOURCE_MEM,
5501 + },
5502 + IRQ(18),
5503 +};
5504 +static struct clk atmel_psif0_pclk = {
5505 + .name = "pclk",
5506 + .parent = &pba_clk,
5507 + .mode = pba_clk_mode,
5508 + .get_rate = pba_clk_get_rate,
5509 + .index = 15,
5510 +};
5511 +
5512 +static struct resource atmel_psif1_resource[] __initdata = {
5513 + {
5514 + .start = 0xffe03d00,
5515 + .end = 0xffe03dff,
5516 + .flags = IORESOURCE_MEM,
5517 + },
5518 + IRQ(18),
5519 +};
5520 +static struct clk atmel_psif1_pclk = {
5521 + .name = "pclk",
5522 + .parent = &pba_clk,
5523 + .mode = pba_clk_mode,
5524 + .get_rate = pba_clk_get_rate,
5525 + .index = 15,
5526 +};
5527 +
5528 +struct platform_device *__init at32_add_device_psif(unsigned int id)
5529 +{
5530 + struct platform_device *pdev;
5531 +
5532 + if (!(id == 0 || id == 1))
5533 + return NULL;
5534 +
5535 + pdev = platform_device_alloc("atmel_psif", id);
5536 + if (!pdev)
5537 + return NULL;
5538 +
5539 + switch (id) {
5540 + case 0:
5541 + if (platform_device_add_resources(pdev, atmel_psif0_resource,
5542 + ARRAY_SIZE(atmel_psif0_resource)))
5543 + goto err_add_resources;
5544 + atmel_psif0_pclk.dev = &pdev->dev;
5545 + select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
5546 + select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
5547 + break;
5548 + case 1:
5549 + if (platform_device_add_resources(pdev, atmel_psif1_resource,
5550 + ARRAY_SIZE(atmel_psif1_resource)))
5551 + goto err_add_resources;
5552 + atmel_psif1_pclk.dev = &pdev->dev;
5553 + select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
5554 + select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
5555 + break;
5556 + default:
5557 + return NULL;
5558 + }
5559 +
5560 + platform_device_add(pdev);
5561 + return pdev;
5562 +
5563 +err_add_resources:
5564 + platform_device_put(pdev);
5565 + return NULL;
5566 +}
5567 +
5568 +/* --------------------------------------------------------------------
5569 * USART
5570 * -------------------------------------------------------------------- */
5571
5572 @@ -951,7 +1190,8 @@
5573 switch (id) {
5574 case 0:
5575 pdev = &atmel_spi0_device;
5576 - select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
5577 + /* pullup MISO so a level is always defined */
5578 + select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP);
5579 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
5580 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
5581 at32_spi_setup_slaves(0, b, n, spi0_pins);
5582 @@ -959,7 +1199,8 @@
5583
5584 case 1:
5585 pdev = &atmel_spi1_device;
5586 - select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
5587 + /* pullup MISO so a level is always defined */
5588 + select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP);
5589 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
5590 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
5591 at32_spi_setup_slaves(1, b, n, spi1_pins);
5592 @@ -989,7 +1230,9 @@
5593 .index = 2,
5594 };
5595
5596 -struct platform_device *__init at32_add_device_twi(unsigned int id)
5597 +struct platform_device *__init at32_add_device_twi(unsigned int id,
5598 + struct i2c_board_info *b,
5599 + unsigned int n)
5600 {
5601 struct platform_device *pdev;
5602
5603 @@ -1009,6 +1252,9 @@
5604
5605 atmel_twi0_pclk.dev = &pdev->dev;
5606
5607 + if (b)
5608 + i2c_register_board_info(id, b, n);
5609 +
5610 platform_device_add(pdev);
5611 return pdev;
5612
5613 @@ -1032,7 +1278,8 @@
5614 .index = 9,
5615 };
5616
5617 -struct platform_device *__init at32_add_device_mci(unsigned int id)
5618 +struct platform_device *__init
5619 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
5620 {
5621 struct platform_device *pdev;
5622
5623 @@ -1041,11 +1288,15 @@
5624
5625 pdev = platform_device_alloc("atmel_mci", id);
5626 if (!pdev)
5627 - return NULL;
5628 + goto fail;
5629
5630 if (platform_device_add_resources(pdev, atmel_mci0_resource,
5631 ARRAY_SIZE(atmel_mci0_resource)))
5632 - goto err_add_resources;
5633 + goto fail;
5634 +
5635 + if (data && platform_device_add_data(pdev, data,
5636 + sizeof(struct mci_platform_data)))
5637 + goto fail;
5638
5639 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
5640 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
5641 @@ -1054,12 +1305,19 @@
5642 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
5643 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
5644
5645 + if (data) {
5646 + if (data->detect_pin != GPIO_PIN_NONE)
5647 + at32_select_gpio(data->detect_pin, 0);
5648 + if (data->wp_pin != GPIO_PIN_NONE)
5649 + at32_select_gpio(data->wp_pin, 0);
5650 + }
5651 +
5652 atmel_mci0_pclk.dev = &pdev->dev;
5653
5654 platform_device_add(pdev);
5655 return pdev;
5656
5657 -err_add_resources:
5658 +fail:
5659 platform_device_put(pdev);
5660 return NULL;
5661 }
5662 @@ -1097,7 +1355,8 @@
5663
5664 struct platform_device *__init
5665 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
5666 - unsigned long fbmem_start, unsigned long fbmem_len)
5667 + unsigned long fbmem_start, unsigned long fbmem_len,
5668 + unsigned int pin_config)
5669 {
5670 struct platform_device *pdev;
5671 struct atmel_lcdfb_info *info;
5672 @@ -1124,37 +1383,77 @@
5673 switch (id) {
5674 case 0:
5675 pdev = &atmel_lcdfb0_device;
5676 - select_peripheral(PC(19), PERIPH_A, 0); /* CC */
5677 - select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
5678 - select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
5679 - select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
5680 - select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
5681 - select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
5682 - select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
5683 - select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
5684 - select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
5685 - select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
5686 - select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
5687 - select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
5688 - select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
5689 - select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
5690 - select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
5691 - select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
5692 - select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
5693 - select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
5694 - select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
5695 - select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
5696 - select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
5697 - select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
5698 - select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
5699 - select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
5700 - select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
5701 - select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
5702 - select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
5703 - select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
5704 - select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
5705 - select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
5706 - select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
5707 +
5708 + switch (pin_config) {
5709 + case 0:
5710 + select_peripheral(PC(19), PERIPH_A, 0); /* CC */
5711 + select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
5712 + select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
5713 + select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
5714 + select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
5715 + select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
5716 + select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
5717 + select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
5718 + select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
5719 + select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
5720 + select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
5721 + select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
5722 + select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
5723 + select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
5724 + select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
5725 + select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
5726 + select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
5727 + select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
5728 + select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
5729 + select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
5730 + select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
5731 + select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
5732 + select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
5733 + select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
5734 + select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
5735 + select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
5736 + select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
5737 + select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
5738 + select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
5739 + select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
5740 + select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
5741 + break;
5742 + case 1:
5743 + select_peripheral(PE(0), PERIPH_B, 0); /* CC */
5744 + select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
5745 + select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
5746 + select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
5747 + select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
5748 + select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
5749 + select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
5750 + select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
5751 + select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
5752 + select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
5753 + select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
5754 + select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
5755 + select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
5756 + select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
5757 + select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
5758 + select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
5759 + select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
5760 + select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
5761 + select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
5762 + select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
5763 + select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
5764 + select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
5765 + select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
5766 + select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
5767 + select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
5768 + select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
5769 + select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
5770 + select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
5771 + select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
5772 + select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
5773 + select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
5774 + break;
5775 + default:
5776 + goto err_invalid_id;
5777 + }
5778
5779 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
5780 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
5781 @@ -1351,9 +1650,39 @@
5782 .index = 6,
5783 };
5784
5785 +#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
5786 + [idx] = { \
5787 + .name = nam, \
5788 + .index = idx, \
5789 + .fifo_size = maxpkt, \
5790 + .nr_banks = maxbk, \
5791 + .can_dma = dma, \
5792 + .can_isoc = isoc, \
5793 + }
5794 +
5795 +static struct usba_ep_data at32_usba_ep[] __initdata = {
5796 + EP("ep0", 0, 64, 1, 0, 0),
5797 + EP("ep1", 1, 512, 2, 1, 1),
5798 + EP("ep2", 2, 512, 2, 1, 1),
5799 + EP("ep3-int", 3, 64, 3, 1, 0),
5800 + EP("ep4-int", 4, 64, 3, 1, 0),
5801 + EP("ep5", 5, 1024, 3, 1, 1),
5802 + EP("ep6", 6, 1024, 3, 1, 1),
5803 +};
5804 +
5805 +#undef EP
5806 +
5807 struct platform_device *__init
5808 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
5809 {
5810 + /*
5811 + * pdata doesn't have room for any endpoints, so we need to
5812 + * append room for the ones we need right after it.
5813 + */
5814 + struct {
5815 + struct usba_platform_data pdata;
5816 + struct usba_ep_data ep[7];
5817 + } usba_data;
5818 struct platform_device *pdev;
5819
5820 if (id != 0)
5821 @@ -1367,13 +1696,20 @@
5822 ARRAY_SIZE(usba0_resource)))
5823 goto out_free_pdev;
5824
5825 - if (data) {
5826 - if (platform_device_add_data(pdev, data, sizeof(*data)))
5827 - goto out_free_pdev;
5828 + if (data)
5829 + usba_data.pdata.vbus_pin = data->vbus_pin;
5830 + else
5831 + usba_data.pdata.vbus_pin = -EINVAL;
5832
5833 - if (data->vbus_pin != GPIO_PIN_NONE)
5834 - at32_select_gpio(data->vbus_pin, 0);
5835 - }
5836 + data = &usba_data.pdata;
5837 + data->num_ep = ARRAY_SIZE(at32_usba_ep);
5838 + memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
5839 +
5840 + if (platform_device_add_data(pdev, data, sizeof(usba_data)))
5841 + goto out_free_pdev;
5842 +
5843 + if (data->vbus_pin >= 0)
5844 + at32_select_gpio(data->vbus_pin, 0);
5845
5846 usba0_pclk.dev = &pdev->dev;
5847 usba0_hclk.dev = &pdev->dev;
5848 @@ -1526,6 +1862,58 @@
5849 #endif
5850
5851 /* --------------------------------------------------------------------
5852 + * NAND Flash / SmartMedia
5853 + * -------------------------------------------------------------------- */
5854 +static struct resource smc_cs3_resource[] __initdata = {
5855 + {
5856 + .start = 0x0c000000,
5857 + .end = 0x0fffffff,
5858 + .flags = IORESOURCE_MEM,
5859 + }, {
5860 + .start = 0xfff03c00,
5861 + .end = 0xfff03fff,
5862 + .flags = IORESOURCE_MEM,
5863 + },
5864 +};
5865 +
5866 +struct platform_device *__init
5867 +at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
5868 +{
5869 + struct platform_device *pdev;
5870 +
5871 + if (id != 0 || !data)
5872 + return NULL;
5873 +
5874 + pdev = platform_device_alloc("atmel_nand", id);
5875 + if (!pdev)
5876 + goto fail;
5877 +
5878 + if (platform_device_add_resources(pdev, smc_cs3_resource,
5879 + ARRAY_SIZE(smc_cs3_resource)))
5880 + goto fail;
5881 +
5882 + if (platform_device_add_data(pdev, data,
5883 + sizeof(struct atmel_nand_data)))
5884 + goto fail;
5885 +
5886 + set_ebi_sfr_bits(HMATRIX_BIT(CS3A));
5887 + if (data->enable_pin)
5888 + at32_select_gpio(data->enable_pin,
5889 + AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
5890 + if (data->rdy_pin)
5891 + at32_select_gpio(data->rdy_pin, 0);
5892 + if (data->det_pin)
5893 + at32_select_gpio(data->det_pin, 0);
5894 +
5895 + platform_device_add(pdev);
5896 + return pdev;
5897 +
5898 +fail:
5899 + platform_device_put(pdev);
5900 + return NULL;
5901 +}
5902 +
5903 +/* --------------------------------------------------------------------
5904 * AC97C
5905 * -------------------------------------------------------------------- */
5906 static struct resource atmel_ac97c0_resource[] __initdata = {
5907 @@ -1540,9 +1928,11 @@
5908 .index = 10,
5909 };
5910
5911 -struct platform_device *__init at32_add_device_ac97c(unsigned int id)
5912 +struct platform_device *__init
5913 +at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
5914 {
5915 struct platform_device *pdev;
5916 + struct ac97c_platform_data _data;
5917
5918 if (id != 0)
5919 return NULL;
5920 @@ -1553,19 +1943,37 @@
5921
5922 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
5923 ARRAY_SIZE(atmel_ac97c0_resource)))
5924 - goto err_add_resources;
5925 + goto fail;
5926
5927 - select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
5928 - select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
5929 - select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
5930 - select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
5931 + if (!data) {
5932 + data = &_data;
5933 + memset(data, 0, sizeof(struct ac97c_platform_data));
5934 + data->reset_pin = GPIO_PIN_NONE;
5935 + }
5936 +
5937 + data->dma_rx_periph_id = 3;
5938 + data->dma_tx_periph_id = 4;
5939 + data->dma_controller_id = 0;
5940 +
5941 + if (platform_device_add_data(pdev, data,
5942 + sizeof(struct ac97c_platform_data)))
5943 + goto fail;
5944 +
5945 + select_peripheral(PB(20), PERIPH_B, 0); /* SDO */
5946 + select_peripheral(PB(21), PERIPH_B, 0); /* SYNC */
5947 + select_peripheral(PB(22), PERIPH_B, 0); /* SCLK */
5948 + select_peripheral(PB(23), PERIPH_B, 0); /* SDI */
5949 +
5950 + /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
5951 + if (data->reset_pin != GPIO_PIN_NONE)
5952 + at32_select_gpio(data->reset_pin, 0);
5953
5954 atmel_ac97c0_pclk.dev = &pdev->dev;
5955
5956 platform_device_add(pdev);
5957 return pdev;
5958
5959 -err_add_resources:
5960 +fail:
5961 platform_device_put(pdev);
5962 return NULL;
5963 }
5964 @@ -1683,6 +2091,7 @@
5965 &hmatrix_clk,
5966 &ebi_clk,
5967 &hramc_clk,
5968 + &sdramc_clk,
5969 &smc0_pclk,
5970 &smc0_mck,
5971 &pdc_hclk,
5972 @@ -1694,7 +2103,10 @@
5973 &pio2_mck,
5974 &pio3_mck,
5975 &pio4_mck,
5976 - &at32_systc0_pclk,
5977 + &at32_tcb0_t0_clk,
5978 + &at32_tcb1_t0_clk,
5979 + &atmel_psif0_pclk,
5980 + &atmel_psif1_pclk,
5981 &atmel_usart0_usart,
5982 &atmel_usart1_usart,
5983 &atmel_usart2_usart,
5984 @@ -1730,16 +2142,7 @@
5985 };
5986 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
5987
5988 -void __init at32_portmux_init(void)
5989 -{
5990 - at32_init_pio(&pio0_device);
5991 - at32_init_pio(&pio1_device);
5992 - at32_init_pio(&pio2_device);
5993 - at32_init_pio(&pio3_device);
5994 - at32_init_pio(&pio4_device);
5995 -}
5996 -
5997 -void __init at32_clock_init(void)
5998 +void __init setup_platform(void)
5999 {
6000 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
6001 int i;
6002 @@ -1794,4 +2197,36 @@
6003 pm_writel(HSB_MASK, hsb_mask);
6004 pm_writel(PBA_MASK, pba_mask);
6005 pm_writel(PBB_MASK, pbb_mask);
6006 +
6007 + /* Initialize the port muxes */
6008 + at32_init_pio(&pio0_device);
6009 + at32_init_pio(&pio1_device);
6010 + at32_init_pio(&pio2_device);
6011 + at32_init_pio(&pio3_device);
6012 + at32_init_pio(&pio4_device);
6013 +}
6014 +
6015 +struct gen_pool *sram_pool;
6016 +
6017 +static int __init sram_init(void)
6018 +{
6019 + struct gen_pool *pool;
6020 +
6021 + /* 1KiB granularity */
6022 + pool = gen_pool_create(10, -1);
6023 + if (!pool)
6024 + goto fail;
6025 +
6026 + if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
6027 + goto err_pool_add;
6028 +
6029 + sram_pool = pool;
6030 + return 0;
6031 +
6032 +err_pool_add:
6033 + gen_pool_destroy(pool);
6034 +fail:
6035 + pr_err("Failed to create SRAM pool\n");
6036 + return -ENOMEM;
6037 }
6038 +core_initcall(sram_init);
6039 --- a/arch/avr32/mach-at32ap/cpufreq.c
6040 +++ b/arch/avr32/mach-at32ap/cpufreq.c
6041 @@ -108,5 +108,4 @@
6042 {
6043 return cpufreq_register_driver(&at32_driver);
6044 }
6045 -
6046 -arch_initcall(at32_cpufreq_init);
6047 +late_initcall(at32_cpufreq_init);
6048 --- /dev/null
6049 +++ b/arch/avr32/mach-at32ap/gpio-dev.c
6050 @@ -0,0 +1,573 @@
6051 +/*
6052 + * GPIO /dev and configfs interface
6053 + *
6054 + * Copyright (C) 2006-2007 Atmel Corporation
6055 + *
6056 + * This program is free software; you can redistribute it and/or modify
6057 + * it under the terms of the GNU General Public License version 2 as
6058 + * published by the Free Software Foundation.
6059 + */
6060 +#include <linux/kernel.h>
6061 +#include <linux/configfs.h>
6062 +#include <linux/cdev.h>
6063 +#include <linux/device.h>
6064 +#include <linux/fs.h>
6065 +#include <linux/interrupt.h>
6066 +#include <linux/module.h>
6067 +#include <linux/poll.h>
6068 +#include <linux/uaccess.h>
6069 +#include <linux/wait.h>
6070 +
6071 +#include <asm/gpio.h>
6072 +#include <asm/arch/portmux.h>
6073 +
6074 +#define GPIO_DEV_MAX 8
6075 +
6076 +static struct class *gpio_dev_class;
6077 +static dev_t gpio_devt;
6078 +
6079 +struct gpio_item {
6080 + spinlock_t lock;
6081 +
6082 + int enabled;
6083 + int initialized;
6084 + int port;
6085 + u32 pin_mask;
6086 + u32 oe_mask;
6087 +
6088 + /* Pin state last time we read it (for blocking reads) */
6089 + u32 pin_state;
6090 + int changed;
6091 +
6092 + wait_queue_head_t change_wq;
6093 + struct fasync_struct *async_queue;
6094 +
6095 + int id;
6096 + struct class_device *gpio_dev;
6097 + struct cdev char_dev;
6098 + struct config_item item;
6099 +};
6100 +
6101 +struct gpio_attribute {
6102 + struct configfs_attribute attr;
6103 + ssize_t (*show)(struct gpio_item *, char *);
6104 + ssize_t (*store)(struct gpio_item *, const char *, size_t);
6105 +};
6106 +
6107 +static irqreturn_t gpio_dev_interrupt(int irq, void *dev_id)
6108 +{
6109 + struct gpio_item *gpio = dev_id;
6110 + u32 old_state, new_state;
6111 +
6112 + old_state = gpio->pin_state;
6113 + new_state = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
6114 + gpio->pin_state = new_state;
6115 +
6116 + if (new_state != old_state) {
6117 + gpio->changed = 1;
6118 + wake_up_interruptible(&gpio->change_wq);
6119 +
6120 + if (gpio->async_queue)
6121 + kill_fasync(&gpio->async_queue, SIGIO, POLL_IN);
6122 + }
6123 +
6124 + return IRQ_HANDLED;
6125 +}
6126 +
6127 +static int gpio_dev_open(struct inode *inode, struct file *file)
6128 +{
6129 + struct gpio_item *gpio = container_of(inode->i_cdev,
6130 + struct gpio_item,
6131 + char_dev);
6132 + unsigned int irq;
6133 + unsigned int i;
6134 + int ret;
6135 +
6136 + nonseekable_open(inode, file);
6137 + config_item_get(&gpio->item);
6138 + file->private_data = gpio;
6139 +
6140 + gpio->pin_state = at32_gpio_get_value_multiple(gpio->port,
6141 + gpio->pin_mask);
6142 + gpio->changed = 1;
6143 +
6144 + for (i = 0; i < 32; i++) {
6145 + if (gpio->pin_mask & (1 << i)) {
6146 + irq = gpio_to_irq(32 * gpio->port + i);
6147 + ret = request_irq(irq, gpio_dev_interrupt, 0,
6148 + "gpio-dev", gpio);
6149 + if (ret)
6150 + goto err_irq;
6151 + }
6152 + }
6153 +
6154 + return 0;
6155 +
6156 +err_irq:
6157 + while (i--) {
6158 + if (gpio->pin_mask & (1 << i)) {
6159 + irq = gpio_to_irq(32 * gpio->port + i);
6160 + free_irq(irq, gpio);
6161 + }
6162 + }
6163 +
6164 + config_item_put(&gpio->item);
6165 +
6166 + return ret;
6167 +}
6168 +
6169 +static int gpio_dev_fasync(int fd, struct file *file, int mode)
6170 +{
6171 + struct gpio_item *gpio = file->private_data;
6172 +
6173 + return fasync_helper(fd, file, mode, &gpio->async_queue);
6174 +}
6175 +
6176 +static int gpio_dev_release(struct inode *inode, struct file *file)
6177 +{
6178 + struct gpio_item *gpio = file->private_data;
6179 + unsigned int irq;
6180 + unsigned int i;
6181 +
6182 + gpio_dev_fasync(-1, file, 0);
6183 +
6184 + for (i = 0; i < 32; i++) {
6185 + if (gpio->pin_mask & (1 << i)) {
6186 + irq = gpio_to_irq(32 * gpio->port + i);
6187 + free_irq(irq, gpio);
6188 + }
6189 + }
6190 +
6191 + config_item_put(&gpio->item);
6192 +
6193 + return 0;
6194 +}
6195 +
6196 +static unsigned int gpio_dev_poll(struct file *file, poll_table *wait)
6197 +{
6198 + struct gpio_item *gpio = file->private_data;
6199 + unsigned int mask = 0;
6200 +
6201 + poll_wait(file, &gpio->change_wq, wait);
6202 + if (gpio->changed)
6203 + mask |= POLLIN | POLLRDNORM;
6204 +
6205 + return mask;
6206 +}
6207 +
6208 +static ssize_t gpio_dev_read(struct file *file, char __user *buf,
6209 + size_t count, loff_t *offset)
6210 +{
6211 + struct gpio_item *gpio = file->private_data;
6212 + u32 value;
6213 +
6214 + spin_lock_irq(&gpio->lock);
6215 + while (!gpio->changed) {
6216 + spin_unlock_irq(&gpio->lock);
6217 +
6218 + if (file->f_flags & O_NONBLOCK)
6219 + return -EAGAIN;
6220 +
6221 + if (wait_event_interruptible(gpio->change_wq, gpio->changed))
6222 + return -ERESTARTSYS;
6223 +
6224 + spin_lock_irq(&gpio->lock);
6225 + }
6226 +
6227 + gpio->changed = 0;
6228 + value = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
6229 +
6230 + spin_unlock_irq(&gpio->lock);
6231 +
6232 + count = min(count, (size_t)4);
6233 + if (copy_to_user(buf, &value, count))
6234 + return -EFAULT;
6235 +
6236 + return count;
6237 +}
6238 +
6239 +static ssize_t gpio_dev_write(struct file *file, const char __user *buf,
6240 + size_t count, loff_t *offset)
6241 +{
6242 + struct gpio_item *gpio = file->private_data;
6243 + u32 value = 0;
6244 + u32 mask = ~0UL;
6245 +
6246 + count = min(count, (size_t)4);
6247 + if (copy_from_user(&value, buf, count))
6248 + return -EFAULT;
6249 +
6250 + /* Assuming big endian */
6251 + mask <<= (4 - count) * 8;
6252 + mask &= gpio->pin_mask;
6253 +
6254 + at32_gpio_set_value_multiple(gpio->port, value, mask);
6255 +
6256 + return count;
6257 +}
6258 +
6259 +static struct file_operations gpio_dev_fops = {
6260 + .owner = THIS_MODULE,
6261 + .llseek = no_llseek,
6262 + .open = gpio_dev_open,
6263 + .release = gpio_dev_release,
6264 + .fasync = gpio_dev_fasync,
6265 + .poll = gpio_dev_poll,
6266 + .read = gpio_dev_read,
6267 + .write = gpio_dev_write,
6268 +};
6269 +
6270 +static struct gpio_item *to_gpio_item(struct config_item *item)
6271 +{
6272 + return item ? container_of(item, struct gpio_item, item) : NULL;
6273 +}
6274 +
6275 +static ssize_t gpio_show_gpio_id(struct gpio_item *gpio, char *page)
6276 +{
6277 + return sprintf(page, "%d\n", gpio->port);
6278 +}
6279 +
6280 +static ssize_t gpio_store_gpio_id(struct gpio_item *gpio,
6281 + const char *page, size_t count)
6282 +{
6283 + unsigned long id;
6284 + char *p = (char *)page;
6285 + ssize_t ret = -EINVAL;
6286 +
6287 + id = simple_strtoul(p, &p, 0);
6288 + if (!p || (*p && (*p != '\n')))
6289 + return -EINVAL;
6290 +
6291 + /* Switching PIO is not allowed when live... */
6292 + spin_lock(&gpio->lock);
6293 + if (!gpio->enabled) {
6294 + ret = -ENXIO;
6295 + if (at32_gpio_port_is_valid(id)) {
6296 + gpio->port = id;
6297 + ret = count;
6298 + }
6299 + }
6300 + spin_unlock(&gpio->lock);
6301 +
6302 + return ret;
6303 +}
6304 +
6305 +static ssize_t gpio_show_pin_mask(struct gpio_item *gpio, char *page)
6306 +{
6307 + return sprintf(page, "0x%08x\n", gpio->pin_mask);
6308 +}
6309 +
6310 +static ssize_t gpio_store_pin_mask(struct gpio_item *gpio,
6311 + const char *page, size_t count)
6312 +{
6313 + u32 new_mask;
6314 + char *p = (char *)page;
6315 + ssize_t ret = -EINVAL;
6316 +
6317 + new_mask = simple_strtoul(p, &p, 0);
6318 + if (!p || (*p && (*p != '\n')))
6319 + return -EINVAL;
6320 +
6321 + /* Can't update the pin mask while live. */
6322 + spin_lock(&gpio->lock);
6323 + if (!gpio->enabled) {
6324 + gpio->oe_mask &= new_mask;
6325 + gpio->pin_mask = new_mask;
6326 + ret = count;
6327 + }
6328 + spin_unlock(&gpio->lock);
6329 +
6330 + return ret;
6331 +}
6332 +
6333 +static ssize_t gpio_show_oe_mask(struct gpio_item *gpio, char *page)
6334 +{
6335 + return sprintf(page, "0x%08x\n", gpio->oe_mask);
6336 +}
6337 +
6338 +static ssize_t gpio_store_oe_mask(struct gpio_item *gpio,
6339 + const char *page, size_t count)
6340 +{
6341 + u32 mask;
6342 + char *p = (char *)page;
6343 + ssize_t ret = -EINVAL;
6344 +
6345 + mask = simple_strtoul(p, &p, 0);
6346 + if (!p || (*p && (*p != '\n')))
6347 + return -EINVAL;
6348 +
6349 + spin_lock(&gpio->lock);
6350 + if (!gpio->enabled) {
6351 + gpio->oe_mask = mask & gpio->pin_mask;
6352 + ret = count;
6353 + }
6354 + spin_unlock(&gpio->lock);
6355 +
6356 + return ret;
6357 +}
6358 +
6359 +static ssize_t gpio_show_enabled(struct gpio_item *gpio, char *page)
6360 +{
6361 + return sprintf(page, "%d\n", gpio->enabled);
6362 +}
6363 +
6364 +static ssize_t gpio_store_enabled(struct gpio_item *gpio,
6365 + const char *page, size_t count)
6366 +{
6367 + char *p = (char *)page;
6368 + int enabled;
6369 + int ret;
6370 +
6371 + enabled = simple_strtoul(p, &p, 0);
6372 + if (!p || (*p && (*p != '\n')))
6373 + return -EINVAL;
6374 +
6375 + /* make it a boolean value */
6376 + enabled = !!enabled;
6377 +
6378 + if (gpio->enabled == enabled)
6379 + /* No change; do nothing. */
6380 + return count;
6381 +
6382 + BUG_ON(gpio->id >= GPIO_DEV_MAX);
6383 +
6384 + if (!enabled) {
6385 + class_device_unregister(gpio->gpio_dev);
6386 + cdev_del(&gpio->char_dev);
6387 + at32_deselect_pins(gpio->port, gpio->pin_mask);
6388 + gpio->initialized = 0;
6389 + } else {
6390 + if (gpio->port < 0 || !gpio->pin_mask)
6391 + return -ENODEV;
6392 + }
6393 +
6394 + /* Disallow any updates to gpio_id or pin_mask */
6395 + spin_lock(&gpio->lock);
6396 + gpio->enabled = enabled;
6397 + spin_unlock(&gpio->lock);
6398 +
6399 + if (!enabled)
6400 + return count;
6401 +
6402 + /* Now, try to allocate the pins */
6403 + ret = at32_select_gpio_pins(gpio->port, gpio->pin_mask, gpio->oe_mask);
6404 + if (ret)
6405 + goto err_alloc_pins;
6406 +
6407 + gpio->initialized = 1;
6408 +
6409 + cdev_init(&gpio->char_dev, &gpio_dev_fops);
6410 + gpio->char_dev.owner = THIS_MODULE;
6411 + ret = cdev_add(&gpio->char_dev, MKDEV(MAJOR(gpio_devt), gpio->id), 1);
6412 + if (ret < 0)
6413 + goto err_cdev_add;
6414 + gpio->gpio_dev = class_device_create(gpio_dev_class, NULL,
6415 + MKDEV(MAJOR(gpio_devt), gpio->id),
6416 + NULL,
6417 + "gpio%d", gpio->id);
6418 + if (IS_ERR(gpio->gpio_dev)) {
6419 + printk(KERN_ERR "failed to create gpio%d\n", gpio->id);
6420 + ret = PTR_ERR(gpio->gpio_dev);
6421 + goto err_class_dev;
6422 + }
6423 +
6424 + printk(KERN_INFO "created gpio%d (port%d/0x%08x) as (%d:%d)\n",
6425 + gpio->id, gpio->port, gpio->pin_mask,
6426 + MAJOR(gpio->gpio_dev->devt), MINOR(gpio->gpio_dev->devt));
6427 +
6428 + return 0;
6429 +
6430 +err_class_dev:
6431 + cdev_del(&gpio->char_dev);
6432 +err_cdev_add:
6433 + at32_deselect_pins(gpio->port, gpio->pin_mask);
6434 + gpio->initialized = 0;
6435 +err_alloc_pins:
6436 + spin_lock(&gpio->lock);
6437 + gpio->enabled = 0;
6438 + spin_unlock(&gpio->lock);
6439 +
6440 + return ret;
6441 +}
6442 +
6443 +static struct gpio_attribute gpio_item_attr_gpio_id = {
6444 + .attr = {
6445 + .ca_owner = THIS_MODULE,
6446 + .ca_name = "gpio_id",
6447 + .ca_mode = S_IRUGO | S_IWUSR,
6448 + },
6449 + .show = gpio_show_gpio_id,
6450 + .store = gpio_store_gpio_id,
6451 +};
6452 +static struct gpio_attribute gpio_item_attr_pin_mask = {
6453 + .attr = {
6454 + .ca_owner = THIS_MODULE,
6455 + .ca_name = "pin_mask",
6456 + .ca_mode = S_IRUGO | S_IWUSR,
6457 + },
6458 + .show = gpio_show_pin_mask,
6459 + .store = gpio_store_pin_mask,
6460 +};
6461 +static struct gpio_attribute gpio_item_attr_oe_mask = {
6462 + .attr = {
6463 + .ca_owner = THIS_MODULE,
6464 + .ca_name = "oe_mask",
6465 + .ca_mode = S_IRUGO | S_IWUSR,
6466 + },
6467 + .show = gpio_show_oe_mask,
6468 + .store = gpio_store_oe_mask,
6469 +};
6470 +static struct gpio_attribute gpio_item_attr_enabled = {
6471 + .attr = {
6472 + .ca_owner = THIS_MODULE,
6473 + .ca_name = "enabled",
6474 + .ca_mode = S_IRUGO | S_IWUSR,
6475 + },
6476 + .show = gpio_show_enabled,
6477 + .store = gpio_store_enabled,
6478 +};
6479 +
6480 +static struct configfs_attribute *gpio_item_attrs[] = {
6481 + &gpio_item_attr_gpio_id.attr,
6482 + &gpio_item_attr_pin_mask.attr,
6483 + &gpio_item_attr_oe_mask.attr,
6484 + &gpio_item_attr_enabled.attr,
6485 + NULL,
6486 +};
6487 +
6488 +static ssize_t gpio_show_attr(struct config_item *item,
6489 + struct configfs_attribute *attr,
6490 + char *page)
6491 +{
6492 + struct gpio_item *gpio_item = to_gpio_item(item);
6493 + struct gpio_attribute *gpio_attr
6494 + = container_of(attr, struct gpio_attribute, attr);
6495 + ssize_t ret = 0;
6496 +
6497 + if (gpio_attr->show)
6498 + ret = gpio_attr->show(gpio_item, page);
6499 + return ret;
6500 +}
6501 +
6502 +static ssize_t gpio_store_attr(struct config_item *item,
6503 + struct configfs_attribute *attr,
6504 + const char *page, size_t count)
6505 +{
6506 + struct gpio_item *gpio_item = to_gpio_item(item);
6507 + struct gpio_attribute *gpio_attr
6508 + = container_of(attr, struct gpio_attribute, attr);
6509 + ssize_t ret = -EINVAL;
6510 +
6511 + if (gpio_attr->store)
6512 + ret = gpio_attr->store(gpio_item, page, count);
6513 + return ret;
6514 +}
6515 +
6516 +static void gpio_release(struct config_item *item)
6517 +{
6518 + kfree(to_gpio_item(item));
6519 +}
6520 +
6521 +static struct configfs_item_operations gpio_item_ops = {
6522 + .release = gpio_release,
6523 + .show_attribute = gpio_show_attr,
6524 + .store_attribute = gpio_store_attr,
6525 +};
6526 +
6527 +static struct config_item_type gpio_item_type = {
6528 + .ct_item_ops = &gpio_item_ops,
6529 + .ct_attrs = gpio_item_attrs,
6530 + .ct_owner = THIS_MODULE,
6531 +};
6532 +
6533 +static struct config_item *gpio_make_item(struct config_group *group,
6534 + const char *name)
6535 +{
6536 + static int next_id;
6537 + struct gpio_item *gpio;
6538 +
6539 + if (next_id >= GPIO_DEV_MAX)
6540 + return NULL;
6541 +
6542 + gpio = kzalloc(sizeof(struct gpio_item), GFP_KERNEL);
6543 + if (!gpio)
6544 + return NULL;
6545 +
6546 + gpio->id = next_id++;
6547 + config_item_init_type_name(&gpio->item, name, &gpio_item_type);
6548 + spin_lock_init(&gpio->lock);
6549 + init_waitqueue_head(&gpio->change_wq);
6550 +
6551 + return &gpio->item;
6552 +}
6553 +
6554 +static void gpio_drop_item(struct config_group *group,
6555 + struct config_item *item)
6556 +{
6557 + struct gpio_item *gpio = to_gpio_item(item);
6558 +
6559 + spin_lock(&gpio->lock);
6560 + if (gpio->enabled) {
6561 + class_device_unregister(gpio->gpio_dev);
6562 + cdev_del(&gpio->char_dev);
6563 + }
6564 +
6565 + if (gpio->initialized) {
6566 + at32_deselect_pins(gpio->port, gpio->pin_mask);
6567 + gpio->initialized = 0;
6568 + gpio->enabled = 0;
6569 + }
6570 + spin_unlock(&gpio->lock);
6571 +}
6572 +
6573 +static struct configfs_group_operations gpio_group_ops = {
6574 + .make_item = gpio_make_item,
6575 + .drop_item = gpio_drop_item,
6576 +};
6577 +
6578 +static struct config_item_type gpio_group_type = {
6579 + .ct_group_ops = &gpio_group_ops,
6580 + .ct_owner = THIS_MODULE,
6581 +};
6582 +
6583 +static struct configfs_subsystem gpio_subsys = {
6584 + .su_group = {
6585 + .cg_item = {
6586 + .ci_namebuf = "gpio",
6587 + .ci_type = &gpio_group_type,
6588 + },
6589 + },
6590 +};
6591 +
6592 +static int __init gpio_dev_init(void)
6593 +{
6594 + int err;
6595 +
6596 + gpio_dev_class = class_create(THIS_MODULE, "gpio-dev");
6597 + if (IS_ERR(gpio_dev_class)) {
6598 + err = PTR_ERR(gpio_dev_class);
6599 + goto err_class_create;
6600 + }
6601 +
6602 + err = alloc_chrdev_region(&gpio_devt, 0, GPIO_DEV_MAX, "gpio");
6603 + if (err < 0)
6604 + goto err_alloc_chrdev;
6605 +
6606 + /* Configfs initialization */
6607 + config_group_init(&gpio_subsys.su_group);
6608 + mutex_init(&gpio_subsys.su_mutex);
6609 + err = configfs_register_subsystem(&gpio_subsys);
6610 + if (err)
6611 + goto err_register_subsys;
6612 +
6613 + return 0;
6614 +
6615 +err_register_subsys:
6616 + unregister_chrdev_region(gpio_devt, GPIO_DEV_MAX);
6617 +err_alloc_chrdev:
6618 + class_destroy(gpio_dev_class);
6619 +err_class_create:
6620 + printk(KERN_WARNING "Failed to initialize gpio /dev interface\n");
6621 + return err;
6622 +}
6623 +late_initcall(gpio_dev_init);
6624 --- a/arch/avr32/mach-at32ap/hsmc.c
6625 +++ b/arch/avr32/mach-at32ap/hsmc.c
6626 @@ -278,4 +278,4 @@
6627 {
6628 return platform_driver_register(&hsmc_driver);
6629 }
6630 -arch_initcall(hsmc_init);
6631 +core_initcall(hsmc_init);
6632 --- a/arch/avr32/mach-at32ap/intc.c
6633 +++ b/arch/avr32/mach-at32ap/intc.c
6634 @@ -1,5 +1,5 @@
6635 /*
6636 - * Copyright (C) 2006 Atmel Corporation
6637 + * Copyright (C) 2006, 2008 Atmel Corporation
6638 *
6639 * This program is free software; you can redistribute it and/or modify
6640 * it under the terms of the GNU General Public License version 2 as
6641 @@ -12,15 +12,20 @@
6642 #include <linux/interrupt.h>
6643 #include <linux/irq.h>
6644 #include <linux/platform_device.h>
6645 +#include <linux/sysdev.h>
6646
6647 -#include <asm/intc.h>
6648 #include <asm/io.h>
6649
6650 #include "intc.h"
6651
6652 struct intc {
6653 - void __iomem *regs;
6654 - struct irq_chip chip;
6655 + void __iomem *regs;
6656 + struct irq_chip chip;
6657 + struct sys_device sysdev;
6658 +#ifdef CONFIG_PM
6659 + unsigned long suspend_ipr;
6660 + unsigned long saved_ipr[64];
6661 +#endif
6662 };
6663
6664 extern struct platform_device at32_intc0_device;
6665 @@ -137,6 +142,74 @@
6666 panic("Interrupt controller initialization failed!\n");
6667 }
6668
6669 +#ifdef CONFIG_PM
6670 +void intc_set_suspend_handler(unsigned long offset)
6671 +{
6672 + intc0.suspend_ipr = offset;
6673 +}
6674 +
6675 +static int intc_suspend(struct sys_device *sdev, pm_message_t state)
6676 +{
6677 + struct intc *intc = container_of(sdev, struct intc, sysdev);
6678 + int i;
6679 +
6680 + if (unlikely(!irqs_disabled())) {
6681 + pr_err("intc_suspend: called with interrupts enabled\n");
6682 + return -EINVAL;
6683 + }
6684 +
6685 + if (unlikely(!intc->suspend_ipr)) {
6686 + pr_err("intc_suspend: suspend_ipr not initialized\n");
6687 + return -EINVAL;
6688 + }
6689 +
6690 + for (i = 0; i < 64; i++) {
6691 + intc->saved_ipr[i] = intc_readl(intc, INTPR0 + 4 * i);
6692 + intc_writel(intc, INTPR0 + 4 * i, intc->suspend_ipr);
6693 + }
6694 +
6695 + return 0;
6696 +}
6697 +
6698 +static int intc_resume(struct sys_device *sdev)
6699 +{
6700 + struct intc *intc = container_of(sdev, struct intc, sysdev);
6701 + int i;
6702 +
6703 + WARN_ON(!irqs_disabled());
6704 +
6705 + for (i = 0; i < 64; i++)
6706 + intc_writel(intc, INTPR0 + 4 * i, intc->saved_ipr[i]);
6707 +
6708 + return 0;
6709 +}
6710 +#else
6711 +#define intc_suspend NULL
6712 +#define intc_resume NULL
6713 +#endif
6714 +
6715 +static struct sysdev_class intc_class = {
6716 + .name = "intc",
6717 + .suspend = intc_suspend,
6718 + .resume = intc_resume,
6719 +};
6720 +
6721 +static int __init intc_init_sysdev(void)
6722 +{
6723 + int ret;
6724 +
6725 + ret = sysdev_class_register(&intc_class);
6726 + if (ret)
6727 + return ret;
6728 +
6729 + intc0.sysdev.id = 0;
6730 + intc0.sysdev.cls = &intc_class;
6731 + ret = sysdev_register(&intc0.sysdev);
6732 +
6733 + return ret;
6734 +}
6735 +device_initcall(intc_init_sysdev);
6736 +
6737 unsigned long intc_get_pending(unsigned int group)
6738 {
6739 return intc_readl(&intc0, INTREQ0 + 4 * group);
6740 --- /dev/null
6741 +++ b/arch/avr32/mach-at32ap/pdc.c
6742 @@ -0,0 +1,48 @@
6743 +/*
6744 + * Copyright (C) 2006 Atmel Corporation
6745 + *
6746 + * This program is free software; you can redistribute it and/or modify
6747 + * it under the terms of the GNU General Public License version 2 as
6748 + * published by the Free Software Foundation.
6749 + */
6750 +
6751 +#include <linux/clk.h>
6752 +#include <linux/err.h>
6753 +#include <linux/init.h>
6754 +#include <linux/platform_device.h>
6755 +
6756 +static int __init pdc_probe(struct platform_device *pdev)
6757 +{
6758 + struct clk *pclk, *hclk;
6759 +
6760 + pclk = clk_get(&pdev->dev, "pclk");
6761 + if (IS_ERR(pclk)) {
6762 + dev_err(&pdev->dev, "no pclk defined\n");
6763 + return PTR_ERR(pclk);
6764 + }
6765 + hclk = clk_get(&pdev->dev, "hclk");
6766 + if (IS_ERR(hclk)) {
6767 + dev_err(&pdev->dev, "no hclk defined\n");
6768 + clk_put(pclk);
6769 + return PTR_ERR(hclk);
6770 + }
6771 +
6772 + clk_enable(pclk);
6773 + clk_enable(hclk);
6774 +
6775 + dev_info(&pdev->dev, "Atmel Peripheral DMA Controller enabled\n");
6776 + return 0;
6777 +}
6778 +
6779 +static struct platform_driver pdc_driver = {
6780 + .probe = pdc_probe,
6781 + .driver = {
6782 + .name = "pdc",
6783 + },
6784 +};
6785 +
6786 +static int __init pdc_init(void)
6787 +{
6788 + return platform_driver_register(&pdc_driver);
6789 +}
6790 +arch_initcall(pdc_init);
6791 --- a/arch/avr32/mach-at32ap/pio.c
6792 +++ b/arch/avr32/mach-at32ap/pio.c
6793 @@ -157,6 +157,82 @@
6794 dump_stack();
6795 }
6796
6797 +#ifdef CONFIG_GPIO_DEV
6798 +
6799 +/* Gang allocators and accessors; used by the GPIO /dev driver */
6800 +int at32_gpio_port_is_valid(unsigned int port)
6801 +{
6802 + return port < MAX_NR_PIO_DEVICES && pio_dev[port].regs != NULL;
6803 +}
6804 +
6805 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask)
6806 +{
6807 + struct pio_device *pio;
6808 + u32 old, new;
6809 +
6810 + pio = &pio_dev[port];
6811 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs || (oe_mask & ~pins));
6812 +
6813 + /* Try to allocate the pins */
6814 + do {
6815 + old = pio->pinmux_mask;
6816 + if (old & pins)
6817 + return -EBUSY;
6818 +
6819 + new = old | pins;
6820 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
6821 +
6822 + /* That went well, now configure the port */
6823 + pio_writel(pio, OER, oe_mask);
6824 + pio_writel(pio, PER, pins);
6825 +
6826 + return 0;
6827 +}
6828 +
6829 +void at32_deselect_pins(unsigned int port, u32 pins)
6830 +{
6831 + struct pio_device *pio;
6832 + u32 old, new;
6833 +
6834 + pio = &pio_dev[port];
6835 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
6836 +
6837 + /* Return to a "safe" mux configuration */
6838 + pio_writel(pio, PUER, pins);
6839 + pio_writel(pio, ODR, pins);
6840 +
6841 + /* Deallocate the pins */
6842 + do {
6843 + old = pio->pinmux_mask;
6844 + new = old & ~pins;
6845 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
6846 +}
6847 +
6848 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins)
6849 +{
6850 + struct pio_device *pio;
6851 +
6852 + pio = &pio_dev[port];
6853 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
6854 +
6855 + return pio_readl(pio, PDSR) & pins;
6856 +}
6857 +
6858 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask)
6859 +{
6860 + struct pio_device *pio;
6861 +
6862 + pio = &pio_dev[port];
6863 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
6864 +
6865 + /* No atomic updates for now... */
6866 + pio_writel(pio, CODR, ~value & mask);
6867 + pio_writel(pio, SODR, value & mask);
6868 +}
6869 +
6870 +#endif /* CONFIG_GPIO_DEV */
6871 +
6872 +
6873 /*--------------------------------------------------------------------------*/
6874
6875 /* GPIO API */
6876 @@ -318,6 +394,8 @@
6877 const char *label;
6878
6879 label = gpiochip_is_requested(chip, i);
6880 + if (!label && (imr & mask))
6881 + label = "[irq]";
6882 if (!label)
6883 continue;
6884
6885 --- a/arch/avr32/mach-at32ap/pio.h
6886 +++ b/arch/avr32/mach-at32ap/pio.h
6887 @@ -57,7 +57,7 @@
6888
6889 /* Bitfields in IFDR */
6890
6891 -/* Bitfields in ISFR */
6892 +/* Bitfields in IFSR */
6893
6894 /* Bitfields in SODR */
6895
6896 --- /dev/null
6897 +++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
6898 @@ -0,0 +1,174 @@
6899 +/*
6900 + * Low-level Power Management code.
6901 + *
6902 + * Copyright (C) 2008 Atmel Corporation
6903 + *
6904 + * This program is free software; you can redistribute it and/or modify
6905 + * it under the terms of the GNU General Public License version 2 as
6906 + * published by the Free Software Foundation.
6907 + */
6908 +#include <asm/asm.h>
6909 +#include <asm/asm-offsets.h>
6910 +#include <asm/thread_info.h>
6911 +#include <asm/arch/pm.h>
6912 +
6913 +#include "pm.h"
6914 +#include "sdramc.h"
6915 +
6916 +/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
6917 +#define PM_BASE -0x100000
6918 +
6919 + .section .bss, "wa", @nobits
6920 + .global disable_idle_sleep
6921 + .type disable_idle_sleep, @object
6922 +disable_idle_sleep:
6923 + .int 4
6924 + .size disable_idle_sleep, . - disable_idle_sleep
6925 +
6926 + /* Keep this close to the irq handlers */
6927 + .section .irq.text, "ax", @progbits
6928 +
6929 + /*
6930 + * void cpu_enter_idle(void)
6931 + *
6932 + * Put the CPU into "idle" mode, in which it will consume
6933 + * significantly less power.
6934 + *
6935 + * If an interrupt comes along in the window between
6936 + * unmask_interrupts and the sleep instruction below, the
6937 + * interrupt code will adjust the return address so that we
6938 + * never execute the sleep instruction. This is required
6939 + * because the AP7000 doesn't unmask interrupts when entering
6940 + * sleep modes; later CPUs may not need this workaround.
6941 + */
6942 + .global cpu_enter_idle
6943 + .type cpu_enter_idle, @function
6944 +cpu_enter_idle:
6945 + mask_interrupts
6946 + get_thread_info r8
6947 + ld.w r9, r8[TI_flags]
6948 + bld r9, TIF_NEED_RESCHED
6949 + brcs .Lret_from_sleep
6950 + sbr r9, TIF_CPU_GOING_TO_SLEEP
6951 + st.w r8[TI_flags], r9
6952 + unmask_interrupts
6953 + sleep CPU_SLEEP_IDLE
6954 + .size cpu_idle_sleep, . - cpu_idle_sleep
6955 +
6956 + /*
6957 + * Common return path for PM functions that don't run from
6958 + * SRAM.
6959 + */
6960 + .global cpu_idle_skip_sleep
6961 + .type cpu_idle_skip_sleep, @function
6962 +cpu_idle_skip_sleep:
6963 + mask_interrupts
6964 + ld.w r9, r8[TI_flags]
6965 + cbr r9, TIF_CPU_GOING_TO_SLEEP
6966 + st.w r8[TI_flags], r9
6967 +.Lret_from_sleep:
6968 + unmask_interrupts
6969 + retal r12
6970 + .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
6971 +
6972 +#ifdef CONFIG_PM
6973 + .section .init.text, "ax", @progbits
6974 +
6975 + .global pm_exception
6976 + .type pm_exception, @function
6977 +pm_exception:
6978 + /*
6979 + * Exceptions are masked when we switch to this handler, so
6980 + * we'll only get "unrecoverable" exceptions (offset 0.)
6981 + */
6982 + sub r12, pc, . - .Lpanic_msg
6983 + lddpc pc, .Lpanic_addr
6984 +
6985 + .align 2
6986 +.Lpanic_addr:
6987 + .long panic
6988 +.Lpanic_msg:
6989 + .asciz "Unrecoverable exception during suspend\n"
6990 + .size pm_exception, . - pm_exception
6991 +
6992 + .global pm_irq0
6993 + .type pm_irq0, @function
6994 +pm_irq0:
6995 + /* Disable interrupts and return after the sleep instruction */
6996 + mfsr r9, SYSREG_RSR_INT0
6997 + mtsr SYSREG_RAR_INT0, r8
6998 + sbr r9, SYSREG_GM_OFFSET
6999 + mtsr SYSREG_RSR_INT0, r9
7000 + rete
7001 +
7002 + /*
7003 + * void cpu_enter_standby(unsigned long sdramc_base)
7004 + *
7005 + * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
7006 + * are suspended and interrupts are disabled. Interrupts
7007 + * marked as 'wakeup' event sources may still come along and
7008 + * get us out of here.
7009 + *
7010 + * The SDRAM will be put into self-refresh mode (which does
7011 + * not require a clock from the CPU), and the CPU will be put
7012 + * into "frozen" mode (HSB bus stopped). The SDRAM controller
7013 + * will automatically bring the SDRAM into normal mode on the
7014 + * first access, and the power manager will automatically
7015 + * start the HSB and CPU clocks upon a wakeup event.
7016 + *
7017 + * This code uses the same "skip sleep" technique as above.
7018 + * It is very important that we jump directly to
7019 + * cpu_after_sleep after the sleep instruction since that's
7020 + * where we'll end up if the interrupt handler decides that we
7021 + * need to skip the sleep instruction.
7022 + */
7023 + .global pm_standby
7024 + .type pm_standby, @function
7025 +pm_standby:
7026 + /*
7027 + * interrupts are already masked at this point, and EVBA
7028 + * points to pm_exception above.
7029 + */
7030 + ld.w r10, r12[SDRAMC_LPR]
7031 + sub r8, pc, . - 1f /* return address for irq handler */
7032 + mov r11, SDRAMC_LPR_LPCB_SELF_RFR
7033 + bfins r10, r11, 0, 2 /* LPCB <- self Refresh */
7034 + sync 0 /* flush write buffer */
7035 + st.w r12[SDRAMC_LPR], r11 /* put SDRAM in self-refresh mode */
7036 + ld.w r11, r12[SDRAMC_LPR]
7037 + unmask_interrupts
7038 + sleep CPU_SLEEP_FROZEN
7039 +1: mask_interrupts
7040 + retal r12
7041 + .size pm_standby, . - pm_standby
7042 +
7043 + .global pm_suspend_to_ram
7044 + .type pm_suspend_to_ram, @function
7045 +pm_suspend_to_ram:
7046 + /*
7047 + * interrupts are already masked at this point, and EVBA
7048 + * points to pm_exception above.
7049 + */
7050 + mov r11, 0
7051 + cache r11[2], 8 /* clean all dcache lines */
7052 + sync 0 /* flush write buffer */
7053 + ld.w r10, r12[SDRAMC_LPR]
7054 + sub r8, pc, . - 1f /* return address for irq handler */
7055 + mov r11, SDRAMC_LPR_LPCB_SELF_RFR
7056 + bfins r10, r11, 0, 2 /* LPCB <- self refresh */
7057 + st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
7058 + ld.w r11, r12[SDRAMC_LPR]
7059 +
7060 + unmask_interrupts
7061 + sleep CPU_SLEEP_STOP
7062 +1: mask_interrupts
7063 +
7064 + retal r12
7065 + .size pm_suspend_to_ram, . - pm_suspend_to_ram
7066 +
7067 + .global pm_sram_end
7068 + .type pm_sram_end, @function
7069 +pm_sram_end:
7070 + .size pm_sram_end, 0
7071 +
7072 +#endif /* CONFIG_PM */
7073 --- /dev/null
7074 +++ b/arch/avr32/mach-at32ap/pm.c
7075 @@ -0,0 +1,245 @@
7076 +/*
7077 + * AVR32 AP Power Management
7078 + *
7079 + * Copyright (C) 2008 Atmel Corporation
7080 + *
7081 + * This program is free software; you can redistribute it and/or
7082 + * modify it under the terms of the GNU General Public License
7083 + * version 2 as published by the Free Software Foundation.
7084 + */
7085 +#include <linux/io.h>
7086 +#include <linux/suspend.h>
7087 +#include <linux/vmalloc.h>
7088 +
7089 +#include <asm/cacheflush.h>
7090 +#include <asm/sysreg.h>
7091 +
7092 +#include <asm/arch/pm.h>
7093 +#include <asm/arch/sram.h>
7094 +
7095 +/* FIXME: This is only valid for AP7000 */
7096 +#define SDRAMC_BASE 0xfff03800
7097 +
7098 +#include "sdramc.h"
7099 +
7100 +#define SRAM_PAGE_FLAGS (SYSREG_BIT(TLBELO_D) | SYSREG_BF(SZ, 1) \
7101 + | SYSREG_BF(AP, 3) | SYSREG_BIT(G))
7102 +
7103 +
7104 +static unsigned long pm_sram_start;
7105 +static size_t pm_sram_size;
7106 +static struct vm_struct *pm_sram_area;
7107 +
7108 +static void (*avr32_pm_enter_standby)(unsigned long sdramc_base);
7109 +static void (*avr32_pm_enter_str)(unsigned long sdramc_base);
7110 +
7111 +/*
7112 + * Must be called with interrupts disabled. Exceptions will be masked
7113 + * on return (i.e. all exceptions will be "unrecoverable".)
7114 + */
7115 +static void *avr32_pm_map_sram(void)
7116 +{
7117 + unsigned long vaddr;
7118 + unsigned long page_addr;
7119 + u32 tlbehi;
7120 + u32 mmucr;
7121 +
7122 + vaddr = (unsigned long)pm_sram_area->addr;
7123 + page_addr = pm_sram_start & PAGE_MASK;
7124 +
7125 + /*
7126 + * Mask exceptions and grab the first TLB entry. We won't be
7127 + * needing it while sleeping.
7128 + */
7129 + asm volatile("ssrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
7130 +
7131 + mmucr = sysreg_read(MMUCR);
7132 + tlbehi = sysreg_read(TLBEHI);
7133 + sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
7134 +
7135 + tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
7136 + tlbehi |= vaddr & PAGE_MASK;
7137 + tlbehi |= SYSREG_BIT(TLBEHI_V);
7138 +
7139 + sysreg_write(TLBELO, page_addr | SRAM_PAGE_FLAGS);
7140 + sysreg_write(TLBEHI, tlbehi);
7141 + __builtin_tlbw();
7142 +
7143 + return (void *)(vaddr + pm_sram_start - page_addr);
7144 +}
7145 +
7146 +/*
7147 + * Must be called with interrupts disabled. Exceptions will be
7148 + * unmasked on return.
7149 + */
7150 +static void avr32_pm_unmap_sram(void)
7151 +{
7152 + u32 mmucr;
7153 + u32 tlbehi;
7154 + u32 tlbarlo;
7155 +
7156 + /* Going to update TLB entry at index 0 */
7157 + mmucr = sysreg_read(MMUCR);
7158 + tlbehi = sysreg_read(TLBEHI);
7159 + sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
7160 +
7161 + /* Clear the "valid" bit */
7162 + tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
7163 + sysreg_write(TLBEHI, tlbehi);
7164 +
7165 + /* Mark it as "not accessed" */
7166 + tlbarlo = sysreg_read(TLBARLO);
7167 + sysreg_write(TLBARLO, tlbarlo | 0x80000000U);
7168 +
7169 + /* Update the TLB */
7170 + __builtin_tlbw();
7171 +
7172 + /* Unmask exceptions */
7173 + asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
7174 +}
7175 +
7176 +static int avr32_pm_valid_state(suspend_state_t state)
7177 +{
7178 + switch (state) {
7179 + case PM_SUSPEND_ON:
7180 + case PM_SUSPEND_STANDBY:
7181 + case PM_SUSPEND_MEM:
7182 + return 1;
7183 +
7184 + default:
7185 + return 0;
7186 + }
7187 +}
7188 +
7189 +static int avr32_pm_enter(suspend_state_t state)
7190 +{
7191 + u32 lpr_saved;
7192 + u32 evba_saved;
7193 + void *sram;
7194 +
7195 + switch (state) {
7196 + case PM_SUSPEND_STANDBY:
7197 + sram = avr32_pm_map_sram();
7198 +
7199 + /* Switch to in-sram exception handlers */
7200 + evba_saved = sysreg_read(EVBA);
7201 + sysreg_write(EVBA, (unsigned long)sram);
7202 +
7203 + /*
7204 + * Save the LPR register so that we can re-enable
7205 + * SDRAM Low Power mode on resume.
7206 + */
7207 + lpr_saved = sdramc_readl(LPR);
7208 + pr_debug("%s: Entering standby...\n", __func__);
7209 + avr32_pm_enter_standby(SDRAMC_BASE);
7210 + sdramc_writel(LPR, lpr_saved);
7211 +
7212 + /* Switch back to regular exception handlers */
7213 + sysreg_write(EVBA, evba_saved);
7214 +
7215 + avr32_pm_unmap_sram();
7216 + break;
7217 +
7218 + case PM_SUSPEND_MEM:
7219 + sram = avr32_pm_map_sram();
7220 +
7221 + /* Switch to in-sram exception handlers */
7222 + evba_saved = sysreg_read(EVBA);
7223 + sysreg_write(EVBA, (unsigned long)sram);
7224 +
7225 + /*
7226 + * Save the LPR register so that we can re-enable
7227 + * SDRAM Low Power mode on resume.
7228 + */
7229 + lpr_saved = sdramc_readl(LPR);
7230 + pr_debug("%s: Entering suspend-to-ram...\n", __func__);
7231 + avr32_pm_enter_str(SDRAMC_BASE);
7232 + sdramc_writel(LPR, lpr_saved);
7233 +
7234 + /* Switch back to regular exception handlers */
7235 + sysreg_write(EVBA, evba_saved);
7236 +
7237 + avr32_pm_unmap_sram();
7238 + break;
7239 +
7240 + case PM_SUSPEND_ON:
7241 + pr_debug("%s: Entering idle...\n", __func__);
7242 + cpu_enter_idle();
7243 + break;
7244 +
7245 + default:
7246 + pr_debug("%s: Invalid suspend state %d\n", __func__, state);
7247 + goto out;
7248 + }
7249 +
7250 + pr_debug("%s: wakeup\n", __func__);
7251 +
7252 +out:
7253 + return 0;
7254 +}
7255 +
7256 +static struct platform_suspend_ops avr32_pm_ops = {
7257 + .valid = avr32_pm_valid_state,
7258 + .enter = avr32_pm_enter,
7259 +};
7260 +
7261 +static unsigned long avr32_pm_offset(void *symbol)
7262 +{
7263 + extern u8 pm_exception[];
7264 +
7265 + return (unsigned long)symbol - (unsigned long)pm_exception;
7266 +}
7267 +
7268 +static int __init avr32_pm_init(void)
7269 +{
7270 + extern u8 pm_exception[];
7271 + extern u8 pm_irq0[];
7272 + extern u8 pm_standby[];
7273 + extern u8 pm_suspend_to_ram[];
7274 + extern u8 pm_sram_end[];
7275 + void *dst;
7276 +
7277 + /*
7278 + * To keep things simple, we depend on not needing more than a
7279 + * single page.
7280 + */
7281 + pm_sram_size = avr32_pm_offset(pm_sram_end);
7282 + if (pm_sram_size > PAGE_SIZE)
7283 + goto err;
7284 +
7285 + pm_sram_start = sram_alloc(pm_sram_size);
7286 + if (!pm_sram_start)
7287 + goto err_alloc_sram;
7288 +
7289 + /* Grab a virtual area we can use later on. */
7290 + pm_sram_area = get_vm_area(pm_sram_size, VM_IOREMAP);
7291 + if (!pm_sram_area)
7292 + goto err_vm_area;
7293 + pm_sram_area->phys_addr = pm_sram_start;
7294 +
7295 + local_irq_disable();
7296 + dst = avr32_pm_map_sram();
7297 + memcpy(dst, pm_exception, pm_sram_size);
7298 + flush_dcache_region(dst, pm_sram_size);
7299 + invalidate_icache_region(dst, pm_sram_size);
7300 + avr32_pm_unmap_sram();
7301 + local_irq_enable();
7302 +
7303 + avr32_pm_enter_standby = dst + avr32_pm_offset(pm_standby);
7304 + avr32_pm_enter_str = dst + avr32_pm_offset(pm_suspend_to_ram);
7305 + intc_set_suspend_handler(avr32_pm_offset(pm_irq0));
7306 +
7307 + suspend_set_ops(&avr32_pm_ops);
7308 +
7309 + printk("AVR32 AP Power Management enabled\n");
7310 +
7311 + return 0;
7312 +
7313 +err_vm_area:
7314 + sram_free(pm_sram_start, pm_sram_size);
7315 +err_alloc_sram:
7316 +err:
7317 + pr_err("AVR32 Power Management initialization failed\n");
7318 + return -ENOMEM;
7319 +}
7320 +arch_initcall(avr32_pm_init);
7321 --- /dev/null
7322 +++ b/arch/avr32/mach-at32ap/sdramc.h
7323 @@ -0,0 +1,76 @@
7324 +/*
7325 + * Register definitions for the AT32AP SDRAM Controller
7326 + *
7327 + * Copyright (C) 2008 Atmel Corporation
7328 + *
7329 + * This program is free software; you can redistribute it and/or
7330 + * modify it under the terms of the GNU General Public License
7331 + * version 2 as published by the Free Software Foundation.
7332 + */
7333 +
7334 +/* Register offsets */
7335 +#define SDRAMC_MR 0x0000
7336 +#define SDRAMC_TR 0x0004
7337 +#define SDRAMC_CR 0x0008
7338 +#define SDRAMC_HSR 0x000c
7339 +#define SDRAMC_LPR 0x0010
7340 +#define SDRAMC_IER 0x0014
7341 +#define SDRAMC_IDR 0x0018
7342 +#define SDRAMC_IMR 0x001c
7343 +#define SDRAMC_ISR 0x0020
7344 +#define SDRAMC_MDR 0x0024
7345 +
7346 +/* MR - Mode Register */
7347 +#define SDRAMC_MR_MODE_NORMAL ( 0 << 0)
7348 +#define SDRAMC_MR_MODE_NOP ( 1 << 0)
7349 +#define SDRAMC_MR_MODE_BANKS_PRECHARGE ( 2 << 0)
7350 +#define SDRAMC_MR_MODE_LOAD_MODE ( 3 << 0)
7351 +#define SDRAMC_MR_MODE_AUTO_REFRESH ( 4 << 0)
7352 +#define SDRAMC_MR_MODE_EXT_LOAD_MODE ( 5 << 0)
7353 +#define SDRAMC_MR_MODE_POWER_DOWN ( 6 << 0)
7354 +
7355 +/* CR - Configuration Register */
7356 +#define SDRAMC_CR_NC_8_BITS ( 0 << 0)
7357 +#define SDRAMC_CR_NC_9_BITS ( 1 << 0)
7358 +#define SDRAMC_CR_NC_10_BITS ( 2 << 0)
7359 +#define SDRAMC_CR_NC_11_BITS ( 3 << 0)
7360 +#define SDRAMC_CR_NR_11_BITS ( 0 << 2)
7361 +#define SDRAMC_CR_NR_12_BITS ( 1 << 2)
7362 +#define SDRAMC_CR_NR_13_BITS ( 2 << 2)
7363 +#define SDRAMC_CR_NB_2_BANKS ( 0 << 4)
7364 +#define SDRAMC_CR_NB_4_BANKS ( 1 << 4)
7365 +#define SDRAMC_CR_CAS(x) ((x) << 5)
7366 +#define SDRAMC_CR_DBW_32_BITS ( 0 << 7)
7367 +#define SDRAMC_CR_DBW_16_BITS ( 1 << 7)
7368 +#define SDRAMC_CR_TWR(x) ((x) << 8)
7369 +#define SDRAMC_CR_TRC(x) ((x) << 12)
7370 +#define SDRAMC_CR_TRP(x) ((x) << 16)
7371 +#define SDRAMC_CR_TRCD(x) ((x) << 20)
7372 +#define SDRAMC_CR_TRAS(x) ((x) << 24)
7373 +#define SDRAMC_CR_TXSR(x) ((x) << 28)
7374 +
7375 +/* HSR - High Speed Register */
7376 +#define SDRAMC_HSR_DA ( 1 << 0)
7377 +
7378 +/* LPR - Low Power Register */
7379 +#define SDRAMC_LPR_LPCB_INHIBIT ( 0 << 0)
7380 +#define SDRAMC_LPR_LPCB_SELF_RFR ( 1 << 0)
7381 +#define SDRAMC_LPR_LPCB_PDOWN ( 2 << 0)
7382 +#define SDRAMC_LPR_LPCB_DEEP_PDOWN ( 3 << 0)
7383 +#define SDRAMC_LPR_PASR(x) ((x) << 4)
7384 +#define SDRAMC_LPR_TCSR(x) ((x) << 8)
7385 +#define SDRAMC_LPR_DS(x) ((x) << 10)
7386 +#define SDRAMC_LPR_TIMEOUT(x) ((x) << 12)
7387 +
7388 +/* IER/IDR/IMR/ISR - Interrupt Enable/Disable/Mask/Status Register */
7389 +#define SDRAMC_ISR_RES ( 1 << 0)
7390 +
7391 +/* MDR - Memory Device Register */
7392 +#define SDRAMC_MDR_MD_SDRAM ( 0 << 0)
7393 +#define SDRAMC_MDR_MD_LOW_PWR_SDRAM ( 1 << 0)
7394 +
7395 +/* Register access macros */
7396 +#define sdramc_readl(reg) \
7397 + __raw_readl((void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
7398 +#define sdramc_writel(reg, value) \
7399 + __raw_writel(value, (void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
7400 --- a/arch/avr32/mach-at32ap/time-tc.c
7401 +++ /dev/null
7402 @@ -1,218 +0,0 @@
7403 -/*
7404 - * Copyright (C) 2004-2007 Atmel Corporation
7405 - *
7406 - * Based on MIPS implementation arch/mips/kernel/time.c
7407 - * Copyright 2001 MontaVista Software Inc.
7408 - *
7409 - * This program is free software; you can redistribute it and/or modify
7410 - * it under the terms of the GNU General Public License version 2 as
7411 - * published by the Free Software Foundation.
7412 - */
7413 -
7414 -#include <linux/clk.h>
7415 -#include <linux/clocksource.h>
7416 -#include <linux/time.h>
7417 -#include <linux/module.h>
7418 -#include <linux/interrupt.h>
7419 -#include <linux/irq.h>
7420 -#include <linux/kernel_stat.h>
7421 -#include <linux/errno.h>
7422 -#include <linux/init.h>
7423 -#include <linux/profile.h>
7424 -#include <linux/sysdev.h>
7425 -#include <linux/err.h>
7426 -
7427 -#include <asm/div64.h>
7428 -#include <asm/sysreg.h>
7429 -#include <asm/io.h>
7430 -#include <asm/sections.h>
7431 -
7432 -#include <asm/arch/time.h>
7433 -
7434 -/* how many counter cycles in a jiffy? */
7435 -static u32 cycles_per_jiffy;
7436 -
7437 -/* the count value for the next timer interrupt */
7438 -static u32 expirelo;
7439 -
7440 -/* the I/O registers of the TC module */
7441 -static void __iomem *ioregs;
7442 -
7443 -cycle_t read_cycle_count(void)
7444 -{
7445 - return (cycle_t)timer_read(ioregs, 0, CV);
7446 -}
7447 -
7448 -struct clocksource clocksource_avr32 = {
7449 - .name = "avr32",
7450 - .rating = 342,
7451 - .read = read_cycle_count,
7452 - .mask = CLOCKSOURCE_MASK(16),
7453 - .shift = 16,
7454 - .flags = CLOCK_SOURCE_IS_CONTINUOUS,
7455 -};
7456 -
7457 -static void avr32_timer_ack(void)
7458 -{
7459 - u16 count = expirelo;
7460 -
7461 - /* Ack this timer interrupt and set the next one, use a u16
7462 - * variable so it will wrap around correctly */
7463 - count += cycles_per_jiffy;
7464 - expirelo = count;
7465 - timer_write(ioregs, 0, RC, expirelo);
7466 -
7467 - /* Check to see if we have missed any timer interrupts */
7468 - count = timer_read(ioregs, 0, CV);
7469 - if ((count - expirelo) < 0x7fff) {
7470 - expirelo = count + cycles_per_jiffy;
7471 - timer_write(ioregs, 0, RC, expirelo);
7472 - }
7473 -}
7474 -
7475 -u32 avr32_hpt_read(void)
7476 -{
7477 - return timer_read(ioregs, 0, CV);
7478 -}
7479 -
7480 -static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk)
7481 -{
7482 - unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2;
7483 - unsigned int divs[] = { 4, 8, 16, 32 };
7484 - int divs_size = ARRAY_SIZE(divs);
7485 - int i = 0;
7486 - unsigned long count_hz;
7487 - unsigned long shift;
7488 - unsigned long mult;
7489 - int clock_div = -1;
7490 - u64 tmp;
7491 -
7492 - shift = clocksource_avr32.shift;
7493 -
7494 - do {
7495 - count_hz = clk_get_rate(pclk) / divs[i];
7496 - mult = clocksource_hz2mult(count_hz, shift);
7497 - clocksource_avr32.mult = mult;
7498 -
7499 - tmp = TICK_NSEC;
7500 - tmp <<= shift;
7501 - tmp += mult / 2;
7502 - do_div(tmp, mult);
7503 -
7504 - cycles_per_jiffy = tmp;
7505 - } while (cycles_per_jiffy > cycles_max && ++i < divs_size);
7506 -
7507 - clock_div = i + 1;
7508 -
7509 - if (clock_div > divs_size) {
7510 - pr_debug("timer: could not calculate clock divider\n");
7511 - return -EFAULT;
7512 - }
7513 -
7514 - /* Set the clock divider */
7515 - timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div));
7516 -
7517 - return 0;
7518 -}
7519 -
7520 -int avr32_hpt_init(unsigned int count)
7521 -{
7522 - struct resource *regs;
7523 - struct clk *pclk;
7524 - int irq = -1;
7525 - int ret = 0;
7526 -
7527 - ret = -ENXIO;
7528 -
7529 - irq = platform_get_irq(&at32_systc0_device, 0);
7530 - if (irq < 0) {
7531 - pr_debug("timer: could not get irq\n");
7532 - goto out_error;
7533 - }
7534 -
7535 - pclk = clk_get(&at32_systc0_device.dev, "pclk");
7536 - if (IS_ERR(pclk)) {
7537 - pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk));
7538 - goto out_error;
7539 - }
7540 - clk_enable(pclk);
7541 -
7542 - regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0);
7543 - if (!regs) {
7544 - pr_debug("timer: could not get resource\n");
7545 - goto out_error_clk;
7546 - }
7547 -
7548 - ioregs = ioremap(regs->start, regs->end - regs->start + 1);
7549 - if (!ioregs) {
7550 - pr_debug("timer: could not get ioregs\n");
7551 - goto out_error_clk;
7552 - }
7553 -
7554 - ret = avr32_timer_calc_div_and_set_jiffies(pclk);
7555 - if (ret)
7556 - goto out_error_io;
7557 -
7558 - ret = setup_irq(irq, &timer_irqaction);
7559 - if (ret) {
7560 - pr_debug("timer: could not request irq %d: %d\n",
7561 - irq, ret);
7562 - goto out_error_io;
7563 - }
7564 -
7565 - expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1)
7566 - * cycles_per_jiffy;
7567 -
7568 - /* Enable clock and interrupts on RC compare */
7569 - timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN));
7570 - timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS));
7571 - /* Set cycles to first interrupt */
7572 - timer_write(ioregs, 0, RC, expirelo);
7573 -
7574 - printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n",
7575 - ioregs, irq);
7576 -
7577 - return 0;
7578 -
7579 -out_error_io:
7580 - iounmap(ioregs);
7581 -out_error_clk:
7582 - clk_put(pclk);
7583 -out_error:
7584 - return ret;
7585 -}
7586 -
7587 -int avr32_hpt_start(void)
7588 -{
7589 - timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG));
7590 - return 0;
7591 -}
7592 -
7593 -irqreturn_t timer_interrupt(int irq, void *dev_id)
7594 -{
7595 - unsigned int sr = timer_read(ioregs, 0, SR);
7596 -
7597 - if (sr & TIMER_BIT(SR_CPCS)) {
7598 - /* ack timer interrupt and try to set next interrupt */
7599 - avr32_timer_ack();
7600 -
7601 - /*
7602 - * Call the generic timer interrupt handler
7603 - */
7604 - write_seqlock(&xtime_lock);
7605 - do_timer(1);
7606 - write_sequnlock(&xtime_lock);
7607 -
7608 - /*
7609 - * In UP mode, we call local_timer_interrupt() to do profiling
7610 - * and process accounting.
7611 - *
7612 - * SMP is not supported yet.
7613 - */
7614 - local_timer_interrupt(irq, dev_id);
7615 -
7616 - return IRQ_HANDLED;
7617 - }
7618 -
7619 - return IRQ_NONE;
7620 -}
7621 --- a/arch/avr32/mm/init.c
7622 +++ b/arch/avr32/mm/init.c
7623 @@ -11,6 +11,7 @@
7624 #include <linux/swap.h>
7625 #include <linux/init.h>
7626 #include <linux/mmzone.h>
7627 +#include <linux/module.h>
7628 #include <linux/bootmem.h>
7629 #include <linux/pagemap.h>
7630 #include <linux/nodemask.h>
7631 @@ -23,20 +24,20 @@
7632 #include <asm/setup.h>
7633 #include <asm/sections.h>
7634
7635 +#define __page_aligned __attribute__((section(".data.page_aligned")))
7636 +
7637 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
7638
7639 -pgd_t swapper_pg_dir[PTRS_PER_PGD];
7640 +pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned;
7641
7642 struct page *empty_zero_page;
7643 +EXPORT_SYMBOL(empty_zero_page);
7644
7645 /*
7646 * Cache of MMU context last used.
7647 */
7648 unsigned long mmu_context_cache = NO_CONTEXT;
7649
7650 -#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
7651 -#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
7652 -
7653 void show_mem(void)
7654 {
7655 int total = 0, reserved = 0, cached = 0;
7656 @@ -109,19 +110,9 @@
7657 zero_page = alloc_bootmem_low_pages_node(NODE_DATA(0),
7658 PAGE_SIZE);
7659
7660 - {
7661 - pgd_t *pg_dir;
7662 - int i;
7663 -
7664 - pg_dir = swapper_pg_dir;
7665 - sysreg_write(PTBR, (unsigned long)pg_dir);
7666 -
7667 - for (i = 0; i < PTRS_PER_PGD; i++)
7668 - pgd_val(pg_dir[i]) = 0;
7669 -
7670 - enable_mmu();
7671 - printk ("CPU: Paging enabled\n");
7672 - }
7673 + sysreg_write(PTBR, (unsigned long)swapper_pg_dir);
7674 + enable_mmu();
7675 + printk ("CPU: Paging enabled\n");
7676
7677 for_each_online_node(nid) {
7678 pg_data_t *pgdat = NODE_DATA(nid);
7679 --- a/arch/avr32/mm/tlb.c
7680 +++ b/arch/avr32/mm/tlb.c
7681 @@ -11,21 +11,21 @@
7682
7683 #include <asm/mmu_context.h>
7684
7685 -#define _TLBEHI_I 0x100
7686 +/* TODO: Get the correct number from the CONFIG1 system register */
7687 +#define NR_TLB_ENTRIES 32
7688
7689 -void show_dtlb_entry(unsigned int index)
7690 +static void show_dtlb_entry(unsigned int index)
7691 {
7692 - unsigned int tlbehi, tlbehi_save, tlbelo, mmucr, mmucr_save;
7693 + u32 tlbehi, tlbehi_save, tlbelo, mmucr, mmucr_save;
7694 unsigned long flags;
7695
7696 local_irq_save(flags);
7697 mmucr_save = sysreg_read(MMUCR);
7698 tlbehi_save = sysreg_read(TLBEHI);
7699 - mmucr = mmucr_save & 0x13;
7700 - mmucr |= index << 14;
7701 + mmucr = SYSREG_BFINS(DRP, index, mmucr_save);
7702 sysreg_write(MMUCR, mmucr);
7703
7704 - asm volatile("tlbr" : : : "memory");
7705 + __builtin_tlbr();
7706 cpu_sync_pipeline();
7707
7708 tlbehi = sysreg_read(TLBEHI);
7709 @@ -33,15 +33,17 @@
7710
7711 printk("%2u: %c %c %02x %05x %05x %o %o %c %c %c %c\n",
7712 index,
7713 - (tlbehi & 0x200)?'1':'0',
7714 - (tlbelo & 0x100)?'1':'0',
7715 - (tlbehi & 0xff),
7716 - (tlbehi >> 12), (tlbelo >> 12),
7717 - (tlbelo >> 4) & 7, (tlbelo >> 2) & 3,
7718 - (tlbelo & 0x200)?'1':'0',
7719 - (tlbelo & 0x080)?'1':'0',
7720 - (tlbelo & 0x001)?'1':'0',
7721 - (tlbelo & 0x002)?'1':'0');
7722 + SYSREG_BFEXT(TLBEHI_V, tlbehi) ? '1' : '0',
7723 + SYSREG_BFEXT(G, tlbelo) ? '1' : '0',
7724 + SYSREG_BFEXT(ASID, tlbehi),
7725 + SYSREG_BFEXT(VPN, tlbehi) >> 2,
7726 + SYSREG_BFEXT(PFN, tlbelo) >> 2,
7727 + SYSREG_BFEXT(AP, tlbelo),
7728 + SYSREG_BFEXT(SZ, tlbelo),
7729 + SYSREG_BFEXT(TLBELO_C, tlbelo) ? 'C' : ' ',
7730 + SYSREG_BFEXT(B, tlbelo) ? 'B' : ' ',
7731 + SYSREG_BFEXT(W, tlbelo) ? 'W' : ' ',
7732 + SYSREG_BFEXT(TLBELO_D, tlbelo) ? 'D' : ' ');
7733
7734 sysreg_write(MMUCR, mmucr_save);
7735 sysreg_write(TLBEHI, tlbehi_save);
7736 @@ -54,29 +56,33 @@
7737 unsigned int i;
7738
7739 printk("ID V G ASID VPN PFN AP SZ C B W D\n");
7740 - for (i = 0; i < 32; i++)
7741 + for (i = 0; i < NR_TLB_ENTRIES; i++)
7742 show_dtlb_entry(i);
7743 }
7744
7745 -static unsigned long last_mmucr;
7746 -
7747 -static inline void set_replacement_pointer(unsigned shift)
7748 +static void update_dtlb(unsigned long address, pte_t pte)
7749 {
7750 - unsigned long mmucr, mmucr_save;
7751 + u32 tlbehi;
7752 + u32 mmucr;
7753
7754 - mmucr = mmucr_save = sysreg_read(MMUCR);
7755 + /*
7756 + * We're not changing the ASID here, so no need to flush the
7757 + * pipeline.
7758 + */
7759 + tlbehi = sysreg_read(TLBEHI);
7760 + tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
7761 + tlbehi |= address & MMU_VPN_MASK;
7762 + tlbehi |= SYSREG_BIT(TLBEHI_V);
7763 + sysreg_write(TLBEHI, tlbehi);
7764
7765 /* Does this mapping already exist? */
7766 - __asm__ __volatile__(
7767 - " tlbs\n"
7768 - " mfsr %0, %1"
7769 - : "=r"(mmucr)
7770 - : "i"(SYSREG_MMUCR));
7771 + __builtin_tlbs();
7772 + mmucr = sysreg_read(MMUCR);
7773
7774 if (mmucr & SYSREG_BIT(MMUCR_N)) {
7775 /* Not found -- pick a not-recently-accessed entry */
7776 - unsigned long rp;
7777 - unsigned long tlbar = sysreg_read(TLBARLO);
7778 + unsigned int rp;
7779 + u32 tlbar = sysreg_read(TLBARLO);
7780
7781 rp = 32 - fls(tlbar);
7782 if (rp == 32) {
7783 @@ -84,30 +90,14 @@
7784 sysreg_write(TLBARLO, -1L);
7785 }
7786
7787 - mmucr &= 0x13;
7788 - mmucr |= (rp << shift);
7789 -
7790 + mmucr = SYSREG_BFINS(DRP, rp, mmucr);
7791 sysreg_write(MMUCR, mmucr);
7792 }
7793
7794 - last_mmucr = mmucr;
7795 -}
7796 -
7797 -static void update_dtlb(unsigned long address, pte_t pte, unsigned long asid)
7798 -{
7799 - unsigned long vpn;
7800 -
7801 - vpn = (address & MMU_VPN_MASK) | _TLBEHI_VALID | asid;
7802 - sysreg_write(TLBEHI, vpn);
7803 - cpu_sync_pipeline();
7804 -
7805 - set_replacement_pointer(14);
7806 -
7807 sysreg_write(TLBELO, pte_val(pte) & _PAGE_FLAGS_HARDWARE_MASK);
7808
7809 /* Let's go */
7810 - asm volatile("nop\n\ttlbw" : : : "memory");
7811 - cpu_sync_pipeline();
7812 + __builtin_tlbw();
7813 }
7814
7815 void update_mmu_cache(struct vm_area_struct *vma,
7816 @@ -120,39 +110,40 @@
7817 return;
7818
7819 local_irq_save(flags);
7820 - update_dtlb(address, pte, get_asid());
7821 + update_dtlb(address, pte);
7822 local_irq_restore(flags);
7823 }
7824
7825 -void __flush_tlb_page(unsigned long asid, unsigned long page)
7826 +static void __flush_tlb_page(unsigned long asid, unsigned long page)
7827 {
7828 - unsigned long mmucr, tlbehi;
7829 + u32 mmucr, tlbehi;
7830
7831 - page |= asid;
7832 - sysreg_write(TLBEHI, page);
7833 - cpu_sync_pipeline();
7834 - asm volatile("tlbs");
7835 + /*
7836 + * Caller is responsible for masking out non-PFN bits in page
7837 + * and changing the current ASID if necessary. This means that
7838 + * we don't need to flush the pipeline after writing TLBEHI.
7839 + */
7840 + tlbehi = page | asid;
7841 + sysreg_write(TLBEHI, tlbehi);
7842 +
7843 + __builtin_tlbs();
7844 mmucr = sysreg_read(MMUCR);
7845
7846 if (!(mmucr & SYSREG_BIT(MMUCR_N))) {
7847 - unsigned long tlbarlo;
7848 - unsigned long entry;
7849 + unsigned int entry;
7850 + u32 tlbarlo;
7851
7852 /* Clear the "valid" bit */
7853 - tlbehi = sysreg_read(TLBEHI);
7854 - tlbehi &= ~_TLBEHI_VALID;
7855 sysreg_write(TLBEHI, tlbehi);
7856 - cpu_sync_pipeline();
7857
7858 /* mark the entry as "not accessed" */
7859 - entry = (mmucr >> 14) & 0x3f;
7860 + entry = SYSREG_BFEXT(DRP, mmucr);
7861 tlbarlo = sysreg_read(TLBARLO);
7862 - tlbarlo |= (0x80000000 >> entry);
7863 + tlbarlo |= (0x80000000UL >> entry);
7864 sysreg_write(TLBARLO, tlbarlo);
7865
7866 /* update the entry with valid bit clear */
7867 - asm volatile("tlbw");
7868 - cpu_sync_pipeline();
7869 + __builtin_tlbw();
7870 }
7871 }
7872
7873 @@ -190,17 +181,22 @@
7874
7875 local_irq_save(flags);
7876 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
7877 +
7878 if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
7879 mm->context = NO_CONTEXT;
7880 if (mm == current->mm)
7881 activate_context(mm);
7882 } else {
7883 - unsigned long asid = mm->context & MMU_CONTEXT_ASID_MASK;
7884 - unsigned long saved_asid = MMU_NO_ASID;
7885 + unsigned long asid;
7886 + unsigned long saved_asid;
7887 +
7888 + asid = mm->context & MMU_CONTEXT_ASID_MASK;
7889 + saved_asid = MMU_NO_ASID;
7890
7891 start &= PAGE_MASK;
7892 end += (PAGE_SIZE - 1);
7893 end &= PAGE_MASK;
7894 +
7895 if (mm != current->mm) {
7896 saved_asid = get_asid();
7897 set_asid(asid);
7898 @@ -218,33 +214,34 @@
7899 }
7900
7901 /*
7902 - * TODO: If this is only called for addresses > TASK_SIZE, we can probably
7903 - * skip the ASID stuff and just use the Global bit...
7904 + * This function depends on the pages to be flushed having the G
7905 + * (global) bit set in their pte. This is true for all
7906 + * PAGE_KERNEL(_RO) pages.
7907 */
7908 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
7909 {
7910 unsigned long flags;
7911 int size;
7912
7913 - local_irq_save(flags);
7914 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
7915 if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
7916 flush_tlb_all();
7917 } else {
7918 - unsigned long asid = init_mm.context & MMU_CONTEXT_ASID_MASK;
7919 - unsigned long saved_asid = get_asid();
7920 + unsigned long asid;
7921 +
7922 + local_irq_save(flags);
7923 + asid = get_asid();
7924
7925 start &= PAGE_MASK;
7926 end += (PAGE_SIZE - 1);
7927 end &= PAGE_MASK;
7928 - set_asid(asid);
7929 +
7930 while (start < end) {
7931 __flush_tlb_page(asid, start);
7932 start += PAGE_SIZE;
7933 }
7934 - set_asid(saved_asid);
7935 + local_irq_restore(flags);
7936 }
7937 - local_irq_restore(flags);
7938 }
7939
7940 void flush_tlb_mm(struct mm_struct *mm)
7941 @@ -280,7 +277,7 @@
7942 {
7943 static unsigned long tlb_index;
7944
7945 - if (*pos >= 32)
7946 + if (*pos >= NR_TLB_ENTRIES)
7947 return NULL;
7948
7949 tlb_index = 0;
7950 @@ -291,7 +288,7 @@
7951 {
7952 unsigned long *index = v;
7953
7954 - if (*index >= 31)
7955 + if (*index >= NR_TLB_ENTRIES - 1)
7956 return NULL;
7957
7958 ++*pos;
7959 @@ -313,16 +310,16 @@
7960 if (*index == 0)
7961 seq_puts(tlb, "ID V G ASID VPN PFN AP SZ C B W D\n");
7962
7963 - BUG_ON(*index >= 32);
7964 + BUG_ON(*index >= NR_TLB_ENTRIES);
7965
7966 local_irq_save(flags);
7967 mmucr_save = sysreg_read(MMUCR);
7968 tlbehi_save = sysreg_read(TLBEHI);
7969 - mmucr = mmucr_save & 0x13;
7970 - mmucr |= *index << 14;
7971 + mmucr = SYSREG_BFINS(DRP, *index, mmucr_save);
7972 sysreg_write(MMUCR, mmucr);
7973
7974 - asm volatile("tlbr" : : : "memory");
7975 + /* TLBR might change the ASID */
7976 + __builtin_tlbr();
7977 cpu_sync_pipeline();
7978
7979 tlbehi = sysreg_read(TLBEHI);
7980 @@ -334,16 +331,18 @@
7981 local_irq_restore(flags);
7982
7983 seq_printf(tlb, "%2lu: %c %c %02x %05x %05x %o %o %c %c %c %c\n",
7984 - *index,
7985 - (tlbehi & 0x200)?'1':'0',
7986 - (tlbelo & 0x100)?'1':'0',
7987 - (tlbehi & 0xff),
7988 - (tlbehi >> 12), (tlbelo >> 12),
7989 - (tlbelo >> 4) & 7, (tlbelo >> 2) & 3,
7990 - (tlbelo & 0x200)?'1':'0',
7991 - (tlbelo & 0x080)?'1':'0',
7992 - (tlbelo & 0x001)?'1':'0',
7993 - (tlbelo & 0x002)?'1':'0');
7994 + *index,
7995 + SYSREG_BFEXT(TLBEHI_V, tlbehi) ? '1' : '0',
7996 + SYSREG_BFEXT(G, tlbelo) ? '1' : '0',
7997 + SYSREG_BFEXT(ASID, tlbehi),
7998 + SYSREG_BFEXT(VPN, tlbehi) >> 2,
7999 + SYSREG_BFEXT(PFN, tlbelo) >> 2,
8000 + SYSREG_BFEXT(AP, tlbelo),
8001 + SYSREG_BFEXT(SZ, tlbelo),
8002 + SYSREG_BFEXT(TLBELO_C, tlbelo) ? '1' : '0',
8003 + SYSREG_BFEXT(B, tlbelo) ? '1' : '0',
8004 + SYSREG_BFEXT(W, tlbelo) ? '1' : '0',
8005 + SYSREG_BFEXT(TLBELO_D, tlbelo) ? '1' : '0');
8006
8007 return 0;
8008 }
8009 --- a/arch/avr32/oprofile/op_model_avr32.c
8010 +++ b/arch/avr32/oprofile/op_model_avr32.c
8011 @@ -16,7 +16,6 @@
8012 #include <linux/sched.h>
8013 #include <linux/types.h>
8014
8015 -#include <asm/intc.h>
8016 #include <asm/sysreg.h>
8017 #include <asm/system.h>
8018
8019 --- a/drivers/char/Kconfig
8020 +++ b/drivers/char/Kconfig
8021 @@ -706,7 +706,7 @@
8022
8023 config RTC
8024 tristate "Enhanced Real Time Clock Support"
8025 - depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV && !ARM && !SUPERH && !S390
8026 + depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV && !ARM && !SUPERH && !S390 && !AVR32
8027 ---help---
8028 If you say Y here and create a character special file /dev/rtc with
8029 major number 10 and minor number 135 using mknod ("man mknod"), you
8030 @@ -776,7 +776,7 @@
8031
8032 config GEN_RTC
8033 tristate "Generic /dev/rtc emulation"
8034 - depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH
8035 + depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH && !AVR32
8036 ---help---
8037 If you say Y here and create a character special file /dev/rtc with
8038 major number 10 and minor number 135 using mknod ("man mknod"), you
8039 --- a/drivers/char/keyboard.c
8040 +++ b/drivers/char/keyboard.c
8041 @@ -1033,7 +1033,8 @@
8042 #if defined(CONFIG_X86) || defined(CONFIG_IA64) || defined(CONFIG_ALPHA) ||\
8043 defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_SPARC) ||\
8044 defined(CONFIG_PARISC) || defined(CONFIG_SUPERH) ||\
8045 - (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC))
8046 + (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC)) ||\
8047 + defined(CONFIG_AVR32)
8048
8049 #define HW_RAW(dev) (test_bit(EV_MSC, dev->evbit) && test_bit(MSC_RAW, dev->mscbit) &&\
8050 ((dev)->id.bustype == BUS_I8042) && ((dev)->id.vendor == 0x0001) && ((dev)->id.product == 0x0001))
8051 --- a/drivers/clocksource/Makefile
8052 +++ b/drivers/clocksource/Makefile
8053 @@ -1,3 +1,4 @@
8054 +obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
8055 obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
8056 obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
8057 obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
8058 --- /dev/null
8059 +++ b/drivers/clocksource/tcb_clksrc.c
8060 @@ -0,0 +1,302 @@
8061 +#include <linux/init.h>
8062 +#include <linux/clocksource.h>
8063 +#include <linux/clockchips.h>
8064 +#include <linux/interrupt.h>
8065 +#include <linux/irq.h>
8066 +
8067 +#include <linux/clk.h>
8068 +#include <linux/err.h>
8069 +#include <linux/ioport.h>
8070 +#include <linux/io.h>
8071 +#include <linux/platform_device.h>
8072 +#include <linux/atmel_tc.h>
8073 +
8074 +
8075 +/*
8076 + * We're configured to use a specific TC block, one that's not hooked
8077 + * up to external hardware, to provide a time solution:
8078 + *
8079 + * - Two channels combine to create a free-running 32 bit counter
8080 + * with a base rate of 5+ MHz, packaged as a clocksource (with
8081 + * resolution better than 200 nsec).
8082 + *
8083 + * - The third channel may be used to provide a 16-bit clockevent
8084 + * source, used in either periodic or oneshot mode. This runs
8085 + * at 32 KiHZ, and can handle delays of up to two seconds.
8086 + *
8087 + * A boot clocksource and clockevent source are also currently needed,
8088 + * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
8089 + * this code can be used when init_timers() is called, well before most
8090 + * devices are set up. (Some low end AT91 parts, which can run uClinux,
8091 + * have only the timers in one TC block... they currently don't support
8092 + * the tclib code, because of that initialization issue.)
8093 + *
8094 + * REVISIT behavior during system suspend states... we should disable
8095 + * all clocks and save the power. Easily done for clockevent devices,
8096 + * but clocksources won't necessarily get the needed notifications.
8097 + * For deeper system sleep states, this will be mandatory...
8098 + */
8099 +
8100 +static void __iomem *tcaddr;
8101 +
8102 +static cycle_t tc_get_cycles(void)
8103 +{
8104 + unsigned long flags;
8105 + u32 lower, upper;
8106 +
8107 + raw_local_irq_save(flags);
8108 + do {
8109 + upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
8110 + lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
8111 + } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
8112 +
8113 + raw_local_irq_restore(flags);
8114 + return (upper << 16) | lower;
8115 +}
8116 +
8117 +static struct clocksource clksrc = {
8118 + .name = "tcb_clksrc",
8119 + .rating = 200,
8120 + .read = tc_get_cycles,
8121 + .mask = CLOCKSOURCE_MASK(32),
8122 + .shift = 18,
8123 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
8124 +};
8125 +
8126 +#ifdef CONFIG_GENERIC_CLOCKEVENTS
8127 +
8128 +struct tc_clkevt_device {
8129 + struct clock_event_device clkevt;
8130 + struct clk *clk;
8131 + void __iomem *regs;
8132 +};
8133 +
8134 +static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
8135 +{
8136 + return container_of(clkevt, struct tc_clkevt_device, clkevt);
8137 +}
8138 +
8139 +/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
8140 + * because using one of the divided clocks would usually mean the
8141 + * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
8142 + *
8143 + * A divided clock could be good for high resolution timers, since
8144 + * 30.5 usec resolution can seem "low".
8145 + */
8146 +static u32 timer_clock;
8147 +
8148 +static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
8149 +{
8150 + struct tc_clkevt_device *tcd = to_tc_clkevt(d);
8151 + void __iomem *regs = tcd->regs;
8152 +
8153 + if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
8154 + || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
8155 + __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
8156 + __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
8157 + clk_disable(tcd->clk);
8158 + }
8159 +
8160 + switch (m) {
8161 +
8162 + /* By not making the gentime core emulate periodic mode on top
8163 + * of oneshot, we get lower overhead and improved accuracy.
8164 + */
8165 + case CLOCK_EVT_MODE_PERIODIC:
8166 + clk_enable(tcd->clk);
8167 +
8168 + /* slow clock, count up to RC, then irq and restart */
8169 + __raw_writel(timer_clock
8170 + | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
8171 + regs + ATMEL_TC_REG(2, CMR));
8172 + __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
8173 +
8174 + /* Enable clock and interrupts on RC compare */
8175 + __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
8176 +
8177 + /* go go gadget! */
8178 + __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
8179 + regs + ATMEL_TC_REG(2, CCR));
8180 + break;
8181 +
8182 + case CLOCK_EVT_MODE_ONESHOT:
8183 + clk_enable(tcd->clk);
8184 +
8185 + /* slow clock, count up to RC, then irq and stop */
8186 + __raw_writel(timer_clock | ATMEL_TC_CPCSTOP
8187 + | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
8188 + regs + ATMEL_TC_REG(2, CMR));
8189 + __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
8190 +
8191 + /* set_next_event() configures and starts the timer */
8192 + break;
8193 +
8194 + default:
8195 + break;
8196 + }
8197 +}
8198 +
8199 +static int tc_next_event(unsigned long delta, struct clock_event_device *d)
8200 +{
8201 + __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
8202 +
8203 + /* go go gadget! */
8204 + __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
8205 + tcaddr + ATMEL_TC_REG(2, CCR));
8206 + return 0;
8207 +}
8208 +
8209 +static struct tc_clkevt_device clkevt = {
8210 + .clkevt = {
8211 + .name = "tc_clkevt",
8212 + .features = CLOCK_EVT_FEAT_PERIODIC
8213 + | CLOCK_EVT_FEAT_ONESHOT,
8214 + .shift = 32,
8215 + /* Should be lower than at91rm9200's system timer */
8216 + .rating = 125,
8217 + .cpumask = CPU_MASK_CPU0,
8218 + .set_next_event = tc_next_event,
8219 + .set_mode = tc_mode,
8220 + },
8221 +};
8222 +
8223 +static irqreturn_t ch2_irq(int irq, void *handle)
8224 +{
8225 + struct tc_clkevt_device *dev = handle;
8226 + unsigned int sr;
8227 +
8228 + sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
8229 + if (sr & ATMEL_TC_CPCS) {
8230 + dev->clkevt.event_handler(&dev->clkevt);
8231 + return IRQ_HANDLED;
8232 + }
8233 +
8234 + return IRQ_NONE;
8235 +}
8236 +
8237 +static struct irqaction tc_irqaction = {
8238 + .name = "tc_clkevt",
8239 + .flags = IRQF_TIMER | IRQF_DISABLED,
8240 + .handler = ch2_irq,
8241 +};
8242 +
8243 +static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
8244 +{
8245 + struct clk *t2_clk = tc->clk[2];
8246 + int irq = tc->irq[2];
8247 +
8248 + clkevt.regs = tc->regs;
8249 + clkevt.clk = t2_clk;
8250 + tc_irqaction.dev_id = &clkevt;
8251 +
8252 + timer_clock = clk32k_divisor_idx;
8253 +
8254 + clkevt.clkevt.mult = div_sc(32768, NSEC_PER_SEC, clkevt.clkevt.shift);
8255 + clkevt.clkevt.max_delta_ns
8256 + = clockevent_delta2ns(0xffff, &clkevt.clkevt);
8257 + clkevt.clkevt.min_delta_ns = clockevent_delta2ns(1, &clkevt.clkevt) + 1;
8258 +
8259 + setup_irq(irq, &tc_irqaction);
8260 +
8261 + clockevents_register_device(&clkevt.clkevt);
8262 +}
8263 +
8264 +#else /* !CONFIG_GENERIC_CLOCKEVENTS */
8265 +
8266 +static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
8267 +{
8268 + /* NOTHING */
8269 +}
8270 +
8271 +#endif
8272 +
8273 +static int __init tcb_clksrc_init(void)
8274 +{
8275 + static char bootinfo[] __initdata
8276 + = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
8277 +
8278 + struct platform_device *pdev;
8279 + struct atmel_tc *tc;
8280 + struct clk *t0_clk;
8281 + u32 rate, divided_rate = 0;
8282 + int best_divisor_idx = -1;
8283 + int clk32k_divisor_idx = -1;
8284 + int i;
8285 +
8286 + tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
8287 + if (!tc) {
8288 + pr_debug("can't alloc TC for clocksource\n");
8289 + return -ENODEV;
8290 + }
8291 + tcaddr = tc->regs;
8292 + pdev = tc->pdev;
8293 +
8294 + t0_clk = tc->clk[0];
8295 + clk_enable(t0_clk);
8296 +
8297 + /* How fast will we be counting? Pick something over 5 MHz. */
8298 + rate = (u32) clk_get_rate(t0_clk);
8299 + for (i = 0; i < 5; i++) {
8300 + unsigned divisor = atmel_tc_divisors[i];
8301 + unsigned tmp;
8302 +
8303 + /* remember 32 KiHz clock for later */
8304 + if (!divisor) {
8305 + clk32k_divisor_idx = i;
8306 + continue;
8307 + }
8308 +
8309 + tmp = rate / divisor;
8310 + pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
8311 + if (best_divisor_idx > 0) {
8312 + if (tmp < 5 * 1000 * 1000)
8313 + continue;
8314 + }
8315 + divided_rate = tmp;
8316 + best_divisor_idx = i;
8317 + }
8318 +
8319 + clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
8320 +
8321 + printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
8322 + divided_rate / 1000000,
8323 + ((divided_rate + 500000) % 1000000) / 1000);
8324 +
8325 + /* tclib will give us three clocks no matter what the
8326 + * underlying platform supports.
8327 + */
8328 + clk_enable(tc->clk[1]);
8329 +
8330 + /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
8331 + __raw_writel(best_divisor_idx /* likely divide-by-8 */
8332 + | ATMEL_TC_WAVE
8333 + | ATMEL_TC_WAVESEL_UP /* free-run */
8334 + | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
8335 + | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
8336 + tcaddr + ATMEL_TC_REG(0, CMR));
8337 + __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
8338 + __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
8339 + __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
8340 + __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
8341 +
8342 + /* channel 1: waveform mode, input TIOA0 */
8343 + __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
8344 + | ATMEL_TC_WAVE
8345 + | ATMEL_TC_WAVESEL_UP, /* free-run */
8346 + tcaddr + ATMEL_TC_REG(1, CMR));
8347 + __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
8348 + __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
8349 +
8350 + /* chain channel 0 to channel 1, then reset all the timers */
8351 + __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
8352 + __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
8353 +
8354 + /* and away we go! */
8355 + clocksource_register(&clksrc);
8356 +
8357 + /* channel 2: periodic and oneshot timer support */
8358 + setup_clkevents(tc, clk32k_divisor_idx);
8359 +
8360 + return 0;
8361 +}
8362 +arch_initcall(tcb_clksrc_init);
8363 --- a/drivers/i2c/busses/Kconfig
8364 +++ b/drivers/i2c/busses/Kconfig
8365 @@ -88,6 +88,14 @@
8366 to support combined I2C messages. Use the i2c-gpio driver
8367 unless your system can cope with those limitations.
8368
8369 +config I2C_ATMELTWI
8370 + tristate "Atmel Two-Wire Interface (TWI)"
8371 + depends on I2C && (ARCH_AT91 || PLATFORM_AT32AP)
8372 + help
8373 + Atmel on-chip TWI controller. Say Y if you have an AT32 or
8374 + AT91-based device and want to use its built-in TWI
8375 + functionality.
8376 +
8377 config I2C_AU1550
8378 tristate "Au1550/Au1200 SMBus interface"
8379 depends on SOC_AU1550 || SOC_AU1200
8380 --- a/drivers/i2c/busses/Makefile
8381 +++ b/drivers/i2c/busses/Makefile
8382 @@ -52,6 +52,7 @@
8383 obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o
8384 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
8385 obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
8386 +obj-$(CONFIG_I2C_ATMELTWI) += i2c-atmeltwi.o
8387
8388 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
8389 EXTRA_CFLAGS += -DDEBUG
8390 --- /dev/null
8391 +++ b/drivers/i2c/busses/i2c-atmeltwi.c
8392 @@ -0,0 +1,436 @@
8393 +/*
8394 + * i2c Support for Atmel's Two-Wire Interface (TWI)
8395 + *
8396 + * Based on the work of Copyright (C) 2004 Rick Bronson
8397 + * Converted to 2.6 by Andrew Victor <andrew at sanpeople.com>
8398 + * Ported to AVR32 and heavily modified by Espen Krangnes
8399 + * <ekrangnes at atmel.com>
8400 + *
8401 + * Copyright (C) 2006 Atmel Corporation
8402 + *
8403 + * Borrowed heavily from the original work by:
8404 + * Copyright (C) 2000 Philip Edelbrock <phil at stimpy.netroedge.com>
8405 + *
8406 + * Partialy rewriten by Karel Hojdar <cmkaho at seznam.cz>
8407 + * bugs removed, interrupt routine markedly rewritten
8408 + *
8409 + * This program is free software; you can redistribute it and/or modify
8410 + * it under the terms of the GNU General Public License as published by
8411 + * the Free Software Foundation; either version 2 of the License, or
8412 + * (at your option) any later version.
8413 + */
8414 +#undef VERBOSE_DEBUG
8415 +
8416 +#include <linux/module.h>
8417 +#include <linux/slab.h>
8418 +#include <linux/i2c.h>
8419 +#include <linux/init.h>
8420 +#include <linux/clk.h>
8421 +#include <linux/err.h>
8422 +#include <linux/interrupt.h>
8423 +#include <linux/platform_device.h>
8424 +#include <linux/completion.h>
8425 +#include <linux/io.h>
8426 +
8427 +#include "i2c-atmeltwi.h"
8428 +
8429 +static unsigned int baudrate = 100 * 1000;
8430 +module_param(baudrate, uint, S_IRUGO);
8431 +MODULE_PARM_DESC(baudrate, "The TWI baudrate");
8432 +
8433 +
8434 +struct atmel_twi {
8435 + void __iomem *regs;
8436 + struct i2c_adapter adapter;
8437 + struct clk *pclk;
8438 + struct completion comp;
8439 + u32 mask;
8440 + u8 *buf;
8441 + u16 len;
8442 + u16 acks_left;
8443 + int status;
8444 + unsigned int irq;
8445 +
8446 +};
8447 +#define to_atmel_twi(adap) container_of(adap, struct atmel_twi, adapter)
8448 +
8449 +/*
8450 + * (Re)Initialize the TWI hardware registers.
8451 + */
8452 +static int twi_hwinit(struct atmel_twi *twi)
8453 +{
8454 + unsigned long cdiv, ckdiv = 0;
8455 +
8456 + /* REVISIT: wait till SCL is high before resetting; otherwise,
8457 + * some versions will wedge forever.
8458 + */
8459 +
8460 + twi_writel(twi, IDR, ~0UL);
8461 + twi_writel(twi, CR, TWI_BIT(SWRST)); /*Reset peripheral*/
8462 + twi_readl(twi, SR);
8463 +
8464 + cdiv = (clk_get_rate(twi->pclk) / (2 * baudrate)) - 4;
8465 +
8466 + while (cdiv > 255) {
8467 + ckdiv++;
8468 + cdiv = cdiv >> 1;
8469 + }
8470 +
8471 + /* REVISIT: there are various errata to consider re CDIV and CHDIV
8472 + * here, at least on at91 parts.
8473 + */
8474 +
8475 + if (ckdiv > 7)
8476 + return -EINVAL;
8477 + else
8478 + twi_writel(twi, CWGR, TWI_BF(CKDIV, ckdiv)
8479 + | TWI_BF(CHDIV, cdiv)
8480 + | TWI_BF(CLDIV, cdiv));
8481 + return 0;
8482 +}
8483 +
8484 +/*
8485 + * Waits for the i2c status register to set the specified bitmask
8486 + * Returns 0 if timed out ... ~100ms is much longer than the SMBus
8487 + * limit, but I2C has no limit at all.
8488 + */
8489 +static int twi_complete(struct atmel_twi *twi, u32 mask)
8490 +{
8491 + int timeout = msecs_to_jiffies(100);
8492 +
8493 + mask |= TWI_BIT(TXCOMP);
8494 + twi->mask = mask | TWI_BIT(NACK) | TWI_BIT(OVRE);
8495 + init_completion(&twi->comp);
8496 +
8497 + twi_writel(twi, IER, mask);
8498 +
8499 + if (!wait_for_completion_timeout(&twi->comp, timeout)) {
8500 + /* RESET TWI interface */
8501 + twi_writel(twi, CR, TWI_BIT(SWRST));
8502 +
8503 + /* Reinitialize TWI */
8504 + twi_hwinit(twi);
8505 +
8506 + return -ETIMEDOUT;
8507 + }
8508 + return 0;
8509 +}
8510 +
8511 +/*
8512 + * Generic i2c master transfer entrypoint.
8513 + */
8514 +static int twi_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
8515 +{
8516 + struct atmel_twi *twi = to_atmel_twi(adap);
8517 + int i;
8518 +
8519 + dev_dbg(&adap->dev, "twi_xfer: processing %d messages:\n", num);
8520 +
8521 + twi->status = 0;
8522 + for (i = 0; i < num; i++, pmsg++) {
8523 + twi->len = pmsg->len;
8524 + twi->buf = pmsg->buf;
8525 + twi->acks_left = pmsg->len;
8526 + twi_writel(twi, MMR, TWI_BF(DADR, pmsg->addr) |
8527 + (pmsg->flags & I2C_M_RD ? TWI_BIT(MREAD) : 0));
8528 + twi_writel(twi, IADR, TWI_BF(IADR, pmsg->addr));
8529 +
8530 + dev_dbg(&adap->dev,
8531 + "#%d: %s %d byte%s %s dev 0x%02x\n",
8532 + i,
8533 + pmsg->flags & I2C_M_RD ? "reading" : "writing",
8534 + pmsg->len,
8535 + pmsg->len > 1 ? "s" : "",
8536 + pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
8537 +
8538 + /* enable */
8539 + twi_writel(twi, CR, TWI_BIT(MSEN));
8540 +
8541 + if (pmsg->flags & I2C_M_RD) {
8542 + /* cleanup after previous RX overruns */
8543 + while (twi_readl(twi, SR) & TWI_BIT(RXRDY))
8544 + twi_readl(twi, RHR);
8545 +
8546 + if (twi->len == 1)
8547 + twi_writel(twi, CR,
8548 + TWI_BIT(START) | TWI_BIT(STOP));
8549 + else
8550 + twi_writel(twi, CR, TWI_BIT(START));
8551 +
8552 + if (twi_complete(twi, TWI_BIT(RXRDY)) == -ETIMEDOUT) {
8553 + dev_dbg(&adap->dev, "RX[%d] timeout. "
8554 + "Stopped with %d bytes left\n",
8555 + i, twi->acks_left);
8556 + return -ETIMEDOUT;
8557 + }
8558 + } else {
8559 + twi_writel(twi, THR, twi->buf[0]);
8560 + twi->acks_left--;
8561 + /* REVISIT: some chips don't start automagically:
8562 + * twi_writel(twi, CR, TWI_BIT(START));
8563 + */
8564 + if (twi_complete(twi, TWI_BIT(TXRDY)) == -ETIMEDOUT) {
8565 + dev_dbg(&adap->dev, "TX[%d] timeout. "
8566 + "Stopped with %d bytes left\n",
8567 + i, twi->acks_left);
8568 + return -ETIMEDOUT;
8569 + }
8570 + /* REVISIT: an erratum workaround may be needed here;
8571 + * see sam9261 "STOP not generated" (START either).
8572 + */
8573 + }
8574 +
8575 + /* Disable TWI interface */
8576 + twi_writel(twi, CR, TWI_BIT(MSDIS));
8577 +
8578 + if (twi->status)
8579 + return twi->status;
8580 +
8581 + /* WARNING: This driver lies about properly supporting
8582 + * repeated start, or it would *ALWAYS* return here. It
8583 + * has issued a STOP. Continuing is a false claim -- that
8584 + * a second (or third, etc.) message is part of the same
8585 + * "combined" (no STOPs between parts) message.
8586 + */
8587 +
8588 + } /* end cur msg */
8589 +
8590 + return i;
8591 +}
8592 +
8593 +
8594 +static irqreturn_t twi_interrupt(int irq, void *dev_id)
8595 +{
8596 + struct atmel_twi *twi = dev_id;
8597 + int status = twi_readl(twi, SR);
8598 +
8599 + /* Save state for later debug prints */
8600 + int old_status = status;
8601 +
8602 + if (twi->mask & status) {
8603 +
8604 + status &= twi->mask;
8605 +
8606 + if (status & TWI_BIT(RXRDY)) {
8607 + if ((status & TWI_BIT(OVRE)) && twi->acks_left) {
8608 + /* Note weakness in fault reporting model:
8609 + * we can't say "the first N of these data
8610 + * bytes are valid".
8611 + */
8612 + dev_err(&twi->adapter.dev,
8613 + "OVERRUN RX! %04x, lost %d\n",
8614 + old_status, twi->acks_left);
8615 + twi->acks_left = 0;
8616 + twi_writel(twi, CR, TWI_BIT(STOP));
8617 + twi->status = -EOVERFLOW;
8618 + } else if (twi->acks_left > 0) {
8619 + twi->buf[twi->len - twi->acks_left] =
8620 + twi_readl(twi, RHR);
8621 + twi->acks_left--;
8622 + }
8623 + if (status & TWI_BIT(TXCOMP))
8624 + goto done;
8625 + if (twi->acks_left == 1)
8626 + twi_writel(twi, CR, TWI_BIT(STOP));
8627 +
8628 + } else if (status & (TWI_BIT(NACK) | TWI_BIT(TXCOMP))) {
8629 + goto done;
8630 +
8631 + } else if (status & TWI_BIT(TXRDY)) {
8632 + if (twi->acks_left > 0) {
8633 + twi_writel(twi, THR,
8634 + twi->buf[twi->len - twi->acks_left]);
8635 + twi->acks_left--;
8636 + } else
8637 + twi_writel(twi, CR, TWI_BIT(STOP));
8638 + }
8639 +
8640 + if (twi->acks_left == 0)
8641 + twi_writel(twi, IDR, ~TWI_BIT(TXCOMP));
8642 + }
8643 +
8644 + /* enabling this message helps trigger overruns/underruns ... */
8645 + dev_vdbg(&twi->adapter.dev,
8646 + "ISR: SR 0x%04X, mask 0x%04X, acks %i\n",
8647 + old_status,
8648 + twi->acks_left ? twi->mask : TWI_BIT(TXCOMP),
8649 + twi->acks_left);
8650 +
8651 + return IRQ_HANDLED;
8652 +
8653 +done:
8654 + /* Note weak fault reporting model: we can't report how many
8655 + * bytes we sent before the NAK, or let upper layers choose
8656 + * whether to continue. The I2C stack doesn't allow that...
8657 + */
8658 + if (status & TWI_BIT(NACK)) {
8659 + dev_dbg(&twi->adapter.dev, "NACK received! %d to go\n",
8660 + twi->acks_left);
8661 + twi->status = -EPIPE;
8662 +
8663 + /* TX underrun morphs automagically into a premature STOP;
8664 + * we'll probably observe UVRE even when it's not documented.
8665 + */
8666 + } else if (twi->acks_left && (twi->mask & TWI_BIT(TXRDY))) {
8667 + dev_err(&twi->adapter.dev, "UNDERRUN TX! %04x, %d to go\n",
8668 + old_status, twi->acks_left);
8669 + twi->status = -ENOSR;
8670 + }
8671 +
8672 + twi_writel(twi, IDR, ~0UL);
8673 + complete(&twi->comp);
8674 +
8675 + dev_dbg(&twi->adapter.dev, "ISR: SR 0x%04X, acks %i --> %d\n",
8676 + old_status, twi->acks_left, twi->status);
8677 +
8678 + return IRQ_HANDLED;
8679 +}
8680 +
8681 +
8682 +/*
8683 + * Return list of supported functionality.
8684 + *
8685 + * NOTE: see warning above about repeated starts; this driver is falsely
8686 + * claiming to support "combined" transfers. The mid-message STOPs mean
8687 + * some slaves will never work with this driver. (Use i2c-gpio...)
8688 + */
8689 +static u32 twi_func(struct i2c_adapter *adapter)
8690 +{
8691 + return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL)
8692 + & ~I2C_FUNC_SMBUS_QUICK;
8693 +}
8694 +
8695 +static struct i2c_algorithm twi_algorithm = {
8696 + .master_xfer = twi_xfer,
8697 + .functionality = twi_func,
8698 +};
8699 +
8700 +/*
8701 + * Main initialization routine.
8702 + */
8703 +static int __init twi_probe(struct platform_device *pdev)
8704 +{
8705 + struct atmel_twi *twi;
8706 + struct resource *regs;
8707 + struct clk *pclk;
8708 + struct i2c_adapter *adapter;
8709 + int rc, irq;
8710 +
8711 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8712 + if (!regs)
8713 + return -ENXIO;
8714 +
8715 + pclk = clk_get(&pdev->dev, "twi_pclk");
8716 + if (IS_ERR(pclk))
8717 + return PTR_ERR(pclk);
8718 + clk_enable(pclk);
8719 +
8720 + rc = -ENOMEM;
8721 + twi = kzalloc(sizeof(struct atmel_twi), GFP_KERNEL);
8722 + if (!twi) {
8723 + dev_dbg(&pdev->dev, "can't allocate interface!\n");
8724 + goto err_alloc_twi;
8725 + }
8726 +
8727 + twi->pclk = pclk;
8728 + twi->regs = ioremap(regs->start, regs->end - regs->start + 1);
8729 + if (!twi->regs)
8730 + goto err_ioremap;
8731 +
8732 + irq = platform_get_irq(pdev, 0);
8733 + rc = request_irq(irq, twi_interrupt, 0, "twi", twi);
8734 + if (rc) {
8735 + dev_dbg(&pdev->dev, "can't bind irq!\n");
8736 + goto err_irq;
8737 + }
8738 + twi->irq = irq;
8739 +
8740 + rc = twi_hwinit(twi);
8741 + if (rc) {
8742 + dev_err(&pdev->dev, "Unable to set baudrate\n");
8743 + goto err_hw_init;
8744 + }
8745 +
8746 + adapter = &twi->adapter;
8747 + sprintf(adapter->name, "TWI");
8748 + adapter->algo = &twi_algorithm;
8749 + adapter->class = I2C_CLASS_ALL;
8750 + adapter->nr = pdev->id;
8751 + adapter->dev.parent = &pdev->dev;
8752 +
8753 + platform_set_drvdata(pdev, twi);
8754 +
8755 + rc = i2c_add_numbered_adapter(adapter);
8756 + if (rc) {
8757 + dev_dbg(&pdev->dev, "Adapter %s registration failed\n",
8758 + adapter->name);
8759 + goto err_register;
8760 + }
8761 +
8762 + dev_info(&pdev->dev,
8763 + "Atmel TWI/I2C adapter (baudrate %dk) at 0x%08lx.\n",
8764 + baudrate/1000, (unsigned long)regs->start);
8765 +
8766 + return 0;
8767 +
8768 +
8769 +err_register:
8770 + platform_set_drvdata(pdev, NULL);
8771 +
8772 +err_hw_init:
8773 + free_irq(irq, twi);
8774 +
8775 +err_irq:
8776 + iounmap(twi->regs);
8777 +
8778 +err_ioremap:
8779 + kfree(twi);
8780 +
8781 +err_alloc_twi:
8782 + clk_disable(pclk);
8783 + clk_put(pclk);
8784 +
8785 + return rc;
8786 +}
8787 +
8788 +static int __exit twi_remove(struct platform_device *pdev)
8789 +{
8790 + struct atmel_twi *twi = platform_get_drvdata(pdev);
8791 + int res;
8792 +
8793 + platform_set_drvdata(pdev, NULL);
8794 + res = i2c_del_adapter(&twi->adapter);
8795 + twi_writel(twi, CR, TWI_BIT(MSDIS));
8796 + iounmap(twi->regs);
8797 + clk_disable(twi->pclk);
8798 + clk_put(twi->pclk);
8799 + free_irq(twi->irq, twi);
8800 + kfree(twi);
8801 +
8802 + return res;
8803 +}
8804 +
8805 +static struct platform_driver twi_driver = {
8806 + .remove = __exit_p(twi_remove),
8807 + .driver = {
8808 + .name = "atmel_twi",
8809 + .owner = THIS_MODULE,
8810 + },
8811 +};
8812 +
8813 +static int __init atmel_twi_init(void)
8814 +{
8815 + return platform_driver_probe(&twi_driver, twi_probe);
8816 +}
8817 +
8818 +static void __exit atmel_twi_exit(void)
8819 +{
8820 + platform_driver_unregister(&twi_driver);
8821 +}
8822 +
8823 +module_init(atmel_twi_init);
8824 +module_exit(atmel_twi_exit);
8825 +
8826 +MODULE_AUTHOR("Espen Krangnes");
8827 +MODULE_DESCRIPTION("I2C driver for Atmel TWI");
8828 +MODULE_LICENSE("GPL");
8829 --- /dev/null
8830 +++ b/drivers/i2c/busses/i2c-atmeltwi.h
8831 @@ -0,0 +1,117 @@
8832 +/*
8833 + * Register definitions for the Atmel Two-Wire Interface
8834 + */
8835 +
8836 +#ifndef __ATMELTWI_H__
8837 +#define __ATMELTWI_H__
8838 +
8839 +/* TWI register offsets */
8840 +#define TWI_CR 0x0000
8841 +#define TWI_MMR 0x0004
8842 +#define TWI_SMR 0x0008
8843 +#define TWI_IADR 0x000c
8844 +#define TWI_CWGR 0x0010
8845 +#define TWI_SR 0x0020
8846 +#define TWI_IER 0x0024
8847 +#define TWI_IDR 0x0028
8848 +#define TWI_IMR 0x002c
8849 +#define TWI_RHR 0x0030
8850 +#define TWI_THR 0x0034
8851 +
8852 +/* Bitfields in CR */
8853 +#define TWI_START_OFFSET 0
8854 +#define TWI_START_SIZE 1
8855 +#define TWI_STOP_OFFSET 1
8856 +#define TWI_STOP_SIZE 1
8857 +#define TWI_MSEN_OFFSET 2
8858 +#define TWI_MSEN_SIZE 1
8859 +#define TWI_MSDIS_OFFSET 3
8860 +#define TWI_MSDIS_SIZE 1
8861 +#define TWI_SVEN_OFFSET 4
8862 +#define TWI_SVEN_SIZE 1
8863 +#define TWI_SVDIS_OFFSET 5
8864 +#define TWI_SVDIS_SIZE 1
8865 +#define TWI_SWRST_OFFSET 7
8866 +#define TWI_SWRST_SIZE 1
8867 +
8868 +/* Bitfields in MMR */
8869 +#define TWI_IADRSZ_OFFSET 8
8870 +#define TWI_IADRSZ_SIZE 2
8871 +#define TWI_MREAD_OFFSET 12
8872 +#define TWI_MREAD_SIZE 1
8873 +#define TWI_DADR_OFFSET 16
8874 +#define TWI_DADR_SIZE 7
8875 +
8876 +/* Bitfields in SMR */
8877 +#define TWI_SADR_OFFSET 16
8878 +#define TWI_SADR_SIZE 7
8879 +
8880 +/* Bitfields in IADR */
8881 +#define TWI_IADR_OFFSET 0
8882 +#define TWI_IADR_SIZE 24
8883 +
8884 +/* Bitfields in CWGR */
8885 +#define TWI_CLDIV_OFFSET 0
8886 +#define TWI_CLDIV_SIZE 8
8887 +#define TWI_CHDIV_OFFSET 8
8888 +#define TWI_CHDIV_SIZE 8
8889 +#define TWI_CKDIV_OFFSET 16
8890 +#define TWI_CKDIV_SIZE 3
8891 +
8892 +/* Bitfields in SR */
8893 +#define TWI_TXCOMP_OFFSET 0
8894 +#define TWI_TXCOMP_SIZE 1
8895 +#define TWI_RXRDY_OFFSET 1
8896 +#define TWI_RXRDY_SIZE 1
8897 +#define TWI_TXRDY_OFFSET 2
8898 +#define TWI_TXRDY_SIZE 1
8899 +#define TWI_SVDIR_OFFSET 3
8900 +#define TWI_SVDIR_SIZE 1
8901 +#define TWI_SVACC_OFFSET 4
8902 +#define TWI_SVACC_SIZE 1
8903 +#define TWI_GCACC_OFFSET 5
8904 +#define TWI_GCACC_SIZE 1
8905 +#define TWI_OVRE_OFFSET 6
8906 +#define TWI_OVRE_SIZE 1
8907 +#define TWI_UNRE_OFFSET 7
8908 +#define TWI_UNRE_SIZE 1
8909 +#define TWI_NACK_OFFSET 8
8910 +#define TWI_NACK_SIZE 1
8911 +#define TWI_ARBLST_OFFSET 9
8912 +#define TWI_ARBLST_SIZE 1
8913 +
8914 +/* Bitfields in RHR */
8915 +#define TWI_RXDATA_OFFSET 0
8916 +#define TWI_RXDATA_SIZE 8
8917 +
8918 +/* Bitfields in THR */
8919 +#define TWI_TXDATA_OFFSET 0
8920 +#define TWI_TXDATA_SIZE 8
8921 +
8922 +/* Constants for IADRSZ */
8923 +#define TWI_IADRSZ_NO_ADDR 0
8924 +#define TWI_IADRSZ_ONE_BYTE 1
8925 +#define TWI_IADRSZ_TWO_BYTES 2
8926 +#define TWI_IADRSZ_THREE_BYTES 3
8927 +
8928 +/* Bit manipulation macros */
8929 +#define TWI_BIT(name) \
8930 + (1 << TWI_##name##_OFFSET)
8931 +#define TWI_BF(name, value) \
8932 + (((value) & ((1 << TWI_##name##_SIZE) - 1)) \
8933 + << TWI_##name##_OFFSET)
8934 +#define TWI_BFEXT(name, value) \
8935 + (((value) >> TWI_##name##_OFFSET) \
8936 + & ((1 << TWI_##name##_SIZE) - 1))
8937 +#define TWI_BFINS(name, value, old) \
8938 + (((old) & ~(((1 << TWI_##name##_SIZE) - 1) \
8939 + << TWI_##name##_OFFSET)) \
8940 + | TWI_BF(name, (value)))
8941 +
8942 +/* Register access macros */
8943 +#define twi_readl(port, reg) \
8944 + __raw_readl((port)->regs + TWI_##reg)
8945 +#define twi_writel(port, reg, value) \
8946 + __raw_writel((value), (port)->regs + TWI_##reg)
8947 +
8948 +#endif /* __ATMELTWI_H__ */
8949 --- a/drivers/input/serio/Kconfig
8950 +++ b/drivers/input/serio/Kconfig
8951 @@ -88,6 +88,17 @@
8952 To compile this driver as a module, choose M here: the
8953 module will be called rpckbd.
8954
8955 +config SERIO_AT32PSIF
8956 + tristate "AVR32 PSIF PS/2 keyboard and mouse controller"
8957 + depends on AVR32
8958 + default n
8959 + help
8960 + Say Y here if you want to use the PSIF peripheral on AVR32 devices
8961 + and connect a PS/2 keyboard and/or mouse to it.
8962 +
8963 + To compile this driver as a module, choose M here: the module will
8964 + be called at32psif.
8965 +
8966 config SERIO_AMBAKMI
8967 tristate "AMBA KMI keyboard controller"
8968 depends on ARM_AMBA
8969 --- a/drivers/input/serio/Makefile
8970 +++ b/drivers/input/serio/Makefile
8971 @@ -12,6 +12,7 @@
8972 obj-$(CONFIG_SERIO_RPCKBD) += rpckbd.o
8973 obj-$(CONFIG_SERIO_SA1111) += sa1111ps2.o
8974 obj-$(CONFIG_SERIO_AMBAKMI) += ambakmi.o
8975 +obj-$(CONFIG_SERIO_AT32PSIF) += at32psif.o
8976 obj-$(CONFIG_SERIO_Q40KBD) += q40kbd.o
8977 obj-$(CONFIG_SERIO_GSCPS2) += gscps2.o
8978 obj-$(CONFIG_HP_SDC) += hp_sdc.o
8979 --- /dev/null
8980 +++ b/drivers/input/serio/at32psif.c
8981 @@ -0,0 +1,351 @@
8982 +/*
8983 + * Copyright (C) 2007 Atmel Corporation
8984 + *
8985 + * Driver for the AT32AP700X PS/2 controller (PSIF).
8986 + *
8987 + * This program is free software; you can redistribute it and/or modify it
8988 + * under the terms of the GNU General Public License version 2 as published
8989 + * by the Free Software Foundation.
8990 + */
8991 +#include <linux/kernel.h>
8992 +#include <linux/module.h>
8993 +#include <linux/device.h>
8994 +#include <linux/init.h>
8995 +#include <linux/serio.h>
8996 +#include <linux/timer.h>
8997 +#include <linux/interrupt.h>
8998 +#include <linux/err.h>
8999 +#include <linux/io.h>
9000 +#include <linux/clk.h>
9001 +#include <linux/platform_device.h>
9002 +
9003 +#include "at32psif.h"
9004 +
9005 +#define PSIF_BUF_SIZE 16
9006 +
9007 +#define ring_is_empty(_psif) (_psif->head == _psif->tail)
9008 +#define ring_next_head(_psif) ((_psif->head + 1) & (PSIF_BUF_SIZE - 1))
9009 +#define ring_next_tail(_psif) ((_psif->tail + 1) & (PSIF_BUF_SIZE - 1))
9010 +
9011 +struct psif {
9012 + struct platform_device *pdev;
9013 + struct clk *pclk;
9014 + struct serio *io;
9015 + struct timer_list tx_timer;
9016 + void __iomem *regs;
9017 + unsigned int irq;
9018 + unsigned int open;
9019 + /* Prevent concurrent writes to circular buffer. */
9020 + spinlock_t lock;
9021 + unsigned int head;
9022 + unsigned int tail;
9023 + unsigned char buffer[PSIF_BUF_SIZE];
9024 +};
9025 +
9026 +static irqreturn_t psif_interrupt(int irq, void *_ptr)
9027 +{
9028 + struct psif *psif = _ptr;
9029 + int retval = IRQ_NONE;
9030 + unsigned int io_flags = 0;
9031 + unsigned long status;
9032 +
9033 + status = psif_readl(psif, SR);
9034 +
9035 + if (status & PSIF_BIT(RXRDY)) {
9036 + unsigned char val = (unsigned char) psif_readl(psif, RHR);
9037 +
9038 + if (status & PSIF_BIT(PARITY))
9039 + io_flags |= SERIO_PARITY;
9040 + if (status & PSIF_BIT(OVRUN))
9041 + dev_err(&psif->pdev->dev, "overrun read error\n");
9042 +
9043 + serio_interrupt(psif->io, val, io_flags);
9044 +
9045 + retval = IRQ_HANDLED;
9046 + }
9047 +
9048 + spin_lock(&psif->lock);
9049 +
9050 + if (status & PSIF_BIT(TXEMPTY)) {
9051 + if (status & PSIF_BIT(NACK))
9052 + dev_err(&psif->pdev->dev, "NACK error\n");
9053 +
9054 + psif_writel(psif, IDR, PSIF_BIT(TXEMPTY));
9055 +
9056 + if (!ring_is_empty(psif))
9057 + mod_timer(&psif->tx_timer,
9058 + jiffies + msecs_to_jiffies(1));
9059 +
9060 + retval = IRQ_HANDLED;
9061 + }
9062 +
9063 + spin_unlock(&psif->lock);
9064 +
9065 + return retval;
9066 +}
9067 +
9068 +static void psif_transmit_data(unsigned long data)
9069 +{
9070 + struct psif *psif = (struct psif *)data;
9071 + unsigned long flags;
9072 +
9073 + spin_lock_irqsave(&psif->lock, flags);
9074 +
9075 + psif_writel(psif, THR, psif->buffer[psif->tail]);
9076 + psif->tail = ring_next_tail(psif);
9077 +
9078 + if (!ring_is_empty(psif))
9079 + psif_writel(psif, IER, PSIF_BIT(TXEMPTY));
9080 +
9081 + spin_unlock_irqrestore(&psif->lock, flags);
9082 +}
9083 +
9084 +static int psif_write(struct serio *io, unsigned char val)
9085 +{
9086 + struct psif *psif = io->port_data;
9087 + unsigned long flags;
9088 + unsigned int head;
9089 +
9090 + spin_lock_irqsave(&psif->lock, flags);
9091 +
9092 + head = ring_next_head(psif);
9093 +
9094 + if (head != psif->tail) {
9095 + psif->buffer[psif->head] = val;
9096 + psif->head = head;
9097 + } else {
9098 + dev_err(&psif->pdev->dev, "underrun write error\n");
9099 + }
9100 +
9101 + spin_unlock_irqrestore(&psif->lock, flags);
9102 +
9103 + /* Make sure TXEMPTY interrupt is enabled. */
9104 + psif_writel(psif, IER, PSIF_BIT(TXEMPTY));
9105 +
9106 + return 0;
9107 +}
9108 +
9109 +static int psif_open(struct serio *io)
9110 +{
9111 + struct psif *psif = io->port_data;
9112 + int retval;
9113 +
9114 + retval = clk_enable(psif->pclk);
9115 + if (retval)
9116 + goto out;
9117 +
9118 + psif_writel(psif, CR, PSIF_BIT(CR_TXEN) | PSIF_BIT(CR_RXEN));
9119 + psif_writel(psif, IER, PSIF_BIT(RXRDY));
9120 +
9121 + psif->open = 1;
9122 +out:
9123 + return retval;
9124 +}
9125 +
9126 +static void psif_close(struct serio *io)
9127 +{
9128 + struct psif *psif = io->port_data;
9129 +
9130 + psif->open = 0;
9131 +
9132 + psif_writel(psif, IDR, ~0UL);
9133 + psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
9134 +
9135 + clk_disable(psif->pclk);
9136 +}
9137 +
9138 +static void psif_set_prescaler(struct psif *psif)
9139 +{
9140 + unsigned long prscv;
9141 + unsigned long rate = clk_get_rate(psif->pclk);
9142 +
9143 + /* PRSCV = Pulse length (100 us) * PSIF module frequency. */
9144 + prscv = 100 * (rate / 1000000UL);
9145 +
9146 + if (prscv > ((1<<PSIF_PSR_PRSCV_SIZE) - 1)) {
9147 + prscv = (1<<PSIF_PSR_PRSCV_SIZE) - 1;
9148 + dev_dbg(&psif->pdev->dev, "pclk too fast, "
9149 + "prescaler set to max\n");
9150 + }
9151 +
9152 + clk_enable(psif->pclk);
9153 + psif_writel(psif, PSR, prscv);
9154 + clk_disable(psif->pclk);
9155 +}
9156 +
9157 +static int __init psif_probe(struct platform_device *pdev)
9158 +{
9159 + struct resource *regs;
9160 + struct psif *psif;
9161 + struct serio *io;
9162 + struct clk *pclk;
9163 + int irq;
9164 + int ret;
9165 +
9166 + psif = kzalloc(sizeof(struct psif), GFP_KERNEL);
9167 + if (!psif) {
9168 + dev_dbg(&pdev->dev, "out of memory\n");
9169 + ret = -ENOMEM;
9170 + goto out;
9171 + }
9172 + psif->pdev = pdev;
9173 +
9174 + io = kzalloc(sizeof(struct serio), GFP_KERNEL);
9175 + if (!io) {
9176 + dev_dbg(&pdev->dev, "out of memory\n");
9177 + ret = -ENOMEM;
9178 + goto out_free_psif;
9179 + }
9180 + psif->io = io;
9181 +
9182 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9183 + if (!regs) {
9184 + dev_dbg(&pdev->dev, "no mmio resources defined\n");
9185 + ret = -ENOMEM;
9186 + goto out_free_io;
9187 + }
9188 +
9189 + psif->regs = ioremap(regs->start, regs->end - regs->start + 1);
9190 + if (!psif->regs) {
9191 + ret = -ENOMEM;
9192 + dev_dbg(&pdev->dev, "could not map I/O memory\n");
9193 + goto out_free_io;
9194 + }
9195 +
9196 + pclk = clk_get(&pdev->dev, "pclk");
9197 + if (IS_ERR(pclk)) {
9198 + dev_dbg(&pdev->dev, "could not get peripheral clock\n");
9199 + ret = PTR_ERR(pclk);
9200 + goto out_iounmap;
9201 + }
9202 + psif->pclk = pclk;
9203 +
9204 + /* Reset the PSIF to enter at a known state. */
9205 + ret = clk_enable(pclk);
9206 + if (ret) {
9207 + dev_dbg(&pdev->dev, "could not enable pclk\n");
9208 + goto out_put_clk;
9209 + }
9210 + psif_writel(psif, CR, PSIF_BIT(CR_SWRST));
9211 + clk_disable(pclk);
9212 +
9213 + setup_timer(&psif->tx_timer, psif_transmit_data, (unsigned long)psif);
9214 +
9215 + irq = platform_get_irq(pdev, 0);
9216 + if (irq < 0) {
9217 + dev_dbg(&pdev->dev, "could not get irq\n");
9218 + ret = -ENXIO;
9219 + goto out_put_clk;
9220 + }
9221 + ret = request_irq(irq, psif_interrupt, IRQF_SHARED, "at32psif", psif);
9222 + if (ret) {
9223 + dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
9224 + goto out_put_clk;
9225 + }
9226 + psif->irq = irq;
9227 +
9228 + io->id.type = SERIO_8042;
9229 + io->write = psif_write;
9230 + io->open = psif_open;
9231 + io->close = psif_close;
9232 + strlcpy(io->name, pdev->dev.bus_id, sizeof(io->name));
9233 + strlcpy(io->phys, pdev->dev.bus_id, sizeof(io->phys));
9234 + io->port_data = psif;
9235 + io->dev.parent = &pdev->dev;
9236 +
9237 + psif_set_prescaler(psif);
9238 +
9239 + spin_lock_init(&psif->lock);
9240 + serio_register_port(psif->io);
9241 + platform_set_drvdata(pdev, psif);
9242 +
9243 + dev_info(&pdev->dev, "Atmel AVR32 PSIF PS/2 driver on 0x%08x irq %d\n",
9244 + (int)psif->regs, psif->irq);
9245 +
9246 + return 0;
9247 +
9248 +out_put_clk:
9249 + clk_put(psif->pclk);
9250 +out_iounmap:
9251 + iounmap(psif->regs);
9252 +out_free_io:
9253 + kfree(io);
9254 +out_free_psif:
9255 + kfree(psif);
9256 +out:
9257 + return ret;
9258 +}
9259 +
9260 +static int __exit psif_remove(struct platform_device *pdev)
9261 +{
9262 + struct psif *psif = platform_get_drvdata(pdev);
9263 +
9264 + psif_writel(psif, IDR, ~0UL);
9265 + psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
9266 +
9267 + serio_unregister_port(psif->io);
9268 + iounmap(psif->regs);
9269 + free_irq(psif->irq, psif);
9270 + clk_put(psif->pclk);
9271 + kfree(psif);
9272 +
9273 + platform_set_drvdata(pdev, NULL);
9274 +
9275 + return 0;
9276 +}
9277 +
9278 +#ifdef CONFIG_PM
9279 +static int psif_suspend(struct platform_device *pdev, pm_message_t state)
9280 +{
9281 + struct psif *psif = platform_get_drvdata(pdev);
9282 +
9283 + if (psif->open) {
9284 + psif_writel(psif, CR, PSIF_BIT(CR_RXDIS) | PSIF_BIT(CR_TXDIS));
9285 + clk_disable(psif->pclk);
9286 + }
9287 +
9288 + return 0;
9289 +}
9290 +
9291 +static int psif_resume(struct platform_device *pdev)
9292 +{
9293 + struct psif *psif = platform_get_drvdata(pdev);
9294 +
9295 + if (psif->open) {
9296 + clk_enable(psif->pclk);
9297 + psif_set_prescaler(psif);
9298 + psif_writel(psif, CR, PSIF_BIT(CR_RXEN) | PSIF_BIT(CR_TXEN));
9299 + }
9300 +
9301 + return 0;
9302 +}
9303 +#else
9304 +#define psif_suspend NULL
9305 +#define psif_resume NULL
9306 +#endif
9307 +
9308 +static struct platform_driver psif_driver = {
9309 + .remove = __exit_p(psif_remove),
9310 + .driver = {
9311 + .name = "atmel_psif",
9312 + },
9313 + .suspend = psif_suspend,
9314 + .resume = psif_resume,
9315 +};
9316 +
9317 +static int __init psif_init(void)
9318 +{
9319 + return platform_driver_probe(&psif_driver, psif_probe);
9320 +}
9321 +
9322 +static void __exit psif_exit(void)
9323 +{
9324 + platform_driver_unregister(&psif_driver);
9325 +}
9326 +
9327 +module_init(psif_init);
9328 +module_exit(psif_exit);
9329 +
9330 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
9331 +MODULE_DESCRIPTION("Atmel AVR32 PSIF PS/2 driver");
9332 +MODULE_LICENSE("GPL");
9333 --- /dev/null
9334 +++ b/drivers/input/serio/at32psif.h
9335 @@ -0,0 +1,82 @@
9336 +/*
9337 + * Copyright (C) 2007 Atmel Corporation
9338 + *
9339 + * Driver for the AT32AP700X PS/2 controller (PSIF).
9340 + *
9341 + * This program is free software; you can redistribute it and/or modify it
9342 + * under the terms of the GNU General Public License version 2 as published
9343 + * by the Free Software Foundation.
9344 + */
9345 +
9346 +#ifndef _AT32PSIF_H
9347 +#define _AT32PSIF_H
9348 +
9349 +/* PSIF register offsets */
9350 +#define PSIF_CR 0x00
9351 +#define PSIF_RHR 0x04
9352 +#define PSIF_THR 0x08
9353 +#define PSIF_SR 0x10
9354 +#define PSIF_IER 0x14
9355 +#define PSIF_IDR 0x18
9356 +#define PSIF_IMR 0x1c
9357 +#define PSIF_PSR 0x24
9358 +
9359 +/* Bitfields in control register. */
9360 +#define PSIF_CR_RXDIS_OFFSET 1
9361 +#define PSIF_CR_RXDIS_SIZE 1
9362 +#define PSIF_CR_RXEN_OFFSET 0
9363 +#define PSIF_CR_RXEN_SIZE 1
9364 +#define PSIF_CR_SWRST_OFFSET 15
9365 +#define PSIF_CR_SWRST_SIZE 1
9366 +#define PSIF_CR_TXDIS_OFFSET 9
9367 +#define PSIF_CR_TXDIS_SIZE 1
9368 +#define PSIF_CR_TXEN_OFFSET 8
9369 +#define PSIF_CR_TXEN_SIZE 1
9370 +
9371 +/* Bitfields in interrupt disable, enable, mask and status register. */
9372 +#define PSIF_NACK_OFFSET 8
9373 +#define PSIF_NACK_SIZE 1
9374 +#define PSIF_OVRUN_OFFSET 5
9375 +#define PSIF_OVRUN_SIZE 1
9376 +#define PSIF_PARITY_OFFSET 9
9377 +#define PSIF_PARITY_SIZE 1
9378 +#define PSIF_RXRDY_OFFSET 4
9379 +#define PSIF_RXRDY_SIZE 1
9380 +#define PSIF_TXEMPTY_OFFSET 1
9381 +#define PSIF_TXEMPTY_SIZE 1
9382 +#define PSIF_TXRDY_OFFSET 0
9383 +#define PSIF_TXRDY_SIZE 1
9384 +
9385 +/* Bitfields in prescale register. */
9386 +#define PSIF_PSR_PRSCV_OFFSET 0
9387 +#define PSIF_PSR_PRSCV_SIZE 12
9388 +
9389 +/* Bitfields in receive hold register. */
9390 +#define PSIF_RHR_RXDATA_OFFSET 0
9391 +#define PSIF_RHR_RXDATA_SIZE 8
9392 +
9393 +/* Bitfields in transmit hold register. */
9394 +#define PSIF_THR_TXDATA_OFFSET 0
9395 +#define PSIF_THR_TXDATA_SIZE 8
9396 +
9397 +/* Bit manipulation macros */
9398 +#define PSIF_BIT(name) \
9399 + (1 << PSIF_##name##_OFFSET)
9400 +#define PSIF_BF(name, value) \
9401 + (((value) & ((1 << PSIF_##name##_SIZE) - 1)) \
9402 + << PSIF_##name##_OFFSET)
9403 +#define PSIF_BFEXT(name, value)\
9404 + (((value) >> PSIF_##name##_OFFSET) \
9405 + & ((1 << PSIF_##name##_SIZE) - 1))
9406 +#define PSIF_BFINS(name, value, old) \
9407 + (((old) & ~(((1 << PSIF_##name##_SIZE) - 1) \
9408 + << PSIF_##name##_OFFSET)) \
9409 + | PSIF_BF(name, value))
9410 +
9411 +/* Register access macros */
9412 +#define psif_readl(port, reg) \
9413 + __raw_readl((port)->regs + PSIF_##reg)
9414 +#define psif_writel(port, reg, value) \
9415 + __raw_writel((value), (port)->regs + PSIF_##reg)
9416 +
9417 +#endif /* _AT32PSIF_H */
9418 --- a/drivers/misc/Kconfig
9419 +++ b/drivers/misc/Kconfig
9420 @@ -22,6 +22,39 @@
9421 purposes including software controlled power-efficent backlights
9422 on LCD displays, motor control, and waveform generation.
9423
9424 +config ATMEL_TCLIB
9425 + bool "Atmel AT32/AT91 Timer/Counter Library"
9426 + depends on (AVR32 || ARCH_AT91)
9427 + help
9428 + Select this if you want a library to allocate the Timer/Counter
9429 + blocks found on many Atmel processors. This facilitates using
9430 + these blocks by different drivers despite processor differences.
9431 +
9432 +config ATMEL_TCB_CLKSRC
9433 + bool "TC Block Clocksource"
9434 + depends on ATMEL_TCLIB && GENERIC_TIME
9435 + default y
9436 + help
9437 + Select this to get a high precision clocksource based on a
9438 + TC block with a 5+ MHz base clock rate. Two timer channels
9439 + are combined to make a single 32-bit timer.
9440 +
9441 + When GENERIC_CLOCKEVENTS is defined, the third timer channel
9442 + may be used as a clock event device supporting oneshot mode
9443 + (delays of up to two seconds) based on the 32 KiHz clock.
9444 +
9445 +config ATMEL_TCB_CLKSRC_BLOCK
9446 + int
9447 + depends on ATMEL_TCB_CLKSRC
9448 + prompt "TC Block" if ARCH_AT91RM9200 || ARCH_AT91SAM9260 || CPU_AT32AP700X
9449 + default 0
9450 + range 0 1
9451 + help
9452 + Some chips provide more than one TC block, so you have the
9453 + choice of which one to use for the clock framework. The other
9454 + TC can be used for other purposes, such as PWM generation and
9455 + interval timing.
9456 +
9457 config IBM_ASM
9458 tristate "Device driver for IBM RSA service processor"
9459 depends on X86 && PCI && INPUT && EXPERIMENTAL
9460 --- a/drivers/misc/Makefile
9461 +++ b/drivers/misc/Makefile
9462 @@ -10,6 +10,7 @@
9463 obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
9464 obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
9465 obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
9466 +obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
9467 obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o
9468 obj-$(CONFIG_LKDTM) += lkdtm.o
9469 obj-$(CONFIG_TIFM_CORE) += tifm_core.o
9470 --- /dev/null
9471 +++ b/drivers/misc/atmel_tclib.c
9472 @@ -0,0 +1,161 @@
9473 +#include <linux/atmel_tc.h>
9474 +#include <linux/clk.h>
9475 +#include <linux/err.h>
9476 +#include <linux/init.h>
9477 +#include <linux/io.h>
9478 +#include <linux/ioport.h>
9479 +#include <linux/kernel.h>
9480 +#include <linux/platform_device.h>
9481 +
9482 +/* Number of bytes to reserve for the iomem resource */
9483 +#define ATMEL_TC_IOMEM_SIZE 256
9484 +
9485 +
9486 +/*
9487 + * This is a thin library to solve the problem of how to portably allocate
9488 + * one of the TC blocks. For simplicity, it doesn't currently expect to
9489 + * share individual timers between different drivers.
9490 + */
9491 +
9492 +#if defined(CONFIG_AVR32)
9493 +/* AVR32 has these divide PBB */
9494 +const u8 atmel_tc_divisors[5] = { 0, 4, 8, 16, 32, };
9495 +EXPORT_SYMBOL(atmel_tc_divisors);
9496 +
9497 +#elif defined(CONFIG_ARCH_AT91)
9498 +/* AT91 has these divide MCK */
9499 +const u8 atmel_tc_divisors[5] = { 2, 8, 32, 128, 0, };
9500 +EXPORT_SYMBOL(atmel_tc_divisors);
9501 +
9502 +#endif
9503 +
9504 +static DEFINE_SPINLOCK(tc_list_lock);
9505 +static LIST_HEAD(tc_list);
9506 +
9507 +/**
9508 + * atmel_tc_alloc - allocate a specified TC block
9509 + * @block: which block to allocate
9510 + * @name: name to be associated with the iomem resource
9511 + *
9512 + * Caller allocates a block. If it is available, a pointer to a
9513 + * pre-initialized struct atmel_tc is returned. The caller can access
9514 + * the registers directly through the "regs" field.
9515 + */
9516 +struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name)
9517 +{
9518 + struct atmel_tc *tc;
9519 + struct platform_device *pdev = NULL;
9520 + struct resource *r;
9521 +
9522 + spin_lock(&tc_list_lock);
9523 + list_for_each_entry(tc, &tc_list, node) {
9524 + if (tc->pdev->id == block) {
9525 + pdev = tc->pdev;
9526 + break;
9527 + }
9528 + }
9529 +
9530 + if (!pdev || tc->iomem)
9531 + goto fail;
9532 +
9533 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9534 + r = request_mem_region(r->start, ATMEL_TC_IOMEM_SIZE, name);
9535 + if (!r)
9536 + goto fail;
9537 +
9538 + tc->regs = ioremap(r->start, ATMEL_TC_IOMEM_SIZE);
9539 + if (!tc->regs)
9540 + goto fail_ioremap;
9541 +
9542 + tc->iomem = r;
9543 +
9544 +out:
9545 + spin_unlock(&tc_list_lock);
9546 + return tc;
9547 +
9548 +fail_ioremap:
9549 + release_resource(r);
9550 +fail:
9551 + tc = NULL;
9552 + goto out;
9553 +}
9554 +EXPORT_SYMBOL_GPL(atmel_tc_alloc);
9555 +
9556 +/**
9557 + * atmel_tc_free - release a specified TC block
9558 + * @tc: Timer/counter block that was returned by atmel_tc_alloc()
9559 + *
9560 + * This reverses the effect of atmel_tc_alloc(), unmapping the I/O
9561 + * registers, invalidating the resource returned by that routine and
9562 + * making the TC available to other drivers.
9563 + */
9564 +void atmel_tc_free(struct atmel_tc *tc)
9565 +{
9566 + spin_lock(&tc_list_lock);
9567 + if (tc->regs) {
9568 + iounmap(tc->regs);
9569 + release_resource(tc->iomem);
9570 + tc->regs = NULL;
9571 + tc->iomem = NULL;
9572 + }
9573 + spin_unlock(&tc_list_lock);
9574 +}
9575 +EXPORT_SYMBOL_GPL(atmel_tc_free);
9576 +
9577 +static int __init tc_probe(struct platform_device *pdev)
9578 +{
9579 + struct atmel_tc *tc;
9580 + struct clk *clk;
9581 + int irq;
9582 +
9583 + if (!platform_get_resource(pdev, IORESOURCE_MEM, 0))
9584 + return -EINVAL;
9585 +
9586 + irq = platform_get_irq(pdev, 0);
9587 + if (irq < 0)
9588 + return -EINVAL;
9589 +
9590 + tc = kzalloc(sizeof(struct atmel_tc), GFP_KERNEL);
9591 + if (!tc)
9592 + return -ENOMEM;
9593 +
9594 + tc->pdev = pdev;
9595 +
9596 + clk = clk_get(&pdev->dev, "t0_clk");
9597 + if (IS_ERR(clk)) {
9598 + kfree(tc);
9599 + return -EINVAL;
9600 + }
9601 +
9602 + tc->clk[0] = clk;
9603 + tc->clk[1] = clk_get(&pdev->dev, "t1_clk");
9604 + if (IS_ERR(tc->clk[1]))
9605 + tc->clk[1] = clk;
9606 + tc->clk[2] = clk_get(&pdev->dev, "t2_clk");
9607 + if (IS_ERR(tc->clk[2]))
9608 + tc->clk[2] = clk;
9609 +
9610 + tc->irq[0] = irq;
9611 + tc->irq[1] = platform_get_irq(pdev, 1);
9612 + if (tc->irq[1] < 0)
9613 + tc->irq[1] = irq;
9614 + tc->irq[2] = platform_get_irq(pdev, 2);
9615 + if (tc->irq[2] < 0)
9616 + tc->irq[2] = irq;
9617 +
9618 + spin_lock(&tc_list_lock);
9619 + list_add_tail(&tc->node, &tc_list);
9620 + spin_unlock(&tc_list_lock);
9621 +
9622 + return 0;
9623 +}
9624 +
9625 +static struct platform_driver tc_driver = {
9626 + .driver.name = "atmel_tcb",
9627 +};
9628 +
9629 +static int __init tc_init(void)
9630 +{
9631 + return platform_driver_probe(&tc_driver, tc_probe);
9632 +}
9633 +arch_initcall(tc_init);
9634 --- a/drivers/mmc/host/Kconfig
9635 +++ b/drivers/mmc/host/Kconfig
9636 @@ -91,6 +91,16 @@
9637
9638 If unsure, say N.
9639
9640 +config MMC_ATMELMCI
9641 + tristate "Atmel Multimedia Card Interface support"
9642 + depends on AVR32 && MMC
9643 + help
9644 + This selects the Atmel Multimedia Card Interface. If you have
9645 + a AT91 (ARM) or AT32 (AVR32) platform with a Multimedia Card
9646 + slot, say Y or M here.
9647 +
9648 + If unsure, say N.
9649 +
9650 config MMC_IMX
9651 tristate "Motorola i.MX Multimedia Card Interface support"
9652 depends on ARCH_IMX
9653 --- a/drivers/mmc/host/Makefile
9654 +++ b/drivers/mmc/host/Makefile
9655 @@ -15,6 +15,7 @@
9656 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
9657 obj-$(CONFIG_MMC_OMAP) += omap.o
9658 obj-$(CONFIG_MMC_AT91) += at91_mci.o
9659 +obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
9660 obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
9661 obj-$(CONFIG_MMC_SPI) += mmc_spi.o
9662
9663 --- /dev/null
9664 +++ b/drivers/mmc/host/atmel-mci.c
9665 @@ -0,0 +1,1234 @@
9666 +/*
9667 + * Atmel MultiMedia Card Interface driver
9668 + *
9669 + * Copyright (C) 2004-2006 Atmel Corporation
9670 + *
9671 + * This program is free software; you can redistribute it and/or modify
9672 + * it under the terms of the GNU General Public License version 2 as
9673 + * published by the Free Software Foundation.
9674 + */
9675 +#include <linux/blkdev.h>
9676 +#include <linux/clk.h>
9677 +#include <linux/device.h>
9678 +#include <linux/dma-mapping.h>
9679 +#include <linux/init.h>
9680 +#include <linux/interrupt.h>
9681 +#include <linux/ioport.h>
9682 +#include <linux/module.h>
9683 +#include <linux/platform_device.h>
9684 +
9685 +#include <linux/mmc/host.h>
9686 +
9687 +#include <asm/dma-controller.h>
9688 +#include <asm/io.h>
9689 +#include <asm/arch/board.h>
9690 +#include <asm/arch/gpio.h>
9691 +
9692 +#include "atmel-mci.h"
9693 +
9694 +#define DRIVER_NAME "atmel_mci"
9695 +
9696 +#define MCI_DATA_ERROR_FLAGS (MCI_BIT(DCRCE) | MCI_BIT(DTOE) | \
9697 + MCI_BIT(OVRE) | MCI_BIT(UNRE))
9698 +
9699 +enum {
9700 + EVENT_CMD_COMPLETE = 0,
9701 + EVENT_DATA_COMPLETE,
9702 + EVENT_DATA_ERROR,
9703 + EVENT_STOP_SENT,
9704 + EVENT_STOP_COMPLETE,
9705 + EVENT_DMA_COMPLETE,
9706 + EVENT_DMA_ERROR,
9707 +};
9708 +
9709 +struct atmel_mci_dma {
9710 + struct dma_request_sg req;
9711 + unsigned short rx_periph_id;
9712 + unsigned short tx_periph_id;
9713 +};
9714 +
9715 +struct atmel_mci {
9716 + struct mmc_host *mmc;
9717 + void __iomem *regs;
9718 + struct atmel_mci_dma dma;
9719 +
9720 + struct mmc_request *mrq;
9721 + struct mmc_command *cmd;
9722 + struct mmc_data *data;
9723 +
9724 + u32 cmd_status;
9725 + u32 data_status;
9726 + u32 stop_status;
9727 + u32 stop_cmdr;
9728 +
9729 + struct tasklet_struct tasklet;
9730 + unsigned long pending_events;
9731 + unsigned long completed_events;
9732 +
9733 + int present;
9734 + int detect_pin;
9735 + int wp_pin;
9736 +
9737 + /* For detect pin debouncing */
9738 + struct timer_list detect_timer;
9739 +
9740 + unsigned long bus_hz;
9741 + unsigned long mapbase;
9742 + struct clk *mck;
9743 + struct platform_device *pdev;
9744 +
9745 + int pending_stop;
9746 +#ifdef CONFIG_DEBUG_FS
9747 + struct dentry *debugfs_root;
9748 + struct dentry *debugfs_regs;
9749 + struct dentry *debugfs_req;
9750 + struct dentry *debugfs_pending_events;
9751 + struct dentry *debugfs_completed_events;
9752 +#endif
9753 +};
9754 +
9755 +/* Those printks take an awful lot of time... */
9756 +#ifndef DEBUG
9757 +static unsigned int fmax = 15000000U;
9758 +#else
9759 +static unsigned int fmax = 1000000U;
9760 +#endif
9761 +module_param(fmax, uint, 0444);
9762 +MODULE_PARM_DESC(fmax, "Max frequency in Hz of the MMC bus clock");
9763 +
9764 +/* Test bit macros for completed events */
9765 +#define mci_cmd_is_complete(host) \
9766 + test_bit(EVENT_CMD_COMPLETE, &host->completed_events)
9767 +#define mci_data_is_complete(host) \
9768 + test_bit(EVENT_DATA_COMPLETE, &host->completed_events)
9769 +#define mci_data_error_is_complete(host) \
9770 + test_bit(EVENT_DATA_ERROR, &host->completed_events)
9771 +#define mci_stop_sent_is_complete(host) \
9772 + test_bit(EVENT_STOP_SENT, &host->completed_events)
9773 +#define mci_stop_is_complete(host) \
9774 + test_bit(EVENT_STOP_COMPLETE, &host->completed_events)
9775 +#define mci_dma_is_complete(host) \
9776 + test_bit(EVENT_DMA_COMPLETE, &host->completed_events)
9777 +#define mci_dma_error_is_complete(host) \
9778 + test_bit(EVENT_DMA_ERROR, &host->completed_events)
9779 +
9780 +/* Test and clear bit macros for pending events */
9781 +#define mci_clear_cmd_is_pending(host) \
9782 + test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
9783 +#define mci_clear_data_is_pending(host) \
9784 + test_and_clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
9785 +#define mci_clear_data_error_is_pending(host) \
9786 + test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)
9787 +#define mci_clear_stop_sent_is_pending(host) \
9788 + test_and_clear_bit(EVENT_STOP_SENT, &host->pending_events)
9789 +#define mci_clear_stop_is_pending(host) \
9790 + test_and_clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
9791 +#define mci_clear_dma_error_is_pending(host) \
9792 + test_and_clear_bit(EVENT_DMA_ERROR, &host->pending_events)
9793 +
9794 +/* Test and set bit macros for completed events */
9795 +#define mci_set_cmd_is_completed(host) \
9796 + test_and_set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
9797 +#define mci_set_data_is_completed(host) \
9798 + test_and_set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
9799 +#define mci_set_data_error_is_completed(host) \
9800 + test_and_set_bit(EVENT_DATA_ERROR, &host->completed_events)
9801 +#define mci_set_stop_sent_is_completed(host) \
9802 + test_and_set_bit(EVENT_STOP_SENT, &host->completed_events)
9803 +#define mci_set_stop_is_completed(host) \
9804 + test_and_set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
9805 +#define mci_set_dma_error_is_completed(host) \
9806 + test_and_set_bit(EVENT_DMA_ERROR, &host->completed_events)
9807 +
9808 +/* Set bit macros for completed events */
9809 +#define mci_set_cmd_complete(host) \
9810 + set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
9811 +#define mci_set_data_complete(host) \
9812 + set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
9813 +#define mci_set_data_error_complete(host) \
9814 + set_bit(EVENT_DATA_ERROR, &host->completed_events)
9815 +#define mci_set_stop_sent_complete(host) \
9816 + set_bit(EVENT_STOP_SENT, &host->completed_events)
9817 +#define mci_set_stop_complete(host) \
9818 + set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
9819 +#define mci_set_dma_complete(host) \
9820 + set_bit(EVENT_DMA_COMPLETE, &host->completed_events)
9821 +#define mci_set_dma_error_complete(host) \
9822 + set_bit(EVENT_DMA_ERROR, &host->completed_events)
9823 +
9824 +/* Set bit macros for pending events */
9825 +#define mci_set_cmd_pending(host) \
9826 + set_bit(EVENT_CMD_COMPLETE, &host->pending_events)
9827 +#define mci_set_data_pending(host) \
9828 + set_bit(EVENT_DATA_COMPLETE, &host->pending_events)
9829 +#define mci_set_data_error_pending(host) \
9830 + set_bit(EVENT_DATA_ERROR, &host->pending_events)
9831 +#define mci_set_stop_sent_pending(host) \
9832 + set_bit(EVENT_STOP_SENT, &host->pending_events)
9833 +#define mci_set_stop_pending(host) \
9834 + set_bit(EVENT_STOP_COMPLETE, &host->pending_events)
9835 +#define mci_set_dma_error_pending(host) \
9836 + set_bit(EVENT_DMA_ERROR, &host->pending_events)
9837 +
9838 +/* Clear bit macros for pending events */
9839 +#define mci_clear_cmd_pending(host) \
9840 + clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
9841 +#define mci_clear_data_pending(host) \
9842 + clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
9843 +#define mci_clear_data_error_pending(host) \
9844 + clear_bit(EVENT_DATA_ERROR, &host->pending_events)
9845 +#define mci_clear_stop_sent_pending(host) \
9846 + clear_bit(EVENT_STOP_SENT, &host->pending_events)
9847 +#define mci_clear_stop_pending(host) \
9848 + clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
9849 +#define mci_clear_dma_error_pending(host) \
9850 + clear_bit(EVENT_DMA_ERROR, &host->pending_events)
9851 +
9852 +
9853 +#ifdef CONFIG_DEBUG_FS
9854 +#include <linux/debugfs.h>
9855 +
9856 +#define DBG_REQ_BUF_SIZE (4096 - sizeof(unsigned int))
9857 +
9858 +struct req_dbg_data {
9859 + unsigned int nbytes;
9860 + char str[DBG_REQ_BUF_SIZE];
9861 +};
9862 +
9863 +static int req_dbg_open(struct inode *inode, struct file *file)
9864 +{
9865 + struct atmel_mci *host;
9866 + struct mmc_request *mrq;
9867 + struct mmc_command *cmd, *stop;
9868 + struct mmc_data *data;
9869 + struct req_dbg_data *priv;
9870 + char *str;
9871 + unsigned long n = 0;
9872 +
9873 + priv = kzalloc(DBG_REQ_BUF_SIZE, GFP_KERNEL);
9874 + if (!priv)
9875 + return -ENOMEM;
9876 + str = priv->str;
9877 +
9878 + mutex_lock(&inode->i_mutex);
9879 + host = inode->i_private;
9880 +
9881 + spin_lock_irq(&host->mmc->lock);
9882 + mrq = host->mrq;
9883 + if (mrq) {
9884 + cmd = mrq->cmd;
9885 + data = mrq->data;
9886 + stop = mrq->stop;
9887 + n = snprintf(str, DBG_REQ_BUF_SIZE,
9888 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
9889 + cmd->opcode, cmd->arg, cmd->flags,
9890 + cmd->resp[0], cmd->resp[1], cmd->resp[2],
9891 + cmd->resp[3], cmd->error);
9892 + if (n < DBG_REQ_BUF_SIZE && data)
9893 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
9894 + "DATA %u * %u (%u) %x (err %u)\n",
9895 + data->blocks, data->blksz,
9896 + data->bytes_xfered, data->flags,
9897 + data->error);
9898 + if (n < DBG_REQ_BUF_SIZE && stop)
9899 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
9900 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
9901 + stop->opcode, stop->arg, stop->flags,
9902 + stop->resp[0], stop->resp[1],
9903 + stop->resp[2], stop->resp[3],
9904 + stop->error);
9905 + }
9906 + spin_unlock_irq(&host->mmc->lock);
9907 + mutex_unlock(&inode->i_mutex);
9908 +
9909 + priv->nbytes = min(n, DBG_REQ_BUF_SIZE);
9910 + file->private_data = priv;
9911 +
9912 + return 0;
9913 +}
9914 +
9915 +static ssize_t req_dbg_read(struct file *file, char __user *buf,
9916 + size_t nbytes, loff_t *ppos)
9917 +{
9918 + struct req_dbg_data *priv = file->private_data;
9919 +
9920 + return simple_read_from_buffer(buf, nbytes, ppos,
9921 + priv->str, priv->nbytes);
9922 +}
9923 +
9924 +static int req_dbg_release(struct inode *inode, struct file *file)
9925 +{
9926 + kfree(file->private_data);
9927 + return 0;
9928 +}
9929 +
9930 +static const struct file_operations req_dbg_fops = {
9931 + .owner = THIS_MODULE,
9932 + .open = req_dbg_open,
9933 + .llseek = no_llseek,
9934 + .read = req_dbg_read,
9935 + .release = req_dbg_release,
9936 +};
9937 +
9938 +static int regs_dbg_open(struct inode *inode, struct file *file)
9939 +{
9940 + struct atmel_mci *host;
9941 + unsigned int i;
9942 + u32 *data;
9943 + int ret = -ENOMEM;
9944 +
9945 + mutex_lock(&inode->i_mutex);
9946 + host = inode->i_private;
9947 + data = kmalloc(inode->i_size, GFP_KERNEL);
9948 + if (!data)
9949 + goto out;
9950 +
9951 + spin_lock_irq(&host->mmc->lock);
9952 + for (i = 0; i < inode->i_size / 4; i++)
9953 + data[i] = __raw_readl(host->regs + i * 4);
9954 + spin_unlock_irq(&host->mmc->lock);
9955 +
9956 + file->private_data = data;
9957 + ret = 0;
9958 +
9959 +out:
9960 + mutex_unlock(&inode->i_mutex);
9961 +
9962 + return ret;
9963 +}
9964 +
9965 +static ssize_t regs_dbg_read(struct file *file, char __user *buf,
9966 + size_t nbytes, loff_t *ppos)
9967 +{
9968 + struct inode *inode = file->f_dentry->d_inode;
9969 + int ret;
9970 +
9971 + mutex_lock(&inode->i_mutex);
9972 + ret = simple_read_from_buffer(buf, nbytes, ppos,
9973 + file->private_data,
9974 + file->f_dentry->d_inode->i_size);
9975 + mutex_unlock(&inode->i_mutex);
9976 +
9977 + return ret;
9978 +}
9979 +
9980 +static int regs_dbg_release(struct inode *inode, struct file *file)
9981 +{
9982 + kfree(file->private_data);
9983 + return 0;
9984 +}
9985 +
9986 +static const struct file_operations regs_dbg_fops = {
9987 + .owner = THIS_MODULE,
9988 + .open = regs_dbg_open,
9989 + .llseek = generic_file_llseek,
9990 + .read = regs_dbg_read,
9991 + .release = regs_dbg_release,
9992 +};
9993 +
9994 +static void atmci_init_debugfs(struct atmel_mci *host)
9995 +{
9996 + struct mmc_host *mmc;
9997 + struct dentry *root, *regs;
9998 + struct resource *res;
9999 +
10000 + mmc = host->mmc;
10001 + root = debugfs_create_dir(mmc_hostname(mmc), NULL);
10002 + if (IS_ERR(root) || !root)
10003 + goto err_root;
10004 + host->debugfs_root = root;
10005 +
10006 + regs = debugfs_create_file("regs", 0400, root, host, &regs_dbg_fops);
10007 + if (!regs)
10008 + goto err_regs;
10009 +
10010 + res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
10011 + regs->d_inode->i_size = res->end - res->start + 1;
10012 + host->debugfs_regs = regs;
10013 +
10014 + host->debugfs_req = debugfs_create_file("req", 0400, root,
10015 + host, &req_dbg_fops);
10016 + if (!host->debugfs_req)
10017 + goto err_req;
10018 +
10019 + host->debugfs_pending_events
10020 + = debugfs_create_u32("pending_events", 0400, root,
10021 + (u32 *)&host->pending_events);
10022 + if (!host->debugfs_pending_events)
10023 + goto err_pending_events;
10024 +
10025 + host->debugfs_completed_events
10026 + = debugfs_create_u32("completed_events", 0400, root,
10027 + (u32 *)&host->completed_events);
10028 + if (!host->debugfs_completed_events)
10029 + goto err_completed_events;
10030 +
10031 + return;
10032 +
10033 +err_completed_events:
10034 + debugfs_remove(host->debugfs_pending_events);
10035 +err_pending_events:
10036 + debugfs_remove(host->debugfs_req);
10037 +err_req:
10038 + debugfs_remove(host->debugfs_regs);
10039 +err_regs:
10040 + debugfs_remove(host->debugfs_root);
10041 +err_root:
10042 + host->debugfs_root = NULL;
10043 + dev_err(&host->pdev->dev,
10044 + "failed to initialize debugfs for %s\n",
10045 + mmc_hostname(mmc));
10046 +}
10047 +
10048 +static void atmci_cleanup_debugfs(struct atmel_mci *host)
10049 +{
10050 + if (host->debugfs_root) {
10051 + debugfs_remove(host->debugfs_completed_events);
10052 + debugfs_remove(host->debugfs_pending_events);
10053 + debugfs_remove(host->debugfs_req);
10054 + debugfs_remove(host->debugfs_regs);
10055 + debugfs_remove(host->debugfs_root);
10056 + host->debugfs_root = NULL;
10057 + }
10058 +}
10059 +#else
10060 +static inline void atmci_init_debugfs(struct atmel_mci *host)
10061 +{
10062 +
10063 +}
10064 +
10065 +static inline void atmci_cleanup_debugfs(struct atmel_mci *host)
10066 +{
10067 +
10068 +}
10069 +#endif /* CONFIG_DEBUG_FS */
10070 +
10071 +static inline unsigned int ns_to_clocks(struct atmel_mci *host,
10072 + unsigned int ns)
10073 +{
10074 + return (ns * (host->bus_hz / 1000000) + 999) / 1000;
10075 +}
10076 +
10077 +static void atmci_set_timeout(struct atmel_mci *host,
10078 + struct mmc_data *data)
10079 +{
10080 + static unsigned dtomul_to_shift[] = {
10081 + 0, 4, 7, 8, 10, 12, 16, 20
10082 + };
10083 + unsigned timeout;
10084 + unsigned dtocyc, dtomul;
10085 +
10086 + timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
10087 +
10088 + for (dtomul = 0; dtomul < 8; dtomul++) {
10089 + unsigned shift = dtomul_to_shift[dtomul];
10090 + dtocyc = (timeout + (1 << shift) - 1) >> shift;
10091 + if (dtocyc < 15)
10092 + break;
10093 + }
10094 +
10095 + if (dtomul >= 8) {
10096 + dtomul = 7;
10097 + dtocyc = 15;
10098 + }
10099 +
10100 + dev_dbg(&host->mmc->class_dev, "setting timeout to %u cycles\n",
10101 + dtocyc << dtomul_to_shift[dtomul]);
10102 + mci_writel(host, DTOR, (MCI_BF(DTOMUL, dtomul)
10103 + | MCI_BF(DTOCYC, dtocyc)));
10104 +}
10105 +
10106 +/*
10107 + * Return mask with command flags to be enabled for this command.
10108 + */
10109 +static u32 atmci_prepare_command(struct mmc_host *mmc,
10110 + struct mmc_command *cmd)
10111 +{
10112 + u32 cmdr;
10113 +
10114 + cmd->error = 0;
10115 +
10116 + cmdr = MCI_BF(CMDNB, cmd->opcode);
10117 +
10118 + if (cmd->flags & MMC_RSP_PRESENT) {
10119 + if (cmd->flags & MMC_RSP_136)
10120 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_136_BIT);
10121 + else
10122 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_48_BIT);
10123 + }
10124 +
10125 + /*
10126 + * This should really be MAXLAT_5 for CMD2 and ACMD41, but
10127 + * it's too difficult to determine whether this is an ACMD or
10128 + * not. Better make it 64.
10129 + */
10130 + cmdr |= MCI_BIT(MAXLAT);
10131 +
10132 + if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
10133 + cmdr |= MCI_BIT(OPDCMD);
10134 +
10135 + dev_dbg(&mmc->class_dev,
10136 + "cmd: op %02x arg %08x flags %08x, cmdflags %08lx\n",
10137 + cmd->opcode, cmd->arg, cmd->flags, (unsigned long)cmdr);
10138 +
10139 + return cmdr;
10140 +}
10141 +
10142 +static void atmci_start_command(struct atmel_mci *host,
10143 + struct mmc_command *cmd,
10144 + u32 cmd_flags)
10145 +{
10146 + WARN_ON(host->cmd);
10147 + host->cmd = cmd;
10148 +
10149 + mci_writel(host, ARGR, cmd->arg);
10150 + mci_writel(host, CMDR, cmd_flags);
10151 +
10152 + if (cmd->data)
10153 + dma_start_request(host->dma.req.req.dmac,
10154 + host->dma.req.req.channel);
10155 +}
10156 +
10157 +/*
10158 + * Returns a mask of flags to be set in the command register when the
10159 + * command to start the transfer is to be sent.
10160 + */
10161 +static u32 atmci_prepare_data(struct mmc_host *mmc, struct mmc_data *data)
10162 +{
10163 + struct atmel_mci *host = mmc_priv(mmc);
10164 + u32 cmd_flags;
10165 +
10166 + WARN_ON(host->data);
10167 + host->data = data;
10168 +
10169 + atmci_set_timeout(host, data);
10170 + mci_writel(host, BLKR, (MCI_BF(BCNT, data->blocks)
10171 + | MCI_BF(BLKLEN, data->blksz)));
10172 + host->dma.req.block_size = data->blksz;
10173 + host->dma.req.nr_blocks = data->blocks;
10174 +
10175 + cmd_flags = MCI_BF(TRCMD, MCI_TRCMD_START_TRANS);
10176 + if (data->flags & MMC_DATA_STREAM)
10177 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
10178 + else if (data->blocks > 1)
10179 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
10180 + else
10181 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_BLOCK);
10182 +
10183 + if (data->flags & MMC_DATA_READ) {
10184 + cmd_flags |= MCI_BIT(TRDIR);
10185 + host->dma.req.nr_sg
10186 + = dma_map_sg(&host->pdev->dev, data->sg,
10187 + data->sg_len, DMA_FROM_DEVICE);
10188 + host->dma.req.periph_id = host->dma.rx_periph_id;
10189 + host->dma.req.direction = DMA_DIR_PERIPH_TO_MEM;
10190 + host->dma.req.data_reg = host->mapbase + MCI_RDR;
10191 + } else {
10192 + host->dma.req.nr_sg
10193 + = dma_map_sg(&host->pdev->dev, data->sg,
10194 + data->sg_len, DMA_TO_DEVICE);
10195 + host->dma.req.periph_id = host->dma.tx_periph_id;
10196 + host->dma.req.direction = DMA_DIR_MEM_TO_PERIPH;
10197 + host->dma.req.data_reg = host->mapbase + MCI_TDR;
10198 + }
10199 + host->dma.req.sg = data->sg;
10200 +
10201 + dma_prepare_request_sg(host->dma.req.req.dmac, &host->dma.req);
10202 +
10203 + return cmd_flags;
10204 +}
10205 +
10206 +static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
10207 +{
10208 + struct atmel_mci *host = mmc_priv(mmc);
10209 + struct mmc_data *data = mrq->data;
10210 + u32 iflags;
10211 + u32 cmdflags = 0;
10212 +
10213 + iflags = mci_readl(host, IMR);
10214 + if (iflags)
10215 + dev_warn(&mmc->class_dev, "WARNING: IMR=0x%08x\n",
10216 + mci_readl(host, IMR));
10217 +
10218 + WARN_ON(host->mrq != NULL);
10219 +
10220 + /*
10221 + * We may "know" the card is gone even though there's still an
10222 + * electrical connection. If so, we really need to communicate
10223 + * this to the MMC core since there won't be any more
10224 + * interrupts as the card is completely removed. Otherwise,
10225 + * the MMC core might believe the card is still there even
10226 + * though the card was just removed very slowly.
10227 + */
10228 + if (!host->present) {
10229 + mrq->cmd->error = -ENOMEDIUM;
10230 + mmc_request_done(mmc, mrq);
10231 + return;
10232 + }
10233 +
10234 + host->mrq = mrq;
10235 + host->pending_events = 0;
10236 + host->completed_events = 0;
10237 +
10238 + iflags = MCI_BIT(CMDRDY);
10239 + cmdflags = atmci_prepare_command(mmc, mrq->cmd);
10240 +
10241 + if (mrq->stop) {
10242 + WARN_ON(!data);
10243 +
10244 + host->stop_cmdr = atmci_prepare_command(mmc, mrq->stop);
10245 + host->stop_cmdr |= MCI_BF(TRCMD, MCI_TRCMD_STOP_TRANS);
10246 + if (!(data->flags & MMC_DATA_WRITE))
10247 + host->stop_cmdr |= MCI_BIT(TRDIR);
10248 + if (data->flags & MMC_DATA_STREAM)
10249 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
10250 + else
10251 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
10252 + }
10253 + if (data) {
10254 + cmdflags |= atmci_prepare_data(mmc, data);
10255 + iflags |= MCI_DATA_ERROR_FLAGS;
10256 + }
10257 +
10258 + atmci_start_command(host, mrq->cmd, cmdflags);
10259 + mci_writel(host, IER, iflags);
10260 +}
10261 +
10262 +static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
10263 +{
10264 + struct atmel_mci *host = mmc_priv(mmc);
10265 + u32 mr;
10266 +
10267 + if (ios->clock) {
10268 + u32 clkdiv;
10269 +
10270 + /* Set clock rate */
10271 + clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * ios->clock) - 1;
10272 + if (clkdiv > 255) {
10273 + dev_warn(&mmc->class_dev,
10274 + "clock %u too slow; using %lu\n",
10275 + ios->clock, host->bus_hz / (2 * 256));
10276 + clkdiv = 255;
10277 + }
10278 +
10279 + mr = mci_readl(host, MR);
10280 + mr = MCI_BFINS(CLKDIV, clkdiv, mr)
10281 + | MCI_BIT(WRPROOF) | MCI_BIT(RDPROOF);
10282 + mci_writel(host, MR, mr);
10283 +
10284 + /* Enable the MCI controller */
10285 + mci_writel(host, CR, MCI_BIT(MCIEN));
10286 + } else {
10287 + /* Disable the MCI controller */
10288 + mci_writel(host, CR, MCI_BIT(MCIDIS));
10289 + }
10290 +
10291 + switch (ios->bus_width) {
10292 + case MMC_BUS_WIDTH_1:
10293 + mci_writel(host, SDCR, 0);
10294 + break;
10295 + case MMC_BUS_WIDTH_4:
10296 + mci_writel(host, SDCR, MCI_BIT(SDCBUS));
10297 + break;
10298 + }
10299 +
10300 + switch (ios->power_mode) {
10301 + case MMC_POWER_ON:
10302 + /* Send init sequence (74 clock cycles) */
10303 + mci_writel(host, IDR, ~0UL);
10304 + mci_writel(host, CMDR, MCI_BF(SPCMD, MCI_SPCMD_INIT_CMD));
10305 + while (!(mci_readl(host, SR) & MCI_BIT(CMDRDY)))
10306 + cpu_relax();
10307 + break;
10308 + default:
10309 + /*
10310 + * TODO: None of the currently available AVR32-based
10311 + * boards allow MMC power to be turned off. Implement
10312 + * power control when this can be tested properly.
10313 + */
10314 + break;
10315 + }
10316 +}
10317 +
10318 +static int atmci_get_ro(struct mmc_host *mmc)
10319 +{
10320 + int read_only = 0;
10321 + struct atmel_mci *host = mmc_priv(mmc);
10322 +
10323 + if (host->wp_pin >= 0) {
10324 + read_only = gpio_get_value(host->wp_pin);
10325 + dev_dbg(&mmc->class_dev, "card is %s\n",
10326 + read_only ? "read-only" : "read-write");
10327 + } else {
10328 + dev_dbg(&mmc->class_dev,
10329 + "no pin for checking read-only switch."
10330 + " Assuming write-enable.\n");
10331 + }
10332 +
10333 + return read_only;
10334 +}
10335 +
10336 +static struct mmc_host_ops atmci_ops = {
10337 + .request = atmci_request,
10338 + .set_ios = atmci_set_ios,
10339 + .get_ro = atmci_get_ro,
10340 +};
10341 +
10342 +static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq)
10343 +{
10344 + struct atmel_mci *host = mmc_priv(mmc);
10345 +
10346 + WARN_ON(host->cmd || host->data);
10347 + host->mrq = NULL;
10348 +
10349 + mmc_request_done(mmc, mrq);
10350 +}
10351 +
10352 +static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data,
10353 + u32 flags)
10354 +{
10355 + struct atmel_mci *host = mmc_priv(mmc);
10356 +
10357 + atmci_start_command(host, data->stop, host->stop_cmdr | flags);
10358 + mci_writel(host, IER, MCI_BIT(CMDRDY));
10359 +}
10360 +
10361 +static void atmci_data_complete(struct atmel_mci *host, struct mmc_data *data)
10362 +{
10363 + host->data = NULL;
10364 + dma_unmap_sg(&host->pdev->dev, data->sg, host->dma.req.nr_sg,
10365 + ((data->flags & MMC_DATA_WRITE)
10366 + ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
10367 +
10368 + /*
10369 + * Data might complete before command for very short transfers
10370 + * (like READ_SCR)
10371 + */
10372 + if (mci_cmd_is_complete(host)
10373 + && (!data->stop || mci_stop_is_complete(host)))
10374 + atmci_request_end(host->mmc, data->mrq);
10375 +}
10376 +
10377 +static void atmci_command_complete(struct atmel_mci *host,
10378 + struct mmc_command *cmd, u32 status)
10379 +{
10380 + if (status & MCI_BIT(RTOE))
10381 + cmd->error = -ETIMEDOUT;
10382 + else if ((cmd->flags & MMC_RSP_CRC)
10383 + && (status & MCI_BIT(RCRCE)))
10384 + cmd->error = -EILSEQ;
10385 + else if (status & (MCI_BIT(RINDE) | MCI_BIT(RDIRE) | MCI_BIT(RENDE)))
10386 + cmd->error = -EIO;
10387 +
10388 + if (cmd->error) {
10389 + dev_dbg(&host->mmc->class_dev,
10390 + "command error: op=0x%x status=0x%08x\n",
10391 + cmd->opcode, status);
10392 +
10393 + if (cmd->data) {
10394 + dma_stop_request(host->dma.req.req.dmac,
10395 + host->dma.req.req.channel);
10396 + mci_writel(host, IDR, MCI_BIT(NOTBUSY)
10397 + | MCI_DATA_ERROR_FLAGS);
10398 + host->data = NULL;
10399 + }
10400 + }
10401 +}
10402 +
10403 +static void atmci_detect_change(unsigned long data)
10404 +{
10405 + struct atmel_mci *host = (struct atmel_mci *)data;
10406 + struct mmc_request *mrq = host->mrq;
10407 + int present;
10408 +
10409 + /*
10410 + * atmci_remove() sets detect_pin to -1 before freeing the
10411 + * interrupt. We must not re-enable the interrupt if it has
10412 + * been freed.
10413 + */
10414 + smp_rmb();
10415 + if (host->detect_pin < 0)
10416 + return;
10417 +
10418 + enable_irq(gpio_to_irq(host->detect_pin));
10419 + present = !gpio_get_value(host->detect_pin);
10420 +
10421 + dev_vdbg(&host->pdev->dev, "detect change: %d (was %d)\n",
10422 + present, host->present);
10423 +
10424 + if (present != host->present) {
10425 + dev_dbg(&host->mmc->class_dev, "card %s\n",
10426 + present ? "inserted" : "removed");
10427 + host->present = present;
10428 +
10429 + /* Reset controller if card is gone */
10430 + if (!present) {
10431 + mci_writel(host, CR, MCI_BIT(SWRST));
10432 + mci_writel(host, IDR, ~0UL);
10433 + mci_writel(host, CR, MCI_BIT(MCIEN));
10434 + }
10435 +
10436 + /* Clean up queue if present */
10437 + if (mrq) {
10438 + if (!mci_cmd_is_complete(host))
10439 + mrq->cmd->error = -ENOMEDIUM;
10440 + if (mrq->data && !mci_data_is_complete(host)
10441 + && !mci_data_error_is_complete(host)) {
10442 + dma_stop_request(host->dma.req.req.dmac,
10443 + host->dma.req.req.channel);
10444 + host->data->error = -ENOMEDIUM;
10445 + atmci_data_complete(host, host->data);
10446 + }
10447 + if (mrq->stop && !mci_stop_is_complete(host))
10448 + mrq->stop->error = -ENOMEDIUM;
10449 +
10450 + host->cmd = NULL;
10451 + atmci_request_end(host->mmc, mrq);
10452 + }
10453 +
10454 + mmc_detect_change(host->mmc, 0);
10455 + }
10456 +}
10457 +
10458 +static void atmci_tasklet_func(unsigned long priv)
10459 +{
10460 + struct mmc_host *mmc = (struct mmc_host *)priv;
10461 + struct atmel_mci *host = mmc_priv(mmc);
10462 + struct mmc_request *mrq = host->mrq;
10463 + struct mmc_data *data = host->data;
10464 +
10465 + dev_vdbg(&mmc->class_dev,
10466 + "tasklet: pending/completed/mask %lx/%lx/%x\n",
10467 + host->pending_events, host->completed_events,
10468 + mci_readl(host, IMR));
10469 +
10470 + if (mci_clear_cmd_is_pending(host)) {
10471 + mci_set_cmd_complete(host);
10472 + atmci_command_complete(host, mrq->cmd, host->cmd_status);
10473 + if (!host->data || mci_data_is_complete(host)
10474 + || mci_data_error_is_complete(host))
10475 + atmci_request_end(mmc, mrq);
10476 + }
10477 + if (mci_clear_stop_is_pending(host)) {
10478 + mci_set_stop_complete(host);
10479 + atmci_command_complete(host, mrq->stop, host->stop_status);
10480 + if (mci_data_is_complete(host)
10481 + || mci_data_error_is_complete(host))
10482 + atmci_request_end(mmc, mrq);
10483 + }
10484 + if (mci_clear_dma_error_is_pending(host)) {
10485 + mci_set_dma_error_complete(host);
10486 + mci_clear_data_pending(host);
10487 +
10488 + /* DMA controller got bus error => invalid address */
10489 + data->error = -EIO;
10490 +
10491 + dev_dbg(&mmc->class_dev, "dma error after %u bytes xfered\n",
10492 + host->data->bytes_xfered);
10493 +
10494 + if (data->stop
10495 + && !mci_set_stop_sent_is_completed(host))
10496 + /* TODO: Check if card is still present */
10497 + send_stop_cmd(host->mmc, data, 0);
10498 +
10499 + atmci_data_complete(host, data);
10500 + }
10501 + if (mci_clear_data_error_is_pending(host)) {
10502 + u32 status = host->data_status;
10503 +
10504 + mci_set_data_error_complete(host);
10505 + mci_clear_data_pending(host);
10506 +
10507 + dma_stop_request(host->dma.req.req.dmac,
10508 + host->dma.req.req.channel);
10509 +
10510 + if (status & MCI_BIT(DCRCE)) {
10511 + dev_dbg(&mmc->class_dev, "data CRC error\n");
10512 + data->error = -EILSEQ;
10513 + } else if (status & MCI_BIT(DTOE)) {
10514 + dev_dbg(&mmc->class_dev, "data timeout error\n");
10515 + data->error = -ETIMEDOUT;
10516 + } else {
10517 + dev_dbg(&mmc->class_dev, "data FIFO error\n");
10518 + data->error = -EIO;
10519 + }
10520 + dev_dbg(&mmc->class_dev, "bytes xfered: %u\n",
10521 + data->bytes_xfered);
10522 +
10523 + if (data->stop
10524 + && !mci_set_stop_sent_is_completed(host))
10525 + /* TODO: Check if card is still present */
10526 + send_stop_cmd(host->mmc, data, 0);
10527 +
10528 + atmci_data_complete(host, data);
10529 + }
10530 + if (mci_clear_data_is_pending(host)) {
10531 + mci_set_data_complete(host);
10532 + data->bytes_xfered = data->blocks * data->blksz;
10533 + atmci_data_complete(host, data);
10534 + }
10535 + /* See if there is a pending STOP which can be sent */
10536 + if (host->pending_stop && mci_cmd_is_complete(host)) {
10537 + host->pending_stop = 0;
10538 + if (mrq->stop && !mci_set_stop_sent_is_completed(host))
10539 + send_stop_cmd(host->mmc, mrq->data, 0);
10540 + }
10541 +}
10542 +
10543 +static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
10544 +{
10545 + struct atmel_mci *host = mmc_priv(mmc);
10546 + struct mmc_command *cmd = host->cmd;
10547 +
10548 + /*
10549 + * Read the response now so that we're free to send a new
10550 + * command immediately.
10551 + */
10552 + cmd->resp[0] = mci_readl(host, RSPR);
10553 + cmd->resp[1] = mci_readl(host, RSPR);
10554 + cmd->resp[2] = mci_readl(host, RSPR);
10555 + cmd->resp[3] = mci_readl(host, RSPR);
10556 +
10557 + mci_writel(host, IDR, MCI_BIT(CMDRDY));
10558 + host->cmd = NULL;
10559 +
10560 + if (mci_stop_sent_is_complete(host)) {
10561 + host->stop_status = status;
10562 + mci_set_stop_pending(host);
10563 + } else {
10564 + struct mmc_request *mrq = host->mrq;
10565 +
10566 + if (mrq->stop && mci_dma_is_complete(host)
10567 + && !mci_set_stop_sent_is_completed(host))
10568 + send_stop_cmd(host->mmc, mrq->data, 0);
10569 + host->cmd_status = status;
10570 + mci_set_cmd_pending(host);
10571 + }
10572 +
10573 + tasklet_schedule(&host->tasklet);
10574 +}
10575 +
10576 +static void atmci_xfer_complete(struct dma_request *_req)
10577 +{
10578 + struct dma_request_sg *req = to_dma_request_sg(_req);
10579 + struct atmel_mci_dma *dma;
10580 + struct atmel_mci *host;
10581 + struct mmc_data *data;
10582 +
10583 + dma = container_of(req, struct atmel_mci_dma, req);
10584 + host = container_of(dma, struct atmel_mci, dma);
10585 + data = host->data;
10586 +
10587 + /*
10588 + * This callback may be called before we see the CMDRDY
10589 + * interrupt under heavy irq load (possibly caused by other
10590 + * drivers) or when interrupts are disabled for a long time.
10591 + */
10592 + mci_set_dma_complete(host);
10593 +
10594 + if (data->stop) {
10595 + if (!mci_cmd_is_complete(host)) {
10596 + /* Just remember a STOP must be sent */
10597 + host->pending_stop = 1;
10598 + } else if (!mci_set_stop_sent_is_completed(host)) {
10599 + send_stop_cmd(host->mmc, data, 0);
10600 + host->pending_stop = 0;
10601 + }
10602 + }
10603 +
10604 + /*
10605 + * Regardless of what the documentation says, we have to wait
10606 + * for NOTBUSY even after block read operations.
10607 + *
10608 + * When the DMA transfer is complete, the controller may still
10609 + * be reading the CRC from the card, i.e. the data transfer is
10610 + * still in progress and we haven't seen all the potential
10611 + * error bits yet.
10612 + */
10613 + mci_writel(host, IER, MCI_BIT(NOTBUSY));
10614 +}
10615 +
10616 +static void atmci_dma_error(struct dma_request *_req)
10617 +{
10618 + struct dma_request_sg *req = to_dma_request_sg(_req);
10619 + struct atmel_mci_dma *dma;
10620 + struct atmel_mci *host;
10621 +
10622 + dma = container_of(req, struct atmel_mci_dma, req);
10623 + host = container_of(dma, struct atmel_mci, dma);
10624 +
10625 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
10626 + | MCI_DATA_ERROR_FLAGS));
10627 +
10628 + mci_set_dma_error_pending(host);
10629 + tasklet_schedule(&host->tasklet);
10630 +}
10631 +
10632 +static irqreturn_t atmci_interrupt(int irq, void *dev_id)
10633 +{
10634 + struct mmc_host *mmc = dev_id;
10635 + struct atmel_mci *host = mmc_priv(mmc);
10636 + u32 status, mask, pending;
10637 +
10638 + spin_lock(&mmc->lock);
10639 +
10640 + status = mci_readl(host, SR);
10641 + mask = mci_readl(host, IMR);
10642 + pending = status & mask;
10643 +
10644 + do {
10645 + if (pending & MCI_DATA_ERROR_FLAGS) {
10646 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
10647 + | MCI_DATA_ERROR_FLAGS));
10648 + host->data_status = status;
10649 + mci_set_data_error_pending(host);
10650 + tasklet_schedule(&host->tasklet);
10651 + break;
10652 + }
10653 + if (pending & MCI_BIT(CMDRDY))
10654 + atmci_cmd_interrupt(mmc, status);
10655 + if (pending & MCI_BIT(NOTBUSY)) {
10656 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
10657 + | MCI_DATA_ERROR_FLAGS));
10658 + mci_set_data_pending(host);
10659 + tasklet_schedule(&host->tasklet);
10660 + }
10661 +
10662 + status = mci_readl(host, SR);
10663 + mask = mci_readl(host, IMR);
10664 + pending = status & mask;
10665 + } while (pending);
10666 +
10667 + spin_unlock(&mmc->lock);
10668 +
10669 + return IRQ_HANDLED;
10670 +}
10671 +
10672 +static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
10673 +{
10674 + struct mmc_host *mmc = dev_id;
10675 + struct atmel_mci *host = mmc_priv(mmc);
10676 +
10677 + /*
10678 + * Disable interrupts until the pin has stabilized and check
10679 + * the state then. Use mod_timer() since we may be in the
10680 + * middle of the timer routine when this interrupt triggers.
10681 + */
10682 + disable_irq_nosync(irq);
10683 + mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20));
10684 +
10685 + return IRQ_HANDLED;
10686 +}
10687 +
10688 +static int __devinit atmci_probe(struct platform_device *pdev)
10689 +{
10690 + struct mci_platform_data *board;
10691 + struct atmel_mci *host;
10692 + struct mmc_host *mmc;
10693 + struct resource *regs;
10694 + int irq;
10695 + int ret;
10696 +
10697 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
10698 + if (!regs)
10699 + return -ENXIO;
10700 + irq = platform_get_irq(pdev, 0);
10701 + if (irq < 0)
10702 + return irq;
10703 +
10704 + board = pdev->dev.platform_data;
10705 +
10706 + mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev);
10707 + if (!mmc)
10708 + return -ENOMEM;
10709 +
10710 + host = mmc_priv(mmc);
10711 + host->pdev = pdev;
10712 + host->mmc = mmc;
10713 + if (board) {
10714 + host->detect_pin = board->detect_pin;
10715 + host->wp_pin = board->wp_pin;
10716 + } else {
10717 + host->detect_pin = -1;
10718 + host->wp_pin = -1;
10719 + }
10720 +
10721 + host->mck = clk_get(&pdev->dev, "mci_clk");
10722 + if (IS_ERR(host->mck)) {
10723 + ret = PTR_ERR(host->mck);
10724 + goto out_free_host;
10725 + }
10726 + clk_enable(host->mck);
10727 +
10728 + ret = -ENOMEM;
10729 + host->regs = ioremap(regs->start, regs->end - regs->start + 1);
10730 + if (!host->regs)
10731 + goto out_disable_clk;
10732 +
10733 + host->bus_hz = clk_get_rate(host->mck);
10734 + host->mapbase = regs->start;
10735 +
10736 + mmc->ops = &atmci_ops;
10737 + mmc->f_min = (host->bus_hz + 511) / 512;
10738 + mmc->f_max = min((unsigned int)(host->bus_hz / 2), fmax);
10739 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
10740 + mmc->caps |= MMC_CAP_4_BIT_DATA;
10741 +
10742 + tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc);
10743 +
10744 + ret = request_irq(irq, atmci_interrupt, 0, "mmci", mmc);
10745 + if (ret)
10746 + goto out_unmap;
10747 +
10748 + /* Assume card is present if we don't have a detect pin */
10749 + host->present = 1;
10750 + if (host->detect_pin >= 0) {
10751 + if (gpio_request(host->detect_pin, "mmc_detect")) {
10752 + dev_dbg(&mmc->class_dev, "no detect pin available\n");
10753 + host->detect_pin = -1;
10754 + } else {
10755 + host->present = !gpio_get_value(host->detect_pin);
10756 + }
10757 + }
10758 + if (host->wp_pin >= 0) {
10759 + if (gpio_request(host->wp_pin, "mmc_wp")) {
10760 + dev_dbg(&mmc->class_dev, "no WP pin available\n");
10761 + host->wp_pin = -1;
10762 + }
10763 + }
10764 +
10765 + /* TODO: Get this information from platform data */
10766 + ret = -ENOMEM;
10767 + host->dma.req.req.dmac = find_dma_controller(0);
10768 + if (!host->dma.req.req.dmac) {
10769 + dev_dbg(&mmc->class_dev, "no DMA controller available\n");
10770 + goto out_free_irq;
10771 + }
10772 + ret = dma_alloc_channel(host->dma.req.req.dmac);
10773 + if (ret < 0) {
10774 + dev_dbg(&mmc->class_dev, "unable to allocate DMA channel\n");
10775 + goto out_free_irq;
10776 + }
10777 + host->dma.req.req.channel = ret;
10778 + host->dma.req.width = DMA_WIDTH_32BIT;
10779 + host->dma.req.req.xfer_complete = atmci_xfer_complete;
10780 + host->dma.req.req.block_complete = NULL; // atmci_block_complete;
10781 + host->dma.req.req.error = atmci_dma_error;
10782 + host->dma.rx_periph_id = 0;
10783 + host->dma.tx_periph_id = 1;
10784 +
10785 + mci_writel(host, CR, MCI_BIT(SWRST));
10786 + mci_writel(host, IDR, ~0UL);
10787 +
10788 + platform_set_drvdata(pdev, host);
10789 +
10790 + mmc_add_host(mmc);
10791 +
10792 + if (host->detect_pin >= 0) {
10793 + setup_timer(&host->detect_timer, atmci_detect_change,
10794 + (unsigned long)host);
10795 +
10796 + ret = request_irq(gpio_to_irq(host->detect_pin),
10797 + atmci_detect_interrupt,
10798 + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
10799 + DRIVER_NAME, mmc);
10800 + if (ret) {
10801 + dev_dbg(&mmc->class_dev,
10802 + "could not request IRQ %d for detect pin\n",
10803 + gpio_to_irq(host->detect_pin));
10804 + gpio_free(host->detect_pin);
10805 + host->detect_pin = -1;
10806 + }
10807 + }
10808 +
10809 + dev_info(&mmc->class_dev, "Atmel MCI controller at 0x%08lx irq %d\n",
10810 + host->mapbase, irq);
10811 +
10812 + atmci_init_debugfs(host);
10813 +
10814 + return 0;
10815 +
10816 +out_free_irq:
10817 + if (host->detect_pin >= 0)
10818 + gpio_free(host->detect_pin);
10819 + if (host->wp_pin >= 0)
10820 + gpio_free(host->wp_pin);
10821 + free_irq(irq, mmc);
10822 +out_unmap:
10823 + iounmap(host->regs);
10824 +out_disable_clk:
10825 + clk_disable(host->mck);
10826 + clk_put(host->mck);
10827 +out_free_host:
10828 + mmc_free_host(mmc);
10829 + return ret;
10830 +}
10831 +
10832 +static int __devexit atmci_remove(struct platform_device *pdev)
10833 +{
10834 + struct atmel_mci *host = platform_get_drvdata(pdev);
10835 +
10836 + platform_set_drvdata(pdev, NULL);
10837 +
10838 + if (host) {
10839 + atmci_cleanup_debugfs(host);
10840 +
10841 + if (host->detect_pin >= 0) {
10842 + int pin = host->detect_pin;
10843 +
10844 + /* Make sure our timer doesn't enable the interrupt */
10845 + host->detect_pin = -1;
10846 + smp_wmb();
10847 +
10848 + free_irq(gpio_to_irq(pin), host->mmc);
10849 + del_timer_sync(&host->detect_timer);
10850 + cancel_delayed_work(&host->mmc->detect);
10851 + gpio_free(pin);
10852 + }
10853 +
10854 + mmc_remove_host(host->mmc);
10855 +
10856 + mci_writel(host, IDR, ~0UL);
10857 + mci_writel(host, CR, MCI_BIT(MCIDIS));
10858 + mci_readl(host, SR);
10859 +
10860 + dma_release_channel(host->dma.req.req.dmac,
10861 + host->dma.req.req.channel);
10862 +
10863 + if (host->wp_pin >= 0)
10864 + gpio_free(host->wp_pin);
10865 +
10866 + free_irq(platform_get_irq(pdev, 0), host->mmc);
10867 + iounmap(host->regs);
10868 +
10869 + clk_disable(host->mck);
10870 + clk_put(host->mck);
10871 +
10872 + mmc_free_host(host->mmc);
10873 + }
10874 + return 0;
10875 +}
10876 +
10877 +static struct platform_driver atmci_driver = {
10878 + .probe = atmci_probe,
10879 + .remove = __devexit_p(atmci_remove),
10880 + .driver = {
10881 + .name = DRIVER_NAME,
10882 + },
10883 +};
10884 +
10885 +static int __init atmci_init(void)
10886 +{
10887 + return platform_driver_register(&atmci_driver);
10888 +}
10889 +
10890 +static void __exit atmci_exit(void)
10891 +{
10892 + platform_driver_unregister(&atmci_driver);
10893 +}
10894 +
10895 +module_init(atmci_init);
10896 +module_exit(atmci_exit);
10897 +
10898 +MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
10899 +MODULE_LICENSE("GPL");
10900 --- /dev/null
10901 +++ b/drivers/mmc/host/atmel-mci.h
10902 @@ -0,0 +1,192 @@
10903 +/*
10904 + * Atmel MultiMedia Card Interface driver
10905 + *
10906 + * Copyright (C) 2004-2006 Atmel Corporation
10907 + *
10908 + * This program is free software; you can redistribute it and/or modify
10909 + * it under the terms of the GNU General Public License version 2 as
10910 + * published by the Free Software Foundation.
10911 + */
10912 +#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
10913 +#define __DRIVERS_MMC_ATMEL_MCI_H__
10914 +
10915 +/* MCI register offsets */
10916 +#define MCI_CR 0x0000
10917 +#define MCI_MR 0x0004
10918 +#define MCI_DTOR 0x0008
10919 +#define MCI_SDCR 0x000c
10920 +#define MCI_ARGR 0x0010
10921 +#define MCI_CMDR 0x0014
10922 +#define MCI_BLKR 0x0018
10923 +#define MCI_RSPR 0x0020
10924 +#define MCI_RSPR1 0x0024
10925 +#define MCI_RSPR2 0x0028
10926 +#define MCI_RSPR3 0x002c
10927 +#define MCI_RDR 0x0030
10928 +#define MCI_TDR 0x0034
10929 +#define MCI_SR 0x0040
10930 +#define MCI_IER 0x0044
10931 +#define MCI_IDR 0x0048
10932 +#define MCI_IMR 0x004c
10933 +
10934 +/* Bitfields in CR */
10935 +#define MCI_MCIEN_OFFSET 0
10936 +#define MCI_MCIEN_SIZE 1
10937 +#define MCI_MCIDIS_OFFSET 1
10938 +#define MCI_MCIDIS_SIZE 1
10939 +#define MCI_PWSEN_OFFSET 2
10940 +#define MCI_PWSEN_SIZE 1
10941 +#define MCI_PWSDIS_OFFSET 3
10942 +#define MCI_PWSDIS_SIZE 1
10943 +#define MCI_SWRST_OFFSET 7
10944 +#define MCI_SWRST_SIZE 1
10945 +
10946 +/* Bitfields in MR */
10947 +#define MCI_CLKDIV_OFFSET 0
10948 +#define MCI_CLKDIV_SIZE 8
10949 +#define MCI_PWSDIV_OFFSET 8
10950 +#define MCI_PWSDIV_SIZE 3
10951 +#define MCI_RDPROOF_OFFSET 11
10952 +#define MCI_RDPROOF_SIZE 1
10953 +#define MCI_WRPROOF_OFFSET 12
10954 +#define MCI_WRPROOF_SIZE 1
10955 +#define MCI_DMAPADV_OFFSET 14
10956 +#define MCI_DMAPADV_SIZE 1
10957 +#define MCI_BLKLEN_OFFSET 16
10958 +#define MCI_BLKLEN_SIZE 16
10959 +
10960 +/* Bitfields in DTOR */
10961 +#define MCI_DTOCYC_OFFSET 0
10962 +#define MCI_DTOCYC_SIZE 4
10963 +#define MCI_DTOMUL_OFFSET 4
10964 +#define MCI_DTOMUL_SIZE 3
10965 +
10966 +/* Bitfields in SDCR */
10967 +#define MCI_SDCSEL_OFFSET 0
10968 +#define MCI_SDCSEL_SIZE 4
10969 +#define MCI_SDCBUS_OFFSET 7
10970 +#define MCI_SDCBUS_SIZE 1
10971 +
10972 +/* Bitfields in ARGR */
10973 +#define MCI_ARG_OFFSET 0
10974 +#define MCI_ARG_SIZE 32
10975 +
10976 +/* Bitfields in CMDR */
10977 +#define MCI_CMDNB_OFFSET 0
10978 +#define MCI_CMDNB_SIZE 6
10979 +#define MCI_RSPTYP_OFFSET 6
10980 +#define MCI_RSPTYP_SIZE 2
10981 +#define MCI_SPCMD_OFFSET 8
10982 +#define MCI_SPCMD_SIZE 3
10983 +#define MCI_OPDCMD_OFFSET 11
10984 +#define MCI_OPDCMD_SIZE 1
10985 +#define MCI_MAXLAT_OFFSET 12
10986 +#define MCI_MAXLAT_SIZE 1
10987 +#define MCI_TRCMD_OFFSET 16
10988 +#define MCI_TRCMD_SIZE 2
10989 +#define MCI_TRDIR_OFFSET 18
10990 +#define MCI_TRDIR_SIZE 1
10991 +#define MCI_TRTYP_OFFSET 19
10992 +#define MCI_TRTYP_SIZE 2
10993 +
10994 +/* Bitfields in BLKR */
10995 +#define MCI_BCNT_OFFSET 0
10996 +#define MCI_BCNT_SIZE 16
10997 +
10998 +/* Bitfields in RSPRn */
10999 +#define MCI_RSP_OFFSET 0
11000 +#define MCI_RSP_SIZE 32
11001 +
11002 +/* Bitfields in SR/IER/IDR/IMR */
11003 +#define MCI_CMDRDY_OFFSET 0
11004 +#define MCI_CMDRDY_SIZE 1
11005 +#define MCI_RXRDY_OFFSET 1
11006 +#define MCI_RXRDY_SIZE 1
11007 +#define MCI_TXRDY_OFFSET 2
11008 +#define MCI_TXRDY_SIZE 1
11009 +#define MCI_BLKE_OFFSET 3
11010 +#define MCI_BLKE_SIZE 1
11011 +#define MCI_DTIP_OFFSET 4
11012 +#define MCI_DTIP_SIZE 1
11013 +#define MCI_NOTBUSY_OFFSET 5
11014 +#define MCI_NOTBUSY_SIZE 1
11015 +#define MCI_ENDRX_OFFSET 6
11016 +#define MCI_ENDRX_SIZE 1
11017 +#define MCI_ENDTX_OFFSET 7
11018 +#define MCI_ENDTX_SIZE 1
11019 +#define MCI_RXBUFF_OFFSET 14
11020 +#define MCI_RXBUFF_SIZE 1
11021 +#define MCI_TXBUFE_OFFSET 15
11022 +#define MCI_TXBUFE_SIZE 1
11023 +#define MCI_RINDE_OFFSET 16
11024 +#define MCI_RINDE_SIZE 1
11025 +#define MCI_RDIRE_OFFSET 17
11026 +#define MCI_RDIRE_SIZE 1
11027 +#define MCI_RCRCE_OFFSET 18
11028 +#define MCI_RCRCE_SIZE 1
11029 +#define MCI_RENDE_OFFSET 19
11030 +#define MCI_RENDE_SIZE 1
11031 +#define MCI_RTOE_OFFSET 20
11032 +#define MCI_RTOE_SIZE 1
11033 +#define MCI_DCRCE_OFFSET 21
11034 +#define MCI_DCRCE_SIZE 1
11035 +#define MCI_DTOE_OFFSET 22
11036 +#define MCI_DTOE_SIZE 1
11037 +#define MCI_OVRE_OFFSET 30
11038 +#define MCI_OVRE_SIZE 1
11039 +#define MCI_UNRE_OFFSET 31
11040 +#define MCI_UNRE_SIZE 1
11041 +
11042 +/* Constants for DTOMUL */
11043 +#define MCI_DTOMUL_1_CYCLE 0
11044 +#define MCI_DTOMUL_16_CYCLES 1
11045 +#define MCI_DTOMUL_128_CYCLES 2
11046 +#define MCI_DTOMUL_256_CYCLES 3
11047 +#define MCI_DTOMUL_1024_CYCLES 4
11048 +#define MCI_DTOMUL_4096_CYCLES 5
11049 +#define MCI_DTOMUL_65536_CYCLES 6
11050 +#define MCI_DTOMUL_1048576_CYCLES 7
11051 +
11052 +/* Constants for RSPTYP */
11053 +#define MCI_RSPTYP_NO_RESP 0
11054 +#define MCI_RSPTYP_48_BIT 1
11055 +#define MCI_RSPTYP_136_BIT 2
11056 +
11057 +/* Constants for SPCMD */
11058 +#define MCI_SPCMD_NO_SPEC_CMD 0
11059 +#define MCI_SPCMD_INIT_CMD 1
11060 +#define MCI_SPCMD_SYNC_CMD 2
11061 +#define MCI_SPCMD_INT_CMD 4
11062 +#define MCI_SPCMD_INT_RESP 5
11063 +
11064 +/* Constants for TRCMD */
11065 +#define MCI_TRCMD_NO_TRANS 0
11066 +#define MCI_TRCMD_START_TRANS 1
11067 +#define MCI_TRCMD_STOP_TRANS 2
11068 +
11069 +/* Constants for TRTYP */
11070 +#define MCI_TRTYP_BLOCK 0
11071 +#define MCI_TRTYP_MULTI_BLOCK 1
11072 +#define MCI_TRTYP_STREAM 2
11073 +
11074 +/* Bit manipulation macros */
11075 +#define MCI_BIT(name) \
11076 + (1 << MCI_##name##_OFFSET)
11077 +#define MCI_BF(name,value) \
11078 + (((value) & ((1 << MCI_##name##_SIZE) - 1)) \
11079 + << MCI_##name##_OFFSET)
11080 +#define MCI_BFEXT(name,value) \
11081 + (((value) >> MCI_##name##_OFFSET) \
11082 + & ((1 << MCI_##name##_SIZE) - 1))
11083 +#define MCI_BFINS(name,value,old) \
11084 + (((old) & ~(((1 << MCI_##name##_SIZE) - 1) \
11085 + << MCI_##name##_OFFSET)) \
11086 + | MCI_BF(name,value))
11087 +
11088 +/* Register access macros */
11089 +#define mci_readl(port,reg) \
11090 + __raw_readl((port)->regs + MCI_##reg)
11091 +#define mci_writel(port,reg,value) \
11092 + __raw_writel((value), (port)->regs + MCI_##reg)
11093 +
11094 +#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
11095 --- a/drivers/mtd/nand/Kconfig
11096 +++ b/drivers/mtd/nand/Kconfig
11097 @@ -272,12 +272,54 @@
11098
11099 If you say "m", the module will be called "cs553x_nand.ko".
11100
11101 -config MTD_NAND_AT91
11102 - bool "Support for NAND Flash / SmartMedia on AT91"
11103 - depends on ARCH_AT91
11104 +config MTD_NAND_ATMEL
11105 + bool "Support for NAND Flash / SmartMedia on AT91 and AVR32"
11106 + depends on ARCH_AT91 || AVR32
11107 help
11108 Enables support for NAND Flash / Smart Media Card interface
11109 - on Atmel AT91 processors.
11110 + on Atmel AT91 and AVR32 processors.
11111 +choice
11112 + prompt "ECC management for NAND Flash / SmartMedia on AT91 / AVR32"
11113 + depends on MTD_NAND_ATMEL
11114 +
11115 +config MTD_NAND_ATMEL_ECC_HW
11116 + bool "Hardware ECC"
11117 + depends on ARCH_AT91SAM9263 || ARCH_AT91SAM9260 || AVR32
11118 + help
11119 + Use hardware ECC instead of software ECC when the chip
11120 + supports it.
11121 +
11122 + The hardware ECC controller is capable of single bit error
11123 + correction and 2-bit random detection per page.
11124 +
11125 + NB : hardware and software ECC schemes are incompatible.
11126 + If you switch from one to another, you'll have to erase your
11127 + mtd partition.
11128 +
11129 + If unsure, say Y
11130 +
11131 +config MTD_NAND_ATMEL_ECC_SOFT
11132 + bool "Software ECC"
11133 + help
11134 + Use software ECC.
11135 +
11136 + NB : hardware and software ECC schemes are incompatible.
11137 + If you switch from one to another, you'll have to erase your
11138 + mtd partition.
11139 +
11140 +config MTD_NAND_ATMEL_ECC_NONE
11141 + bool "No ECC (testing only, DANGEROUS)"
11142 + depends on DEBUG_KERNEL
11143 + help
11144 + No ECC will be used.
11145 + It's not a good idea and it should be reserved for testing
11146 + purpose only.
11147 +
11148 + If unsure, say N
11149 +
11150 + endchoice
11151 +
11152 +endchoice
11153
11154 config MTD_NAND_CM_X270
11155 tristate "Support for NAND Flash on CM-X270 modules"
11156 --- a/drivers/mtd/nand/Makefile
11157 +++ b/drivers/mtd/nand/Makefile
11158 @@ -24,7 +24,7 @@
11159 obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
11160 obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
11161 obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o
11162 -obj-$(CONFIG_MTD_NAND_AT91) += at91_nand.o
11163 +obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o
11164 obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
11165 obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
11166 obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
11167 --- a/drivers/mtd/nand/at91_nand.c
11168 +++ /dev/null
11169 @@ -1,236 +0,0 @@
11170 -/*
11171 - * drivers/mtd/nand/at91_nand.c
11172 - *
11173 - * Copyright (C) 2003 Rick Bronson
11174 - *
11175 - * Derived from drivers/mtd/nand/autcpu12.c
11176 - * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
11177 - *
11178 - * Derived from drivers/mtd/spia.c
11179 - * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
11180 - *
11181 - * This program is free software; you can redistribute it and/or modify
11182 - * it under the terms of the GNU General Public License version 2 as
11183 - * published by the Free Software Foundation.
11184 - *
11185 - */
11186 -
11187 -#include <linux/slab.h>
11188 -#include <linux/module.h>
11189 -#include <linux/platform_device.h>
11190 -#include <linux/mtd/mtd.h>
11191 -#include <linux/mtd/nand.h>
11192 -#include <linux/mtd/partitions.h>
11193 -
11194 -#include <asm/io.h>
11195 -#include <asm/sizes.h>
11196 -
11197 -#include <asm/hardware.h>
11198 -#include <asm/arch/board.h>
11199 -#include <asm/arch/gpio.h>
11200 -
11201 -struct at91_nand_host {
11202 - struct nand_chip nand_chip;
11203 - struct mtd_info mtd;
11204 - void __iomem *io_base;
11205 - struct at91_nand_data *board;
11206 -};
11207 -
11208 -/*
11209 - * Hardware specific access to control-lines
11210 - */
11211 -static void at91_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
11212 -{
11213 - struct nand_chip *nand_chip = mtd->priv;
11214 - struct at91_nand_host *host = nand_chip->priv;
11215 -
11216 - if (cmd == NAND_CMD_NONE)
11217 - return;
11218 -
11219 - if (ctrl & NAND_CLE)
11220 - writeb(cmd, host->io_base + (1 << host->board->cle));
11221 - else
11222 - writeb(cmd, host->io_base + (1 << host->board->ale));
11223 -}
11224 -
11225 -/*
11226 - * Read the Device Ready pin.
11227 - */
11228 -static int at91_nand_device_ready(struct mtd_info *mtd)
11229 -{
11230 - struct nand_chip *nand_chip = mtd->priv;
11231 - struct at91_nand_host *host = nand_chip->priv;
11232 -
11233 - return at91_get_gpio_value(host->board->rdy_pin);
11234 -}
11235 -
11236 -/*
11237 - * Enable NAND.
11238 - */
11239 -static void at91_nand_enable(struct at91_nand_host *host)
11240 -{
11241 - if (host->board->enable_pin)
11242 - at91_set_gpio_value(host->board->enable_pin, 0);
11243 -}
11244 -
11245 -/*
11246 - * Disable NAND.
11247 - */
11248 -static void at91_nand_disable(struct at91_nand_host *host)
11249 -{
11250 - if (host->board->enable_pin)
11251 - at91_set_gpio_value(host->board->enable_pin, 1);
11252 -}
11253 -
11254 -#ifdef CONFIG_MTD_PARTITIONS
11255 -const char *part_probes[] = { "cmdlinepart", NULL };
11256 -#endif
11257 -
11258 -/*
11259 - * Probe for the NAND device.
11260 - */
11261 -static int __init at91_nand_probe(struct platform_device *pdev)
11262 -{
11263 - struct at91_nand_host *host;
11264 - struct mtd_info *mtd;
11265 - struct nand_chip *nand_chip;
11266 - int res;
11267 -
11268 -#ifdef CONFIG_MTD_PARTITIONS
11269 - struct mtd_partition *partitions = NULL;
11270 - int num_partitions = 0;
11271 -#endif
11272 -
11273 - /* Allocate memory for the device structure (and zero it) */
11274 - host = kzalloc(sizeof(struct at91_nand_host), GFP_KERNEL);
11275 - if (!host) {
11276 - printk(KERN_ERR "at91_nand: failed to allocate device structure.\n");
11277 - return -ENOMEM;
11278 - }
11279 -
11280 - host->io_base = ioremap(pdev->resource[0].start,
11281 - pdev->resource[0].end - pdev->resource[0].start + 1);
11282 - if (host->io_base == NULL) {
11283 - printk(KERN_ERR "at91_nand: ioremap failed\n");
11284 - kfree(host);
11285 - return -EIO;
11286 - }
11287 -
11288 - mtd = &host->mtd;
11289 - nand_chip = &host->nand_chip;
11290 - host->board = pdev->dev.platform_data;
11291 -
11292 - nand_chip->priv = host; /* link the private data structures */
11293 - mtd->priv = nand_chip;
11294 - mtd->owner = THIS_MODULE;
11295 -
11296 - /* Set address of NAND IO lines */
11297 - nand_chip->IO_ADDR_R = host->io_base;
11298 - nand_chip->IO_ADDR_W = host->io_base;
11299 - nand_chip->cmd_ctrl = at91_nand_cmd_ctrl;
11300 -
11301 - if (host->board->rdy_pin)
11302 - nand_chip->dev_ready = at91_nand_device_ready;
11303 -
11304 - nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
11305 - nand_chip->chip_delay = 20; /* 20us command delay time */
11306 -
11307 - if (host->board->bus_width_16) /* 16-bit bus width */
11308 - nand_chip->options |= NAND_BUSWIDTH_16;
11309 -
11310 - platform_set_drvdata(pdev, host);
11311 - at91_nand_enable(host);
11312 -
11313 - if (host->board->det_pin) {
11314 - if (at91_get_gpio_value(host->board->det_pin)) {
11315 - printk ("No SmartMedia card inserted.\n");
11316 - res = ENXIO;
11317 - goto out;
11318 - }
11319 - }
11320 -
11321 - /* Scan to find existance of the device */
11322 - if (nand_scan(mtd, 1)) {
11323 - res = -ENXIO;
11324 - goto out;
11325 - }
11326 -
11327 -#ifdef CONFIG_MTD_PARTITIONS
11328 -#ifdef CONFIG_MTD_CMDLINE_PARTS
11329 - mtd->name = "at91_nand";
11330 - num_partitions = parse_mtd_partitions(mtd, part_probes,
11331 - &partitions, 0);
11332 -#endif
11333 - if (num_partitions <= 0 && host->board->partition_info)
11334 - partitions = host->board->partition_info(mtd->size,
11335 - &num_partitions);
11336 -
11337 - if ((!partitions) || (num_partitions == 0)) {
11338 - printk(KERN_ERR "at91_nand: No parititions defined, or unsupported device.\n");
11339 - res = ENXIO;
11340 - goto release;
11341 - }
11342 -
11343 - res = add_mtd_partitions(mtd, partitions, num_partitions);
11344 -#else
11345 - res = add_mtd_device(mtd);
11346 -#endif
11347 -
11348 - if (!res)
11349 - return res;
11350 -
11351 -release:
11352 - nand_release(mtd);
11353 -out:
11354 - at91_nand_disable(host);
11355 - platform_set_drvdata(pdev, NULL);
11356 - iounmap(host->io_base);
11357 - kfree(host);
11358 - return res;
11359 -}
11360 -
11361 -/*
11362 - * Remove a NAND device.
11363 - */
11364 -static int __devexit at91_nand_remove(struct platform_device *pdev)
11365 -{
11366 - struct at91_nand_host *host = platform_get_drvdata(pdev);
11367 - struct mtd_info *mtd = &host->mtd;
11368 -
11369 - nand_release(mtd);
11370 -
11371 - at91_nand_disable(host);
11372 -
11373 - iounmap(host->io_base);
11374 - kfree(host);
11375 -
11376 - return 0;
11377 -}
11378 -
11379 -static struct platform_driver at91_nand_driver = {
11380 - .probe = at91_nand_probe,
11381 - .remove = at91_nand_remove,
11382 - .driver = {
11383 - .name = "at91_nand",
11384 - .owner = THIS_MODULE,
11385 - },
11386 -};
11387 -
11388 -static int __init at91_nand_init(void)
11389 -{
11390 - return platform_driver_register(&at91_nand_driver);
11391 -}
11392 -
11393 -
11394 -static void __exit at91_nand_exit(void)
11395 -{
11396 - platform_driver_unregister(&at91_nand_driver);
11397 -}
11398 -
11399 -
11400 -module_init(at91_nand_init);
11401 -module_exit(at91_nand_exit);
11402 -
11403 -MODULE_LICENSE("GPL");
11404 -MODULE_AUTHOR("Rick Bronson");
11405 -MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91RM9200");
11406 --- /dev/null
11407 +++ b/drivers/mtd/nand/atmel_nand.c
11408 @@ -0,0 +1,650 @@
11409 +/*
11410 + * Copyright (C) 2003 Rick Bronson
11411 + *
11412 + * Derived from drivers/mtd/nand/autcpu12.c
11413 + * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
11414 + *
11415 + * Derived from drivers/mtd/spia.c
11416 + * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
11417 + *
11418 + *
11419 + * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
11420 + * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
11421 + *
11422 + * Derived from Das U-Boot source code
11423 + * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
11424 + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
11425 + *
11426 + *
11427 + * This program is free software; you can redistribute it and/or modify
11428 + * it under the terms of the GNU General Public License version 2 as
11429 + * published by the Free Software Foundation.
11430 + *
11431 + */
11432 +
11433 +#include <linux/slab.h>
11434 +#include <linux/module.h>
11435 +#include <linux/platform_device.h>
11436 +#include <linux/mtd/mtd.h>
11437 +#include <linux/mtd/nand.h>
11438 +#include <linux/mtd/partitions.h>
11439 +
11440 +#include <linux/gpio.h>
11441 +#include <linux/io.h>
11442 +
11443 +#include <asm/arch/board.h>
11444 +#include <asm/arch/cpu.h>
11445 +
11446 +#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
11447 +#define hard_ecc 1
11448 +#else
11449 +#define hard_ecc 0
11450 +#endif
11451 +
11452 +#ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
11453 +#define no_ecc 1
11454 +#else
11455 +#define no_ecc 0
11456 +#endif
11457 +
11458 +/* Register access macros */
11459 +#define ecc_readl(add, reg) \
11460 + __raw_readl(add + ATMEL_ECC_##reg)
11461 +#define ecc_writel(add, reg, value) \
11462 + __raw_writel((value), add + ATMEL_ECC_##reg)
11463 +
11464 +#include "atmel_nand_ecc.h" /* Hardware ECC registers */
11465 +
11466 +/* oob layout for large page size
11467 + * bad block info is on bytes 0 and 1
11468 + * the bytes have to be consecutives to avoid
11469 + * several NAND_CMD_RNDOUT during read
11470 + */
11471 +static struct nand_ecclayout atmel_oobinfo_large = {
11472 + .eccbytes = 4,
11473 + .eccpos = {60, 61, 62, 63},
11474 + .oobfree = {
11475 + {2, 58}
11476 + },
11477 +};
11478 +
11479 +/* oob layout for small page size
11480 + * bad block info is on bytes 4 and 5
11481 + * the bytes have to be consecutives to avoid
11482 + * several NAND_CMD_RNDOUT during read
11483 + */
11484 +static struct nand_ecclayout atmel_oobinfo_small = {
11485 + .eccbytes = 4,
11486 + .eccpos = {0, 1, 2, 3},
11487 + .oobfree = {
11488 + {6, 10}
11489 + },
11490 +};
11491 +
11492 +struct atmel_nand_host {
11493 + struct nand_chip nand_chip;
11494 + struct mtd_info mtd;
11495 + void __iomem *io_base;
11496 + struct atmel_nand_data *board;
11497 + struct device *dev;
11498 + void __iomem *ecc;
11499 +};
11500 +
11501 +/*
11502 + * Enable NAND.
11503 + */
11504 +static void atmel_nand_enable(struct atmel_nand_host *host)
11505 +{
11506 + if (host->board->enable_pin)
11507 + gpio_set_value(host->board->enable_pin, 0);
11508 +}
11509 +
11510 +/*
11511 + * Disable NAND.
11512 + */
11513 +static void atmel_nand_disable(struct atmel_nand_host *host)
11514 +{
11515 + if (host->board->enable_pin)
11516 + gpio_set_value(host->board->enable_pin, 1);
11517 +}
11518 +
11519 +/*
11520 + * Hardware specific access to control-lines
11521 + */
11522 +static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
11523 +{
11524 + struct nand_chip *nand_chip = mtd->priv;
11525 + struct atmel_nand_host *host = nand_chip->priv;
11526 +
11527 + if (ctrl & NAND_CTRL_CHANGE) {
11528 + if (ctrl & NAND_NCE)
11529 + atmel_nand_enable(host);
11530 + else
11531 + atmel_nand_disable(host);
11532 + }
11533 + if (cmd == NAND_CMD_NONE)
11534 + return;
11535 +
11536 + if (ctrl & NAND_CLE)
11537 + writeb(cmd, host->io_base + (1 << host->board->cle));
11538 + else
11539 + writeb(cmd, host->io_base + (1 << host->board->ale));
11540 +}
11541 +
11542 +/*
11543 + * Read the Device Ready pin.
11544 + */
11545 +static int atmel_nand_device_ready(struct mtd_info *mtd)
11546 +{
11547 + struct nand_chip *nand_chip = mtd->priv;
11548 + struct atmel_nand_host *host = nand_chip->priv;
11549 +
11550 + return gpio_get_value(host->board->rdy_pin);
11551 +}
11552 +
11553 +/*
11554 + * Minimal-overhead PIO for data access.
11555 + */
11556 +static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
11557 +{
11558 + struct nand_chip *nand_chip = mtd->priv;
11559 +
11560 + __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
11561 +}
11562 +
11563 +static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
11564 +{
11565 + struct nand_chip *nand_chip = mtd->priv;
11566 +
11567 + __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
11568 +}
11569 +
11570 +static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
11571 +{
11572 + struct nand_chip *nand_chip = mtd->priv;
11573 +
11574 + __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
11575 +}
11576 +
11577 +static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
11578 +{
11579 + struct nand_chip *nand_chip = mtd->priv;
11580 +
11581 + __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
11582 +}
11583 +
11584 +/*
11585 + * write oob for small pages
11586 + */
11587 +static int atmel_nand_write_oob_512(struct mtd_info *mtd,
11588 + struct nand_chip *chip, int page)
11589 +{
11590 + int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
11591 + int eccsize = chip->ecc.size, length = mtd->oobsize;
11592 + int len, pos, status = 0;
11593 + const uint8_t *bufpoi = chip->oob_poi;
11594 +
11595 + pos = eccsize + chunk;
11596 +
11597 + chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
11598 + len = min_t(int, length, chunk);
11599 + chip->write_buf(mtd, bufpoi, len);
11600 + bufpoi += len;
11601 + length -= len;
11602 + if (length > 0)
11603 + chip->write_buf(mtd, bufpoi, length);
11604 +
11605 + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
11606 + status = chip->waitfunc(mtd, chip);
11607 +
11608 + return status & NAND_STATUS_FAIL ? -EIO : 0;
11609 +
11610 +}
11611 +
11612 +/*
11613 + * read oob for small pages
11614 + */
11615 +static int atmel_nand_read_oob_512(struct mtd_info *mtd,
11616 + struct nand_chip *chip, int page, int sndcmd)
11617 +{
11618 + if (sndcmd) {
11619 + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
11620 + sndcmd = 0;
11621 + }
11622 + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
11623 + return sndcmd;
11624 +}
11625 +
11626 +/*
11627 + * Calculate HW ECC
11628 + *
11629 + * function called after a write
11630 + *
11631 + * mtd: MTD block structure
11632 + * dat: raw data (unused)
11633 + * ecc_code: buffer for ECC
11634 + */
11635 +static int atmel_nand_calculate(struct mtd_info *mtd,
11636 + const u_char *dat, unsigned char *ecc_code)
11637 +{
11638 + struct nand_chip *nand_chip = mtd->priv;
11639 + struct atmel_nand_host *host = nand_chip->priv;
11640 + uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
11641 + unsigned int ecc_value;
11642 +
11643 + /* get the first 2 ECC bytes */
11644 + ecc_value = ecc_readl(host->ecc, PR);
11645 +
11646 + ecc_code[eccpos[0]] = ecc_value & 0xFF;
11647 + ecc_code[eccpos[1]] = (ecc_value >> 8) & 0xFF;
11648 +
11649 + /* get the last 2 ECC bytes */
11650 + ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
11651 +
11652 + ecc_code[eccpos[2]] = ecc_value & 0xFF;
11653 + ecc_code[eccpos[3]] = (ecc_value >> 8) & 0xFF;
11654 +
11655 + return 0;
11656 +}
11657 +
11658 +/*
11659 + * HW ECC read page function
11660 + *
11661 + * mtd: mtd info structure
11662 + * chip: nand chip info structure
11663 + * buf: buffer to store read data
11664 + */
11665 +static int atmel_nand_read_page(struct mtd_info *mtd,
11666 + struct nand_chip *chip, uint8_t *buf)
11667 +{
11668 + int eccsize = chip->ecc.size;
11669 + int eccbytes = chip->ecc.bytes;
11670 + uint32_t *eccpos = chip->ecc.layout->eccpos;
11671 + uint8_t *p = buf;
11672 + uint8_t *oob = chip->oob_poi;
11673 + uint8_t *ecc_pos;
11674 + int stat;
11675 +
11676 + /*
11677 + * Errata: ALE is incorrectly wired up to the ECC controller
11678 + * on the AP7000, so it will include the address cycles in the
11679 + * ECC calculation.
11680 + *
11681 + * Workaround: Reset the parity registers before reading the
11682 + * actual data.
11683 + */
11684 + if (cpu_is_at32ap7000()) {
11685 + struct atmel_nand_host *host = chip->priv;
11686 + ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
11687 + }
11688 +
11689 + /* read the page */
11690 + chip->read_buf(mtd, p, eccsize);
11691 +
11692 + /* move to ECC position if needed */
11693 + if (eccpos[0] != 0) {
11694 + /* This only works on large pages
11695 + * because the ECC controller waits for
11696 + * NAND_CMD_RNDOUTSTART after the
11697 + * NAND_CMD_RNDOUT.
11698 + * anyway, for small pages, the eccpos[0] == 0
11699 + */
11700 + chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
11701 + mtd->writesize + eccpos[0], -1);
11702 + }
11703 +
11704 + /* the ECC controller needs to read the ECC just after the data */
11705 + ecc_pos = oob + eccpos[0];
11706 + chip->read_buf(mtd, ecc_pos, eccbytes);
11707 +
11708 + /* check if there's an error */
11709 + stat = chip->ecc.correct(mtd, p, oob, NULL);
11710 +
11711 + if (stat < 0)
11712 + mtd->ecc_stats.failed++;
11713 + else
11714 + mtd->ecc_stats.corrected += stat;
11715 +
11716 + /* get back to oob start (end of page) */
11717 + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
11718 +
11719 + /* read the oob */
11720 + chip->read_buf(mtd, oob, mtd->oobsize);
11721 +
11722 + return 0;
11723 +}
11724 +
11725 +/*
11726 + * HW ECC Correction
11727 + *
11728 + * function called after a read
11729 + *
11730 + * mtd: MTD block structure
11731 + * dat: raw data read from the chip
11732 + * read_ecc: ECC from the chip (unused)
11733 + * isnull: unused
11734 + *
11735 + * Detect and correct a 1 bit error for a page
11736 + */
11737 +static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
11738 + u_char *read_ecc, u_char *isnull)
11739 +{
11740 + struct nand_chip *nand_chip = mtd->priv;
11741 + struct atmel_nand_host *host = nand_chip->priv;
11742 + unsigned int ecc_status;
11743 + unsigned int ecc_word, ecc_bit;
11744 +
11745 + /* get the status from the Status Register */
11746 + ecc_status = ecc_readl(host->ecc, SR);
11747 +
11748 + /* if there's no error */
11749 + if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
11750 + return 0;
11751 +
11752 + /* get error bit offset (4 bits) */
11753 + ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
11754 + /* get word address (12 bits) */
11755 + ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
11756 + ecc_word >>= 4;
11757 +
11758 + /* if there are multiple errors */
11759 + if (ecc_status & ATMEL_ECC_MULERR) {
11760 + /* check if it is a freshly erased block
11761 + * (filled with 0xff) */
11762 + if ((ecc_bit == ATMEL_ECC_BITADDR)
11763 + && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
11764 + /* the block has just been erased, return OK */
11765 + return 0;
11766 + }
11767 + /* it doesn't seems to be a freshly
11768 + * erased block.
11769 + * We can't correct so many errors */
11770 + dev_dbg(host->dev, "atmel_nand : multiple errors detected."
11771 + " Unable to correct.\n");
11772 + return -EIO;
11773 + }
11774 +
11775 + /* if there's a single bit error : we can correct it */
11776 + if (ecc_status & ATMEL_ECC_ECCERR) {
11777 + /* there's nothing much to do here.
11778 + * the bit error is on the ECC itself.
11779 + */
11780 + dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
11781 + " Nothing to correct\n");
11782 + return 0;
11783 + }
11784 +
11785 + dev_dbg(host->dev, "atmel_nand : one bit error on data."
11786 + " (word offset in the page :"
11787 + " 0x%x bit offset : 0x%x)\n",
11788 + ecc_word, ecc_bit);
11789 + /* correct the error */
11790 + if (nand_chip->options & NAND_BUSWIDTH_16) {
11791 + /* 16 bits words */
11792 + ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
11793 + } else {
11794 + /* 8 bits words */
11795 + dat[ecc_word] ^= (1 << ecc_bit);
11796 + }
11797 + dev_dbg(host->dev, "atmel_nand : error corrected\n");
11798 + return 1;
11799 +}
11800 +
11801 +/*
11802 + * Enable HW ECC : unused on most chips
11803 + */
11804 +static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
11805 +{
11806 + if (cpu_is_at32ap7000()) {
11807 + struct nand_chip *nand_chip = mtd->priv;
11808 + struct atmel_nand_host *host = nand_chip->priv;
11809 + ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
11810 + }
11811 +}
11812 +
11813 +#ifdef CONFIG_MTD_PARTITIONS
11814 +static const char *part_probes[] = { "cmdlinepart", NULL };
11815 +#endif
11816 +
11817 +/*
11818 + * Probe for the NAND device.
11819 + */
11820 +static int __init atmel_nand_probe(struct platform_device *pdev)
11821 +{
11822 + struct atmel_nand_host *host;
11823 + struct mtd_info *mtd;
11824 + struct nand_chip *nand_chip;
11825 + struct resource *regs;
11826 + struct resource *mem;
11827 + int res;
11828 +
11829 +#ifdef CONFIG_MTD_PARTITIONS
11830 + struct mtd_partition *partitions = NULL;
11831 + int num_partitions = 0;
11832 +#endif
11833 +
11834 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
11835 + if (!mem) {
11836 + printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
11837 + return -ENXIO;
11838 + }
11839 +
11840 + /* Allocate memory for the device structure (and zero it) */
11841 + host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
11842 + if (!host) {
11843 + printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
11844 + return -ENOMEM;
11845 + }
11846 +
11847 + host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
11848 + if (host->io_base == NULL) {
11849 + printk(KERN_ERR "atmel_nand: ioremap failed\n");
11850 + res = -EIO;
11851 + goto err_nand_ioremap;
11852 + }
11853 +
11854 + mtd = &host->mtd;
11855 + nand_chip = &host->nand_chip;
11856 + host->board = pdev->dev.platform_data;
11857 + host->dev = &pdev->dev;
11858 +
11859 + nand_chip->priv = host; /* link the private data structures */
11860 + mtd->priv = nand_chip;
11861 + mtd->owner = THIS_MODULE;
11862 +
11863 + /* Set address of NAND IO lines */
11864 + nand_chip->IO_ADDR_R = host->io_base;
11865 + nand_chip->IO_ADDR_W = host->io_base;
11866 + nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
11867 +
11868 + if (host->board->rdy_pin)
11869 + nand_chip->dev_ready = atmel_nand_device_ready;
11870 +
11871 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
11872 + if (!regs && hard_ecc) {
11873 + printk(KERN_ERR "atmel_nand: can't get I/O resource "
11874 + "regs\nFalling back on software ECC\n");
11875 + }
11876 +
11877 + nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
11878 + if (no_ecc)
11879 + nand_chip->ecc.mode = NAND_ECC_NONE;
11880 + if (hard_ecc && regs) {
11881 + host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
11882 + if (host->ecc == NULL) {
11883 + printk(KERN_ERR "atmel_nand: ioremap failed\n");
11884 + res = -EIO;
11885 + goto err_ecc_ioremap;
11886 + }
11887 + nand_chip->ecc.mode = NAND_ECC_HW_SYNDROME;
11888 + nand_chip->ecc.calculate = atmel_nand_calculate;
11889 + nand_chip->ecc.correct = atmel_nand_correct;
11890 + nand_chip->ecc.hwctl = atmel_nand_hwctl;
11891 + nand_chip->ecc.read_page = atmel_nand_read_page;
11892 + nand_chip->ecc.bytes = 4;
11893 + nand_chip->ecc.prepad = 0;
11894 + nand_chip->ecc.postpad = 0;
11895 + }
11896 +
11897 + nand_chip->chip_delay = 20; /* 20us command delay time */
11898 +
11899 + if (host->board->bus_width_16) { /* 16-bit bus width */
11900 + nand_chip->options |= NAND_BUSWIDTH_16;
11901 + nand_chip->read_buf = atmel_read_buf16;
11902 + nand_chip->write_buf = atmel_write_buf16;
11903 + } else {
11904 + nand_chip->read_buf = atmel_read_buf;
11905 + nand_chip->write_buf = atmel_write_buf;
11906 + }
11907 +
11908 + platform_set_drvdata(pdev, host);
11909 + atmel_nand_enable(host);
11910 +
11911 + if (host->board->det_pin) {
11912 + if (gpio_get_value(host->board->det_pin)) {
11913 + printk("No SmartMedia card inserted.\n");
11914 + res = ENXIO;
11915 + goto err_no_card;
11916 + }
11917 + }
11918 +
11919 + /* first scan to find the device and get the page size */
11920 + if (nand_scan_ident(mtd, 1)) {
11921 + res = -ENXIO;
11922 + goto err_scan_ident;
11923 + }
11924 +
11925 + if (nand_chip->ecc.mode == NAND_ECC_HW_SYNDROME) {
11926 + /* ECC is calculated for the whole page (1 step) */
11927 + nand_chip->ecc.size = mtd->writesize;
11928 +
11929 + /* set ECC page size and oob layout */
11930 + switch (mtd->writesize) {
11931 + case 512:
11932 + nand_chip->ecc.layout = &atmel_oobinfo_small;
11933 + nand_chip->ecc.read_oob = atmel_nand_read_oob_512;
11934 + nand_chip->ecc.write_oob = atmel_nand_write_oob_512;
11935 + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
11936 + break;
11937 + case 1024:
11938 + nand_chip->ecc.layout = &atmel_oobinfo_large;
11939 + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
11940 + break;
11941 + case 2048:
11942 + nand_chip->ecc.layout = &atmel_oobinfo_large;
11943 + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
11944 + break;
11945 + case 4096:
11946 + nand_chip->ecc.layout = &atmel_oobinfo_large;
11947 + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
11948 + break;
11949 + default:
11950 + /* page size not handled by HW ECC */
11951 + /* switching back to soft ECC */
11952 + nand_chip->ecc.mode = NAND_ECC_SOFT;
11953 + nand_chip->ecc.calculate = NULL;
11954 + nand_chip->ecc.correct = NULL;
11955 + nand_chip->ecc.hwctl = NULL;
11956 + nand_chip->ecc.read_page = NULL;
11957 + nand_chip->ecc.postpad = 0;
11958 + nand_chip->ecc.prepad = 0;
11959 + nand_chip->ecc.bytes = 0;
11960 + break;
11961 + }
11962 + }
11963 +
11964 + /* second phase scan */
11965 + if (nand_scan_tail(mtd)) {
11966 + res = -ENXIO;
11967 + goto err_scan_tail;
11968 + }
11969 +
11970 +#ifdef CONFIG_MTD_PARTITIONS
11971 +#ifdef CONFIG_MTD_CMDLINE_PARTS
11972 + mtd->name = "atmel_nand";
11973 + num_partitions = parse_mtd_partitions(mtd, part_probes,
11974 + &partitions, 0);
11975 +#endif
11976 + if (num_partitions <= 0 && host->board->partition_info)
11977 + partitions = host->board->partition_info(mtd->size,
11978 + &num_partitions);
11979 +
11980 + if ((!partitions) || (num_partitions == 0)) {
11981 + printk(KERN_ERR "atmel_nand: No parititions defined, or unsupported device.\n");
11982 + res = ENXIO;
11983 + goto err_no_partitions;
11984 + }
11985 +
11986 + res = add_mtd_partitions(mtd, partitions, num_partitions);
11987 +#else
11988 + res = add_mtd_device(mtd);
11989 +#endif
11990 +
11991 + if (!res)
11992 + return res;
11993 +
11994 +#ifdef CONFIG_MTD_PARTITIONS
11995 +err_no_partitions:
11996 +#endif
11997 + nand_release(mtd);
11998 +err_scan_tail:
11999 +err_scan_ident:
12000 +err_no_card:
12001 + atmel_nand_disable(host);
12002 + platform_set_drvdata(pdev, NULL);
12003 + if (host->ecc)
12004 + iounmap(host->ecc);
12005 +err_ecc_ioremap:
12006 + iounmap(host->io_base);
12007 +err_nand_ioremap:
12008 + kfree(host);
12009 + return res;
12010 +}
12011 +
12012 +/*
12013 + * Remove a NAND device.
12014 + */
12015 +static int __exit atmel_nand_remove(struct platform_device *pdev)
12016 +{
12017 + struct atmel_nand_host *host = platform_get_drvdata(pdev);
12018 + struct mtd_info *mtd = &host->mtd;
12019 +
12020 + nand_release(mtd);
12021 +
12022 + atmel_nand_disable(host);
12023 +
12024 + if (host->ecc)
12025 + iounmap(host->ecc);
12026 + iounmap(host->io_base);
12027 + kfree(host);
12028 +
12029 + return 0;
12030 +}
12031 +
12032 +static struct platform_driver atmel_nand_driver = {
12033 + .remove = __exit_p(atmel_nand_remove),
12034 + .driver = {
12035 + .name = "atmel_nand",
12036 + .owner = THIS_MODULE,
12037 + },
12038 +};
12039 +
12040 +static int __init atmel_nand_init(void)
12041 +{
12042 + return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
12043 +}
12044 +
12045 +
12046 +static void __exit atmel_nand_exit(void)
12047 +{
12048 + platform_driver_unregister(&atmel_nand_driver);
12049 +}
12050 +
12051 +
12052 +module_init(atmel_nand_init);
12053 +module_exit(atmel_nand_exit);
12054 +
12055 +MODULE_LICENSE("GPL");
12056 +MODULE_AUTHOR("Rick Bronson");
12057 +MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
12058 +MODULE_ALIAS("platform:atmel_nand");
12059 --- /dev/null
12060 +++ b/drivers/mtd/nand/atmel_nand_ecc.h
12061 @@ -0,0 +1,36 @@
12062 +/*
12063 + * Error Corrected Code Controller (ECC) - System peripherals regsters.
12064 + * Based on AT91SAM9260 datasheet revision B.
12065 + *
12066 + * This program is free software; you can redistribute it and/or modify it
12067 + * under the terms of the GNU General Public License as published by the
12068 + * Free Software Foundation; either version 2 of the License, or (at your
12069 + * option) any later version.
12070 + */
12071 +
12072 +#ifndef ATMEL_NAND_ECC_H
12073 +#define ATMEL_NAND_ECC_H
12074 +
12075 +#define ATMEL_ECC_CR 0x00 /* Control register */
12076 +#define ATMEL_ECC_RST (1 << 0) /* Reset parity */
12077 +
12078 +#define ATMEL_ECC_MR 0x04 /* Mode register */
12079 +#define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */
12080 +#define ATMEL_ECC_PAGESIZE_528 (0)
12081 +#define ATMEL_ECC_PAGESIZE_1056 (1)
12082 +#define ATMEL_ECC_PAGESIZE_2112 (2)
12083 +#define ATMEL_ECC_PAGESIZE_4224 (3)
12084 +
12085 +#define ATMEL_ECC_SR 0x08 /* Status register */
12086 +#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */
12087 +#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
12088 +#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */
12089 +
12090 +#define ATMEL_ECC_PR 0x0c /* Parity register */
12091 +#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
12092 +#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
12093 +
12094 +#define ATMEL_ECC_NPR 0x10 /* NParity register */
12095 +#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
12096 +
12097 +#endif
12098 --- a/drivers/mtd/nand/bf5xx_nand.c
12099 +++ b/drivers/mtd/nand/bf5xx_nand.c
12100 @@ -803,3 +803,4 @@
12101 MODULE_LICENSE("GPL");
12102 MODULE_AUTHOR(DRV_AUTHOR);
12103 MODULE_DESCRIPTION(DRV_DESC);
12104 +MODULE_ALIAS("platform:" DRV_NAME);
12105 --- a/drivers/mtd/nand/ndfc.c
12106 +++ b/drivers/mtd/nand/ndfc.c
12107 @@ -317,3 +317,5 @@
12108 MODULE_LICENSE("GPL");
12109 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
12110 MODULE_DESCRIPTION("Platform driver for NDFC");
12111 +MODULE_ALIAS("platform:ndfc-chip");
12112 +MODULE_ALIAS("platform:ndfc-nand");
12113 --- a/drivers/mtd/nand/orion_nand.c
12114 +++ b/drivers/mtd/nand/orion_nand.c
12115 @@ -169,3 +169,4 @@
12116 MODULE_LICENSE("GPL");
12117 MODULE_AUTHOR("Tzachi Perelstein");
12118 MODULE_DESCRIPTION("NAND glue for Orion platforms");
12119 +MODULE_ALIAS("platform:orion_nand");
12120 --- a/drivers/mtd/nand/plat_nand.c
12121 +++ b/drivers/mtd/nand/plat_nand.c
12122 @@ -161,3 +161,4 @@
12123 MODULE_LICENSE("GPL");
12124 MODULE_AUTHOR("Vitaly Wool");
12125 MODULE_DESCRIPTION("Simple generic NAND driver");
12126 +MODULE_ALIAS("platform:gen_nand");
12127 --- a/drivers/mtd/nand/s3c2410.c
12128 +++ b/drivers/mtd/nand/s3c2410.c
12129 @@ -927,3 +927,6 @@
12130 MODULE_LICENSE("GPL");
12131 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
12132 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
12133 +MODULE_ALIAS("platform:s3c2410-nand");
12134 +MODULE_ALIAS("platform:s3c2412-nand");
12135 +MODULE_ALIAS("platform:s3c2440-nand");
12136 --- a/drivers/net/macb.c
12137 +++ b/drivers/net/macb.c
12138 @@ -1277,8 +1277,45 @@
12139 return 0;
12140 }
12141
12142 +#ifdef CONFIG_PM
12143 +static int macb_suspend(struct platform_device *pdev, pm_message_t state)
12144 +{
12145 + struct net_device *netdev = platform_get_drvdata(pdev);
12146 + struct macb *bp = netdev_priv(netdev);
12147 +
12148 + netif_device_detach(netdev);
12149 +
12150 +#ifndef CONFIG_ARCH_AT91
12151 + clk_disable(bp->hclk);
12152 +#endif
12153 + clk_disable(bp->pclk);
12154 +
12155 + return 0;
12156 +}
12157 +
12158 +static int macb_resume(struct platform_device *pdev)
12159 +{
12160 + struct net_device *netdev = platform_get_drvdata(pdev);
12161 + struct macb *bp = netdev_priv(netdev);
12162 +
12163 + clk_enable(bp->pclk);
12164 +#ifndef CONFIG_ARCH_AT91
12165 + clk_enable(bp->hclk);
12166 +#endif
12167 +
12168 + netif_device_attach(netdev);
12169 +
12170 + return 0;
12171 +}
12172 +#else
12173 +#define macb_suspend NULL
12174 +#define macb_resume NULL
12175 +#endif
12176 +
12177 static struct platform_driver macb_driver = {
12178 .remove = __exit_p(macb_remove),
12179 + .suspend = macb_suspend,
12180 + .resume = macb_resume,
12181 .driver = {
12182 .name = "macb",
12183 },
12184 --- a/drivers/parport/Kconfig
12185 +++ b/drivers/parport/Kconfig
12186 @@ -36,7 +36,7 @@
12187 config PARPORT_PC
12188 tristate "PC-style hardware"
12189 depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \
12190 - (!M68K || ISA) && !MN10300
12191 + (!M68K || ISA) && !MN10300 && !AVR32
12192 ---help---
12193 You should say Y here if you have a PC-style parallel port. All
12194 IBM PC compatible computers and some Alphas have PC-style
12195 --- a/drivers/pcmcia/Kconfig
12196 +++ b/drivers/pcmcia/Kconfig
12197 @@ -277,6 +277,13 @@
12198 Say Y here to support the CompactFlash controller on the
12199 PA Semi Electra eval board.
12200
12201 +config AT32_CF
12202 + tristate "AT32AP CompactFlash Controller"
12203 + depends on PCMCIA && AVR32 && PLATFORM_AT32AP
12204 + help
12205 + Say Y here to support the CompactFlash controller on AT32 chips.
12206 + Or choose M to compile the driver as a module named "at32_cf".
12207 +
12208 config PCCARD_NONSTATIC
12209 tristate
12210
12211 --- a/drivers/pcmcia/Makefile
12212 +++ b/drivers/pcmcia/Makefile
12213 @@ -38,6 +38,7 @@
12214 obj-$(CONFIG_OMAP_CF) += omap_cf.o
12215 obj-$(CONFIG_AT91_CF) += at91_cf.o
12216 obj-$(CONFIG_ELECTRA_CF) += electra_cf.o
12217 +obj-$(CONFIG_AT32_CF) += at32_cf.o
12218
12219 sa11xx_core-y += soc_common.o sa11xx_base.o
12220 pxa2xx_core-y += soc_common.o pxa2xx_base.o
12221 --- /dev/null
12222 +++ b/drivers/pcmcia/at32_cf.c
12223 @@ -0,0 +1,533 @@
12224 +/*
12225 + * Driver for AVR32 Static Memory Controller: CompactFlash support
12226 + *
12227 + * Copyright (C) 2006 Atmel Norway
12228 + *
12229 + * This program is free software; you can redistribute it and/or
12230 + * modify it under the terms of the GNU General Public License as
12231 + * published by the Free Software Foundation; either version 2 of the
12232 + * License, or (at your option) any later version.
12233 + *
12234 + * This program is distributed in the hope that it will be useful, but
12235 + * WITHOUT ANY WARRANTY; without even the implied warranty of
12236 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12237 + * General Public License for more details.
12238 + *
12239 + * You should have received a copy of the GNU General Public License
12240 + * along with this program; if not, write to the Free Software
12241 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
12242 + * 02111-1307, USA.
12243 + *
12244 + * The full GNU General Public License is included in this
12245 + * distribution in the file called COPYING.
12246 + */
12247 +#include <linux/module.h>
12248 +#include <linux/kernel.h>
12249 +#include <linux/platform_device.h>
12250 +#include <linux/init.h>
12251 +#include <linux/device.h>
12252 +#include <linux/delay.h>
12253 +#include <linux/interrupt.h>
12254 +#include <linux/err.h>
12255 +#include <linux/clk.h>
12256 +#include <linux/dma-mapping.h>
12257 +
12258 +#include <pcmcia/ss.h>
12259 +
12260 +#include <asm/gpio.h>
12261 +#include <asm/io.h>
12262 +#include <asm/arch/board.h>
12263 +
12264 +#include <asm/arch/smc.h>
12265 +
12266 +struct at32_cf_socket {
12267 + struct pcmcia_socket socket;
12268 + int detect_pin;
12269 + int reset_pin;
12270 + int vcc_pin;
12271 + int ready_pin;
12272 + struct resource res_attr;
12273 + struct resource res_mem;
12274 + struct resource res_io;
12275 + struct smc_config smc;
12276 + unsigned int irq;
12277 + unsigned int cf_cs;
12278 + socket_state_t state;
12279 + unsigned present:1;
12280 +};
12281 +#define to_at32_cf(sock) container_of(sock, struct at32_cf_socket, socket)
12282 +
12283 +/*
12284 + * We have the following memory layout relative to the base address:
12285 + *
12286 + * Alt IDE Mode: 00e0 0000 -> 00ff ffff
12287 + * True IDE Mode: 00c0 0000 -> 00df ffff
12288 + * I/O memory: 0080 0000 -> 00bf ffff
12289 + * Common memory: 0040 0000 -> 007f ffff
12290 + * Attribute memory: 0000 0000 -> 003f ffff
12291 + */
12292 +#define CF_ATTR_OFFSET 0x00000000
12293 +#define CF_MEM_OFFSET 0x00400000
12294 +#define CF_IO_OFFSET 0x00800000
12295 +#define CF_RES_SIZE 4096
12296 +
12297 +#ifdef DEBUG
12298 +
12299 +static int pc_debug;
12300 +module_param(pc_debug, int, 0644);
12301 +
12302 +static void at32_cf_debug(struct at32_cf_socket *cf, const char *func,
12303 + int level, const char *fmt, ...)
12304 +{
12305 + va_list args;
12306 +
12307 + if (pc_debug > level) {
12308 + printk(KERN_DEBUG "at32_cf/%u: %s: ", cf->cf_cs, func);
12309 + va_start(args, fmt);
12310 + vprintk(fmt, args);
12311 + va_end(args);
12312 + }
12313 +}
12314 +
12315 +#define debug(cf, lvl, fmt, arg...) \
12316 + at32_cf_debug(cf, __func__, lvl, fmt, ##arg)
12317 +
12318 +#else
12319 +#define debug(cf, lvl, fmt, arg...) do { } while (0)
12320 +#endif
12321 +
12322 +static inline int at32_cf_present(struct at32_cf_socket *cf)
12323 +{
12324 + int present = 1;
12325 +
12326 + /* If we don't have a detect pin, assume the card is present */
12327 + if (cf->detect_pin >= 0)
12328 + present = !gpio_get_value(cf->detect_pin);
12329 +
12330 + return present;
12331 +}
12332 +
12333 +static irqreturn_t at32_cf_irq(int irq, void *dev_id)
12334 +{
12335 + struct at32_cf_socket *cf = dev_id;
12336 + unsigned int present;
12337 +
12338 + present = at32_cf_present(cf);
12339 + if (present != cf->present) {
12340 + cf->present = present;
12341 + debug(cf, 3, "card %s\n", present ? "present" : "gone");
12342 + pcmcia_parse_events(&cf->socket, SS_DETECT);
12343 + }
12344 +
12345 + return IRQ_HANDLED;
12346 +}
12347 +
12348 +static int at32_cf_get_status(struct pcmcia_socket *sock, u_int *value)
12349 +{
12350 + struct at32_cf_socket *cf;
12351 + u_int status = 0;
12352 +
12353 + cf = container_of(sock, struct at32_cf_socket, socket);
12354 +
12355 + if (at32_cf_present(cf)) {
12356 + /* NOTE: gpio on AP7xxx is 3.3V */
12357 + status = SS_DETECT | SS_3VCARD;
12358 + if (cf->ready_pin < 0 || gpio_get_value(cf->ready_pin))
12359 + status |= SS_READY;
12360 + if (cf->vcc_pin < 0 || gpio_get_value(cf->vcc_pin))
12361 + status |= SS_POWERON;
12362 + }
12363 +
12364 + *value = status;
12365 + return 0;
12366 +}
12367 +
12368 +static int at32_cf_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
12369 +{
12370 + struct at32_cf_socket *cf = container_of(sock, struct at32_cf_socket, socket);
12371 +
12372 + debug(cf, 2, "mask: %s%s%s%s%s%sflags: %s%s%s%s%s%sVcc %d Vpp %d irq %d\n",
12373 + (state->csc_mask==0)?"<NONE> ":"",
12374 + (state->csc_mask&SS_DETECT)?"DETECT ":"",
12375 + (state->csc_mask&SS_READY)?"READY ":"",
12376 + (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"",
12377 + (state->csc_mask&SS_BATWARN)?"BATWARN ":"",
12378 + (state->csc_mask&SS_STSCHG)?"STSCHG ":"",
12379 + (state->flags==0)?"<NONE> ":"",
12380 + (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"",
12381 + (state->flags&SS_IOCARD)?"IOCARD ":"",
12382 + (state->flags&SS_RESET)?"RESET ":"",
12383 + (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"",
12384 + (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"",
12385 + state->Vcc, state->Vpp, state->io_irq);
12386 +
12387 + /*
12388 + * TODO: Allow boards to override this in case they have level
12389 + * converters.
12390 + */
12391 + switch (state->Vcc) {
12392 + case 0:
12393 + if (cf->vcc_pin >= 0)
12394 + gpio_set_value(cf->vcc_pin, 0);
12395 + break;
12396 + case 33:
12397 + if (cf->vcc_pin >= 0)
12398 + gpio_set_value(cf->vcc_pin, 1);
12399 + break;
12400 + default:
12401 + return -EINVAL;
12402 + }
12403 +
12404 + if (cf->reset_pin >= 0)
12405 + gpio_set_value(cf->reset_pin, state->flags & SS_RESET);
12406 +
12407 + cf->state = *state;
12408 +
12409 + return 0;
12410 +}
12411 +
12412 +static int at32_cf_socket_init(struct pcmcia_socket *sock)
12413 +{
12414 + debug(to_at32_cf(sock), 2, "called\n");
12415 +
12416 + return 0;
12417 +}
12418 +
12419 +static int at32_cf_suspend(struct pcmcia_socket *sock)
12420 +{
12421 + debug(to_at32_cf(sock), 2, "called\n");
12422 +
12423 + at32_cf_set_socket(sock, &dead_socket);
12424 +
12425 + return 0;
12426 +}
12427 +
12428 +static int at32_cf_set_io_map(struct pcmcia_socket *sock,
12429 + struct pccard_io_map *map)
12430 +{
12431 + struct at32_cf_socket *cf = container_of(sock, struct at32_cf_socket, socket);
12432 + int retval;
12433 +
12434 + debug(cf, 2, "map %u speed %u start 0x%08x stop 0x%08x\n",
12435 + map->map, map->speed, map->start, map->stop);
12436 + debug(cf, 2, "flags: %s%s%s%s%s%s%s%s\n",
12437 + (map->flags == 0) ? "<NONE>":"",
12438 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
12439 + (map->flags & MAP_16BIT) ? "16BIT " : "",
12440 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
12441 + (map->flags & MAP_0WS) ? "0WS " : "",
12442 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
12443 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
12444 + (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
12445 +
12446 + map->flags &= MAP_ACTIVE | MAP_16BIT | MAP_USE_WAIT;
12447 +
12448 + if (map->flags & MAP_16BIT)
12449 + cf->smc.bus_width = 2;
12450 + else
12451 + cf->smc.bus_width = 1;
12452 +
12453 + if (map->flags & MAP_USE_WAIT)
12454 + cf->smc.nwait_mode = 3;
12455 + else
12456 + cf->smc.nwait_mode = 0;
12457 +
12458 + retval = smc_set_configuration(cf->cf_cs, &cf->smc);
12459 + if (retval) {
12460 + printk(KERN_ERR "at32_cf: could not set up SMC for I/O\n");
12461 + return retval;
12462 + }
12463 +
12464 + map->start = cf->socket.io_offset;
12465 + map->stop = map->start + CF_RES_SIZE - 1;
12466 +
12467 + return 0;
12468 +}
12469 +
12470 +static int
12471 +at32_cf_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map)
12472 +{
12473 + struct at32_cf_socket *cf;
12474 + struct resource *res;
12475 + int retval;
12476 +
12477 + cf = container_of(sock, struct at32_cf_socket, socket);
12478 +
12479 + debug(cf, 2, "map %u speed %u card_start %08x\n",
12480 + map->map, map->speed, map->card_start);
12481 + debug(cf, 2, "flags: %s%s%s%s%s%s%s%s\n",
12482 + (map->flags==0)?"<NONE>":"",
12483 + (map->flags&MAP_ACTIVE)?"ACTIVE ":"",
12484 + (map->flags&MAP_16BIT)?"16BIT ":"",
12485 + (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"",
12486 + (map->flags&MAP_0WS)?"0WS ":"",
12487 + (map->flags&MAP_WRPROT)?"WRPROT ":"",
12488 + (map->flags&MAP_ATTRIB)?"ATTRIB ":"",
12489 + (map->flags&MAP_USE_WAIT)?"USE_WAIT ":"");
12490 +
12491 + if (map->card_start)
12492 + return -EINVAL;
12493 +
12494 + map->flags &= MAP_ACTIVE | MAP_ATTRIB | MAP_16BIT | MAP_USE_WAIT;
12495 +
12496 + if (map->flags & MAP_ATTRIB) {
12497 + res = &cf->res_attr;
12498 +
12499 + /* Linksys WCF12 seems to use WAIT when reading CIS */
12500 + map->flags |= MAP_USE_WAIT;
12501 + } else {
12502 + res = &cf->res_mem;
12503 + }
12504 +
12505 + if (map->flags & MAP_USE_WAIT)
12506 + cf->smc.nwait_mode = 3;
12507 + else
12508 + cf->smc.nwait_mode = 0;
12509 +
12510 + retval = smc_set_configuration(cf->cf_cs, &cf->smc);
12511 + if (retval) {
12512 + printk(KERN_ERR "at32_cf: could not set up SMC for mem\n");
12513 + return retval;
12514 + }
12515 +
12516 + map->static_start = res->start;
12517 +
12518 + return 0;
12519 +}
12520 +
12521 +static struct pccard_operations at32_cf_ops = {
12522 + .init = at32_cf_socket_init,
12523 + .suspend = at32_cf_suspend,
12524 + .get_status = at32_cf_get_status,
12525 + .set_socket = at32_cf_set_socket,
12526 + .set_io_map = at32_cf_set_io_map,
12527 + .set_mem_map = at32_cf_set_mem_map,
12528 +};
12529 +
12530 +static int __init request_pin(struct platform_device *pdev,
12531 + unsigned int pin, const char *name)
12532 +{
12533 + if (gpio_request(pin, name)) {
12534 + dev_warn(&pdev->dev, "failed to request %s pin\n", name);
12535 + return -1;
12536 + }
12537 +
12538 + return pin;
12539 +}
12540 +
12541 +static struct smc_timing at32_cf_timing __initdata = {
12542 + .ncs_read_setup = 30,
12543 + .nrd_setup = 100,
12544 + .ncs_write_setup = 30,
12545 + .nwe_setup = 100,
12546 +
12547 + .ncs_read_pulse = 360,
12548 + .nrd_pulse = 290,
12549 + .ncs_write_pulse = 360,
12550 + .nwe_pulse = 290,
12551 +
12552 + .read_cycle = 420,
12553 + .write_cycle = 420,
12554 +};
12555 +
12556 +static int __init at32_cf_probe(struct platform_device *pdev)
12557 +{
12558 + struct at32_cf_socket *cf;
12559 + struct cf_platform_data *board = pdev->dev.platform_data;
12560 + struct resource *res_skt;
12561 + int irq;
12562 + int ret;
12563 +
12564 + dev_dbg(&pdev->dev, "probe");
12565 +
12566 + if (!board)
12567 + return -ENXIO;
12568 +
12569 + res_skt = platform_get_resource(pdev, IORESOURCE_MEM, 0);
12570 + if (!res_skt)
12571 + return -ENXIO;
12572 +
12573 + irq = platform_get_irq(pdev, 0);
12574 + if (irq < 0)
12575 + return irq;
12576 +
12577 + cf = kzalloc(sizeof(struct at32_cf_socket), GFP_KERNEL);
12578 + if (!cf)
12579 + return -ENOMEM;
12580 +
12581 + cf->detect_pin = -1;
12582 + cf->reset_pin = -1;
12583 + cf->vcc_pin = -1;
12584 + cf->ready_pin = -1;
12585 + cf->cf_cs = board->cs;
12586 +
12587 + if (board->detect_pin != GPIO_PIN_NONE)
12588 + cf->detect_pin = request_pin(pdev, board->detect_pin,
12589 + "cf_detect");
12590 + if (board->reset_pin != GPIO_PIN_NONE)
12591 + cf->reset_pin = request_pin(pdev, board->reset_pin,
12592 + "cf_reset");
12593 + if (board->vcc_pin != GPIO_PIN_NONE)
12594 + cf->vcc_pin = request_pin(pdev, board->vcc_pin,
12595 + "cf_vcc");
12596 + if (board->ready_pin != GPIO_PIN_NONE)
12597 + /* READY is also used for irq through EIM */
12598 + cf->ready_pin = board->ready_pin;
12599 +
12600 + debug(cf, 2, "pins: detect=%d reset=%d vcc=%d\n",
12601 + cf->detect_pin, cf->reset_pin, cf->vcc_pin);
12602 +
12603 + cf->socket.pci_irq = irq;
12604 + cf->socket.ops = &at32_cf_ops;
12605 + cf->socket.resource_ops = &pccard_static_ops;
12606 + cf->socket.dev.parent = &pdev->dev;
12607 + cf->socket.owner = THIS_MODULE;
12608 + cf->socket.features =
12609 + SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP | SS_CAP_PCCARD;
12610 + cf->socket.map_size = CF_RES_SIZE;
12611 +
12612 + cf->res_attr.start = res_skt->start + CF_ATTR_OFFSET;
12613 + cf->res_attr.end = cf->res_attr.start + CF_RES_SIZE - 1;
12614 + cf->res_attr.name = "attribute";
12615 + cf->res_attr.flags = IORESOURCE_MEM;
12616 + ret = request_resource(res_skt, &cf->res_attr);
12617 + if (ret)
12618 + goto err_request_res_attr;
12619 +
12620 + cf->res_mem.start = res_skt->start + CF_MEM_OFFSET;
12621 + cf->res_mem.end = cf->res_mem.start + CF_RES_SIZE - 1;
12622 + cf->res_mem.name = "memory";
12623 + cf->res_mem.flags = IORESOURCE_MEM;
12624 + ret = request_resource(res_skt, &cf->res_mem);
12625 + if (ret)
12626 + goto err_request_res_mem;
12627 +
12628 + cf->res_io.start = res_skt->start + CF_IO_OFFSET;
12629 + cf->res_io.end = cf->res_io.start + CF_RES_SIZE - 1;
12630 + cf->res_io.name = "io";
12631 + cf->res_io.flags = IORESOURCE_MEM;
12632 + ret = request_resource(res_skt, &cf->res_io);
12633 + if (ret)
12634 + goto err_request_res_io;
12635 +
12636 + cf->socket.io_offset = cf->res_io.start;
12637 +
12638 + if (cf->detect_pin >= 0) {
12639 + ret = request_irq(gpio_to_irq(cf->detect_pin), at32_cf_irq,
12640 + IRQF_SHARED, "cf_detect", cf);
12641 + if (ret) {
12642 + debug(cf, 1,
12643 + "failed to request cf_detect interrupt\n");
12644 + goto err_detect_irq;
12645 + }
12646 + }
12647 +
12648 + cf->present = at32_cf_present(cf);
12649 +
12650 + /* Setup SMC timings */
12651 + smc_set_timing(&cf->smc, &at32_cf_timing);
12652 +
12653 + cf->smc.bus_width = 2;
12654 + cf->smc.nrd_controlled = 1;
12655 + cf->smc.nwe_controlled = 1;
12656 + cf->smc.nwait_mode = 0;
12657 + cf->smc.byte_write = 0;
12658 + cf->smc.tdf_cycles = 8;
12659 + cf->smc.tdf_mode = 0;
12660 +
12661 + ret = smc_set_configuration(cf->cf_cs, &cf->smc);
12662 + if (ret) {
12663 + debug(cf, 1, "failed to configure SMC\n", ret);
12664 + goto err_smc;
12665 + }
12666 +
12667 + ret = pcmcia_register_socket(&cf->socket);
12668 + if (ret) {
12669 + debug(cf, 1, "failed to register socket: %d\n", ret);
12670 + goto err_register_socket;
12671 + }
12672 +
12673 + if (cf->reset_pin >= 0)
12674 + gpio_direction_output(cf->reset_pin, 0);
12675 +
12676 + platform_set_drvdata(pdev, cf);
12677 +
12678 + dev_info(&pdev->dev, "Atmel SMC CF interface at 0x%08lx\n",
12679 + (unsigned long)res_skt->start);
12680 +
12681 + return 0;
12682 +
12683 +err_register_socket:
12684 +err_smc:
12685 + if (cf->detect_pin >= 0)
12686 + free_irq(gpio_to_irq(cf->detect_pin), cf);
12687 +err_detect_irq:
12688 + release_resource(&cf->res_io);
12689 +err_request_res_io:
12690 + release_resource(&cf->res_mem);
12691 +err_request_res_mem:
12692 + release_resource(&cf->res_attr);
12693 +err_request_res_attr:
12694 + if (cf->vcc_pin >= 0)
12695 + gpio_free(cf->vcc_pin);
12696 + if (cf->reset_pin >= 0)
12697 + gpio_free(cf->reset_pin);
12698 + if (cf->detect_pin >= 0)
12699 + gpio_free(cf->detect_pin);
12700 + kfree(cf);
12701 +
12702 + return ret;
12703 +}
12704 +
12705 +static int __exit at32_cf_remove(struct platform_device *pdev)
12706 +{
12707 + struct at32_cf_socket *cf = platform_get_drvdata(pdev);
12708 +
12709 + pcmcia_unregister_socket(&cf->socket);
12710 + if (cf->detect_pin >= 0) {
12711 + free_irq(gpio_to_irq(cf->detect_pin), cf);
12712 + gpio_free(cf->detect_pin);
12713 + }
12714 + if (cf->vcc_pin >= 0)
12715 + gpio_free(cf->vcc_pin);
12716 + if (cf->reset_pin >= 0)
12717 + gpio_free(cf->reset_pin);
12718 +
12719 + release_resource(&cf->res_io);
12720 + release_resource(&cf->res_mem);
12721 + release_resource(&cf->res_attr);
12722 + kfree(cf);
12723 + platform_set_drvdata(pdev, NULL);
12724 +
12725 + return 0;
12726 +}
12727 +
12728 +static struct platform_driver at32_cf_driver = {
12729 + .remove = __exit_p(at32_cf_remove),
12730 + .driver = {
12731 + .name = "at32_cf",
12732 + .owner = THIS_MODULE,
12733 + },
12734 +};
12735 +
12736 +static int __init at32_cf_init(void)
12737 +{
12738 + int ret;
12739 +
12740 + ret = platform_driver_probe(&at32_cf_driver, at32_cf_probe);
12741 + if (ret)
12742 + printk(KERN_ERR "at32_cf: probe failed: %d\n", ret);
12743 + return ret;
12744 +}
12745 +
12746 +static void __exit at32_cf_exit(void)
12747 +{
12748 + platform_driver_unregister(&at32_cf_driver);
12749 +}
12750 +
12751 +module_init(at32_cf_init);
12752 +module_exit(at32_cf_exit);
12753 +
12754 +MODULE_LICENSE("GPL");
12755 +MODULE_DESCRIPTION("Driver for SMC PCMCIA interface");
12756 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
12757 --- a/drivers/rtc/rtc-at32ap700x.c
12758 +++ b/drivers/rtc/rtc-at32ap700x.c
12759 @@ -262,6 +262,7 @@
12760 }
12761
12762 platform_set_drvdata(pdev, rtc);
12763 + device_init_wakeup(&pdev->dev, 1);
12764
12765 dev_info(&pdev->dev, "Atmel RTC for AT32AP700x at %08lx irq %ld\n",
12766 (unsigned long)rtc->regs, rtc->irq);
12767 @@ -281,6 +282,8 @@
12768 {
12769 struct rtc_at32ap700x *rtc = platform_get_drvdata(pdev);
12770
12771 + device_init_wakeup(&pdev->dev, 0);
12772 +
12773 free_irq(rtc->irq, rtc);
12774 iounmap(rtc->regs);
12775 rtc_device_unregister(rtc->rtc);
12776 --- a/drivers/serial/atmel_serial.c
12777 +++ b/drivers/serial/atmel_serial.c
12778 @@ -957,6 +957,20 @@
12779 }
12780
12781 /*
12782 + * Flush any TX data submitted for DMA. Called when the TX circular
12783 + * buffer is reset.
12784 + */
12785 +static void atmel_flush_buffer(struct uart_port *port)
12786 +{
12787 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
12788 +
12789 + if (atmel_use_dma_tx(port)) {
12790 + UART_PUT_TCR(port, 0);
12791 + atmel_port->pdc_tx.ofs = 0;
12792 + }
12793 +}
12794 +
12795 +/*
12796 * Power / Clock management.
12797 */
12798 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
12799 @@ -1190,6 +1204,7 @@
12800 .break_ctl = atmel_break_ctl,
12801 .startup = atmel_startup,
12802 .shutdown = atmel_shutdown,
12803 + .flush_buffer = atmel_flush_buffer,
12804 .set_termios = atmel_set_termios,
12805 .type = atmel_type,
12806 .release_port = atmel_release_port,
12807 @@ -1440,6 +1455,15 @@
12808 };
12809
12810 #ifdef CONFIG_PM
12811 +static bool atmel_serial_clk_will_stop(void)
12812 +{
12813 +#ifdef CONFIG_ARCH_AT91
12814 + return at91_suspend_entering_slow_clock();
12815 +#else
12816 + return false;
12817 +#endif
12818 +}
12819 +
12820 static int atmel_serial_suspend(struct platform_device *pdev,
12821 pm_message_t state)
12822 {
12823 @@ -1447,7 +1471,7 @@
12824 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
12825
12826 if (device_may_wakeup(&pdev->dev)
12827 - && !at91_suspend_entering_slow_clock())
12828 + && !atmel_serial_clk_will_stop())
12829 enable_irq_wake(port->irq);
12830 else {
12831 uart_suspend_port(&atmel_uart, port);
12832 --- a/drivers/serial/serial_core.c
12833 +++ b/drivers/serial/serial_core.c
12834 @@ -552,6 +552,8 @@
12835
12836 spin_lock_irqsave(&port->lock, flags);
12837 uart_circ_clear(&state->info->xmit);
12838 + if (port->ops->flush_buffer)
12839 + port->ops->flush_buffer(port);
12840 spin_unlock_irqrestore(&port->lock, flags);
12841 tty_wakeup(tty);
12842 }
12843 --- a/drivers/spi/atmel_spi.c
12844 +++ b/drivers/spi/atmel_spi.c
12845 @@ -51,9 +51,7 @@
12846 u8 stopping;
12847 struct list_head queue;
12848 struct spi_transfer *current_transfer;
12849 - unsigned long current_remaining_bytes;
12850 - struct spi_transfer *next_transfer;
12851 - unsigned long next_remaining_bytes;
12852 + unsigned long remaining_bytes;
12853
12854 void *buffer;
12855 dma_addr_t buffer_dma;
12856 @@ -133,48 +131,6 @@
12857 gpio_set_value(gpio, !active);
12858 }
12859
12860 -static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
12861 - struct spi_transfer *xfer)
12862 -{
12863 - return msg->transfers.prev == &xfer->transfer_list;
12864 -}
12865 -
12866 -static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
12867 -{
12868 - return xfer->delay_usecs == 0 && !xfer->cs_change;
12869 -}
12870 -
12871 -static void atmel_spi_next_xfer_data(struct spi_master *master,
12872 - struct spi_transfer *xfer,
12873 - dma_addr_t *tx_dma,
12874 - dma_addr_t *rx_dma,
12875 - u32 *plen)
12876 -{
12877 - struct atmel_spi *as = spi_master_get_devdata(master);
12878 - u32 len = *plen;
12879 -
12880 - /* use scratch buffer only when rx or tx data is unspecified */
12881 - if (xfer->rx_buf)
12882 - *rx_dma = xfer->rx_dma + xfer->len - len;
12883 - else {
12884 - *rx_dma = as->buffer_dma;
12885 - if (len > BUFFER_SIZE)
12886 - len = BUFFER_SIZE;
12887 - }
12888 - if (xfer->tx_buf)
12889 - *tx_dma = xfer->tx_dma + xfer->len - len;
12890 - else {
12891 - *tx_dma = as->buffer_dma;
12892 - if (len > BUFFER_SIZE)
12893 - len = BUFFER_SIZE;
12894 - memset(as->buffer, 0, len);
12895 - dma_sync_single_for_device(&as->pdev->dev,
12896 - as->buffer_dma, len, DMA_TO_DEVICE);
12897 - }
12898 -
12899 - *plen = len;
12900 -}
12901 -
12902 /*
12903 * Submit next transfer for DMA.
12904 * lock is held, spi irq is blocked
12905 @@ -184,78 +140,53 @@
12906 {
12907 struct atmel_spi *as = spi_master_get_devdata(master);
12908 struct spi_transfer *xfer;
12909 - u32 len, remaining, total;
12910 + u32 len;
12911 dma_addr_t tx_dma, rx_dma;
12912
12913 - if (!as->current_transfer)
12914 - xfer = list_entry(msg->transfers.next,
12915 - struct spi_transfer, transfer_list);
12916 - else if (!as->next_transfer)
12917 - xfer = list_entry(as->current_transfer->transfer_list.next,
12918 - struct spi_transfer, transfer_list);
12919 - else
12920 - xfer = NULL;
12921 -
12922 - if (xfer) {
12923 - len = xfer->len;
12924 - atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
12925 - remaining = xfer->len - len;
12926 -
12927 - spi_writel(as, RPR, rx_dma);
12928 - spi_writel(as, TPR, tx_dma);
12929 -
12930 - if (msg->spi->bits_per_word > 8)
12931 - len >>= 1;
12932 - spi_writel(as, RCR, len);
12933 - spi_writel(as, TCR, len);
12934 -
12935 - dev_dbg(&msg->spi->dev,
12936 - " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
12937 - xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
12938 - xfer->rx_buf, xfer->rx_dma);
12939 - } else {
12940 - xfer = as->next_transfer;
12941 - remaining = as->next_remaining_bytes;
12942 + xfer = as->current_transfer;
12943 + if (!xfer || as->remaining_bytes == 0) {
12944 + if (xfer)
12945 + xfer = list_entry(xfer->transfer_list.next,
12946 + struct spi_transfer, transfer_list);
12947 + else
12948 + xfer = list_entry(msg->transfers.next,
12949 + struct spi_transfer, transfer_list);
12950 + as->remaining_bytes = xfer->len;
12951 + as->current_transfer = xfer;
12952 }
12953
12954 - as->current_transfer = xfer;
12955 - as->current_remaining_bytes = remaining;
12956 -
12957 - if (remaining > 0)
12958 - len = remaining;
12959 - else if (!atmel_spi_xfer_is_last(msg, xfer)
12960 - && atmel_spi_xfer_can_be_chained(xfer)) {
12961 - xfer = list_entry(xfer->transfer_list.next,
12962 - struct spi_transfer, transfer_list);
12963 - len = xfer->len;
12964 - } else
12965 - xfer = NULL;
12966 + len = as->remaining_bytes;
12967
12968 - as->next_transfer = xfer;
12969 + tx_dma = xfer->tx_dma + xfer->len - len;
12970 + rx_dma = xfer->rx_dma + xfer->len - len;
12971
12972 - if (xfer) {
12973 - total = len;
12974 - atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
12975 - as->next_remaining_bytes = total - len;
12976 -
12977 - spi_writel(as, RNPR, rx_dma);
12978 - spi_writel(as, TNPR, tx_dma);
12979 -
12980 - if (msg->spi->bits_per_word > 8)
12981 - len >>= 1;
12982 - spi_writel(as, RNCR, len);
12983 - spi_writel(as, TNCR, len);
12984 -
12985 - dev_dbg(&msg->spi->dev,
12986 - " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
12987 - xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
12988 - xfer->rx_buf, xfer->rx_dma);
12989 - } else {
12990 - spi_writel(as, RNCR, 0);
12991 - spi_writel(as, TNCR, 0);
12992 + /* use scratch buffer only when rx or tx data is unspecified */
12993 + if (!xfer->rx_buf) {
12994 + rx_dma = as->buffer_dma;
12995 + if (len > BUFFER_SIZE)
12996 + len = BUFFER_SIZE;
12997 }
12998 + if (!xfer->tx_buf) {
12999 + tx_dma = as->buffer_dma;
13000 + if (len > BUFFER_SIZE)
13001 + len = BUFFER_SIZE;
13002 + memset(as->buffer, 0, len);
13003 + dma_sync_single_for_device(&as->pdev->dev,
13004 + as->buffer_dma, len, DMA_TO_DEVICE);
13005 + }
13006 +
13007 + spi_writel(as, RPR, rx_dma);
13008 + spi_writel(as, TPR, tx_dma);
13009
13010 - /* REVISIT: We're waiting for ENDRX before we start the next
13011 + as->remaining_bytes -= len;
13012 + if (msg->spi->bits_per_word > 8)
13013 + len >>= 1;
13014 +
13015 + /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
13016 + * mechanism might help avoid the IRQ latency between transfers
13017 + * (and improve the nCS0 errata handling on at91rm9200 chips)
13018 + *
13019 + * We're also waiting for ENDRX before we start the next
13020 * transfer because we need to handle some difficult timing
13021 * issues otherwise. If we wait for ENDTX in one transfer and
13022 * then starts waiting for ENDRX in the next, it's difficult
13023 @@ -265,7 +196,17 @@
13024 *
13025 * It should be doable, though. Just not now...
13026 */
13027 + spi_writel(as, TNCR, 0);
13028 + spi_writel(as, RNCR, 0);
13029 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
13030 +
13031 + dev_dbg(&msg->spi->dev,
13032 + " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
13033 + xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
13034 + xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR));
13035 +
13036 + spi_writel(as, RCR, len);
13037 + spi_writel(as, TCR, len);
13038 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
13039 }
13040
13041 @@ -363,7 +304,6 @@
13042 spin_lock(&as->lock);
13043
13044 as->current_transfer = NULL;
13045 - as->next_transfer = NULL;
13046
13047 /* continue if needed */
13048 if (list_empty(&as->queue) || as->stopping)
13049 @@ -447,7 +387,7 @@
13050
13051 spi_writel(as, IDR, pending);
13052
13053 - if (as->current_remaining_bytes == 0) {
13054 + if (as->remaining_bytes == 0) {
13055 msg->actual_length += xfer->len;
13056
13057 if (!msg->is_dma_mapped)
13058 @@ -457,7 +397,7 @@
13059 if (xfer->delay_usecs)
13060 udelay(xfer->delay_usecs);
13061
13062 - if (atmel_spi_xfer_is_last(msg, xfer)) {
13063 + if (msg->transfers.prev == &xfer->transfer_list) {
13064 /* report completed message */
13065 atmel_spi_msg_done(master, as, msg, 0,
13066 xfer->cs_change);
13067 --- a/drivers/usb/gadget/Kconfig
13068 +++ b/drivers/usb/gadget/Kconfig
13069 @@ -118,10 +118,10 @@
13070 config USB_GADGET_ATMEL_USBA
13071 boolean "Atmel USBA"
13072 select USB_GADGET_DUALSPEED
13073 - depends on AVR32
13074 + depends on AVR32 || ARCH_AT91CAP9
13075 help
13076 USBA is the integrated high-speed USB Device controller on
13077 - the AT32AP700x processors from Atmel.
13078 + the AT32AP700x and AT91CAP9 processors from Atmel.
13079
13080 config USB_ATMEL_USBA
13081 tristate
13082 --- a/drivers/usb/gadget/atmel_usba_udc.c
13083 +++ b/drivers/usb/gadget/atmel_usba_udc.c
13084 @@ -18,6 +18,7 @@
13085 #include <linux/platform_device.h>
13086 #include <linux/usb/ch9.h>
13087 #include <linux/usb/gadget.h>
13088 +#include <linux/usb/atmel_usba_udc.h>
13089 #include <linux/delay.h>
13090
13091 #include <asm/gpio.h>
13092 @@ -27,6 +28,7 @@
13093
13094
13095 static struct usba_udc the_udc;
13096 +static struct usba_ep *usba_ep;
13097
13098 #ifdef CONFIG_USB_GADGET_DEBUG_FS
13099 #include <linux/debugfs.h>
13100 @@ -324,53 +326,28 @@
13101 return 1;
13102 }
13103
13104 -static void copy_to_fifo(void __iomem *fifo, const void *buf, int len)
13105 -{
13106 - unsigned long tmp;
13107 +#if defined(CONFIG_AVR32)
13108
13109 - DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
13110 - for (; len > 0; len -= 4, buf += 4, fifo += 4) {
13111 - tmp = *(unsigned long *)buf;
13112 - if (len >= 4) {
13113 - DBG(DBG_FIFO, " -> %08lx\n", tmp);
13114 - __raw_writel(tmp, fifo);
13115 - } else {
13116 - do {
13117 - DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
13118 - __raw_writeb(tmp >> 24, fifo);
13119 - fifo++;
13120 - tmp <<= 8;
13121 - } while (--len);
13122 - break;
13123 - }
13124 - }
13125 +static void toggle_bias(int is_on)
13126 +{
13127 }
13128
13129 -static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
13130 +#elif defined(CONFIG_ARCH_AT91)
13131 +
13132 +#include <asm/arch/at91_pmc.h>
13133 +
13134 +static void toggle_bias(int is_on)
13135 {
13136 - union {
13137 - unsigned long *w;
13138 - unsigned char *b;
13139 - } p;
13140 - unsigned long tmp;
13141 -
13142 - DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
13143 - for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
13144 - if (len >= 4) {
13145 - tmp = __raw_readl(fifo);
13146 - *p.w = tmp;
13147 - DBG(DBG_FIFO, " -> %08lx\n", tmp);
13148 - } else {
13149 - do {
13150 - tmp = __raw_readb(fifo);
13151 - *p.b = tmp;
13152 - DBG(DBG_FIFO, " -> %02lx\n", tmp);
13153 - fifo++, p.b++;
13154 - } while (--len);
13155 - }
13156 - }
13157 + unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
13158 +
13159 + if (is_on)
13160 + at91_sys_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
13161 + else
13162 + at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
13163 }
13164
13165 +#endif /* CONFIG_ARCH_AT91 */
13166 +
13167 static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
13168 {
13169 unsigned int transaction_len;
13170 @@ -387,7 +364,7 @@
13171 ep->ep.name, req, transaction_len,
13172 req->last_transaction ? ", done" : "");
13173
13174 - copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
13175 + memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
13176 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
13177 req->req.actual += transaction_len;
13178 }
13179 @@ -476,7 +453,7 @@
13180 bytecount = req->req.length - req->req.actual;
13181 }
13182
13183 - copy_from_fifo(req->req.buf + req->req.actual,
13184 + memcpy_fromio(req->req.buf + req->req.actual,
13185 ep->fifo, bytecount);
13186 req->req.actual += bytecount;
13187
13188 @@ -1029,33 +1006,6 @@
13189 .set_selfpowered = usba_udc_set_selfpowered,
13190 };
13191
13192 -#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
13193 -{ \
13194 - .ep = { \
13195 - .ops = &usba_ep_ops, \
13196 - .name = nam, \
13197 - .maxpacket = maxpkt, \
13198 - }, \
13199 - .udc = &the_udc, \
13200 - .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
13201 - .fifo_size = maxpkt, \
13202 - .nr_banks = maxbk, \
13203 - .index = idx, \
13204 - .can_dma = dma, \
13205 - .can_isoc = isoc, \
13206 -}
13207 -
13208 -static struct usba_ep usba_ep[] = {
13209 - EP("ep0", 0, 64, 1, 0, 0),
13210 - EP("ep1in-bulk", 1, 512, 2, 1, 1),
13211 - EP("ep2out-bulk", 2, 512, 2, 1, 1),
13212 - EP("ep3in-int", 3, 64, 3, 1, 0),
13213 - EP("ep4out-int", 4, 64, 3, 1, 0),
13214 - EP("ep5in-iso", 5, 1024, 3, 1, 1),
13215 - EP("ep6out-iso", 6, 1024, 3, 1, 1),
13216 -};
13217 -#undef EP
13218 -
13219 static struct usb_endpoint_descriptor usba_ep0_desc = {
13220 .bLength = USB_DT_ENDPOINT_SIZE,
13221 .bDescriptorType = USB_DT_ENDPOINT,
13222 @@ -1074,7 +1024,6 @@
13223 static struct usba_udc the_udc = {
13224 .gadget = {
13225 .ops = &usba_udc_ops,
13226 - .ep0 = &usba_ep[0].ep,
13227 .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
13228 .is_dualspeed = 1,
13229 .name = "atmel_usba_udc",
13230 @@ -1231,7 +1180,7 @@
13231 } else {
13232 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
13233 usba_writel(udc, TST, USBA_TST_PKT_MODE);
13234 - copy_to_fifo(ep->fifo, test_packet_buffer,
13235 + memcpy_toio(ep->fifo, test_packet_buffer,
13236 sizeof(test_packet_buffer));
13237 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
13238 dev_info(dev, "Entering Test_Packet mode...\n");
13239 @@ -1530,13 +1479,13 @@
13240 DBG(DBG_HW, "Packet length: %u\n", pkt_len);
13241 if (pkt_len != sizeof(crq)) {
13242 pr_warning("udc: Invalid packet length %u "
13243 - "(expected %lu)\n", pkt_len, sizeof(crq));
13244 + "(expected %zu)\n", pkt_len, sizeof(crq));
13245 set_protocol_stall(udc, ep);
13246 return;
13247 }
13248
13249 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
13250 - copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
13251 + memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
13252
13253 /* Free up one bank in the FIFO so that we can
13254 * generate or receive a reply right away. */
13255 @@ -1688,6 +1637,7 @@
13256 DBG(DBG_INT, "irq, status=%#08x\n", status);
13257
13258 if (status & USBA_DET_SUSPEND) {
13259 + toggle_bias(0);
13260 usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
13261 DBG(DBG_BUS, "Suspend detected\n");
13262 if (udc->gadget.speed != USB_SPEED_UNKNOWN
13263 @@ -1699,6 +1649,7 @@
13264 }
13265
13266 if (status & USBA_WAKE_UP) {
13267 + toggle_bias(1);
13268 usba_writel(udc, INT_CLR, USBA_WAKE_UP);
13269 DBG(DBG_BUS, "Wake Up CPU detected\n");
13270 }
13271 @@ -1792,12 +1743,14 @@
13272 vbus = gpio_get_value(udc->vbus_pin);
13273 if (vbus != udc->vbus_prev) {
13274 if (vbus) {
13275 - usba_writel(udc, CTRL, USBA_EN_USBA);
13276 + toggle_bias(1);
13277 + usba_writel(udc, CTRL, USBA_ENABLE_MASK);
13278 usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
13279 } else {
13280 udc->gadget.speed = USB_SPEED_UNKNOWN;
13281 reset_all_endpoints(udc);
13282 - usba_writel(udc, CTRL, 0);
13283 + toggle_bias(0);
13284 + usba_writel(udc, CTRL, USBA_DISABLE_MASK);
13285 spin_unlock(&udc->lock);
13286 udc->driver->disconnect(&udc->gadget);
13287 spin_lock(&udc->lock);
13288 @@ -1850,7 +1803,8 @@
13289 /* If Vbus is present, enable the controller and wait for reset */
13290 spin_lock_irqsave(&udc->lock, flags);
13291 if (vbus_is_present(udc) && udc->vbus_prev == 0) {
13292 - usba_writel(udc, CTRL, USBA_EN_USBA);
13293 + toggle_bias(1);
13294 + usba_writel(udc, CTRL, USBA_ENABLE_MASK);
13295 usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
13296 }
13297 spin_unlock_irqrestore(&udc->lock, flags);
13298 @@ -1883,7 +1837,8 @@
13299 spin_unlock_irqrestore(&udc->lock, flags);
13300
13301 /* This will also disable the DP pullup */
13302 - usba_writel(udc, CTRL, 0);
13303 + toggle_bias(0);
13304 + usba_writel(udc, CTRL, USBA_DISABLE_MASK);
13305
13306 driver->unbind(&udc->gadget);
13307 udc->gadget.dev.driver = NULL;
13308 @@ -1908,7 +1863,7 @@
13309
13310 regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
13311 fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
13312 - if (!regs || !fifo)
13313 + if (!regs || !fifo || !pdata)
13314 return -ENXIO;
13315
13316 irq = platform_get_irq(pdev, 0);
13317 @@ -1953,19 +1908,48 @@
13318
13319 /* Make sure we start from a clean slate */
13320 clk_enable(pclk);
13321 - usba_writel(udc, CTRL, 0);
13322 + toggle_bias(0);
13323 + usba_writel(udc, CTRL, USBA_DISABLE_MASK);
13324 clk_disable(pclk);
13325
13326 + usba_ep = kmalloc(sizeof(struct usba_ep) * pdata->num_ep,
13327 + GFP_KERNEL);
13328 + if (!usba_ep)
13329 + goto err_alloc_ep;
13330 +
13331 + the_udc.gadget.ep0 = &usba_ep[0].ep;
13332 +
13333 INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
13334 usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
13335 usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
13336 usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
13337 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++) {
13338 + usba_ep[0].ep.ops = &usba_ep_ops;
13339 + usba_ep[0].ep.name = pdata->ep[0].name;
13340 + usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
13341 + usba_ep[0].udc = &the_udc;
13342 + INIT_LIST_HEAD(&usba_ep[0].queue);
13343 + usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
13344 + usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
13345 + usba_ep[0].index = pdata->ep[0].index;
13346 + usba_ep[0].can_dma = pdata->ep[0].can_dma;
13347 + usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
13348 +
13349 + for (i = 1; i < pdata->num_ep; i++) {
13350 struct usba_ep *ep = &usba_ep[i];
13351
13352 ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
13353 ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
13354 ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
13355 + ep->ep.ops = &usba_ep_ops;
13356 + ep->ep.name = pdata->ep[i].name;
13357 + ep->ep.maxpacket = pdata->ep[i].fifo_size;
13358 + ep->udc = &the_udc;
13359 + INIT_LIST_HEAD(&ep->queue);
13360 + ep->fifo_size = pdata->ep[i].fifo_size;
13361 + ep->nr_banks = pdata->ep[i].nr_banks;
13362 + ep->index = pdata->ep[i].index;
13363 + ep->can_dma = pdata->ep[i].can_dma;
13364 + ep->can_isoc = pdata->ep[i].can_isoc;
13365
13366 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
13367 }
13368 @@ -1984,7 +1968,7 @@
13369 goto err_device_add;
13370 }
13371
13372 - if (pdata && pdata->vbus_pin != GPIO_PIN_NONE) {
13373 + if (pdata->vbus_pin >= 0) {
13374 if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
13375 udc->vbus_pin = pdata->vbus_pin;
13376
13377 @@ -2004,7 +1988,7 @@
13378 }
13379
13380 usba_init_debugfs(udc);
13381 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
13382 + for (i = 1; i < pdata->num_ep; i++)
13383 usba_ep_init_debugfs(udc, &usba_ep[i]);
13384
13385 return 0;
13386 @@ -2012,6 +1996,8 @@
13387 err_device_add:
13388 free_irq(irq, udc);
13389 err_request_irq:
13390 + kfree(usba_ep);
13391 +err_alloc_ep:
13392 iounmap(udc->fifo);
13393 err_map_fifo:
13394 iounmap(udc->regs);
13395 @@ -2029,10 +2015,11 @@
13396 {
13397 struct usba_udc *udc;
13398 int i;
13399 + struct usba_platform_data *pdata = pdev->dev.platform_data;
13400
13401 udc = platform_get_drvdata(pdev);
13402
13403 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
13404 + for (i = 1; i < pdata->num_ep; i++)
13405 usba_ep_cleanup_debugfs(&usba_ep[i]);
13406 usba_cleanup_debugfs(udc);
13407
13408 @@ -2040,6 +2027,7 @@
13409 gpio_free(udc->vbus_pin);
13410
13411 free_irq(udc->irq, udc);
13412 + kfree(usba_ep);
13413 iounmap(udc->fifo);
13414 iounmap(udc->regs);
13415 clk_put(udc->hclk);
13416 --- a/drivers/usb/gadget/atmel_usba_udc.h
13417 +++ b/drivers/usb/gadget/atmel_usba_udc.h
13418 @@ -41,6 +41,15 @@
13419 #define USBA_EN_USBA (1 << 8)
13420 #define USBA_DETACH (1 << 9)
13421 #define USBA_REMOTE_WAKE_UP (1 << 10)
13422 +#define USBA_PULLD_DIS (1 << 11)
13423 +
13424 +#if defined(CONFIG_AVR32)
13425 +#define USBA_ENABLE_MASK USBA_EN_USBA
13426 +#define USBA_DISABLE_MASK 0
13427 +#elif defined(CONFIG_ARCH_AT91)
13428 +#define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS)
13429 +#define USBA_DISABLE_MASK USBA_DETACH
13430 +#endif /* CONFIG_ARCH_AT91 */
13431
13432 /* Bitfields in FNUM */
13433 #define USBA_MICRO_FRAME_NUM_OFFSET 0
13434 --- a/drivers/video/atmel_lcdfb.c
13435 +++ b/drivers/video/atmel_lcdfb.c
13436 @@ -38,7 +38,9 @@
13437 #endif
13438
13439 #if defined(CONFIG_ARCH_AT91)
13440 -#define ATMEL_LCDFB_FBINFO_DEFAULT FBINFO_DEFAULT
13441 +#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
13442 + | FBINFO_PARTIAL_PAN_OK \
13443 + | FBINFO_HWACCEL_YPAN)
13444
13445 static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
13446 struct fb_var_screeninfo *var)
13447 @@ -176,7 +178,7 @@
13448 .type = FB_TYPE_PACKED_PIXELS,
13449 .visual = FB_VISUAL_TRUECOLOR,
13450 .xpanstep = 0,
13451 - .ypanstep = 0,
13452 + .ypanstep = 1,
13453 .ywrapstep = 0,
13454 .accel = FB_ACCEL_NONE,
13455 };
13456 @@ -250,6 +252,8 @@
13457 return -ENOMEM;
13458 }
13459
13460 + memset(info->screen_base, 0, info->fix.smem_len);
13461 +
13462 return 0;
13463 }
13464
13465 @@ -634,7 +638,6 @@
13466 struct fb_info *info = sinfo->info;
13467 int ret = 0;
13468
13469 - memset_io(info->screen_base, 0, info->fix.smem_len);
13470 info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
13471
13472 dev_info(info->device,
13473 @@ -764,6 +767,11 @@
13474 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
13475 if (!info->screen_base)
13476 goto release_intmem;
13477 +
13478 + /*
13479 + * Don't clear the framebuffer -- someone may have set
13480 + * up a splash image.
13481 + */
13482 } else {
13483 /* alocate memory buffer */
13484 ret = atmel_lcdfb_alloc_video_memory(sinfo);
13485 --- a/fs/fs-writeback.c
13486 +++ b/fs/fs-writeback.c
13487 @@ -385,8 +385,6 @@
13488 * WB_SYNC_HOLD is a hack for sys_sync(): reattach the inode to sb->s_dirty so
13489 * that it can be located for waiting on in __writeback_single_inode().
13490 *
13491 - * Called under inode_lock.
13492 - *
13493 * If `bdi' is non-zero then we're being asked to writeback a specific queue.
13494 * This function assumes that the blockdev superblock's inodes are backed by
13495 * a variety of queues, so all inodes are searched. For other superblocks,
13496 @@ -402,11 +400,12 @@
13497 * on the writer throttling path, and we get decent balancing between many
13498 * throttled threads: we don't want them all piling up on inode_sync_wait.
13499 */
13500 -static void
13501 -sync_sb_inodes(struct super_block *sb, struct writeback_control *wbc)
13502 +void generic_sync_sb_inodes(struct super_block *sb,
13503 + struct writeback_control *wbc)
13504 {
13505 const unsigned long start = jiffies; /* livelock avoidance */
13506
13507 + spin_lock(&inode_lock);
13508 if (!wbc->for_kupdate || list_empty(&sb->s_io))
13509 queue_io(sb, wbc->older_than_this);
13510
13511 @@ -485,8 +484,16 @@
13512 if (!list_empty(&sb->s_more_io))
13513 wbc->more_io = 1;
13514 }
13515 + spin_unlock(&inode_lock);
13516 return; /* Leave any unwritten inodes on s_io */
13517 }
13518 +EXPORT_SYMBOL_GPL(generic_sync_sb_inodes);
13519 +
13520 +static void sync_sb_inodes(struct super_block *sb,
13521 + struct writeback_control *wbc)
13522 +{
13523 + generic_sync_sb_inodes(sb, wbc);
13524 +}
13525
13526 /*
13527 * Start writeback of dirty pagecache data against all unlocked inodes.
13528 @@ -526,11 +533,8 @@
13529 * be unmounted by the time it is released.
13530 */
13531 if (down_read_trylock(&sb->s_umount)) {
13532 - if (sb->s_root) {
13533 - spin_lock(&inode_lock);
13534 + if (sb->s_root)
13535 sync_sb_inodes(sb, wbc);
13536 - spin_unlock(&inode_lock);
13537 - }
13538 up_read(&sb->s_umount);
13539 }
13540 spin_lock(&sb_lock);
13541 @@ -568,9 +572,7 @@
13542 (inodes_stat.nr_inodes - inodes_stat.nr_unused) +
13543 nr_dirty + nr_unstable;
13544 wbc.nr_to_write += wbc.nr_to_write / 2; /* Bit more for luck */
13545 - spin_lock(&inode_lock);
13546 sync_sb_inodes(sb, &wbc);
13547 - spin_unlock(&inode_lock);
13548 }
13549
13550 /*
13551 --- a/include/asm-avr32/arch-at32ap/board.h
13552 +++ b/include/asm-avr32/arch-at32ap/board.h
13553 @@ -8,6 +8,12 @@
13554
13555 #define GPIO_PIN_NONE (-1)
13556
13557 +/*
13558 + * Clock rates for various on-board oscillators. The number of entries
13559 + * in this array is chip-dependent.
13560 + */
13561 +extern unsigned long at32_board_osc_rates[];
13562 +
13563 /* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
13564 void at32_add_system_devices(void);
13565
13566 @@ -36,11 +42,10 @@
13567 struct atmel_lcdfb_info;
13568 struct platform_device *
13569 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
13570 - unsigned long fbmem_start, unsigned long fbmem_len);
13571 + unsigned long fbmem_start, unsigned long fbmem_len,
13572 + unsigned int pin_config);
13573
13574 -struct usba_platform_data {
13575 - int vbus_pin;
13576 -};
13577 +struct usba_platform_data;
13578 struct platform_device *
13579 at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
13580
13581 @@ -68,9 +73,27 @@
13582 struct platform_device *
13583 at32_add_device_ssc(unsigned int id, unsigned int flags);
13584
13585 -struct platform_device *at32_add_device_twi(unsigned int id);
13586 -struct platform_device *at32_add_device_mci(unsigned int id);
13587 -struct platform_device *at32_add_device_ac97c(unsigned int id);
13588 +struct i2c_board_info;
13589 +struct platform_device *at32_add_device_twi(unsigned int id,
13590 + struct i2c_board_info *b,
13591 + unsigned int n);
13592 +
13593 +struct mci_platform_data {
13594 + int detect_pin;
13595 + int wp_pin;
13596 +};
13597 +struct platform_device *
13598 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
13599 +
13600 +struct ac97c_platform_data {
13601 + unsigned short dma_rx_periph_id;
13602 + unsigned short dma_tx_periph_id;
13603 + unsigned short dma_controller_id;
13604 + int reset_pin;
13605 +};
13606 +struct platform_device *
13607 +at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data);
13608 +
13609 struct platform_device *at32_add_device_abdac(unsigned int id);
13610
13611 struct cf_platform_data {
13612 @@ -84,4 +107,20 @@
13613 at32_add_device_cf(unsigned int id, unsigned int extint,
13614 struct cf_platform_data *data);
13615
13616 +struct platform_device *
13617 +at32_add_device_psif(unsigned int id);
13618 +
13619 +/* NAND / SmartMedia */
13620 +struct atmel_nand_data {
13621 + int enable_pin; /* chip enable */
13622 + int det_pin; /* card detect */
13623 + int rdy_pin; /* ready/busy */
13624 + u8 ale; /* address line number connected to ALE */
13625 + u8 cle; /* address line number connected to CLE */
13626 + u8 bus_width_16; /* buswidth is 16 bit */
13627 + struct mtd_partition *(*partition_info)(int size, int *num_partitions);
13628 +};
13629 +struct platform_device *
13630 +at32_add_device_nand(unsigned int id, struct atmel_nand_data *data);
13631 +
13632 #endif /* __ASM_ARCH_BOARD_H */
13633 --- a/include/asm-avr32/arch-at32ap/init.h
13634 +++ b/include/asm-avr32/arch-at32ap/init.h
13635 @@ -13,10 +13,6 @@
13636 void setup_platform(void);
13637 void setup_board(void);
13638
13639 -/* Called by setup_platform */
13640 -void at32_clock_init(void);
13641 -void at32_portmux_init(void);
13642 -
13643 void at32_setup_serial_console(unsigned int usart_id);
13644
13645 #endif /* __ASM_AVR32_AT32AP_INIT_H__ */
13646 --- /dev/null
13647 +++ b/include/asm-avr32/arch-at32ap/pm.h
13648 @@ -0,0 +1,51 @@
13649 +/*
13650 + * AVR32 AP Power Management.
13651 + *
13652 + * Copyright (C) 2008 Atmel Corporation
13653 + *
13654 + * This program is free software; you can redistribute it and/or modify
13655 + * it under the terms of the GNU General Public License version 2 as
13656 + * published by the Free Software Foundation.
13657 + */
13658 +#ifndef __ASM_AVR32_ARCH_PM_H
13659 +#define __ASM_AVR32_ARCH_PM_H
13660 +
13661 +/* Possible arguments to the "sleep" instruction */
13662 +#define CPU_SLEEP_IDLE 0
13663 +#define CPU_SLEEP_FROZEN 1
13664 +#define CPU_SLEEP_STANDBY 2
13665 +#define CPU_SLEEP_STOP 3
13666 +#define CPU_SLEEP_STATIC 5
13667 +
13668 +#ifndef __ASSEMBLY__
13669 +extern void cpu_enter_idle(void);
13670 +extern void cpu_enter_standby(unsigned long sdramc_base);
13671 +
13672 +extern bool disable_idle_sleep;
13673 +
13674 +static inline void cpu_disable_idle_sleep(void)
13675 +{
13676 + disable_idle_sleep = true;
13677 +}
13678 +
13679 +static inline void cpu_enable_idle_sleep(void)
13680 +{
13681 + disable_idle_sleep = false;
13682 +}
13683 +
13684 +static inline void cpu_idle_sleep(void)
13685 +{
13686 + /*
13687 + * If we're using the COUNT and COMPARE registers for
13688 + * timekeeping, we can't use the IDLE state.
13689 + */
13690 + if (disable_idle_sleep)
13691 + cpu_relax();
13692 + else
13693 + cpu_enter_idle();
13694 +}
13695 +
13696 +void intc_set_suspend_handler(unsigned long offset);
13697 +#endif
13698 +
13699 +#endif /* __ASM_AVR32_ARCH_PM_H */
13700 --- a/include/asm-avr32/arch-at32ap/portmux.h
13701 +++ b/include/asm-avr32/arch-at32ap/portmux.h
13702 @@ -26,4 +26,16 @@
13703 void at32_select_gpio(unsigned int pin, unsigned long flags);
13704 void at32_reserve_pin(unsigned int pin);
13705
13706 +#ifdef CONFIG_GPIO_DEV
13707 +
13708 +/* Gang allocators and accessors; used by the GPIO /dev driver */
13709 +int at32_gpio_port_is_valid(unsigned int port);
13710 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask);
13711 +void at32_deselect_pins(unsigned int port, u32 pins);
13712 +
13713 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins);
13714 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask);
13715 +
13716 +#endif /* CONFIG_GPIO_DEV */
13717 +
13718 #endif /* __ASM_ARCH_PORTMUX_H__ */
13719 --- /dev/null
13720 +++ b/include/asm-avr32/arch-at32ap/sram.h
13721 @@ -0,0 +1,30 @@
13722 +/*
13723 + * Simple SRAM allocator
13724 + *
13725 + * Copyright (C) 2008 Atmel Corporation
13726 + *
13727 + * This program is free software; you can redistribute it and/or modify
13728 + * it under the terms of the GNU General Public License version 2 as
13729 + * published by the Free Software Foundation.
13730 + */
13731 +#ifndef __ASM_AVR32_ARCH_SRAM_H
13732 +#define __ASM_AVR32_ARCH_SRAM_H
13733 +
13734 +#include <linux/genalloc.h>
13735 +
13736 +extern struct gen_pool *sram_pool;
13737 +
13738 +static inline unsigned long sram_alloc(size_t len)
13739 +{
13740 + if (!sram_pool)
13741 + return 0UL;
13742 +
13743 + return gen_pool_alloc(sram_pool, len);
13744 +}
13745 +
13746 +static inline void sram_free(unsigned long addr, size_t len)
13747 +{
13748 + return gen_pool_free(sram_pool, addr, len);
13749 +}
13750 +
13751 +#endif /* __ASM_AVR32_ARCH_SRAM_H */
13752 --- a/include/asm-avr32/arch-at32ap/time.h
13753 +++ /dev/null
13754 @@ -1,112 +0,0 @@
13755 -/*
13756 - * Copyright (C) 2007 Atmel Corporation
13757 - *
13758 - * This program is free software; you can redistribute it and/or modify
13759 - * it under the terms of the GNU General Public License version 2 as
13760 - * published by the Free Software Foundation.
13761 - */
13762 -
13763 -#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
13764 -#define _ASM_AVR32_ARCH_AT32AP_TIME_H
13765 -
13766 -#include <linux/platform_device.h>
13767 -
13768 -extern struct irqaction timer_irqaction;
13769 -extern struct platform_device at32_systc0_device;
13770 -extern void local_timer_interrupt(int irq, void *dev_id);
13771 -
13772 -#define TIMER_BCR 0x000000c0
13773 -#define TIMER_BCR_SYNC 0
13774 -#define TIMER_BMR 0x000000c4
13775 -#define TIMER_BMR_TC0XC0S 0
13776 -#define TIMER_BMR_TC1XC1S 2
13777 -#define TIMER_BMR_TC2XC2S 4
13778 -#define TIMER_CCR 0x00000000
13779 -#define TIMER_CCR_CLKDIS 1
13780 -#define TIMER_CCR_CLKEN 0
13781 -#define TIMER_CCR_SWTRG 2
13782 -#define TIMER_CMR 0x00000004
13783 -#define TIMER_CMR_ABETRG 10
13784 -#define TIMER_CMR_ACPA 16
13785 -#define TIMER_CMR_ACPC 18
13786 -#define TIMER_CMR_AEEVT 20
13787 -#define TIMER_CMR_ASWTRG 22
13788 -#define TIMER_CMR_BCPB 24
13789 -#define TIMER_CMR_BCPC 26
13790 -#define TIMER_CMR_BEEVT 28
13791 -#define TIMER_CMR_BSWTRG 30
13792 -#define TIMER_CMR_BURST 4
13793 -#define TIMER_CMR_CLKI 3
13794 -#define TIMER_CMR_CPCDIS 7
13795 -#define TIMER_CMR_CPCSTOP 6
13796 -#define TIMER_CMR_CPCTRG 14
13797 -#define TIMER_CMR_EEVT 10
13798 -#define TIMER_CMR_EEVTEDG 8
13799 -#define TIMER_CMR_ENETRG 12
13800 -#define TIMER_CMR_ETRGEDG 8
13801 -#define TIMER_CMR_LDBDIS 7
13802 -#define TIMER_CMR_LDBSTOP 6
13803 -#define TIMER_CMR_LDRA 16
13804 -#define TIMER_CMR_LDRB 18
13805 -#define TIMER_CMR_TCCLKS 0
13806 -#define TIMER_CMR_WAVE 15
13807 -#define TIMER_CMR_WAVSEL 13
13808 -#define TIMER_CV 0x00000010
13809 -#define TIMER_CV_CV 0
13810 -#define TIMER_IDR 0x00000028
13811 -#define TIMER_IDR_COVFS 0
13812 -#define TIMER_IDR_CPAS 2
13813 -#define TIMER_IDR_CPBS 3
13814 -#define TIMER_IDR_CPCS 4
13815 -#define TIMER_IDR_ETRGS 7
13816 -#define TIMER_IDR_LDRAS 5
13817 -#define TIMER_IDR_LDRBS 6
13818 -#define TIMER_IDR_LOVRS 1
13819 -#define TIMER_IER 0x00000024
13820 -#define TIMER_IER_COVFS 0
13821 -#define TIMER_IER_CPAS 2
13822 -#define TIMER_IER_CPBS 3
13823 -#define TIMER_IER_CPCS 4
13824 -#define TIMER_IER_ETRGS 7
13825 -#define TIMER_IER_LDRAS 5
13826 -#define TIMER_IER_LDRBS 6
13827 -#define TIMER_IER_LOVRS 1
13828 -#define TIMER_IMR 0x0000002c
13829 -#define TIMER_IMR_COVFS 0
13830 -#define TIMER_IMR_CPAS 2
13831 -#define TIMER_IMR_CPBS 3
13832 -#define TIMER_IMR_CPCS 4
13833 -#define TIMER_IMR_ETRGS 7
13834 -#define TIMER_IMR_LDRAS 5
13835 -#define TIMER_IMR_LDRBS 6
13836 -#define TIMER_IMR_LOVRS 1
13837 -#define TIMER_RA 0x00000014
13838 -#define TIMER_RA_RA 0
13839 -#define TIMER_RB 0x00000018
13840 -#define TIMER_RB_RB 0
13841 -#define TIMER_RC 0x0000001c
13842 -#define TIMER_RC_RC 0
13843 -#define TIMER_SR 0x00000020
13844 -#define TIMER_SR_CLKSTA 16
13845 -#define TIMER_SR_COVFS 0
13846 -#define TIMER_SR_CPAS 2
13847 -#define TIMER_SR_CPBS 3
13848 -#define TIMER_SR_CPCS 4
13849 -#define TIMER_SR_ETRGS 7
13850 -#define TIMER_SR_LDRAS 5
13851 -#define TIMER_SR_LDRBS 6
13852 -#define TIMER_SR_LOVRS 1
13853 -#define TIMER_SR_MTIOA 17
13854 -#define TIMER_SR_MTIOB 18
13855 -
13856 -/* Bit manipulation macros */
13857 -#define TIMER_BIT(name) (1 << TIMER_##name)
13858 -#define TIMER_BF(name,value) ((value) << TIMER_##name)
13859 -
13860 -/* Register access macros */
13861 -#define timer_read(port,instance,reg) \
13862 - __raw_readl(port + (0x40 * instance) + TIMER_##reg)
13863 -#define timer_write(port,instance,reg,value) \
13864 - __raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
13865 -
13866 -#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
13867 --- a/include/asm-avr32/asm.h
13868 +++ b/include/asm-avr32/asm.h
13869 @@ -12,10 +12,10 @@
13870 #include <asm/asm-offsets.h>
13871 #include <asm/thread_info.h>
13872
13873 -#define mask_interrupts ssrf SR_GM_BIT
13874 -#define mask_exceptions ssrf SR_EM_BIT
13875 -#define unmask_interrupts csrf SR_GM_BIT
13876 -#define unmask_exceptions csrf SR_EM_BIT
13877 +#define mask_interrupts ssrf SYSREG_GM_OFFSET
13878 +#define mask_exceptions ssrf SYSREG_EM_OFFSET
13879 +#define unmask_interrupts csrf SYSREG_GM_OFFSET
13880 +#define unmask_exceptions csrf SYSREG_EM_OFFSET
13881
13882 #ifdef CONFIG_FRAME_POINTER
13883 .macro save_fp
13884 --- /dev/null
13885 +++ b/include/asm-avr32/dma-controller.h
13886 @@ -0,0 +1,166 @@
13887 +/*
13888 + * Copyright (C) 2005-2006 Atmel Corporation
13889 + *
13890 + * This program is free software; you can redistribute it and/or modify
13891 + * it under the terms of the GNU General Public License version 2 as
13892 + * published by the Free Software Foundation.
13893 + */
13894 +#ifndef __ASM_AVR32_DMA_CONTROLLER_H
13895 +#define __ASM_AVR32_DMA_CONTROLLER_H
13896 +
13897 +#include <linux/device.h>
13898 +
13899 +#define DMA_DIR_MEM_TO_MEM 0x0000
13900 +#define DMA_DIR_MEM_TO_PERIPH 0x0001
13901 +#define DMA_DIR_PERIPH_TO_MEM 0x0002
13902 +#define DMA_DIR_PERIPH_TO_PERIPH 0x0003
13903 +
13904 +#define DMA_WIDTH_8BIT 0
13905 +#define DMA_WIDTH_16BIT 1
13906 +#define DMA_WIDTH_32BIT 2
13907 +
13908 +struct dma_request {
13909 + struct dma_controller *dmac;
13910 + struct list_head list;
13911 +
13912 + unsigned short channel;
13913 +
13914 + void (*xfer_complete)(struct dma_request *req);
13915 + void (*block_complete)(struct dma_request *req);
13916 + void (*error)(struct dma_request *req);
13917 +};
13918 +
13919 +struct dma_request_sg {
13920 + struct dma_request req;
13921 +
13922 + int nr_sg;
13923 + struct scatterlist *sg;
13924 + unsigned long block_size;
13925 + unsigned int nr_blocks;
13926 +
13927 + dma_addr_t data_reg;
13928 + unsigned short periph_id;
13929 +
13930 + unsigned char direction;
13931 + unsigned char width;
13932 +};
13933 +#define to_dma_request_sg(_req) \
13934 + container_of(_req, struct dma_request_sg, req)
13935 +
13936 +struct dma_request_cyclic {
13937 + struct dma_request req;
13938 +
13939 + int periods;
13940 + unsigned long buffer_size;
13941 +
13942 + dma_addr_t buffer_start;
13943 + dma_addr_t data_reg;
13944 +
13945 + unsigned short periph_id;
13946 + unsigned char direction;
13947 + unsigned char width;
13948 +
13949 + void *dev_id;
13950 +};
13951 +#define to_dma_request_cyclic(_req) \
13952 + container_of(_req, struct dma_request_cyclic, req)
13953 +
13954 +struct dma_request_memcpy {
13955 + struct dma_request req;
13956 +
13957 + dma_addr_t src_addr;
13958 + unsigned int src_width;
13959 + unsigned int src_stride;
13960 +
13961 + dma_addr_t dst_addr;
13962 + unsigned int dst_width;
13963 + unsigned int dst_stride;
13964 +
13965 + size_t length;
13966 +
13967 + unsigned short src_reverse:1;
13968 + unsigned short dst_reverse:1;
13969 +};
13970 +#define to_dma_request_memcpy(_req) \
13971 + container_of(_req, struct dma_request_memcpy, req)
13972 +
13973 +struct dma_controller {
13974 + struct list_head list;
13975 + int id;
13976 + struct device *dev;
13977 +
13978 + int (*alloc_channel)(struct dma_controller *dmac);
13979 + void (*release_channel)(struct dma_controller *dmac,
13980 + int channel);
13981 + int (*prepare_request_sg)(struct dma_controller *dmac,
13982 + struct dma_request_sg *req);
13983 + int (*prepare_request_cyclic)(struct dma_controller *dmac,
13984 + struct dma_request_cyclic *req);
13985 + int (*prepare_request_memcpy)(struct dma_controller *dmac,
13986 + struct dma_request_memcpy *req);
13987 + int (*start_request)(struct dma_controller *dmac,
13988 + unsigned int channel);
13989 + int (*stop_request)(struct dma_controller *dmac,
13990 + unsigned int channel);
13991 + dma_addr_t (*get_current_pos)(struct dma_controller *dmac,
13992 + unsigned int channel);
13993 +};
13994 +
13995 +static inline int
13996 +dma_alloc_channel(struct dma_controller *dmac)
13997 +{
13998 + return dmac->alloc_channel(dmac);
13999 +}
14000 +
14001 +static inline void
14002 +dma_release_channel(struct dma_controller *dmac, int chan)
14003 +{
14004 + dmac->release_channel(dmac, chan);
14005 +}
14006 +
14007 +static inline int
14008 +dma_prepare_request_sg(struct dma_controller *dmac,
14009 + struct dma_request_sg *req)
14010 +{
14011 + return dmac->prepare_request_sg(dmac, req);
14012 +}
14013 +
14014 +static inline int
14015 +dma_prepare_request_cyclic(struct dma_controller *dmac,
14016 + struct dma_request_cyclic *req)
14017 +{
14018 + return dmac->prepare_request_cyclic(dmac, req);
14019 +}
14020 +
14021 +static inline int
14022 +dma_prepare_request_memcpy(struct dma_controller *dmac,
14023 + struct dma_request_memcpy *req)
14024 +{
14025 + return dmac->prepare_request_memcpy(dmac, req);
14026 +}
14027 +
14028 +static inline int
14029 +dma_start_request(struct dma_controller *dmac,
14030 + unsigned int channel)
14031 +{
14032 + return dmac->start_request(dmac, channel);
14033 +}
14034 +
14035 +static inline int
14036 +dma_stop_request(struct dma_controller *dmac,
14037 + unsigned int channel)
14038 +{
14039 + return dmac->stop_request(dmac, channel);
14040 +}
14041 +
14042 +static inline dma_addr_t
14043 +dma_get_current_pos(struct dma_controller *dmac,
14044 + unsigned int channel)
14045 +{
14046 + return dmac->get_current_pos(dmac, channel);
14047 +}
14048 +
14049 +extern int register_dma_controller(struct dma_controller *dmac);
14050 +extern struct dma_controller *find_dma_controller(int id);
14051 +
14052 +#endif /* __ASM_AVR32_DMA_CONTROLLER_H */
14053 --- a/include/asm-avr32/intc.h
14054 +++ /dev/null
14055 @@ -1,128 +0,0 @@
14056 -#ifndef __ASM_AVR32_INTC_H
14057 -#define __ASM_AVR32_INTC_H
14058 -
14059 -#include <linux/sysdev.h>
14060 -#include <linux/interrupt.h>
14061 -
14062 -struct irq_controller;
14063 -struct irqaction;
14064 -struct pt_regs;
14065 -
14066 -struct platform_device;
14067 -
14068 -/* Information about the internal interrupt controller */
14069 -struct intc_device {
14070 - /* ioremapped address of configuration block */
14071 - void __iomem *regs;
14072 -
14073 - /* the physical device */
14074 - struct platform_device *pdev;
14075 -
14076 - /* Number of interrupt lines per group. */
14077 - unsigned int irqs_per_group;
14078 -
14079 - /* The highest group ID + 1 */
14080 - unsigned int nr_groups;
14081 -
14082 - /*
14083 - * Bitfield indicating which groups are actually in use. The
14084 - * size of the array is
14085 - * ceil(group_max / (8 * sizeof(unsigned int))).
14086 - */
14087 - unsigned int group_mask[];
14088 -};
14089 -
14090 -struct irq_controller_class {
14091 - /*
14092 - * A short name identifying this kind of controller.
14093 - */
14094 - const char *typename;
14095 - /*
14096 - * Handle the IRQ. Must do any necessary acking and masking.
14097 - */
14098 - irqreturn_t (*handle)(int irq, void *dev_id, struct pt_regs *regs);
14099 - /*
14100 - * Register a new IRQ handler.
14101 - */
14102 - int (*setup)(struct irq_controller *ctrl, unsigned int irq,
14103 - struct irqaction *action);
14104 - /*
14105 - * Unregister a IRQ handler.
14106 - */
14107 - void (*free)(struct irq_controller *ctrl, unsigned int irq,
14108 - void *dev_id);
14109 - /*
14110 - * Mask the IRQ in the interrupt controller.
14111 - */
14112 - void (*mask)(struct irq_controller *ctrl, unsigned int irq);
14113 - /*
14114 - * Unmask the IRQ in the interrupt controller.
14115 - */
14116 - void (*unmask)(struct irq_controller *ctrl, unsigned int irq);
14117 - /*
14118 - * Set the type of the IRQ. See below for possible types.
14119 - * Return -EINVAL if a given type is not supported
14120 - */
14121 - int (*set_type)(struct irq_controller *ctrl, unsigned int irq,
14122 - unsigned int type);
14123 - /*
14124 - * Return the IRQ type currently set
14125 - */
14126 - unsigned int (*get_type)(struct irq_controller *ctrl, unsigned int irq);
14127 -};
14128 -
14129 -struct irq_controller {
14130 - struct irq_controller_class *class;
14131 - unsigned int irq_group;
14132 - unsigned int first_irq;
14133 - unsigned int nr_irqs;
14134 - struct list_head list;
14135 -};
14136 -
14137 -struct intc_group_desc {
14138 - struct irq_controller *ctrl;
14139 - irqreturn_t (*handle)(int, void *, struct pt_regs *);
14140 - unsigned long flags;
14141 - void *dev_id;
14142 - const char *devname;
14143 -};
14144 -
14145 -/*
14146 - * The internal interrupt controller. Defined in board/part-specific
14147 - * devices.c.
14148 - * TODO: Should probably be defined per-cpu.
14149 - */
14150 -extern struct intc_device intc;
14151 -
14152 -extern int request_internal_irq(unsigned int irq,
14153 - irqreturn_t (*handler)(int, void *, struct pt_regs *),
14154 - unsigned long irqflags,
14155 - const char *devname, void *dev_id);
14156 -extern void free_internal_irq(unsigned int irq);
14157 -
14158 -/* Only used by time_init() */
14159 -extern int setup_internal_irq(unsigned int irq, struct intc_group_desc *desc);
14160 -
14161 -/*
14162 - * Set interrupt priority for a given group. `group' can be found by
14163 - * using irq_to_group(irq). Priority can be from 0 (lowest) to 3
14164 - * (highest). Higher-priority interrupts will preempt lower-priority
14165 - * interrupts (unless interrupts are masked globally).
14166 - *
14167 - * This function does not check for conflicts within a group.
14168 - */
14169 -extern int intc_set_priority(unsigned int group,
14170 - unsigned int priority);
14171 -
14172 -/*
14173 - * Returns a bitmask of pending interrupts in a group.
14174 - */
14175 -extern unsigned long intc_get_pending(unsigned int group);
14176 -
14177 -/*
14178 - * Register a new external interrupt controller. Returns the first
14179 - * external IRQ number that is assigned to the new controller.
14180 - */
14181 -extern int intc_register_controller(struct irq_controller *ctrl);
14182 -
14183 -#endif /* __ASM_AVR32_INTC_H */
14184 --- a/include/asm-avr32/irq.h
14185 +++ b/include/asm-avr32/irq.h
14186 @@ -14,6 +14,11 @@
14187 #ifndef __ASSEMBLER__
14188 int nmi_enable(void);
14189 void nmi_disable(void);
14190 +
14191 +/*
14192 + * Returns a bitmask of pending interrupts in a group.
14193 + */
14194 +extern unsigned long intc_get_pending(unsigned int group);
14195 #endif
14196
14197 #endif /* __ASM_AVR32_IOCTLS_H */
14198 --- a/include/asm-avr32/mmu_context.h
14199 +++ b/include/asm-avr32/mmu_context.h
14200 @@ -13,7 +13,6 @@
14201 #define __ASM_AVR32_MMU_CONTEXT_H
14202
14203 #include <asm/tlbflush.h>
14204 -#include <asm/pgalloc.h>
14205 #include <asm/sysreg.h>
14206 #include <asm-generic/mm_hooks.h>
14207
14208 --- a/include/asm-avr32/page.h
14209 +++ b/include/asm-avr32/page.h
14210 @@ -8,13 +8,11 @@
14211 #ifndef __ASM_AVR32_PAGE_H
14212 #define __ASM_AVR32_PAGE_H
14213
14214 +#include <linux/const.h>
14215 +
14216 /* PAGE_SHIFT determines the page size */
14217 #define PAGE_SHIFT 12
14218 -#ifdef __ASSEMBLY__
14219 -#define PAGE_SIZE (1 << PAGE_SHIFT)
14220 -#else
14221 -#define PAGE_SIZE (1UL << PAGE_SHIFT)
14222 -#endif
14223 +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
14224 #define PAGE_MASK (~(PAGE_SIZE-1))
14225 #define PTE_MASK PAGE_MASK
14226
14227 --- a/include/asm-avr32/pci.h
14228 +++ b/include/asm-avr32/pci.h
14229 @@ -5,4 +5,6 @@
14230
14231 #define PCI_DMA_BUS_IS_PHYS (1)
14232
14233 +#include <asm-generic/pci-dma-compat.h>
14234 +
14235 #endif /* __ASM_AVR32_PCI_H__ */
14236 --- a/include/asm-avr32/pgalloc.h
14237 +++ b/include/asm-avr32/pgalloc.h
14238 @@ -8,65 +8,79 @@
14239 #ifndef __ASM_AVR32_PGALLOC_H
14240 #define __ASM_AVR32_PGALLOC_H
14241
14242 -#include <asm/processor.h>
14243 -#include <linux/threads.h>
14244 -#include <linux/slab.h>
14245 -#include <linux/mm.h>
14246 +#include <linux/quicklist.h>
14247 +#include <asm/page.h>
14248 +#include <asm/pgtable.h>
14249
14250 -#define pmd_populate_kernel(mm, pmd, pte) \
14251 - set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
14252 +#define QUICK_PGD 0 /* Preserve kernel mappings over free */
14253 +#define QUICK_PT 1 /* Zero on free */
14254
14255 -static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
14256 +static inline void pmd_populate_kernel(struct mm_struct *mm,
14257 + pmd_t *pmd, pte_t *pte)
14258 +{
14259 + set_pmd(pmd, __pmd((unsigned long)pte));
14260 +}
14261 +
14262 +static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
14263 pgtable_t pte)
14264 {
14265 - set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
14266 + set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
14267 }
14268 #define pmd_pgtable(pmd) pmd_page(pmd)
14269
14270 +static inline void pgd_ctor(void *x)
14271 +{
14272 + pgd_t *pgd = x;
14273 +
14274 + memcpy(pgd + USER_PTRS_PER_PGD,
14275 + swapper_pg_dir + USER_PTRS_PER_PGD,
14276 + (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
14277 +}
14278 +
14279 /*
14280 * Allocate and free page tables
14281 */
14282 -static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm)
14283 +static inline pgd_t *pgd_alloc(struct mm_struct *mm)
14284 {
14285 - return kcalloc(USER_PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
14286 + return quicklist_alloc(QUICK_PGD, GFP_KERNEL | __GFP_REPEAT, pgd_ctor);
14287 }
14288
14289 static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
14290 {
14291 - kfree(pgd);
14292 + quicklist_free(QUICK_PGD, NULL, pgd);
14293 }
14294
14295 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
14296 unsigned long address)
14297 {
14298 - pte_t *pte;
14299 -
14300 - pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
14301 -
14302 - return pte;
14303 + return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
14304 }
14305
14306 -static inline struct page *pte_alloc_one(struct mm_struct *mm,
14307 +static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
14308 unsigned long address)
14309 {
14310 - struct page *pte;
14311 + struct page *page;
14312 + void *pg;
14313
14314 - pte = alloc_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
14315 - if (!pte)
14316 + pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
14317 + if (!pg)
14318 return NULL;
14319 - pgtable_page_ctor(pte);
14320 - return pte;
14321 +
14322 + page = virt_to_page(pg);
14323 + pgtable_page_ctor(page);
14324 +
14325 + return page;
14326 }
14327
14328 static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
14329 {
14330 - free_page((unsigned long)pte);
14331 + quicklist_free(QUICK_PT, NULL, pte);
14332 }
14333
14334 static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
14335 {
14336 pgtable_page_dtor(pte);
14337 - __free_page(pte);
14338 + quicklist_free_page(QUICK_PT, NULL, pte);
14339 }
14340
14341 #define __pte_free_tlb(tlb,pte) \
14342 @@ -75,6 +89,10 @@
14343 tlb_remove_page((tlb), pte); \
14344 } while (0)
14345
14346 -#define check_pgt_cache() do { } while(0)
14347 +static inline void check_pgt_cache(void)
14348 +{
14349 + quicklist_trim(QUICK_PGD, NULL, 25, 16);
14350 + quicklist_trim(QUICK_PT, NULL, 25, 16);
14351 +}
14352
14353 #endif /* __ASM_AVR32_PGALLOC_H */
14354 --- a/include/asm-avr32/pgtable.h
14355 +++ b/include/asm-avr32/pgtable.h
14356 @@ -129,13 +129,6 @@
14357
14358 #define _PAGE_FLAGS_CACHE_MASK (_PAGE_CACHABLE | _PAGE_BUFFER | _PAGE_WT)
14359
14360 -/* TODO: Check for saneness */
14361 -/* User-mode page table flags (to be set in a pgd or pmd entry) */
14362 -#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_TYPE_SMALL | _PAGE_RW \
14363 - | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
14364 -/* Kernel-mode page table flags */
14365 -#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_TYPE_SMALL | _PAGE_RW \
14366 - | _PAGE_ACCESSED | _PAGE_DIRTY)
14367 /* Flags that may be modified by software */
14368 #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY \
14369 | _PAGE_FLAGS_CACHE_MASK)
14370 @@ -254,10 +247,14 @@
14371 }
14372
14373 #define pmd_none(x) (!pmd_val(x))
14374 -#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
14375 -#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
14376 -#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) \
14377 - != _KERNPG_TABLE)
14378 +#define pmd_present(x) (pmd_val(x))
14379 +
14380 +static inline void pmd_clear(pmd_t *pmdp)
14381 +{
14382 + set_pmd(pmdp, __pmd(0));
14383 +}
14384 +
14385 +#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
14386
14387 /*
14388 * Permanent address of a page. We don't support highmem, so this is
14389 @@ -295,19 +292,16 @@
14390
14391 #define page_pte(page) page_pte_prot(page, __pgprot(0))
14392
14393 -#define pmd_page_vaddr(pmd) \
14394 - ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
14395 -
14396 -#define pmd_page(pmd) (phys_to_page(pmd_val(pmd)))
14397 +#define pmd_page_vaddr(pmd) pmd_val(pmd)
14398 +#define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
14399
14400 /* to find an entry in a page-table-directory. */
14401 -#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
14402 -#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
14403 -#define pgd_offset_current(address) \
14404 - ((pgd_t *)__mfsr(SYSREG_PTBR) + pgd_index(address))
14405 +#define pgd_index(address) (((address) >> PGDIR_SHIFT) \
14406 + & (PTRS_PER_PGD - 1))
14407 +#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
14408
14409 /* to find an entry in a kernel page-table-directory */
14410 -#define pgd_offset_k(address) pgd_offset(&init_mm, address)
14411 +#define pgd_offset_k(address) pgd_offset(&init_mm, address)
14412
14413 /* Find an entry in the third-level page table.. */
14414 #define pte_index(address) \
14415 --- /dev/null
14416 +++ b/include/asm-avr32/serial.h
14417 @@ -0,0 +1,13 @@
14418 +#ifndef _ASM_SERIAL_H
14419 +#define _ASM_SERIAL_H
14420 +
14421 +/*
14422 + * This assumes you have a 1.8432 MHz clock for your UART.
14423 + *
14424 + * It'd be nice if someone built a serial card with a 24.576 MHz
14425 + * clock, since the 16550A is capable of handling a top speed of 1.5
14426 + * megabits/second; but this requires the faster clock.
14427 + */
14428 +#define BASE_BAUD (1843200 / 16)
14429 +
14430 +#endif /* _ASM_SERIAL_H */
14431 --- a/include/asm-avr32/thread_info.h
14432 +++ b/include/asm-avr32/thread_info.h
14433 @@ -88,6 +88,7 @@
14434 #define TIF_MEMDIE 6
14435 #define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */
14436 #define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */
14437 +#define TIF_FREEZE 29
14438 #define TIF_DEBUG 30 /* debugging enabled */
14439 #define TIF_USERSPACE 31 /* true if FS sets userspace */
14440
14441 --- a/include/asm-avr32/tlbflush.h
14442 +++ b/include/asm-avr32/tlbflush.h
14443 @@ -26,7 +26,6 @@
14444 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
14445 unsigned long end);
14446 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
14447 -extern void __flush_tlb_page(unsigned long asid, unsigned long page);
14448
14449 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
14450
14451 --- /dev/null
14452 +++ b/include/asm-avr32/xor.h
14453 @@ -0,0 +1,6 @@
14454 +#ifndef _ASM_XOR_H
14455 +#define _ASM_XOR_H
14456 +
14457 +#include <asm-generic/xor.h>
14458 +
14459 +#endif
14460 --- /dev/null
14461 +++ b/include/linux/atmel_tc.h
14462 @@ -0,0 +1,252 @@
14463 +/*
14464 + * Timer/Counter Unit (TC) registers.
14465 + *
14466 + * This program is free software; you can redistribute it and/or modify
14467 + * it under the terms of the GNU General Public License as published by
14468 + * the Free Software Foundation; either version 2 of the License, or
14469 + * (at your option) any later version.
14470 + */
14471 +
14472 +#ifndef ATMEL_TC_H
14473 +#define ATMEL_TC_H
14474 +
14475 +#include <linux/compiler.h>
14476 +#include <linux/list.h>
14477 +
14478 +/*
14479 + * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
14480 + * three general-purpose 16-bit timers. These timers share one register bank.
14481 + * Depending on the SOC, each timer may have its own clock and IRQ, or those
14482 + * may be shared by the whole TC block.
14483 + *
14484 + * These TC blocks may have up to nine external pins: TCLK0..2 signals for
14485 + * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
14486 + * or triggering. Those pins need to be set up for use with the TC block,
14487 + * else they will be used as GPIOs or for a different controller.
14488 + *
14489 + * Although we expect each TC block to have a platform_device node, those
14490 + * nodes are not what drivers bind to. Instead, they ask for a specific
14491 + * TC block, by number ... which is a common approach on systems with many
14492 + * timers. Then they use clk_get() and platform_get_irq() to get clock and
14493 + * IRQ resources.
14494 + */
14495 +
14496 +struct clk;
14497 +
14498 +/**
14499 + * struct atmel_tc - information about a Timer/Counter Block
14500 + * @pdev: physical device
14501 + * @iomem: resource associated with the I/O register
14502 + * @regs: mapping through which the I/O registers can be accessed
14503 + * @irq: irq for each of the three channels
14504 + * @clk: internal clock source for each of the three channels
14505 + * @node: list node, for tclib internal use
14506 + *
14507 + * On some platforms, each TC channel has its own clocks and IRQs,
14508 + * while on others, all TC channels share the same clock and IRQ.
14509 + * Drivers should clk_enable() all the clocks they need even though
14510 + * all the entries in @clk may point to the same physical clock.
14511 + * Likewise, drivers should request irqs independently for each
14512 + * channel, but they must use IRQF_SHARED in case some of the entries
14513 + * in @irq are actually the same IRQ.
14514 + */
14515 +struct atmel_tc {
14516 + struct platform_device *pdev;
14517 + struct resource *iomem;
14518 + void __iomem *regs;
14519 + int irq[3];
14520 + struct clk *clk[3];
14521 + struct list_head node;
14522 +};
14523 +
14524 +extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
14525 +extern void atmel_tc_free(struct atmel_tc *tc);
14526 +
14527 +/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
14528 +extern const u8 atmel_tc_divisors[5];
14529 +
14530 +
14531 +/*
14532 + * Two registers have block-wide controls. These are: configuring the three
14533 + * "external" clocks (or event sources) used by the timer channels; and
14534 + * synchronizing the timers by resetting them all at once.
14535 + *
14536 + * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
14537 + * signals. Or, it can mean "external to timer", using the TIOA output from
14538 + * one of the other two timers that's being run in waveform mode.
14539 + */
14540 +
14541 +#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
14542 +#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
14543 +
14544 +#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
14545 +#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
14546 +#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
14547 +#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
14548 +#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
14549 +#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
14550 +#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
14551 +#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
14552 +#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
14553 +#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
14554 +#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
14555 +#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
14556 +#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
14557 +#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
14558 +#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
14559 +#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
14560 +
14561 +
14562 +/*
14563 + * Each TC block has three "channels", each with one counter and controls.
14564 + *
14565 + * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
14566 + * when it's not "external") is silicon-specific. AT91 platforms use one
14567 + * set of definitions; AVR32 platforms use a different set. Don't hard-wire
14568 + * such knowledge into your code, use the global "atmel_tc_divisors" ...
14569 + * where index N is the divisor for clock N+1, else zero to indicate it uses
14570 + * the 32 KiHz clock.
14571 + *
14572 + * The timers can be chained in various ways, and operated in "waveform"
14573 + * generation mode (including PWM) or "capture" mode (to time events). In
14574 + * both modes, behavior can be configured in many ways.
14575 + *
14576 + * Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
14577 + * PWM output, and TIOB as either another PWM or as a trigger. Capture mode
14578 + * uses them only as inputs.
14579 + */
14580 +#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
14581 +#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
14582 +
14583 +#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
14584 +#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
14585 +#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
14586 +#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
14587 +
14588 +#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
14589 +
14590 +/* Both modes share some CMR bits */
14591 +#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
14592 +#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
14593 +#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
14594 +#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
14595 +#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
14596 +#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
14597 +#define ATMEL_TC_XC0 (5 << 0)
14598 +#define ATMEL_TC_XC1 (6 << 0)
14599 +#define ATMEL_TC_XC2 (7 << 0)
14600 +#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
14601 +#define ATMEL_TC_BURST (3 << 4) /* clock gating */
14602 +#define ATMEL_TC_GATE_NONE (0 << 4)
14603 +#define ATMEL_TC_GATE_XC0 (1 << 4)
14604 +#define ATMEL_TC_GATE_XC1 (2 << 4)
14605 +#define ATMEL_TC_GATE_XC2 (3 << 4)
14606 +#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
14607 +
14608 +/* CAPTURE mode CMR bits */
14609 +#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
14610 +#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
14611 +#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
14612 +#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
14613 +#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
14614 +#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
14615 +#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
14616 +#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
14617 +#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
14618 +#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
14619 +#define ATMEL_TC_LDRA_NONE (0 << 16)
14620 +#define ATMEL_TC_LDRA_RISING (1 << 16)
14621 +#define ATMEL_TC_LDRA_FALLING (2 << 16)
14622 +#define ATMEL_TC_LDRA_BOTH (3 << 16)
14623 +#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
14624 +#define ATMEL_TC_LDRB_NONE (0 << 18)
14625 +#define ATMEL_TC_LDRB_RISING (1 << 18)
14626 +#define ATMEL_TC_LDRB_FALLING (2 << 18)
14627 +#define ATMEL_TC_LDRB_BOTH (3 << 18)
14628 +
14629 +/* WAVEFORM mode CMR bits */
14630 +#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
14631 +#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
14632 +#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
14633 +#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
14634 +#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
14635 +#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
14636 +#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
14637 +#define ATMEL_TC_EEVT (3 << 10) /* external event source */
14638 +#define ATMEL_TC_EEVT_TIOB (0 << 10)
14639 +#define ATMEL_TC_EEVT_XC0 (1 << 10)
14640 +#define ATMEL_TC_EEVT_XC1 (2 << 10)
14641 +#define ATMEL_TC_EEVT_XC2 (3 << 10)
14642 +#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
14643 +#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
14644 +#define ATMEL_TC_WAVESEL_UP (0 << 13)
14645 +#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
14646 +#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
14647 +#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
14648 +#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
14649 +#define ATMEL_TC_ACPA_NONE (0 << 16)
14650 +#define ATMEL_TC_ACPA_SET (1 << 16)
14651 +#define ATMEL_TC_ACPA_CLEAR (2 << 16)
14652 +#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
14653 +#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
14654 +#define ATMEL_TC_ACPC_NONE (0 << 18)
14655 +#define ATMEL_TC_ACPC_SET (1 << 18)
14656 +#define ATMEL_TC_ACPC_CLEAR (2 << 18)
14657 +#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
14658 +#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
14659 +#define ATMEL_TC_AEEVT_NONE (0 << 20)
14660 +#define ATMEL_TC_AEEVT_SET (1 << 20)
14661 +#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
14662 +#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
14663 +#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
14664 +#define ATMEL_TC_ASWTRG_NONE (0 << 22)
14665 +#define ATMEL_TC_ASWTRG_SET (1 << 22)
14666 +#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
14667 +#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
14668 +#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
14669 +#define ATMEL_TC_BCPB_NONE (0 << 24)
14670 +#define ATMEL_TC_BCPB_SET (1 << 24)
14671 +#define ATMEL_TC_BCPB_CLEAR (2 << 24)
14672 +#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
14673 +#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
14674 +#define ATMEL_TC_BCPC_NONE (0 << 26)
14675 +#define ATMEL_TC_BCPC_SET (1 << 26)
14676 +#define ATMEL_TC_BCPC_CLEAR (2 << 26)
14677 +#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
14678 +#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
14679 +#define ATMEL_TC_BEEVT_NONE (0 << 28)
14680 +#define ATMEL_TC_BEEVT_SET (1 << 28)
14681 +#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
14682 +#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
14683 +#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
14684 +#define ATMEL_TC_BSWTRG_NONE (0 << 30)
14685 +#define ATMEL_TC_BSWTRG_SET (1 << 30)
14686 +#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
14687 +#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
14688 +
14689 +#define ATMEL_TC_CV 0x10 /* counter Value */
14690 +#define ATMEL_TC_RA 0x14 /* register A */
14691 +#define ATMEL_TC_RB 0x18 /* register B */
14692 +#define ATMEL_TC_RC 0x1c /* register C */
14693 +
14694 +#define ATMEL_TC_SR 0x20 /* status (read-only) */
14695 +/* Status-only flags */
14696 +#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
14697 +#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
14698 +#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
14699 +
14700 +#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
14701 +#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
14702 +#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
14703 +
14704 +/* Status and IRQ flags */
14705 +#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
14706 +#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
14707 +#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
14708 +#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
14709 +#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
14710 +#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
14711 +#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
14712 +#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
14713 +
14714 +#endif
14715 --- a/include/linux/fs.h
14716 +++ b/include/linux/fs.h
14717 @@ -1691,6 +1691,8 @@
14718 extern int invalidate_inode_pages2(struct address_space *mapping);
14719 extern int invalidate_inode_pages2_range(struct address_space *mapping,
14720 pgoff_t start, pgoff_t end);
14721 +extern void generic_sync_sb_inodes(struct super_block *sb,
14722 + struct writeback_control *wbc);
14723 extern int write_inode_now(struct inode *, int);
14724 extern int filemap_fdatawrite(struct address_space *);
14725 extern int filemap_flush(struct address_space *);
14726 --- a/include/linux/serial_core.h
14727 +++ b/include/linux/serial_core.h
14728 @@ -188,6 +188,7 @@
14729 void (*break_ctl)(struct uart_port *, int ctl);
14730 int (*startup)(struct uart_port *);
14731 void (*shutdown)(struct uart_port *);
14732 + void (*flush_buffer)(struct uart_port *);
14733 void (*set_termios)(struct uart_port *, struct ktermios *new,
14734 struct ktermios *old);
14735 void (*pm)(struct uart_port *, unsigned int state,
14736 --- /dev/null
14737 +++ b/include/linux/usb/atmel_usba_udc.h
14738 @@ -0,0 +1,22 @@
14739 +/*
14740 + * Platform data definitions for Atmel USBA gadget driver.
14741 + */
14742 +#ifndef __LINUX_USB_USBA_H
14743 +#define __LINUX_USB_USBA_H
14744 +
14745 +struct usba_ep_data {
14746 + char *name;
14747 + int index;
14748 + int fifo_size;
14749 + int nr_banks;
14750 + int can_dma;
14751 + int can_isoc;
14752 +};
14753 +
14754 +struct usba_platform_data {
14755 + int vbus_pin;
14756 + int num_ep;
14757 + struct usba_ep_data ep[0];
14758 +};
14759 +
14760 +#endif /* __LINUX_USB_USBA_H */
14761 --- a/mm/Kconfig
14762 +++ b/mm/Kconfig
14763 @@ -187,7 +187,7 @@
14764 config NR_QUICK
14765 int
14766 depends on QUICKLIST
14767 - default "2" if SUPERH
14768 + default "2" if SUPERH || AVR32
14769 default "1"
14770
14771 config VIRT_TO_BUS
14772 --- a/sound/Kconfig
14773 +++ b/sound/Kconfig
14774 @@ -63,6 +63,8 @@
14775
14776 source "sound/arm/Kconfig"
14777
14778 +source "sound/avr32/Kconfig"
14779 +
14780 if SPI
14781 source "sound/spi/Kconfig"
14782 endif
14783 --- a/sound/Makefile
14784 +++ b/sound/Makefile
14785 @@ -6,7 +6,7 @@
14786 obj-$(CONFIG_SOUND_PRIME) += oss/
14787 obj-$(CONFIG_DMASOUND) += oss/
14788 obj-$(CONFIG_SND) += core/ i2c/ drivers/ isa/ pci/ ppc/ arm/ sh/ synth/ usb/ \
14789 - sparc/ spi/ parisc/ pcmcia/ mips/ soc/
14790 + sparc/ spi/ parisc/ pcmcia/ mips/ soc/ avr32/
14791 obj-$(CONFIG_SND_AOA) += aoa/
14792
14793 # This one must be compilable even if sound is configured out
14794 --- /dev/null
14795 +++ b/sound/avr32/Kconfig
14796 @@ -0,0 +1,11 @@
14797 +menu "AVR32 devices"
14798 + depends on SND != n && AVR32
14799 +
14800 +config SND_ATMEL_AC97
14801 + tristate "Atmel AC97 Controller Driver"
14802 + select SND_PCM
14803 + select SND_AC97_CODEC
14804 + help
14805 + ALSA sound driver for the Atmel AC97 controller.
14806 +
14807 +endmenu
14808 --- /dev/null
14809 +++ b/sound/avr32/Makefile
14810 @@ -0,0 +1,3 @@
14811 +snd-atmel-ac97-objs := ac97c.o
14812 +
14813 +obj-$(CONFIG_SND_ATMEL_AC97) += snd-atmel-ac97.o
14814 --- /dev/null
14815 +++ b/sound/avr32/ac97c.c
14816 @@ -0,0 +1,951 @@
14817 +/*
14818 + * Driver for the Atmel AC97 controller
14819 + *
14820 + * Copyright (C) 2005-2007 Atmel Corporation
14821 + *
14822 + * This program is free software; you can redistribute it and/or modify it
14823 + * under the terms of the GNU General Public License version 2 as published by
14824 + * the Free Software Foundation.
14825 + */
14826 +#include <linux/clk.h>
14827 +#include <linux/delay.h>
14828 +#include <linux/dma-mapping.h>
14829 +#include <linux/gpio.h>
14830 +#include <linux/init.h>
14831 +#include <linux/interrupt.h>
14832 +#include <linux/module.h>
14833 +#include <linux/platform_device.h>
14834 +#include <linux/mutex.h>
14835 +#include <linux/io.h>
14836 +
14837 +#include <sound/core.h>
14838 +#include <sound/initval.h>
14839 +#include <sound/pcm.h>
14840 +#include <sound/pcm_params.h>
14841 +#include <sound/ac97_codec.h>
14842 +#include <sound/memalloc.h>
14843 +
14844 +#include <asm/arch/board.h>
14845 +#include <asm/dma-controller.h>
14846 +
14847 +#include "ac97c.h"
14848 +
14849 +/* Serialize access to opened */
14850 +static DEFINE_MUTEX(opened_mutex);
14851 +
14852 +struct atmel_ac97_dma_info {
14853 + struct dma_request_cyclic req_tx;
14854 + struct dma_request_cyclic req_rx;
14855 + unsigned short rx_periph_id;
14856 + unsigned short tx_periph_id;
14857 + unsigned short controller;
14858 +};
14859 +
14860 +struct atmel_ac97 {
14861 + /* Serialize access to opened */
14862 + spinlock_t lock;
14863 + void __iomem *regs;
14864 + struct snd_pcm_substream *playback_substream;
14865 + struct snd_pcm_substream *capture_substream;
14866 + struct snd_card *card;
14867 + struct snd_pcm *pcm;
14868 + struct snd_ac97 *ac97;
14869 + struct snd_ac97_bus *ac97_bus;
14870 + int opened;
14871 + int period;
14872 + int reset_pin;
14873 + u64 cur_format;
14874 + unsigned int cur_rate;
14875 + struct clk *mck;
14876 + struct platform_device *pdev;
14877 + struct atmel_ac97_dma_info dma;
14878 +};
14879 +
14880 +#define get_chip(card) ((struct atmel_ac97 *)(card)->private_data)
14881 +
14882 +#define ac97c_writel(chip, reg, val) \
14883 + __raw_writel((val), (chip)->regs + AC97C_##reg)
14884 +#define ac97c_readl(chip, reg) \
14885 + __raw_readl((chip)->regs + AC97C_##reg)
14886 +
14887 +/*
14888 + * PCM part
14889 + */
14890 +static struct snd_pcm_hardware snd_atmel_ac97_playback_hw = {
14891 + .info = (SNDRV_PCM_INFO_INTERLEAVED
14892 + | SNDRV_PCM_INFO_MMAP
14893 + | SNDRV_PCM_INFO_MMAP_VALID
14894 + | SNDRV_PCM_INFO_BLOCK_TRANSFER
14895 + | SNDRV_PCM_INFO_JOINT_DUPLEX),
14896 + .formats = (SNDRV_PCM_FMTBIT_S16_BE
14897 + | SNDRV_PCM_FMTBIT_S16_LE),
14898 + .rates = (SNDRV_PCM_RATE_CONTINUOUS),
14899 + .rate_min = 4000,
14900 + .rate_max = 48000,
14901 + .channels_min = 1,
14902 + .channels_max = 6,
14903 + .buffer_bytes_max = 64*1024,
14904 + .period_bytes_min = 512,
14905 + .period_bytes_max = 4095,
14906 + .periods_min = 8,
14907 + .periods_max = 1024,
14908 +};
14909 +
14910 +static struct snd_pcm_hardware snd_atmel_ac97_capture_hw = {
14911 + .info = (SNDRV_PCM_INFO_INTERLEAVED
14912 + | SNDRV_PCM_INFO_MMAP
14913 + | SNDRV_PCM_INFO_MMAP_VALID
14914 + | SNDRV_PCM_INFO_BLOCK_TRANSFER
14915 + | SNDRV_PCM_INFO_JOINT_DUPLEX),
14916 + .formats = (SNDRV_PCM_FMTBIT_S16_BE
14917 + | SNDRV_PCM_FMTBIT_S16_LE),
14918 + .rates = (SNDRV_PCM_RATE_CONTINUOUS),
14919 + .rate_min = 4000,
14920 + .rate_max = 48000,
14921 + .channels_min = 1,
14922 + .channels_max = 2,
14923 + .buffer_bytes_max = 64*1024,
14924 + .period_bytes_min = 512,
14925 + .period_bytes_max = 4095,
14926 + .periods_min = 8,
14927 + .periods_max = 1024,
14928 +};
14929 +
14930 +/*
14931 + * PCM functions
14932 + */
14933 +static int
14934 +snd_atmel_ac97_playback_open(struct snd_pcm_substream *substream)
14935 +{
14936 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14937 + struct snd_pcm_runtime *runtime = substream->runtime;
14938 +
14939 + mutex_lock(&opened_mutex);
14940 + chip->opened++;
14941 + runtime->hw = snd_atmel_ac97_playback_hw;
14942 + if (chip->cur_rate) {
14943 + runtime->hw.rate_min = chip->cur_rate;
14944 + runtime->hw.rate_max = chip->cur_rate;
14945 + }
14946 + if (chip->cur_format)
14947 + runtime->hw.formats = (1ULL << chip->cur_format);
14948 + mutex_unlock(&opened_mutex);
14949 + chip->playback_substream = substream;
14950 + chip->period = 0;
14951 + return 0;
14952 +}
14953 +
14954 +static int
14955 +snd_atmel_ac97_capture_open(struct snd_pcm_substream *substream)
14956 +{
14957 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14958 + struct snd_pcm_runtime *runtime = substream->runtime;
14959 +
14960 + mutex_lock(&opened_mutex);
14961 + chip->opened++;
14962 + runtime->hw = snd_atmel_ac97_capture_hw;
14963 + if (chip->cur_rate) {
14964 + runtime->hw.rate_min = chip->cur_rate;
14965 + runtime->hw.rate_max = chip->cur_rate;
14966 + }
14967 + if (chip->cur_format)
14968 + runtime->hw.formats = (1ULL << chip->cur_format);
14969 + mutex_unlock(&opened_mutex);
14970 + chip->capture_substream = substream;
14971 + chip->period = 0;
14972 + return 0;
14973 +}
14974 +
14975 +static int snd_atmel_ac97_playback_close(struct snd_pcm_substream *substream)
14976 +{
14977 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14978 + mutex_lock(&opened_mutex);
14979 + chip->opened--;
14980 + if (!chip->opened) {
14981 + chip->cur_rate = 0;
14982 + chip->cur_format = 0;
14983 + }
14984 + mutex_unlock(&opened_mutex);
14985 + return 0;
14986 +}
14987 +
14988 +static int snd_atmel_ac97_capture_close(struct snd_pcm_substream *substream)
14989 +{
14990 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14991 + mutex_lock(&opened_mutex);
14992 + chip->opened--;
14993 + if (!chip->opened) {
14994 + chip->cur_rate = 0;
14995 + chip->cur_format = 0;
14996 + }
14997 + mutex_unlock(&opened_mutex);
14998 + return 0;
14999 +}
15000 +
15001 +static int
15002 +snd_atmel_ac97_playback_hw_params(struct snd_pcm_substream *substream,
15003 + struct snd_pcm_hw_params *hw_params)
15004 +{
15005 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
15006 + int err;
15007 +
15008 + err = snd_pcm_lib_malloc_pages(substream,
15009 + params_buffer_bytes(hw_params));
15010 + if (err < 0)
15011 + return err;
15012 +
15013 + /* Set restrictions to params */
15014 + mutex_lock(&opened_mutex);
15015 + chip->cur_rate = params_rate(hw_params);
15016 + chip->cur_format = params_format(hw_params);
15017 + mutex_unlock(&opened_mutex);
15018 +
15019 + return 0;
15020 +}
15021 +
15022 +static int
15023 +snd_atmel_ac97_capture_hw_params(struct snd_pcm_substream *substream,
15024 + struct snd_pcm_hw_params *hw_params)
15025 +{
15026 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
15027 + int err;
15028 +
15029 + err = snd_pcm_lib_malloc_pages(substream,
15030 + params_buffer_bytes(hw_params));
15031 + if (err < 0)
15032 + return err;
15033 +
15034 + /* Set restrictions to params */
15035 + mutex_lock(&opened_mutex);
15036 + chip->cur_rate = params_rate(hw_params);
15037 + chip->cur_format = params_format(hw_params);
15038 + mutex_unlock(&opened_mutex);
15039 +
15040 + return 0;
15041 +}
15042 +
15043 +static int snd_atmel_ac97_playback_hw_free(struct snd_pcm_substream *substream)
15044 +{
15045 + return snd_pcm_lib_free_pages(substream);
15046 +}
15047 +
15048 +static int snd_atmel_ac97_capture_hw_free(struct snd_pcm_substream *substream)
15049 +{
15050 +
15051 + return snd_pcm_lib_free_pages(substream);
15052 +}
15053 +
15054 +static int snd_atmel_ac97_playback_prepare(struct snd_pcm_substream *substream)
15055 +{
15056 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
15057 + struct platform_device *pdev = chip->pdev;
15058 + struct snd_pcm_runtime *runtime = substream->runtime;
15059 + int block_size = frames_to_bytes(runtime, runtime->period_size);
15060 + unsigned long word = 0;
15061 + unsigned long buffer_size = 0;
15062 +
15063 + dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
15064 + block_size * 2, DMA_TO_DEVICE);
15065 +
15066 + /* Assign slots to channels */
15067 + switch (substream->runtime->channels) {
15068 + case 1:
15069 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
15070 + break;
15071 + case 2:
15072 + /* Assign Left and Right slot to Channel A */
15073 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
15074 + | AC97C_CH_ASSIGN(PCM_RIGHT, A);
15075 + break;
15076 + default:
15077 + /* TODO: support more than two channels */
15078 + return -EINVAL;
15079 + break;
15080 + }
15081 + ac97c_writel(chip, OCA, word);
15082 +
15083 + /* Configure sample format and size */
15084 + word = AC97C_CMR_PDCEN | AC97C_CMR_SIZE_16;
15085 +
15086 + switch (runtime->format) {
15087 + case SNDRV_PCM_FORMAT_S16_LE:
15088 + word |= AC97C_CMR_CEM_LITTLE;
15089 + break;
15090 + case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
15091 + default:
15092 + word &= ~AC97C_CMR_CEM_LITTLE;
15093 + break;
15094 + }
15095 +
15096 + ac97c_writel(chip, CAMR, word);
15097 +
15098 + /* Set variable rate if needed */
15099 + if (runtime->rate != 48000) {
15100 + word = ac97c_readl(chip, MR);
15101 + word |= AC97C_MR_VRA;
15102 + ac97c_writel(chip, MR, word);
15103 + } else {
15104 + /* Clear Variable Rate Bit */
15105 + word = ac97c_readl(chip, MR);
15106 + word &= ~AC97C_MR_VRA;
15107 + ac97c_writel(chip, MR, word);
15108 + }
15109 +
15110 + /* Set rate */
15111 + snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate);
15112 +
15113 + buffer_size = frames_to_bytes(runtime, runtime->period_size) *
15114 + runtime->periods;
15115 +
15116 + chip->dma.req_tx.buffer_size = buffer_size;
15117 + chip->dma.req_tx.periods = runtime->periods;
15118 +
15119 + BUG_ON(chip->dma.req_tx.buffer_size !=
15120 + (chip->dma.req_tx.periods *
15121 + frames_to_bytes(runtime, runtime->period_size)));
15122 +
15123 + chip->dma.req_tx.buffer_start = runtime->dma_addr;
15124 + chip->dma.req_tx.data_reg = (dma_addr_t)(chip->regs + AC97C_CATHR + 2);
15125 + chip->dma.req_tx.periph_id = chip->dma.tx_periph_id;
15126 + chip->dma.req_tx.direction = DMA_DIR_MEM_TO_PERIPH;
15127 + chip->dma.req_tx.width = DMA_WIDTH_16BIT;
15128 + chip->dma.req_tx.dev_id = chip;
15129 +
15130 + return 0;
15131 +}
15132 +
15133 +static int snd_atmel_ac97_capture_prepare(struct snd_pcm_substream *substream)
15134 +{
15135 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
15136 + struct platform_device *pdev = chip->pdev;
15137 + struct snd_pcm_runtime *runtime = substream->runtime;
15138 + int block_size = frames_to_bytes(runtime, runtime->period_size);
15139 + unsigned long word = 0;
15140 + unsigned long buffer_size = 0;
15141 +
15142 + dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
15143 + block_size * 2, DMA_FROM_DEVICE);
15144 +
15145 + /* Assign slots to channels */
15146 + switch (substream->runtime->channels) {
15147 + case 1:
15148 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
15149 + break;
15150 + case 2:
15151 + /* Assign Left and Right slot to Channel A */
15152 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
15153 + | AC97C_CH_ASSIGN(PCM_RIGHT, A);
15154 + break;
15155 + default:
15156 + /* TODO: support more than two channels */
15157 + return -EINVAL;
15158 + break;
15159 + }
15160 + ac97c_writel(chip, ICA, word);
15161 +
15162 + /* Configure sample format and size */
15163 + word = AC97C_CMR_PDCEN | AC97C_CMR_SIZE_16;
15164 +
15165 + switch (runtime->format) {
15166 + case SNDRV_PCM_FORMAT_S16_LE:
15167 + word |= AC97C_CMR_CEM_LITTLE;
15168 + break;
15169 + case SNDRV_PCM_FORMAT_S16_BE:
15170 + default:
15171 + word &= ~(AC97C_CMR_CEM_LITTLE);
15172 + break;
15173 + }
15174 +
15175 + ac97c_writel(chip, CAMR, word);
15176 +
15177 + /* Set variable rate if needed */
15178 + if (runtime->rate != 48000) {
15179 + word = ac97c_readl(chip, MR);
15180 + word |= AC97C_MR_VRA;
15181 + ac97c_writel(chip, MR, word);
15182 + } else {
15183 + /* Clear Variable Rate Bit */
15184 + word = ac97c_readl(chip, MR);
15185 + word &= ~(AC97C_MR_VRA);
15186 + ac97c_writel(chip, MR, word);
15187 + }
15188 +
15189 + /* Set rate */
15190 + snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
15191 +
15192 + buffer_size = frames_to_bytes(runtime, runtime->period_size) *
15193 + runtime->periods;
15194 +
15195 + chip->dma.req_rx.buffer_size = buffer_size;
15196 + chip->dma.req_rx.periods = runtime->periods;
15197 +
15198 + BUG_ON(chip->dma.req_rx.buffer_size !=
15199 + (chip->dma.req_rx.periods *
15200 + frames_to_bytes(runtime, runtime->period_size)));
15201 +
15202 + chip->dma.req_rx.buffer_start = runtime->dma_addr;
15203 + chip->dma.req_rx.data_reg = (dma_addr_t)(chip->regs + AC97C_CARHR + 2);
15204 + chip->dma.req_rx.periph_id = chip->dma.rx_periph_id;
15205 + chip->dma.req_rx.direction = DMA_DIR_PERIPH_TO_MEM;
15206 + chip->dma.req_rx.width = DMA_WIDTH_16BIT;
15207 + chip->dma.req_rx.dev_id = chip;
15208 +
15209 + return 0;
15210 +}
15211 +
15212 + static int
15213 +snd_atmel_ac97_playback_trigger(struct snd_pcm_substream *substream, int cmd)
15214 +{
15215 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
15216 + unsigned long camr;
15217 + int flags, err = 0;
15218 +
15219 + spin_lock_irqsave(&chip->lock, flags);
15220 + camr = ac97c_readl(chip, CAMR);
15221 +
15222 + switch (cmd) {
15223 + case SNDRV_PCM_TRIGGER_START:
15224 + err = dma_prepare_request_cyclic(chip->dma.req_tx.req.dmac,
15225 + &chip->dma.req_tx);
15226 + dma_start_request(chip->dma.req_tx.req.dmac,
15227 + chip->dma.req_tx.req.channel);
15228 + camr |= AC97C_CMR_CENA;
15229 + break;
15230 + case SNDRV_PCM_TRIGGER_STOP:
15231 + err = dma_stop_request(chip->dma.req_tx.req.dmac,
15232 + chip->dma.req_tx.req.channel);
15233 + if (chip->opened <= 1)
15234 + camr &= ~AC97C_CMR_CENA;
15235 + break;
15236 + default:
15237 + err = -EINVAL;
15238 + break;
15239 + }
15240 +
15241 + ac97c_writel(chip, CAMR, camr);
15242 +
15243 + spin_unlock_irqrestore(&chip->lock, flags);
15244 + return err;
15245 +}
15246 +
15247 + static int
15248 +snd_atmel_ac97_capture_trigger(struct snd_pcm_substream *substream, int cmd)
15249 +{
15250 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
15251 + unsigned long camr;
15252 + int flags, err = 0;
15253 +
15254 + spin_lock_irqsave(&chip->lock, flags);
15255 + camr = ac97c_readl(chip, CAMR);
15256 +
15257 + switch (cmd) {
15258 + case SNDRV_PCM_TRIGGER_START:
15259 + err = dma_prepare_request_cyclic(chip->dma.req_rx.req.dmac,
15260 + &chip->dma.req_rx);
15261 + dma_start_request(chip->dma.req_rx.req.dmac,
15262 + chip->dma.req_rx.req.channel);
15263 + camr |= AC97C_CMR_CENA;
15264 + break;
15265 + case SNDRV_PCM_TRIGGER_STOP:
15266 + err = dma_stop_request(chip->dma.req_rx.req.dmac,
15267 + chip->dma.req_rx.req.channel);
15268 + mutex_lock(&opened_mutex);
15269 + if (chip->opened <= 1)
15270 + camr &= ~AC97C_CMR_CENA;
15271 + mutex_unlock(&opened_mutex);
15272 + break;
15273 + default:
15274 + err = -EINVAL;
15275 + break;
15276 + }
15277 +
15278 + ac97c_writel(chip, CAMR, camr);
15279 +
15280 + spin_unlock_irqrestore(&chip->lock, flags);
15281 + return err;
15282 +}
15283 +
15284 + static snd_pcm_uframes_t
15285 +snd_atmel_ac97_playback_pointer(struct snd_pcm_substream *substream)
15286 +{
15287 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
15288 + struct snd_pcm_runtime *runtime = substream->runtime;
15289 + snd_pcm_uframes_t pos;
15290 + unsigned long bytes;
15291 +
15292 + bytes = (dma_get_current_pos
15293 + (chip->dma.req_tx.req.dmac,
15294 + chip->dma.req_tx.req.channel) - runtime->dma_addr);
15295 + pos = bytes_to_frames(runtime, bytes);
15296 + if (pos >= runtime->buffer_size)
15297 + pos -= runtime->buffer_size;
15298 +
15299 + return pos;
15300 +}
15301 +
15302 + static snd_pcm_uframes_t
15303 +snd_atmel_ac97_capture_pointer(struct snd_pcm_substream *substream)
15304 +{
15305 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
15306 + struct snd_pcm_runtime *runtime = substream->runtime;
15307 + snd_pcm_uframes_t pos;
15308 + unsigned long bytes;
15309 +
15310 + bytes = (dma_get_current_pos
15311 + (chip->dma.req_rx.req.dmac,
15312 + chip->dma.req_rx.req.channel)
15313 + - runtime->dma_addr);
15314 + pos = bytes_to_frames(runtime, bytes);
15315 + if (pos >= runtime->buffer_size)
15316 + pos -= runtime->buffer_size;
15317 +
15318 +
15319 + return pos;
15320 +}
15321 +
15322 +static struct snd_pcm_ops atmel_ac97_playback_ops = {
15323 + .open = snd_atmel_ac97_playback_open,
15324 + .close = snd_atmel_ac97_playback_close,
15325 + .ioctl = snd_pcm_lib_ioctl,
15326 + .hw_params = snd_atmel_ac97_playback_hw_params,
15327 + .hw_free = snd_atmel_ac97_playback_hw_free,
15328 + .prepare = snd_atmel_ac97_playback_prepare,
15329 + .trigger = snd_atmel_ac97_playback_trigger,
15330 + .pointer = snd_atmel_ac97_playback_pointer,
15331 +};
15332 +
15333 +static struct snd_pcm_ops atmel_ac97_capture_ops = {
15334 + .open = snd_atmel_ac97_capture_open,
15335 + .close = snd_atmel_ac97_capture_close,
15336 + .ioctl = snd_pcm_lib_ioctl,
15337 + .hw_params = snd_atmel_ac97_capture_hw_params,
15338 + .hw_free = snd_atmel_ac97_capture_hw_free,
15339 + .prepare = snd_atmel_ac97_capture_prepare,
15340 + .trigger = snd_atmel_ac97_capture_trigger,
15341 + .pointer = snd_atmel_ac97_capture_pointer,
15342 +};
15343 +
15344 +static struct ac97_pcm atmel_ac97_pcm_defs[] __devinitdata = {
15345 + /* Playback */
15346 + {
15347 + .exclusive = 1,
15348 + .r = { {
15349 + .slots = ((1 << AC97_SLOT_PCM_LEFT)
15350 + | (1 << AC97_SLOT_PCM_RIGHT)
15351 + | (1 << AC97_SLOT_PCM_CENTER)
15352 + | (1 << AC97_SLOT_PCM_SLEFT)
15353 + | (1 << AC97_SLOT_PCM_SRIGHT)
15354 + | (1 << AC97_SLOT_LFE)),
15355 + } }
15356 + },
15357 + /* PCM in */
15358 + {
15359 + .stream = 1,
15360 + .exclusive = 1,
15361 + .r = { {
15362 + .slots = ((1 << AC97_SLOT_PCM_LEFT)
15363 + | (1 << AC97_SLOT_PCM_RIGHT)),
15364 + } }
15365 + },
15366 + /* Mic in */
15367 + {
15368 + .stream = 1,
15369 + .exclusive = 1,
15370 + .r = { {
15371 + .slots = (1<<AC97_SLOT_MIC),
15372 + } }
15373 + },
15374 +};
15375 +
15376 +static int __devinit snd_atmel_ac97_pcm_new(struct atmel_ac97 *chip)
15377 +{
15378 + struct snd_pcm *pcm;
15379 + int err;
15380 +
15381 + err = snd_ac97_pcm_assign(chip->ac97_bus,
15382 + ARRAY_SIZE(atmel_ac97_pcm_defs),
15383 + atmel_ac97_pcm_defs);
15384 + if (err)
15385 + return err;
15386 +
15387 + err = snd_pcm_new(chip->card, "Atmel-AC97", 0, 1, 1, &pcm);
15388 + if (err)
15389 + return err;
15390 +
15391 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
15392 + &atmel_ac97_playback_ops);
15393 +
15394 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
15395 + &atmel_ac97_capture_ops);
15396 +
15397 + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
15398 + &chip->pdev->dev,
15399 + 128 * 1024, 128 * 1024);
15400 +
15401 + pcm->private_data = chip;
15402 + pcm->info_flags = 0;
15403 + strcpy(pcm->name, "Atmel-AC97");
15404 + chip->pcm = pcm;
15405 +
15406 + return 0;
15407 +}
15408 +
15409 +/*
15410 + * Mixer part.
15411 + */
15412 +static int snd_atmel_ac97_mixer_new(struct atmel_ac97 *chip)
15413 +{
15414 + int err;
15415 + struct snd_ac97_template template;
15416 +
15417 + memset(&template, 0, sizeof(template));
15418 + template.private_data = chip;
15419 + err = snd_ac97_mixer(chip->ac97_bus, &template, &chip->ac97);
15420 +
15421 + return err;
15422 +}
15423 +
15424 +static void atmel_ac97_error(struct dma_request *_req)
15425 +{
15426 + struct dma_request_cyclic *req = to_dma_request_cyclic(_req);
15427 + struct atmel_ac97 *chip = req->dev_id;
15428 +
15429 + dev_dbg(&chip->pdev->dev, "DMA Controller error, channel %d\n",
15430 + req->req.channel);
15431 +}
15432 +
15433 +static void atmel_ac97_block_complete(struct dma_request *_req)
15434 +{
15435 + struct dma_request_cyclic *req = to_dma_request_cyclic(_req);
15436 + struct atmel_ac97 *chip = req->dev_id;
15437 + if (req->periph_id == chip->dma.tx_periph_id)
15438 + snd_pcm_period_elapsed(chip->playback_substream);
15439 + else
15440 + snd_pcm_period_elapsed(chip->capture_substream);
15441 +}
15442 +
15443 +/*
15444 + * Codec part.
15445 + */
15446 +static void snd_atmel_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
15447 + unsigned short val)
15448 +{
15449 + struct atmel_ac97 *chip = get_chip(ac97);
15450 + unsigned long word;
15451 + int timeout = 40;
15452 +
15453 + word = (reg & 0x7f) << 16 | val;
15454 +
15455 + do {
15456 + if (ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) {
15457 + ac97c_writel(chip, COTHR, word);
15458 + return;
15459 + }
15460 + udelay(1);
15461 + } while (--timeout);
15462 +
15463 + dev_dbg(&chip->pdev->dev, "codec write timeout\n");
15464 +}
15465 +
15466 +static unsigned short snd_atmel_ac97_read(struct snd_ac97 *ac97,
15467 + unsigned short reg)
15468 +{
15469 + struct atmel_ac97 *chip = get_chip(ac97);
15470 + unsigned long word;
15471 + int timeout = 40;
15472 + int write = 10;
15473 +
15474 + word = (0x80 | (reg & 0x7f)) << 16;
15475 +
15476 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0)
15477 + ac97c_readl(chip, CORHR);
15478 +
15479 +retry_write:
15480 + timeout = 40;
15481 +
15482 + do {
15483 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) != 0) {
15484 + ac97c_writel(chip, COTHR, word);
15485 + goto read_reg;
15486 + }
15487 + udelay(10);
15488 + } while (--timeout);
15489 +
15490 + if (!--write)
15491 + goto timed_out;
15492 + goto retry_write;
15493 +
15494 +read_reg:
15495 + do {
15496 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0) {
15497 + unsigned short val = ac97c_readl(chip, CORHR);
15498 + return val;
15499 + }
15500 + udelay(10);
15501 + } while (--timeout);
15502 +
15503 + if (!--write)
15504 + goto timed_out;
15505 + goto retry_write;
15506 +
15507 +timed_out:
15508 + dev_dbg(&chip->pdev->dev, "codec read timeout\n");
15509 + return 0xffff;
15510 +}
15511 +
15512 +static void snd_atmel_ac97_reset(struct atmel_ac97 *chip)
15513 +{
15514 + /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
15515 + if (chip->reset_pin >= 0) {
15516 + gpio_set_value(chip->reset_pin, 0);
15517 + /* AC97 v2.2 specifications says minimum 1 us. */
15518 + udelay(5);
15519 + gpio_set_value(chip->reset_pin, 1);
15520 + }
15521 +
15522 + ac97c_writel(chip, MR, AC97C_MR_WRST);
15523 + mdelay(1);
15524 + ac97c_writel(chip, MR, AC97C_MR_ENA);
15525 +}
15526 +
15527 +static void snd_atmel_ac97_destroy(struct snd_card *card)
15528 +{
15529 + struct atmel_ac97 *chip = get_chip(card);
15530 +
15531 + if (chip->regs)
15532 + iounmap(chip->regs);
15533 +
15534 + if (chip->mck) {
15535 + clk_disable(chip->mck);
15536 + clk_put(chip->mck);
15537 + }
15538 +
15539 + if (chip->dma.req_tx.req.dmac) {
15540 + dma_release_channel(chip->dma.req_tx.req.dmac,
15541 + chip->dma.req_tx.req.channel);
15542 + }
15543 + if (chip->dma.req_rx.req.dmac) {
15544 + dma_release_channel(chip->dma.req_rx.req.dmac,
15545 + chip->dma.req_rx.req.channel);
15546 + }
15547 +}
15548 +
15549 +static int __devinit snd_atmel_ac97_create(struct snd_card *card,
15550 + struct platform_device *pdev)
15551 +{
15552 + static struct snd_ac97_bus_ops ops = {
15553 + .write = snd_atmel_ac97_write,
15554 + .read = snd_atmel_ac97_read,
15555 + };
15556 + struct atmel_ac97 *chip = get_chip(card);
15557 + struct ac97c_platform_data *pdata;
15558 + struct resource *regs;
15559 + struct clk *mck;
15560 + int err;
15561 +
15562 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
15563 + if (!regs)
15564 + return -ENXIO;
15565 +
15566 + pdata = pdev->dev.platform_data;
15567 + if (!pdata)
15568 + return -ENXIO;
15569 +
15570 + chip->reset_pin = pdata->reset_pin;
15571 +
15572 + /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
15573 + if (chip->reset_pin >= 0) {
15574 + if (gpio_request(chip->reset_pin, chip->card->shortname)) {
15575 + dev_dbg(&pdev->dev, "ac97: reset pin not available\n");
15576 + chip->reset_pin = -1;
15577 + } else {
15578 + gpio_direction_output(chip->reset_pin, 1);
15579 + }
15580 + }
15581 +
15582 + chip->dma.rx_periph_id = pdata->dma_rx_periph_id;
15583 + chip->dma.tx_periph_id = pdata->dma_tx_periph_id;
15584 + chip->dma.controller = pdata->dma_controller_id;
15585 +
15586 + mck = clk_get(&pdev->dev, "pclk");
15587 + if (IS_ERR(mck))
15588 + return PTR_ERR(mck);
15589 + clk_enable(mck);
15590 + chip->mck = mck;
15591 +
15592 + card->private_free = snd_atmel_ac97_destroy;
15593 +
15594 + spin_lock_init(&chip->lock);
15595 + chip->card = card;
15596 + chip->pdev = pdev;
15597 +
15598 + chip->regs = ioremap(regs->start, regs->end - regs->start + 1);
15599 + if (!chip->regs)
15600 + return -ENOMEM;
15601 +
15602 + snd_card_set_dev(card, &pdev->dev);
15603 +
15604 + err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
15605 +
15606 + return err;
15607 +}
15608 +
15609 +static int __devinit snd_atmel_ac97_probe(struct platform_device *pdev)
15610 +{
15611 + static int dev;
15612 + struct snd_card *card;
15613 + struct atmel_ac97 *chip;
15614 + int err;
15615 + int ch;
15616 +
15617 + mutex_init(&opened_mutex);
15618 +
15619 + err = -ENOMEM;
15620 + card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
15621 + THIS_MODULE, sizeof(struct atmel_ac97));
15622 + if (!card)
15623 + goto out;
15624 +
15625 + chip = get_chip(card);
15626 + chip->reset_pin = -1;
15627 +
15628 + err = snd_atmel_ac97_create(card, pdev);
15629 + if (err)
15630 + goto out_free_card;
15631 +
15632 + snd_atmel_ac97_reset(chip);
15633 +
15634 + err = snd_atmel_ac97_mixer_new(chip);
15635 + if (err)
15636 + goto out_free_card;
15637 +
15638 + err = snd_atmel_ac97_pcm_new(chip);
15639 + if (err)
15640 + goto out_free_card;
15641 +
15642 + chip->dma.req_tx.req.dmac = find_dma_controller(chip->dma.controller);
15643 + if (!chip->dma.req_tx.req.dmac) {
15644 + dev_dbg(&chip->pdev->dev, "DMA controller for TX missing\n");
15645 + err = -ENODEV;
15646 + goto out_free_card;
15647 + }
15648 + chip->dma.req_rx.req.dmac = find_dma_controller(chip->dma.controller);
15649 + if (!chip->dma.req_rx.req.dmac) {
15650 + dev_dbg(&chip->pdev->dev, "DMA controller for RX missing\n");
15651 + err = -ENODEV;
15652 + goto out_free_card;
15653 + }
15654 +
15655 + ch = dma_alloc_channel(chip->dma.req_tx.req.dmac);
15656 + if (ch < 0) {
15657 + dev_dbg(&chip->pdev->dev,
15658 + "could not allocate TX DMA channel\n");
15659 + err = ch;
15660 + goto out_free_card;
15661 + }
15662 + chip->dma.req_tx.req.channel = ch;
15663 + chip->dma.req_tx.width = DMA_WIDTH_16BIT;
15664 + chip->dma.req_tx.req.block_complete = atmel_ac97_block_complete;
15665 + chip->dma.req_tx.req.error = atmel_ac97_error;
15666 +
15667 + ch = dma_alloc_channel(chip->dma.req_rx.req.dmac);
15668 + if (ch < 0) {
15669 + dev_dbg(&chip->pdev->dev,
15670 + "could not allocate RX DMA channel\n");
15671 + err = ch;
15672 + goto out_free_card;
15673 + }
15674 + chip->dma.req_rx.req.channel = ch;
15675 + chip->dma.req_rx.width = DMA_WIDTH_16BIT;
15676 + chip->dma.req_rx.req.block_complete = atmel_ac97_block_complete;
15677 + chip->dma.req_rx.req.error = atmel_ac97_error;
15678 +
15679 + strcpy(card->driver, "atmel_ac97c");
15680 + strcpy(card->shortname, "atmel_ac97c");
15681 + sprintf(card->longname, "Atmel AVR32 AC97 controller");
15682 +
15683 + err = snd_card_register(card);
15684 + if (err)
15685 + goto out_free_card;
15686 +
15687 + platform_set_drvdata(pdev, card);
15688 + dev++;
15689 +
15690 + dev_info(&pdev->dev, "Atmel AVR32 AC97 controller at 0x%p\n",
15691 + chip->regs);
15692 +
15693 + return 0;
15694 +
15695 +out_free_card:
15696 + /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
15697 + if (chip->reset_pin >= 0)
15698 + gpio_free(chip->reset_pin);
15699 + snd_card_free(card);
15700 +out:
15701 + return err;
15702 +}
15703 +
15704 +#ifdef CONFIG_PM
15705 + static int
15706 +snd_atmel_ac97_suspend(struct platform_device *pdev, pm_message_t msg)
15707 +{
15708 + struct snd_card *card = platform_get_drvdata(pdev);
15709 + struct atmel_ac97 *chip = card->private_data;
15710 +
15711 + clk_disable(chip->mck);
15712 +
15713 + return 0;
15714 +}
15715 +
15716 +static int snd_atmel_ac97_resume(struct platform_device *pdev)
15717 +{
15718 + struct snd_card *card = platform_get_drvdata(pdev);
15719 + struct atmel_ac97 *chip = card->private_data;
15720 +
15721 + clk_enable(chip->mck);
15722 +
15723 + return 0;
15724 +}
15725 +#else
15726 +#define snd_atmel_ac97_suspend NULL
15727 +#define snd_atmel_ac97_resume NULL
15728 +#endif
15729 +
15730 +static int __devexit snd_atmel_ac97_remove(struct platform_device *pdev)
15731 +{
15732 + struct snd_card *card = platform_get_drvdata(pdev);
15733 + struct atmel_ac97 *chip = get_chip(card);
15734 +
15735 + /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
15736 + if (chip->reset_pin >= 0)
15737 + gpio_free(chip->reset_pin);
15738 + snd_card_free(card);
15739 + platform_set_drvdata(pdev, NULL);
15740 + return 0;
15741 +}
15742 +
15743 +static struct platform_driver atmel_ac97_driver = {
15744 + .remove = __devexit_p(snd_atmel_ac97_remove),
15745 + .driver = {
15746 + .name = "atmel_ac97c",
15747 + },
15748 + .suspend = snd_atmel_ac97_suspend,
15749 + .resume = snd_atmel_ac97_resume,
15750 +};
15751 +
15752 +static int __init atmel_ac97_init(void)
15753 +{
15754 + return platform_driver_probe(&atmel_ac97_driver,
15755 + snd_atmel_ac97_probe);
15756 +}
15757 +module_init(atmel_ac97_init);
15758 +
15759 +static void __exit atmel_ac97_exit(void)
15760 +{
15761 + platform_driver_unregister(&atmel_ac97_driver);
15762 +}
15763 +module_exit(atmel_ac97_exit);
15764 +
15765 +MODULE_LICENSE("GPL");
15766 +MODULE_DESCRIPTION("Driver for Atmel AC97 Controller");
15767 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
15768 --- /dev/null
15769 +++ b/sound/avr32/ac97c.h
15770 @@ -0,0 +1,71 @@
15771 +/*
15772 + * Register definitions for the Atmel AC97 Controller.
15773 + *
15774 + * Copyright (C) 2005-2006 Atmel Corporation
15775 + *
15776 + * This program is free software; you can redistribute it and/or modify
15777 + * it under the terms of the GNU General Public License version 2 as
15778 + * published by the Free Software Foundation.
15779 + */
15780 +#ifndef __SOUND_AVR32_AC97C_H
15781 +#define __SOUND_AVR32_AC97C_H
15782 +
15783 +#define AC97C_MR 0x08
15784 +#define AC97C_ICA 0x10
15785 +#define AC97C_OCA 0x14
15786 +#define AC97C_CARHR 0x20
15787 +#define AC97C_CATHR 0x24
15788 +#define AC97C_CASR 0x28
15789 +#define AC97C_CAMR 0x2c
15790 +#define AC97C_CBRHR 0x30
15791 +#define AC97C_CBTHR 0x34
15792 +#define AC97C_CBSR 0x38
15793 +#define AC97C_CBMR 0x3c
15794 +#define AC97C_CORHR 0x40
15795 +#define AC97C_COTHR 0x44
15796 +#define AC97C_COSR 0x48
15797 +#define AC97C_COMR 0x4c
15798 +#define AC97C_SR 0x50
15799 +#define AC97C_IER 0x54
15800 +#define AC97C_IDR 0x58
15801 +#define AC97C_IMR 0x5c
15802 +#define AC97C_VERSION 0xfc
15803 +
15804 +#define AC97C_CATPR PDC_TPR
15805 +#define AC97C_CATCR PDC_TCR
15806 +#define AC97C_CATNPR PDC_TNPR
15807 +#define AC97C_CATNCR PDC_TNCR
15808 +#define AC97C_CARPR PDC_RPR
15809 +#define AC97C_CARCR PDC_RCR
15810 +#define AC97C_CARNPR PDC_RNPR
15811 +#define AC97C_CARNCR PDC_RNCR
15812 +#define AC97C_PTCR PDC_PTCR
15813 +
15814 +#define AC97C_MR_ENA (1 << 0)
15815 +#define AC97C_MR_WRST (1 << 1)
15816 +#define AC97C_MR_VRA (1 << 2)
15817 +
15818 +#define AC97C_CSR_TXRDY (1 << 0)
15819 +#define AC97C_CSR_UNRUN (1 << 2)
15820 +#define AC97C_CSR_RXRDY (1 << 4)
15821 +#define AC97C_CSR_ENDTX (1 << 10)
15822 +#define AC97C_CSR_ENDRX (1 << 14)
15823 +
15824 +#define AC97C_CMR_SIZE_20 (0 << 16)
15825 +#define AC97C_CMR_SIZE_18 (1 << 16)
15826 +#define AC97C_CMR_SIZE_16 (2 << 16)
15827 +#define AC97C_CMR_SIZE_10 (3 << 16)
15828 +#define AC97C_CMR_CEM_LITTLE (1 << 18)
15829 +#define AC97C_CMR_CEM_BIG (0 << 18)
15830 +#define AC97C_CMR_CENA (1 << 21)
15831 +#define AC97C_CMR_PDCEN (1 << 22)
15832 +
15833 +#define AC97C_SR_CAEVT (1 << 3)
15834 +
15835 +#define AC97C_CH_ASSIGN(slot, channel) \
15836 + (AC97C_CHANNEL_##channel << (3 * (AC97_SLOT_##slot - 3)))
15837 +#define AC97C_CHANNEL_NONE 0x0
15838 +#define AC97C_CHANNEL_A 0x1
15839 +#define AC97C_CHANNEL_B 0x2
15840 +
15841 +#endif /* __SOUND_AVR32_AC97C_H */
15842 --- a/sound/oss/Kconfig
15843 +++ b/sound/oss/Kconfig
15844 @@ -654,3 +654,7 @@
15845 int "DAC channel"
15846 default "1"
15847 depends on SOUND_SH_DAC_AUDIO
15848 +
15849 +config SOUND_AT32_ABDAC
15850 + tristate "Atmel AT32 Audio Bitstream DAC (ABDAC) support"
15851 + depends on SOUND_PRIME && AVR32
15852 --- a/sound/oss/Makefile
15853 +++ b/sound/oss/Makefile
15854 @@ -9,6 +9,7 @@
15855
15856 # Please leave it as is, cause the link order is significant !
15857
15858 +obj-$(CONFIG_SOUND_AT32_ABDAC) += at32_abdac.o
15859 obj-$(CONFIG_SOUND_SH_DAC_AUDIO) += sh_dac_audio.o
15860 obj-$(CONFIG_SOUND_HAL2) += hal2.o
15861 obj-$(CONFIG_SOUND_AEDSP16) += aedsp16.o
15862 --- /dev/null
15863 +++ b/sound/oss/at32_abdac.c
15864 @@ -0,0 +1,722 @@
15865 +/*
15866 + * OSS Sound Driver for the Atmel AT32 on-chip DAC.
15867 + *
15868 + * Copyright (C) 2006 Atmel Corporation
15869 + *
15870 + * This program is free software; you can redistribute it and/or modify
15871 + * it under the terms of the GNU General Public License version 2 as
15872 + * published by the Free Software Foundation.
15873 + */
15874 +#include <linux/clk.h>
15875 +#include <linux/dma-mapping.h>
15876 +#include <linux/fs.h>
15877 +#include <linux/init.h>
15878 +#include <linux/interrupt.h>
15879 +#include <linux/kernel.h>
15880 +#include <linux/module.h>
15881 +#include <linux/platform_device.h>
15882 +#include <linux/sound.h>
15883 +#include <linux/soundcard.h>
15884 +
15885 +#include <asm/byteorder.h>
15886 +#include <asm/dma-controller.h>
15887 +#include <asm/io.h>
15888 +#include <asm/uaccess.h>
15889 +
15890 +/* We want to use the "bizarre" swap-bytes-in-each-halfword macro */
15891 +#include <linux/byteorder/swabb.h>
15892 +
15893 +#include "at32_abdac.h"
15894 +
15895 +#define DMA_BUFFER_SIZE 32768
15896 +#define DMA_PERIOD_SHIFT 10
15897 +#define DMA_PERIOD_SIZE (1 << DMA_PERIOD_SHIFT)
15898 +#define DMA_WRITE_THRESHOLD DMA_PERIOD_SIZE
15899 +
15900 +struct sound_settings {
15901 + unsigned int format;
15902 + unsigned int channels;
15903 + unsigned int sample_rate;
15904 + /* log2(bytes per sample) */
15905 + unsigned int input_order;
15906 +};
15907 +
15908 +struct at32_dac {
15909 + spinlock_t lock;
15910 + void __iomem *regs;
15911 +
15912 + /* head and tail refer to number of words */
15913 + struct {
15914 + u32 *buf;
15915 + int head;
15916 + int tail;
15917 + } dma;
15918 +
15919 + struct semaphore sem;
15920 + wait_queue_head_t write_wait;
15921 +
15922 + /*
15923 + * Read at most ucount bytes from ubuf, translate to 2-channel
15924 + * signed 16-bit big endian format and write to the DMA buffer
15925 + * as long as there is room left. Return the number of bytes
15926 + * successfully copied from ubuf, or -EFAULT if the first
15927 + * sample from ubuf couldn't be read. This function is not
15928 + * called unless there is room for at least one sample (4
15929 + * bytes) in the DMA buffer.
15930 + */
15931 + ssize_t (*trans)(struct at32_dac *dac, const char __user *ubuf,
15932 + size_t ucount);
15933 +
15934 + struct sound_settings dsp_settings;
15935 + struct dma_request_cyclic req;
15936 +
15937 + struct clk *mck;
15938 + struct clk *sample_clk;
15939 + struct platform_device *pdev;
15940 + int busy;
15941 + int playing;
15942 + int dev_dsp;
15943 +};
15944 +static struct at32_dac *the_dac;
15945 +
15946 +static inline unsigned int abdac_get_head(struct at32_dac *dac)
15947 +{
15948 + return dac->dma.head & ((DMA_BUFFER_SIZE / 4) - 1);
15949 +}
15950 +
15951 +static inline unsigned int abdac_get_tail(struct at32_dac *dac)
15952 +{
15953 + return dac->dma.tail & ((DMA_BUFFER_SIZE / 4) - 1);
15954 +}
15955 +
15956 +static inline unsigned int abdac_dma_space(struct at32_dac *dac)
15957 +{
15958 + unsigned int space;
15959 +
15960 + space = ((dac->dma.tail - dac->dma.head - 1)
15961 + & ((DMA_BUFFER_SIZE / 4) - 1));
15962 + return space;
15963 +}
15964 +
15965 +static void abdac_update_dma_tail(struct at32_dac *dac)
15966 +{
15967 + dma_addr_t dma_addr;
15968 + unsigned int new_tail;
15969 +
15970 + if (dac->playing) {
15971 + dma_addr = dma_get_current_pos(dac->req.req.dmac,
15972 + dac->req.req.channel);
15973 + new_tail = (dma_addr - dac->req.buffer_start) / 4;
15974 + if (new_tail >= dac->dma.head
15975 + && (dac->dma.tail < dac->dma.head
15976 + || dac->dma.tail > new_tail))
15977 + dev_notice(&dac->pdev->dev, "DMA underrun detected!\n");
15978 + dac->dma.tail = new_tail;
15979 + dev_dbg(&dac->pdev->dev, "update tail: 0x%x - 0x%x = %u\n",
15980 + dma_addr, dac->req.buffer_start, dac->dma.tail);
15981 + }
15982 +}
15983 +
15984 +static int abdac_start(struct at32_dac *dac)
15985 +{
15986 + int ret;
15987 +
15988 + if (dac->playing)
15989 + return 0;
15990 +
15991 + memset(dac->dma.buf, 0, DMA_BUFFER_SIZE);
15992 +
15993 + clk_enable(dac->sample_clk);
15994 +
15995 + ret = dma_prepare_request_cyclic(dac->req.req.dmac, &dac->req);
15996 + if (ret)
15997 + goto out_stop_clock;
15998 +
15999 + dev_dbg(&dac->pdev->dev, "starting DMA...\n");
16000 + ret = dma_start_request(dac->req.req.dmac, dac->req.req.channel);
16001 + if (ret)
16002 + goto out_stop_request;
16003 +
16004 + dac_writel(dac, CTRL, DAC_BIT(EN));
16005 + dac->playing = 1;
16006 +
16007 + return 0;
16008 +
16009 +out_stop_request:
16010 + dma_stop_request(dac->req.req.dmac,
16011 + dac->req.req.channel);
16012 +out_stop_clock:
16013 + clk_disable(dac->sample_clk);
16014 + return ret;
16015 +}
16016 +
16017 +static int abdac_stop(struct at32_dac *dac)
16018 +{
16019 + if (dac->playing) {
16020 + dma_stop_request(dac->req.req.dmac, dac->req.req.channel);
16021 + dac_writel(dac, DATA, 0);
16022 + dac_writel(dac, CTRL, 0);
16023 + dac->playing = 0;
16024 + clk_disable(dac->sample_clk);
16025 + }
16026 +
16027 + return 0;
16028 +}
16029 +
16030 +static int abdac_dma_prepare(struct at32_dac *dac)
16031 +{
16032 + dac->dma.buf = dma_alloc_coherent(&dac->pdev->dev, DMA_BUFFER_SIZE,
16033 + &dac->req.buffer_start, GFP_KERNEL);
16034 + if (!dac->dma.buf)
16035 + return -ENOMEM;
16036 +
16037 + dac->dma.head = dac->dma.tail = 0;
16038 + dac->req.periods = DMA_BUFFER_SIZE / DMA_PERIOD_SIZE;
16039 + dac->req.buffer_size = DMA_BUFFER_SIZE;
16040 +
16041 + return 0;
16042 +}
16043 +
16044 +static void abdac_dma_cleanup(struct at32_dac *dac)
16045 +{
16046 + if (dac->dma.buf)
16047 + dma_free_coherent(&dac->pdev->dev, DMA_BUFFER_SIZE,
16048 + dac->dma.buf, dac->req.buffer_start);
16049 + dac->dma.buf = NULL;
16050 +}
16051 +
16052 +static void abdac_dma_block_complete(struct dma_request *req)
16053 +{
16054 + struct dma_request_cyclic *creq = to_dma_request_cyclic(req);
16055 + struct at32_dac *dac = container_of(creq, struct at32_dac, req);
16056 +
16057 + wake_up(&dac->write_wait);
16058 +}
16059 +
16060 +static void abdac_dma_error(struct dma_request *req)
16061 +{
16062 + struct dma_request_cyclic *creq = to_dma_request_cyclic(req);
16063 + struct at32_dac *dac = container_of(creq, struct at32_dac, req);
16064 +
16065 + dev_err(&dac->pdev->dev, "DMA error\n");
16066 +}
16067 +
16068 +static irqreturn_t abdac_interrupt(int irq, void *dev_id)
16069 +{
16070 + struct at32_dac *dac = dev_id;
16071 + u32 status;
16072 +
16073 + status = dac_readl(dac, INT_STATUS);
16074 + if (status & DAC_BIT(UNDERRUN)) {
16075 + dev_err(&dac->pdev->dev, "Underrun detected!\n");
16076 + dac_writel(dac, INT_CLR, DAC_BIT(UNDERRUN));
16077 + } else {
16078 + dev_err(&dac->pdev->dev, "Spurious interrupt (status=0x%x)\n",
16079 + status);
16080 + dac_writel(dac, INT_CLR, status);
16081 + }
16082 +
16083 + return IRQ_HANDLED;
16084 +}
16085 +
16086 +static ssize_t trans_s16be(struct at32_dac *dac, const char __user *ubuf,
16087 + size_t ucount)
16088 +{
16089 + ssize_t ret;
16090 +
16091 + if (dac->dsp_settings.channels == 2) {
16092 + const u32 __user *up = (const u32 __user *)ubuf;
16093 + u32 sample;
16094 +
16095 + for (ret = 0; ret < (ssize_t)(ucount - 3); ret += 4) {
16096 + if (!abdac_dma_space(dac))
16097 + break;
16098 +
16099 + if (unlikely(__get_user(sample, up++))) {
16100 + if (ret == 0)
16101 + ret = -EFAULT;
16102 + break;
16103 + }
16104 + dac->dma.buf[abdac_get_head(dac)] = sample;
16105 + dac->dma.head++;
16106 + }
16107 + } else {
16108 + const u16 __user *up = (const u16 __user *)ubuf;
16109 + u16 sample;
16110 +
16111 + for (ret = 0; ret < (ssize_t)(ucount - 1); ret += 2) {
16112 + if (!abdac_dma_space(dac))
16113 + break;
16114 +
16115 + if (unlikely(__get_user(sample, up++))) {
16116 + if (ret == 0)
16117 + ret = -EFAULT;
16118 + break;
16119 + }
16120 + dac->dma.buf[abdac_get_head(dac)]
16121 + = (sample << 16) | sample;
16122 + dac->dma.head++;
16123 + }
16124 + }
16125 +
16126 + return ret;
16127 +}
16128 +
16129 +static ssize_t trans_s16le(struct at32_dac *dac, const char __user *ubuf,
16130 + size_t ucount)
16131 +{
16132 + ssize_t ret;
16133 +
16134 + if (dac->dsp_settings.channels == 2) {
16135 + const u32 __user *up = (const u32 __user *)ubuf;
16136 + u32 sample;
16137 +
16138 + for (ret = 0; ret < (ssize_t)(ucount - 3); ret += 4) {
16139 + if (!abdac_dma_space(dac))
16140 + break;
16141 +
16142 + if (unlikely(__get_user(sample, up++))) {
16143 + if (ret == 0)
16144 + ret = -EFAULT;
16145 + break;
16146 + }
16147 + /* Swap bytes in each halfword */
16148 + dac->dma.buf[abdac_get_head(dac)] = swahb32(sample);
16149 + dac->dma.head++;
16150 + }
16151 + } else {
16152 + const u16 __user *up = (const u16 __user *)ubuf;
16153 + u16 sample;
16154 +
16155 + for (ret = 0; ret < (ssize_t)(ucount - 1); ret += 2) {
16156 + if (!abdac_dma_space(dac))
16157 + break;
16158 +
16159 + if (unlikely(__get_user(sample, up++))) {
16160 + if (ret == 0)
16161 + ret = -EFAULT;
16162 + break;
16163 + }
16164 + sample = swab16(sample);
16165 + dac->dma.buf[abdac_get_head(dac)]
16166 + = (sample << 16) | sample;
16167 + dac->dma.head++;
16168 + }
16169 + }
16170 +
16171 + return ret;
16172 +}
16173 +
16174 +static ssize_t abdac_dma_translate_from_user(struct at32_dac *dac,
16175 + const char __user *buffer,
16176 + size_t count)
16177 +{
16178 + /* At least one buffer must be available at this point */
16179 + dev_dbg(&dac->pdev->dev, "copying %zu bytes from user...\n", count);
16180 +
16181 + return dac->trans(dac, buffer, count);
16182 +}
16183 +
16184 +static int abdac_set_format(struct at32_dac *dac, int format)
16185 +{
16186 + unsigned int order;
16187 +
16188 + switch (format) {
16189 + case AFMT_S16_BE:
16190 + order = 1;
16191 + dac->trans = trans_s16be;
16192 + break;
16193 + case AFMT_S16_LE:
16194 + order = 1;
16195 + dac->trans = trans_s16le;
16196 + break;
16197 + default:
16198 + dev_dbg(&dac->pdev->dev, "unsupported format: %d\n", format);
16199 + return -EINVAL;
16200 + }
16201 +
16202 + if (dac->dsp_settings.channels == 2)
16203 + order++;
16204 +
16205 + dac->dsp_settings.input_order = order;
16206 + dac->dsp_settings.format = format;
16207 + return 0;
16208 +}
16209 +
16210 +static int abdac_set_sample_rate(struct at32_dac *dac, unsigned long rate)
16211 +{
16212 + unsigned long new_rate;
16213 + int ret;
16214 +
16215 + ret = clk_set_rate(dac->sample_clk, 256 * rate);
16216 + if (ret < 0)
16217 + return ret;
16218 +
16219 + /* TODO: mplayer seems to have a problem with this */
16220 +#if 0
16221 + new_rate = clk_get_rate(dac->sample_clk);
16222 + dac->dsp_settings.sample_rate = new_rate / 256;
16223 +#else
16224 + dac->dsp_settings.sample_rate = rate;
16225 +#endif
16226 +
16227 + return 0;
16228 +}
16229 +
16230 +static ssize_t abdac_dsp_write(struct file *file,
16231 + const char __user *buffer,
16232 + size_t count, loff_t *ppos)
16233 +{
16234 + struct at32_dac *dac = file->private_data;
16235 + DECLARE_WAITQUEUE(wait, current);
16236 + unsigned int avail;
16237 + ssize_t copied;
16238 + ssize_t ret;
16239 +
16240 + /* Avoid address space checking in the translation functions */
16241 + if (!access_ok(buffer, count, VERIFY_READ))
16242 + return -EFAULT;
16243 +
16244 + down(&dac->sem);
16245 +
16246 + if (!dac->dma.buf) {
16247 + ret = abdac_dma_prepare(dac);
16248 + if (ret)
16249 + goto out;
16250 + }
16251 +
16252 + add_wait_queue(&dac->write_wait, &wait);
16253 + ret = 0;
16254 + while (count > 0) {
16255 + do {
16256 + abdac_update_dma_tail(dac);
16257 + avail = abdac_dma_space(dac);
16258 + set_current_state(TASK_INTERRUPTIBLE);
16259 + if (avail >= DMA_WRITE_THRESHOLD)
16260 + break;
16261 +
16262 + if (file->f_flags & O_NONBLOCK) {
16263 + if (!ret)
16264 + ret = -EAGAIN;
16265 + goto out;
16266 + }
16267 +
16268 + pr_debug("Going to wait (avail = %u, count = %zu)\n",
16269 + avail, count);
16270 +
16271 + up(&dac->sem);
16272 + schedule();
16273 + if (signal_pending(current)) {
16274 + if (!ret)
16275 + ret = -ERESTARTSYS;
16276 + goto out_nosem;
16277 + }
16278 + down(&dac->sem);
16279 + } while (1);
16280 +
16281 + copied = abdac_dma_translate_from_user(dac, buffer, count);
16282 + if (copied < 0) {
16283 + if (!ret)
16284 + ret = -EFAULT;
16285 + goto out;
16286 + }
16287 +
16288 + abdac_start(dac);
16289 +
16290 + count -= copied;
16291 + ret += copied;
16292 + }
16293 +
16294 +out:
16295 + up(&dac->sem);
16296 +out_nosem:
16297 + remove_wait_queue(&dac->write_wait, &wait);
16298 + set_current_state(TASK_RUNNING);
16299 + return ret;
16300 +}
16301 +
16302 +static int abdac_dsp_ioctl(struct inode *inode, struct file *file,
16303 + unsigned int cmd, unsigned long arg)
16304 +{
16305 + struct at32_dac *dac = file->private_data;
16306 + int __user *up = (int __user *)arg;
16307 + struct audio_buf_info abinfo;
16308 + int val, ret;
16309 +
16310 + switch (cmd) {
16311 + case OSS_GETVERSION:
16312 + return put_user(SOUND_VERSION, up);
16313 +
16314 + case SNDCTL_DSP_SPEED:
16315 + if (get_user(val, up))
16316 + return -EFAULT;
16317 + if (val >= 0) {
16318 + abdac_stop(dac);
16319 + ret = abdac_set_sample_rate(dac, val);
16320 + if (ret)
16321 + return ret;
16322 + }
16323 + return put_user(dac->dsp_settings.sample_rate, up);
16324 +
16325 + case SNDCTL_DSP_STEREO:
16326 + if (get_user(val, up))
16327 + return -EFAULT;
16328 + abdac_stop(dac);
16329 + if (val && dac->dsp_settings.channels == 1)
16330 + dac->dsp_settings.input_order++;
16331 + else if (!val && dac->dsp_settings.channels != 1)
16332 + dac->dsp_settings.input_order--;
16333 + dac->dsp_settings.channels = val ? 2 : 1;
16334 + return 0;
16335 +
16336 + case SNDCTL_DSP_CHANNELS:
16337 + if (get_user(val, up))
16338 + return -EFAULT;
16339 +
16340 + if (val) {
16341 + if (val < 0 || val > 2)
16342 + return -EINVAL;
16343 +
16344 + abdac_stop(dac);
16345 + dac->dsp_settings.input_order
16346 + += val - dac->dsp_settings.channels;
16347 + dac->dsp_settings.channels = val;
16348 + }
16349 + return put_user(val, (int *)arg);
16350 +
16351 + case SNDCTL_DSP_GETFMTS:
16352 + return put_user(AFMT_S16_BE | AFMT_S16_BE, up);
16353 +
16354 + case SNDCTL_DSP_SETFMT:
16355 + if (get_user(val, up))
16356 + return -EFAULT;
16357 +
16358 + if (val == AFMT_QUERY) {
16359 + val = dac->dsp_settings.format;
16360 + } else {
16361 + ret = abdac_set_format(dac, val);
16362 + if (ret)
16363 + return ret;
16364 + }
16365 + return put_user(val, up);
16366 +
16367 + case SNDCTL_DSP_GETOSPACE:
16368 + abdac_update_dma_tail(dac);
16369 + abinfo.fragsize = ((1 << dac->dsp_settings.input_order)
16370 + * (DMA_PERIOD_SIZE / 4));
16371 + abinfo.bytes = (abdac_dma_space(dac)
16372 + << dac->dsp_settings.input_order);
16373 + abinfo.fragstotal = ((DMA_BUFFER_SIZE * 4)
16374 + >> (DMA_PERIOD_SHIFT
16375 + + dac->dsp_settings.input_order));
16376 + abinfo.fragments = ((abinfo.bytes
16377 + >> dac->dsp_settings.input_order)
16378 + / (DMA_PERIOD_SIZE / 4));
16379 + pr_debug("fragments=%d fragstotal=%d fragsize=%d bytes=%d\n",
16380 + abinfo.fragments, abinfo.fragstotal, abinfo.fragsize,
16381 + abinfo.bytes);
16382 + return copy_to_user(up, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
16383 +
16384 + default:
16385 + dev_dbg(&dac->pdev->dev, "Unimplemented ioctl cmd: 0x%x\n", cmd);
16386 + return -EINVAL;
16387 + }
16388 +}
16389 +
16390 +static int abdac_dsp_open(struct inode *inode, struct file *file)
16391 +{
16392 + struct at32_dac *dac = the_dac;
16393 + int ret;
16394 +
16395 + if (file->f_mode & FMODE_READ)
16396 + return -ENXIO;
16397 +
16398 + down(&dac->sem);
16399 + ret = -EBUSY;
16400 + if (dac->busy)
16401 + goto out;
16402 +
16403 + dac->dma.head = dac->dma.tail = 0;
16404 +
16405 + /* FIXME: What are the correct defaults? */
16406 + dac->dsp_settings.channels = 2;
16407 + abdac_set_format(dac, AFMT_S16_BE);
16408 + ret = abdac_set_sample_rate(dac, 8000);
16409 + if (ret)
16410 + goto out;
16411 +
16412 + file->private_data = dac;
16413 + dac->busy = 1;
16414 +
16415 + ret = 0;
16416 +
16417 +out:
16418 + up(&dac->sem);
16419 + return ret;
16420 +}
16421 +
16422 +static int abdac_dsp_release(struct inode *inode, struct file *file)
16423 +{
16424 + struct at32_dac *dac = file->private_data;
16425 +
16426 + down(&dac->sem);
16427 +
16428 + abdac_stop(dac);
16429 + abdac_dma_cleanup(dac);
16430 + dac->busy = 0;
16431 +
16432 + up(&dac->sem);
16433 +
16434 + return 0;
16435 +}
16436 +
16437 +static struct file_operations abdac_dsp_fops = {
16438 + .owner = THIS_MODULE,
16439 + .llseek = no_llseek,
16440 + .write = abdac_dsp_write,
16441 + .ioctl = abdac_dsp_ioctl,
16442 + .open = abdac_dsp_open,
16443 + .release = abdac_dsp_release,
16444 +};
16445 +
16446 +static int __init abdac_probe(struct platform_device *pdev)
16447 +{
16448 + struct at32_dac *dac;
16449 + struct resource *regs;
16450 + struct clk *mck;
16451 + struct clk *sample_clk;
16452 + int irq;
16453 + int ret;
16454 +
16455 + if (the_dac)
16456 + return -EBUSY;
16457 +
16458 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
16459 + if (!regs)
16460 + return -ENXIO;
16461 + irq = platform_get_irq(pdev, 0);
16462 + if (irq < 0)
16463 + return irq;
16464 +
16465 + mck = clk_get(&pdev->dev, "pclk");
16466 + if (IS_ERR(mck))
16467 + return PTR_ERR(mck);
16468 + sample_clk = clk_get(&pdev->dev, "sample_clk");
16469 + if (IS_ERR(sample_clk)) {
16470 + ret = PTR_ERR(sample_clk);
16471 + goto out_put_mck;
16472 + }
16473 + clk_enable(mck);
16474 +
16475 + ret = -ENOMEM;
16476 + dac = kzalloc(sizeof(struct at32_dac), GFP_KERNEL);
16477 + if (!dac)
16478 + goto out_disable_clk;
16479 +
16480 + spin_lock_init(&dac->lock);
16481 + init_MUTEX(&dac->sem);
16482 + init_waitqueue_head(&dac->write_wait);
16483 + dac->pdev = pdev;
16484 + dac->mck = mck;
16485 + dac->sample_clk = sample_clk;
16486 +
16487 + dac->regs = ioremap(regs->start, regs->end - regs->start + 1);
16488 + if (!dac->regs)
16489 + goto out_free_dac;
16490 +
16491 + ret = request_irq(irq, abdac_interrupt, 0, "dac", dac);
16492 + if (ret)
16493 + goto out_unmap_regs;
16494 +
16495 + /* FIXME */
16496 + dac->req.req.dmac = find_dma_controller(0);
16497 + if (!dac->req.req.dmac)
16498 + goto out_free_irq;
16499 +
16500 + ret = dma_alloc_channel(dac->req.req.dmac);
16501 + if (ret < 0)
16502 + goto out_free_irq;
16503 +
16504 + dac->req.req.channel = ret;
16505 + dac->req.req.block_complete = abdac_dma_block_complete;
16506 + dac->req.req.error = abdac_dma_error;
16507 + dac->req.data_reg = regs->start + DAC_DATA;
16508 + dac->req.periph_id = 2; /* FIXME */
16509 + dac->req.direction = DMA_DIR_MEM_TO_PERIPH;
16510 + dac->req.width = DMA_WIDTH_32BIT;
16511 +
16512 + /* Make sure the DAC is silent and disabled */
16513 + dac_writel(dac, DATA, 0);
16514 + dac_writel(dac, CTRL, 0);
16515 +
16516 + ret = register_sound_dsp(&abdac_dsp_fops, -1);
16517 + if (ret < 0)
16518 + goto out_free_dma;
16519 + dac->dev_dsp = ret;
16520 +
16521 + /* TODO: Register mixer */
16522 +
16523 + the_dac = dac;
16524 + platform_set_drvdata(pdev, dac);
16525 +
16526 + return 0;
16527 +
16528 +out_free_dma:
16529 + dma_release_channel(dac->req.req.dmac, dac->req.req.channel);
16530 +out_free_irq:
16531 + free_irq(irq, dac);
16532 +out_unmap_regs:
16533 + iounmap(dac->regs);
16534 +out_free_dac:
16535 + kfree(dac);
16536 +out_disable_clk:
16537 + clk_disable(mck);
16538 + clk_put(sample_clk);
16539 +out_put_mck:
16540 + clk_put(mck);
16541 + return ret;
16542 +}
16543 +
16544 +static int __exit abdac_remove(struct platform_device *pdev)
16545 +{
16546 + struct at32_dac *dac;
16547 +
16548 + dac = platform_get_drvdata(pdev);
16549 + if (dac) {
16550 + unregister_sound_dsp(dac->dev_dsp);
16551 + dma_release_channel(dac->req.req.dmac, dac->req.req.channel);
16552 + free_irq(platform_get_irq(pdev, 0), dac);
16553 + iounmap(dac->regs);
16554 + clk_disable(dac->mck);
16555 + clk_put(dac->sample_clk);
16556 + clk_put(dac->mck);
16557 + kfree(dac);
16558 + platform_set_drvdata(pdev, NULL);
16559 + the_dac = NULL;
16560 + }
16561 +
16562 + return 0;
16563 +}
16564 +
16565 +static struct platform_driver abdac_driver = {
16566 + .remove = __exit_p(abdac_remove),
16567 + .driver = {
16568 + .name = "abdac",
16569 + },
16570 +};
16571 +
16572 +static int __init abdac_init(void)
16573 +{
16574 + return platform_driver_probe(&abdac_driver, abdac_probe);
16575 +}
16576 +module_init(abdac_init);
16577 +
16578 +static void __exit abdac_exit(void)
16579 +{
16580 + platform_driver_unregister(&abdac_driver);
16581 +}
16582 +module_exit(abdac_exit);
16583 +
16584 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
16585 +MODULE_DESCRIPTION("Sound Driver for the Atmel AT32 ABDAC");
16586 +MODULE_LICENSE("GPL");
16587 --- /dev/null
16588 +++ b/sound/oss/at32_abdac.h
16589 @@ -0,0 +1,59 @@
16590 +/*
16591 + * Register definitions for the Atmel AT32 on-chip DAC.
16592 + *
16593 + * Copyright (C) 2006 Atmel Corporation
16594 + *
16595 + * This program is free software; you can redistribute it and/or modify
16596 + * it under the terms of the GNU General Public License version 2 as
16597 + * published by the Free Software Foundation.
16598 + */
16599 +#ifndef __SOUND_OSS_AT32_ABDAC_H__
16600 +#define __SOUND_OSS_AT32_ABDAC_H__
16601 +
16602 +/* DAC register offsets */
16603 +#define DAC_DATA 0x0000
16604 +#define DAC_CTRL 0x0008
16605 +#define DAC_INT_MASK 0x000c
16606 +#define DAC_INT_EN 0x0010
16607 +#define DAC_INT_DIS 0x0014
16608 +#define DAC_INT_CLR 0x0018
16609 +#define DAC_INT_STATUS 0x001c
16610 +#define DAC_PDC_DATA 0x0020
16611 +
16612 +/* Bitfields in CTRL */
16613 +#define DAC_SWAP_OFFSET 30
16614 +#define DAC_SWAP_SIZE 1
16615 +#define DAC_EN_OFFSET 31
16616 +#define DAC_EN_SIZE 1
16617 +
16618 +/* Bitfields in INT_MASK/INT_EN/INT_DIS/INT_STATUS/INT_CLR */
16619 +#define DAC_UNDERRUN_OFFSET 28
16620 +#define DAC_UNDERRUN_SIZE 1
16621 +#define DAC_TX_READY_OFFSET 29
16622 +#define DAC_TX_READY_SIZE 1
16623 +#define DAC_TX_BUFFER_EMPTY_OFFSET 30
16624 +#define DAC_TX_BUFFER_EMPTY_SIZE 1
16625 +#define DAC_CHANNEL_TX_END_OFFSET 31
16626 +#define DAC_CHANNEL_TX_END_SIZE 1
16627 +
16628 +/* Bit manipulation macros */
16629 +#define DAC_BIT(name) \
16630 + (1 << DAC_##name##_OFFSET)
16631 +#define DAC_BF(name, value) \
16632 + (((value) & ((1 << DAC_##name##_SIZE) - 1)) \
16633 + << DAC_##name##_OFFSET)
16634 +#define DAC_BFEXT(name, value) \
16635 + (((value) >> DAC_##name##_OFFSET) \
16636 + & ((1 << DAC_##name##_SIZE) - 1))
16637 +#define DAC_BFINS(name, value, old) \
16638 + (((old) & ~(((1 << DAC_##name##_SIZE) - 1) \
16639 + << DAC_##name##_OFFSET)) \
16640 + | DAC_BF(name,value))
16641 +
16642 +/* Register access macros */
16643 +#define dac_readl(port, reg) \
16644 + __raw_readl((port)->regs + DAC_##reg)
16645 +#define dac_writel(port, reg, value) \
16646 + __raw_writel((value), (port)->regs + DAC_##reg)
16647 +
16648 +#endif /* __SOUND_OSS_AT32_ABDAC_H__ */
16649 --- a/sound/spi/at73c213.c
16650 +++ b/sound/spi/at73c213.c
16651 @@ -737,7 +737,7 @@
16652 /*
16653 * Device functions
16654 */
16655 -static int snd_at73c213_ssc_init(struct snd_at73c213 *chip)
16656 +static int __devinit snd_at73c213_ssc_init(struct snd_at73c213 *chip)
16657 {
16658 /*
16659 * Continuous clock output.
16660 @@ -767,7 +767,7 @@
16661 return 0;
16662 }
16663
16664 -static int snd_at73c213_chip_init(struct snd_at73c213 *chip)
16665 +static int __devinit snd_at73c213_chip_init(struct snd_at73c213 *chip)
16666 {
16667 int retval;
16668 unsigned char dac_ctrl = 0;
16669 @@ -933,7 +933,7 @@
16670 return retval;
16671 }
16672
16673 -static int snd_at73c213_probe(struct spi_device *spi)
16674 +static int __devinit snd_at73c213_probe(struct spi_device *spi)
16675 {
16676 struct snd_card *card;
16677 struct snd_at73c213 *chip;
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