target/linux/brcm2708/patches-4.4/0291-drm-vc4-Fix-setting-of-vertical-timings-in-the-CRTC.patch

   1 From c6f8dd873098c2c41e97606d55b806a8c5965b3e Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Mon, 15 Feb 2016 17:31:41 -0800
   4 Subject: [PATCH 291/381] drm/vc4: Fix setting of vertical timings in the CRTC.
   5
   6 It looks like when I went to add the interlaced bits, I just took the
   7 existing PV_VERT* block and indented it, instead of copy and pasting
   8 it first.  Without this, changing resolution never worked.
   9
  10 Signed-off-by: Eric Anholt <eric@anholt.net>
  11 (cherry picked from commit a7c5047d1ce178dd2b1fa577fc8909ad663d56d5)
  12 ---
  13  drivers/gpu/drm/vc4/vc4_crtc.c | 10 ++++++++++
  14  1 file changed, 10 insertions(+)
  15
  16 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  17 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  18 @@ -217,6 +217,16 @@ static void vc4_crtc_mode_set_nofb(struc
  19                                  PV_HORZB_HFP) |
  20                    VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
  21
  22 +       CRTC_WRITE(PV_VERTA,
  23 +                  VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
  24 +                                PV_VERTA_VBP) |
  25 +                  VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
  26 +                                PV_VERTA_VSYNC));
  27 +       CRTC_WRITE(PV_VERTB,
  28 +                  VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
  29 +                                PV_VERTB_VFP) |
  30 +                  VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
  31 +
  32         if (interlace) {
  33                 CRTC_WRITE(PV_VERTA_EVEN,
  34                            VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,