projects / openwrt / staging / lynxis / omap.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ar8216: add reading ARL table for AR8216/AR8236/AR8316
[openwrt/staging/lynxis/omap.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
37
38 #include "ar8216.h"
39
40 extern const struct ar8xxx_chip ar8327_chip;
41 extern const struct ar8xxx_chip ar8337_chip;
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 #define MIB_DESC(_s , _o, _n) \
46 { \
47 .size = (_s), \
48 .offset = (_o), \
49 .name = (_n), \
50 }
51
52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
90 };
91
92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
132 };
133
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
135 static LIST_HEAD(ar8xxx_dev_list);
136
137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
138 static int
139 ar8xxx_phy_poll_reset(struct mii_bus *bus)
140 {
141 unsigned int sleep_msecs = 20;
142 int ret, elapsed, i;
143
144 for (elapsed = sleep_msecs; elapsed <= 600;
145 elapsed += sleep_msecs) {
146 msleep(sleep_msecs);
147 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
148 ret = mdiobus_read(bus, i, MII_BMCR);
149 if (ret < 0)
150 return ret;
151 if (ret & BMCR_RESET)
152 break;
153 if (i == AR8XXX_NUM_PHYS - 1) {
154 usleep_range(1000, 2000);
155 return 0;
156 }
157 }
158 }
159 return -ETIMEDOUT;
160 }
161
162 static int
163 ar8xxx_phy_check_aneg(struct phy_device *phydev)
164 {
165 int ret;
166
167 if (phydev->autoneg != AUTONEG_ENABLE)
168 return 0;
169 /*
170 * BMCR_ANENABLE might have been cleared
171 * by phy_init_hw in certain kernel versions
172 * therefore check for it
173 */
174 ret = phy_read(phydev, MII_BMCR);
175 if (ret < 0)
176 return ret;
177 if (ret & BMCR_ANENABLE)
178 return 0;
179
180 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
181 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
182 return phy_write(phydev, MII_BMCR, ret);
183 }
184
185 void
186 ar8xxx_phy_init(struct ar8xxx_priv *priv)
187 {
188 int i;
189 struct mii_bus *bus;
190
191 bus = priv->mii_bus;
192 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
193 if (priv->chip->phy_fixup)
194 priv->chip->phy_fixup(priv, i);
195
196 /* initialize the port itself */
197 mdiobus_write(bus, i, MII_ADVERTISE,
198 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
199 if (ar8xxx_has_gige(priv))
200 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
201 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
202 }
203
204 ar8xxx_phy_poll_reset(bus);
205 }
206
207 u32
208 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
209 {
210 struct mii_bus *bus = priv->mii_bus;
211 u16 lo, hi;
212
213 lo = bus->read(bus, phy_id, regnum);
214 hi = bus->read(bus, phy_id, regnum + 1);
215
216 return (hi << 16) | lo;
217 }
218
219 void
220 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
221 {
222 struct mii_bus *bus = priv->mii_bus;
223 u16 lo, hi;
224
225 lo = val & 0xffff;
226 hi = (u16) (val >> 16);
227
228 if (priv->chip->mii_lo_first)
229 {
230 bus->write(bus, phy_id, regnum, lo);
231 bus->write(bus, phy_id, regnum + 1, hi);
232 } else {
233 bus->write(bus, phy_id, regnum + 1, hi);
234 bus->write(bus, phy_id, regnum, lo);
235 }
236 }
237
238 u32
239 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
240 {
241 struct mii_bus *bus = priv->mii_bus;
242 u16 r1, r2, page;
243 u32 val;
244
245 split_addr((u32) reg, &r1, &r2, &page);
246
247 mutex_lock(&bus->mdio_lock);
248
249 bus->write(bus, 0x18, 0, page);
250 wait_for_page_switch();
251 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
252
253 mutex_unlock(&bus->mdio_lock);
254
255 return val;
256 }
257
258 void
259 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
260 {
261 struct mii_bus *bus = priv->mii_bus;
262 u16 r1, r2, page;
263
264 split_addr((u32) reg, &r1, &r2, &page);
265
266 mutex_lock(&bus->mdio_lock);
267
268 bus->write(bus, 0x18, 0, page);
269 wait_for_page_switch();
270 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
271
272 mutex_unlock(&bus->mdio_lock);
273 }
274
275 u32
276 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
277 {
278 struct mii_bus *bus = priv->mii_bus;
279 u16 r1, r2, page;
280 u32 ret;
281
282 split_addr((u32) reg, &r1, &r2, &page);
283
284 mutex_lock(&bus->mdio_lock);
285
286 bus->write(bus, 0x18, 0, page);
287 wait_for_page_switch();
288
289 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
290 ret &= ~mask;
291 ret |= val;
292 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
293
294 mutex_unlock(&bus->mdio_lock);
295
296 return ret;
297 }
298
299 void
300 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
301 u16 dbg_addr, u16 dbg_data)
302 {
303 struct mii_bus *bus = priv->mii_bus;
304
305 mutex_lock(&bus->mdio_lock);
306 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
307 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
308 mutex_unlock(&bus->mdio_lock);
309 }
310
311 void
312 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
313 {
314 struct mii_bus *bus = priv->mii_bus;
315
316 mutex_lock(&bus->mdio_lock);
317 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
318 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
319 mutex_unlock(&bus->mdio_lock);
320 }
321
322 u16
323 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr)
324 {
325 struct mii_bus *bus = priv->mii_bus;
326 u16 data;
327
328 mutex_lock(&bus->mdio_lock);
329 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
330 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
331 mutex_unlock(&bus->mdio_lock);
332
333 return data;
334 }
335
336 static int
337 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
338 unsigned timeout)
339 {
340 int i;
341
342 for (i = 0; i < timeout; i++) {
343 u32 t;
344
345 t = ar8xxx_read(priv, reg);
346 if ((t & mask) == val)
347 return 0;
348
349 usleep_range(1000, 2000);
350 }
351
352 return -ETIMEDOUT;
353 }
354
355 static int
356 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
357 {
358 unsigned mib_func = priv->chip->mib_func;
359 int ret;
360
361 lockdep_assert_held(&priv->mib_lock);
362
363 /* Capture the hardware statistics for all ports */
364 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
365
366 /* Wait for the capturing to complete. */
367 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
368 if (ret)
369 goto out;
370
371 ret = 0;
372
373 out:
374 return ret;
375 }
376
377 static int
378 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
379 {
380 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
381 }
382
383 static int
384 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
385 {
386 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
387 }
388
389 static void
390 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
391 {
392 unsigned int base;
393 u64 *mib_stats;
394 int i;
395
396 WARN_ON(port >= priv->dev.ports);
397
398 lockdep_assert_held(&priv->mib_lock);
399
400 base = priv->chip->reg_port_stats_start +
401 priv->chip->reg_port_stats_length * port;
402
403 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
404 for (i = 0; i < priv->chip->num_mibs; i++) {
405 const struct ar8xxx_mib_desc *mib;
406 u64 t;
407
408 mib = &priv->chip->mib_decs[i];
409 t = ar8xxx_read(priv, base + mib->offset);
410 if (mib->size == 2) {
411 u64 hi;
412
413 hi = ar8xxx_read(priv, base + mib->offset + 4);
414 t |= hi << 32;
415 }
416
417 if (flush)
418 mib_stats[i] = 0;
419 else
420 mib_stats[i] += t;
421 }
422 }
423
424 static void
425 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
426 struct switch_port_link *link)
427 {
428 u32 status;
429 u32 speed;
430
431 memset(link, '\0', sizeof(*link));
432
433 status = priv->chip->read_port_status(priv, port);
434
435 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
436 if (link->aneg) {
437 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
438 } else {
439 link->link = true;
440
441 if (priv->get_port_link) {
442 int err;
443
444 err = priv->get_port_link(port);
445 if (err >= 0)
446 link->link = !!err;
447 }
448 }
449
450 if (!link->link)
451 return;
452
453 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
454 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
455 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
456
457 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
458 link->eee = priv->chip->read_port_eee_status(priv, port);
459
460 speed = (status & AR8216_PORT_STATUS_SPEED) >>
461 AR8216_PORT_STATUS_SPEED_S;
462
463 switch (speed) {
464 case AR8216_PORT_SPEED_10M:
465 link->speed = SWITCH_PORT_SPEED_10;
466 break;
467 case AR8216_PORT_SPEED_100M:
468 link->speed = SWITCH_PORT_SPEED_100;
469 break;
470 case AR8216_PORT_SPEED_1000M:
471 link->speed = SWITCH_PORT_SPEED_1000;
472 break;
473 default:
474 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
475 break;
476 }
477 }
478
479 static struct sk_buff *
480 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
481 {
482 struct ar8xxx_priv *priv = dev->phy_ptr;
483 unsigned char *buf;
484
485 if (unlikely(!priv))
486 goto error;
487
488 if (!priv->vlan)
489 goto send;
490
491 if (unlikely(skb_headroom(skb) < 2)) {
492 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
493 goto error;
494 }
495
496 buf = skb_push(skb, 2);
497 buf[0] = 0x10;
498 buf[1] = 0x80;
499
500 send:
501 return skb;
502
503 error:
504 dev_kfree_skb_any(skb);
505 return NULL;
506 }
507
508 static void
509 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
510 {
511 struct ar8xxx_priv *priv;
512 unsigned char *buf;
513 int port, vlan;
514
515 priv = dev->phy_ptr;
516 if (!priv)
517 return;
518
519 /* don't strip the header if vlan mode is disabled */
520 if (!priv->vlan)
521 return;
522
523 /* strip header, get vlan id */
524 buf = skb->data;
525 skb_pull(skb, 2);
526
527 /* check for vlan header presence */
528 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
529 return;
530
531 port = buf[0] & 0xf;
532
533 /* no need to fix up packets coming from a tagged source */
534 if (priv->vlan_tagged & (1 << port))
535 return;
536
537 /* lookup port vid from local table, the switch passes an invalid vlan id */
538 vlan = priv->vlan_id[priv->pvid[port]];
539
540 buf[14 + 2] &= 0xf0;
541 buf[14 + 2] |= vlan >> 8;
542 buf[15 + 2] = vlan & 0xff;
543 }
544
545 int
546 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
547 {
548 int timeout = 20;
549 u32 t = 0;
550
551 while (1) {
552 t = ar8xxx_read(priv, reg);
553 if ((t & mask) == val)
554 return 0;
555
556 if (timeout-- <= 0)
557 break;
558
559 udelay(10);
560 }
561
562 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
563 (unsigned int) reg, t, mask, val);
564 return -ETIMEDOUT;
565 }
566
567 static void
568 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
569 {
570 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
571 return;
572 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
573 val &= AR8216_VTUDATA_MEMBER;
574 val |= AR8216_VTUDATA_VALID;
575 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
576 }
577 op |= AR8216_VTU_ACTIVE;
578 ar8xxx_write(priv, AR8216_REG_VTU, op);
579 }
580
581 static void
582 ar8216_vtu_flush(struct ar8xxx_priv *priv)
583 {
584 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
585 }
586
587 static void
588 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
589 {
590 u32 op;
591
592 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
593 ar8216_vtu_op(priv, op, port_mask);
594 }
595
596 static int
597 ar8216_atu_flush(struct ar8xxx_priv *priv)
598 {
599 int ret;
600
601 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
602 if (!ret)
603 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
604 AR8216_ATU_ACTIVE);
605
606 return ret;
607 }
608
609 static u32
610 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
611 {
612 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
613 }
614
615 static void
616 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
617 {
618 u32 header;
619 u32 egress, ingress;
620 u32 pvid;
621
622 if (priv->vlan) {
623 pvid = priv->vlan_id[priv->pvid[port]];
624 if (priv->vlan_tagged & (1 << port))
625 egress = AR8216_OUT_ADD_VLAN;
626 else
627 egress = AR8216_OUT_STRIP_VLAN;
628 ingress = AR8216_IN_SECURE;
629 } else {
630 pvid = port;
631 egress = AR8216_OUT_KEEP;
632 ingress = AR8216_IN_PORT_ONLY;
633 }
634
635 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
636 header = AR8216_PORT_CTRL_HEADER;
637 else
638 header = 0;
639
640 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
641 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
642 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
643 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
644 AR8216_PORT_CTRL_LEARN | header |
645 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
646 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
647
648 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
649 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
650 AR8216_PORT_VLAN_DEFAULT_ID,
651 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
652 (ingress << AR8216_PORT_VLAN_MODE_S) |
653 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
654 }
655
656 static int
657 ar8216_hw_init(struct ar8xxx_priv *priv)
658 {
659 if (priv->initialized)
660 return 0;
661
662 ar8xxx_phy_init(priv);
663
664 priv->initialized = true;
665 return 0;
666 }
667
668 static void
669 ar8216_init_globals(struct ar8xxx_priv *priv)
670 {
671 /* standard atheros magic */
672 ar8xxx_write(priv, 0x38, 0xc000050e);
673
674 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
675 AR8216_GCTRL_MTU, 1518 + 8 + 2);
676 }
677
678 static void
679 ar8216_init_port(struct ar8xxx_priv *priv, int port)
680 {
681 /* Enable port learning and tx */
682 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
683 AR8216_PORT_CTRL_LEARN |
684 (4 << AR8216_PORT_CTRL_STATE_S));
685
686 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
687
688 if (port == AR8216_PORT_CPU) {
689 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
690 AR8216_PORT_STATUS_LINK_UP |
691 (ar8xxx_has_gige(priv) ?
692 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
693 AR8216_PORT_STATUS_TXMAC |
694 AR8216_PORT_STATUS_RXMAC |
695 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
696 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
697 AR8216_PORT_STATUS_DUPLEX);
698 } else {
699 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
700 AR8216_PORT_STATUS_LINK_AUTO);
701 }
702 }
703
704 static void
705 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
706 {
707 int timeout = 20;
708
709 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
710 udelay(10);
711
712 if (!timeout)
713 pr_err("ar8216: timeout waiting for atu to become ready\n");
714 }
715
716 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
717 struct arl_entry *a, u32 *status, enum arl_op op)
718 {
719 struct mii_bus *bus = priv->mii_bus;
720 u16 r2, page;
721 u16 r1_func0, r1_func1, r1_func2;
722 u32 t, val0, val1, val2;
723 int i;
724
725 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
726 r2 |= 0x10;
727
728 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
729 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
730
731 switch (op) {
732 case AR8XXX_ARL_INITIALIZE:
733 /* all ATU registers are on the same page
734 * therefore set page only once
735 */
736 bus->write(bus, 0x18, 0, page);
737 wait_for_page_switch();
738
739 ar8216_wait_atu_ready(priv, r2, r1_func0);
740
741 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
742 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
743 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
744 break;
745 case AR8XXX_ARL_GET_NEXT:
746 t = ar8xxx_mii_read32(priv, r2, r1_func0);
747 t |= AR8216_ATU_ACTIVE;
748 ar8xxx_mii_write32(priv, r2, r1_func0, t);
749 ar8216_wait_atu_ready(priv, r2, r1_func0);
750
751 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
752 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
753 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
754
755 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
756 if (!*status)
757 break;
758
759 i = 0;
760 t = AR8216_ATU_PORT0;
761 while (!(val2 & t) && ++i < priv->dev.ports)
762 t <<= 1;
763
764 a->port = i;
765 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
766 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
767 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
768 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
769 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
770 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
771 break;
772 }
773 }
774
775 static void
776 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
777 {
778 u32 egress, ingress;
779 u32 pvid;
780
781 if (priv->vlan) {
782 pvid = priv->vlan_id[priv->pvid[port]];
783 if (priv->vlan_tagged & (1 << port))
784 egress = AR8216_OUT_ADD_VLAN;
785 else
786 egress = AR8216_OUT_STRIP_VLAN;
787 ingress = AR8216_IN_SECURE;
788 } else {
789 pvid = port;
790 egress = AR8216_OUT_KEEP;
791 ingress = AR8216_IN_PORT_ONLY;
792 }
793
794 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
795 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
796 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
797 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
798 AR8216_PORT_CTRL_LEARN |
799 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
800 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
801
802 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
803 AR8236_PORT_VLAN_DEFAULT_ID,
804 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
805
806 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
807 AR8236_PORT_VLAN2_VLAN_MODE |
808 AR8236_PORT_VLAN2_MEMBER,
809 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
810 (members << AR8236_PORT_VLAN2_MEMBER_S));
811 }
812
813 static void
814 ar8236_init_globals(struct ar8xxx_priv *priv)
815 {
816 /* enable jumbo frames */
817 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
818 AR8316_GCTRL_MTU, 9018 + 8 + 2);
819
820 /* enable cpu port to receive arp frames */
821 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
822 AR8236_ATU_CTRL_RES);
823
824 /* enable cpu port to receive multicast and broadcast frames */
825 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
826 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
827
828 /* Enable MIB counters */
829 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
830 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
831 AR8236_MIB_EN);
832 }
833
834 static int
835 ar8316_hw_init(struct ar8xxx_priv *priv)
836 {
837 u32 val, newval;
838
839 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
840
841 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
842 if (priv->port4_phy) {
843 /* value taken from Ubiquiti RouterStation Pro */
844 newval = 0x81461bea;
845 pr_info("ar8316: Using port 4 as PHY\n");
846 } else {
847 newval = 0x01261be2;
848 pr_info("ar8316: Using port 4 as switch port\n");
849 }
850 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
851 /* value taken from AVM Fritz!Box 7390 sources */
852 newval = 0x010e5b71;
853 } else {
854 /* no known value for phy interface */
855 pr_err("ar8316: unsupported mii mode: %d.\n",
856 priv->phy->interface);
857 return -EINVAL;
858 }
859
860 if (val == newval)
861 goto out;
862
863 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
864
865 if (priv->port4_phy &&
866 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
867 /* work around for phy4 rgmii mode */
868 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
869 /* rx delay */
870 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
871 /* tx delay */
872 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
873 msleep(1000);
874 }
875
876 ar8xxx_phy_init(priv);
877
878 out:
879 priv->initialized = true;
880 return 0;
881 }
882
883 static void
884 ar8316_init_globals(struct ar8xxx_priv *priv)
885 {
886 /* standard atheros magic */
887 ar8xxx_write(priv, 0x38, 0xc000050e);
888
889 /* enable cpu port to receive multicast and broadcast frames */
890 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
891
892 /* enable jumbo frames */
893 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
894 AR8316_GCTRL_MTU, 9018 + 8 + 2);
895
896 /* Enable MIB counters */
897 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
898 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
899 AR8236_MIB_EN);
900 }
901
902 int
903 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
904 struct switch_val *val)
905 {
906 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
907 priv->vlan = !!val->value.i;
908 return 0;
909 }
910
911 int
912 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
913 struct switch_val *val)
914 {
915 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
916 val->value.i = priv->vlan;
917 return 0;
918 }
919
920
921 int
922 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
923 {
924 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
925
926 /* make sure no invalid PVIDs get set */
927
928 if (vlan >= dev->vlans)
929 return -EINVAL;
930
931 priv->pvid[port] = vlan;
932 return 0;
933 }
934
935 int
936 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
937 {
938 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
939 *vlan = priv->pvid[port];
940 return 0;
941 }
942
943 static int
944 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
945 struct switch_val *val)
946 {
947 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
948 priv->vlan_id[val->port_vlan] = val->value.i;
949 return 0;
950 }
951
952 static int
953 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
954 struct switch_val *val)
955 {
956 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
957 val->value.i = priv->vlan_id[val->port_vlan];
958 return 0;
959 }
960
961 int
962 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
963 struct switch_port_link *link)
964 {
965 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
966
967 ar8216_read_port_link(priv, port, link);
968 return 0;
969 }
970
971 static int
972 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
973 {
974 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
975 u8 ports = priv->vlan_table[val->port_vlan];
976 int i;
977
978 val->len = 0;
979 for (i = 0; i < dev->ports; i++) {
980 struct switch_port *p;
981
982 if (!(ports & (1 << i)))
983 continue;
984
985 p = &val->value.ports[val->len++];
986 p->id = i;
987 if (priv->vlan_tagged & (1 << i))
988 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
989 else
990 p->flags = 0;
991 }
992 return 0;
993 }
994
995 static int
996 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
997 {
998 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
999 u8 *vt = &priv->vlan_table[val->port_vlan];
1000 int i, j;
1001
1002 *vt = 0;
1003 for (i = 0; i < val->len; i++) {
1004 struct switch_port *p = &val->value.ports[i];
1005
1006 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1007 priv->vlan_tagged |= (1 << p->id);
1008 } else {
1009 priv->vlan_tagged &= ~(1 << p->id);
1010 priv->pvid[p->id] = val->port_vlan;
1011
1012 /* make sure that an untagged port does not
1013 * appear in other vlans */
1014 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1015 if (j == val->port_vlan)
1016 continue;
1017 priv->vlan_table[j] &= ~(1 << p->id);
1018 }
1019 }
1020
1021 *vt |= 1 << p->id;
1022 }
1023 return 0;
1024 }
1025
1026 static void
1027 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1028 {
1029 int port;
1030
1031 /* reset all mirror registers */
1032 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1033 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1034 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1035 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1036 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1037 AR8216_PORT_CTRL_MIRROR_RX);
1038
1039 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1040 AR8216_PORT_CTRL_MIRROR_TX);
1041 }
1042
1043 /* now enable mirroring if necessary */
1044 if (priv->source_port >= AR8216_NUM_PORTS ||
1045 priv->monitor_port >= AR8216_NUM_PORTS ||
1046 priv->source_port == priv->monitor_port) {
1047 return;
1048 }
1049
1050 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1051 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1052 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1053
1054 if (priv->mirror_rx)
1055 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1056 AR8216_PORT_CTRL_MIRROR_RX);
1057
1058 if (priv->mirror_tx)
1059 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1060 AR8216_PORT_CTRL_MIRROR_TX);
1061 }
1062
1063 int
1064 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1065 {
1066 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1067 u8 portmask[AR8X16_MAX_PORTS];
1068 int i, j;
1069
1070 mutex_lock(&priv->reg_mutex);
1071 /* flush all vlan translation unit entries */
1072 priv->chip->vtu_flush(priv);
1073
1074 memset(portmask, 0, sizeof(portmask));
1075 if (!priv->init) {
1076 /* calculate the port destination masks and load vlans
1077 * into the vlan translation unit */
1078 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1079 u8 vp = priv->vlan_table[j];
1080
1081 if (!vp)
1082 continue;
1083
1084 for (i = 0; i < dev->ports; i++) {
1085 u8 mask = (1 << i);
1086 if (vp & mask)
1087 portmask[i] |= vp & ~mask;
1088 }
1089
1090 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1091 priv->vlan_table[j]);
1092 }
1093 } else {
1094 /* vlan disabled:
1095 * isolate all ports, but connect them to the cpu port */
1096 for (i = 0; i < dev->ports; i++) {
1097 if (i == AR8216_PORT_CPU)
1098 continue;
1099
1100 portmask[i] = 1 << AR8216_PORT_CPU;
1101 portmask[AR8216_PORT_CPU] |= (1 << i);
1102 }
1103 }
1104
1105 /* update the port destination mask registers and tag settings */
1106 for (i = 0; i < dev->ports; i++) {
1107 priv->chip->setup_port(priv, i, portmask[i]);
1108 }
1109
1110 priv->chip->set_mirror_regs(priv);
1111
1112 mutex_unlock(&priv->reg_mutex);
1113 return 0;
1114 }
1115
1116 int
1117 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1118 {
1119 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1120 const struct ar8xxx_chip *chip = priv->chip;
1121 int i;
1122
1123 mutex_lock(&priv->reg_mutex);
1124 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1125 offsetof(struct ar8xxx_priv, vlan));
1126
1127 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1128 priv->vlan_id[i] = i;
1129
1130 /* Configure all ports */
1131 for (i = 0; i < dev->ports; i++)
1132 chip->init_port(priv, i);
1133
1134 priv->mirror_rx = false;
1135 priv->mirror_tx = false;
1136 priv->source_port = 0;
1137 priv->monitor_port = 0;
1138
1139 chip->init_globals(priv);
1140
1141 mutex_unlock(&priv->reg_mutex);
1142
1143 return chip->sw_hw_apply(dev);
1144 }
1145
1146 int
1147 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1148 const struct switch_attr *attr,
1149 struct switch_val *val)
1150 {
1151 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1152 unsigned int len;
1153 int ret;
1154
1155 if (!ar8xxx_has_mib_counters(priv))
1156 return -EOPNOTSUPP;
1157
1158 mutex_lock(&priv->mib_lock);
1159
1160 len = priv->dev.ports * priv->chip->num_mibs *
1161 sizeof(*priv->mib_stats);
1162 memset(priv->mib_stats, '\0', len);
1163 ret = ar8xxx_mib_flush(priv);
1164 if (ret)
1165 goto unlock;
1166
1167 ret = 0;
1168
1169 unlock:
1170 mutex_unlock(&priv->mib_lock);
1171 return ret;
1172 }
1173
1174 int
1175 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1176 const struct switch_attr *attr,
1177 struct switch_val *val)
1178 {
1179 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1180
1181 mutex_lock(&priv->reg_mutex);
1182 priv->mirror_rx = !!val->value.i;
1183 priv->chip->set_mirror_regs(priv);
1184 mutex_unlock(&priv->reg_mutex);
1185
1186 return 0;
1187 }
1188
1189 int
1190 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1191 const struct switch_attr *attr,
1192 struct switch_val *val)
1193 {
1194 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1195 val->value.i = priv->mirror_rx;
1196 return 0;
1197 }
1198
1199 int
1200 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1201 const struct switch_attr *attr,
1202 struct switch_val *val)
1203 {
1204 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1205
1206 mutex_lock(&priv->reg_mutex);
1207 priv->mirror_tx = !!val->value.i;
1208 priv->chip->set_mirror_regs(priv);
1209 mutex_unlock(&priv->reg_mutex);
1210
1211 return 0;
1212 }
1213
1214 int
1215 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1216 const struct switch_attr *attr,
1217 struct switch_val *val)
1218 {
1219 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1220 val->value.i = priv->mirror_tx;
1221 return 0;
1222 }
1223
1224 int
1225 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1226 const struct switch_attr *attr,
1227 struct switch_val *val)
1228 {
1229 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1230
1231 mutex_lock(&priv->reg_mutex);
1232 priv->monitor_port = val->value.i;
1233 priv->chip->set_mirror_regs(priv);
1234 mutex_unlock(&priv->reg_mutex);
1235
1236 return 0;
1237 }
1238
1239 int
1240 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1241 const struct switch_attr *attr,
1242 struct switch_val *val)
1243 {
1244 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1245 val->value.i = priv->monitor_port;
1246 return 0;
1247 }
1248
1249 int
1250 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1251 const struct switch_attr *attr,
1252 struct switch_val *val)
1253 {
1254 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1255
1256 mutex_lock(&priv->reg_mutex);
1257 priv->source_port = val->value.i;
1258 priv->chip->set_mirror_regs(priv);
1259 mutex_unlock(&priv->reg_mutex);
1260
1261 return 0;
1262 }
1263
1264 int
1265 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1266 const struct switch_attr *attr,
1267 struct switch_val *val)
1268 {
1269 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1270 val->value.i = priv->source_port;
1271 return 0;
1272 }
1273
1274 int
1275 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1276 const struct switch_attr *attr,
1277 struct switch_val *val)
1278 {
1279 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1280 int port;
1281 int ret;
1282
1283 if (!ar8xxx_has_mib_counters(priv))
1284 return -EOPNOTSUPP;
1285
1286 port = val->port_vlan;
1287 if (port >= dev->ports)
1288 return -EINVAL;
1289
1290 mutex_lock(&priv->mib_lock);
1291 ret = ar8xxx_mib_capture(priv);
1292 if (ret)
1293 goto unlock;
1294
1295 ar8xxx_mib_fetch_port_stat(priv, port, true);
1296
1297 ret = 0;
1298
1299 unlock:
1300 mutex_unlock(&priv->mib_lock);
1301 return ret;
1302 }
1303
1304 int
1305 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1306 const struct switch_attr *attr,
1307 struct switch_val *val)
1308 {
1309 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1310 const struct ar8xxx_chip *chip = priv->chip;
1311 u64 *mib_stats;
1312 int port;
1313 int ret;
1314 char *buf = priv->buf;
1315 int i, len = 0;
1316
1317 if (!ar8xxx_has_mib_counters(priv))
1318 return -EOPNOTSUPP;
1319
1320 port = val->port_vlan;
1321 if (port >= dev->ports)
1322 return -EINVAL;
1323
1324 mutex_lock(&priv->mib_lock);
1325 ret = ar8xxx_mib_capture(priv);
1326 if (ret)
1327 goto unlock;
1328
1329 ar8xxx_mib_fetch_port_stat(priv, port, false);
1330
1331 len += snprintf(buf + len, sizeof(priv->buf) - len,
1332 "Port %d MIB counters\n",
1333 port);
1334
1335 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1336 for (i = 0; i < chip->num_mibs; i++)
1337 len += snprintf(buf + len, sizeof(priv->buf) - len,
1338 "%-12s: %llu\n",
1339 chip->mib_decs[i].name,
1340 mib_stats[i]);
1341
1342 val->value.s = buf;
1343 val->len = len;
1344
1345 ret = 0;
1346
1347 unlock:
1348 mutex_unlock(&priv->mib_lock);
1349 return ret;
1350 }
1351
1352 int
1353 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1354 const struct switch_attr *attr,
1355 struct switch_val *val)
1356 {
1357 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1358 struct mii_bus *bus = priv->mii_bus;
1359 const struct ar8xxx_chip *chip = priv->chip;
1360 char *buf = priv->arl_buf;
1361 int i, j, k, len = 0;
1362 struct arl_entry *a, *a1;
1363 u32 status;
1364
1365 if (!chip->get_arl_entry)
1366 return -EOPNOTSUPP;
1367
1368 mutex_lock(&priv->reg_mutex);
1369 mutex_lock(&bus->mdio_lock);
1370
1371 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1372
1373 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1374 a = &priv->arl_table[i];
1375 duplicate:
1376 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1377
1378 if (!status)
1379 break;
1380
1381 /* avoid duplicates
1382 * ARL table can include multiple valid entries
1383 * per MAC, just with differing status codes
1384 */
1385 for (j = 0; j < i; ++j) {
1386 a1 = &priv->arl_table[j];
1387 if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
1388 goto duplicate;
1389 }
1390 }
1391
1392 mutex_unlock(&bus->mdio_lock);
1393
1394 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1395 "address resolution table\n");
1396
1397 if (i == AR8XXX_NUM_ARL_RECORDS)
1398 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1399 "Too many entries found, displaying the first %d only!\n",
1400 AR8XXX_NUM_ARL_RECORDS);
1401
1402 for (j = 0; j < priv->dev.ports; ++j) {
1403 for (k = 0; k < i; ++k) {
1404 a = &priv->arl_table[k];
1405 if (a->port != j)
1406 continue;
1407 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1408 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1409 j,
1410 a->mac[5], a->mac[4], a->mac[3],
1411 a->mac[2], a->mac[1], a->mac[0]);
1412 }
1413 }
1414
1415 val->value.s = buf;
1416 val->len = len;
1417
1418 mutex_unlock(&priv->reg_mutex);
1419
1420 return 0;
1421 }
1422
1423 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1424 {
1425 .type = SWITCH_TYPE_INT,
1426 .name = "enable_vlan",
1427 .description = "Enable VLAN mode",
1428 .set = ar8xxx_sw_set_vlan,
1429 .get = ar8xxx_sw_get_vlan,
1430 .max = 1
1431 },
1432 {
1433 .type = SWITCH_TYPE_NOVAL,
1434 .name = "reset_mibs",
1435 .description = "Reset all MIB counters",
1436 .set = ar8xxx_sw_set_reset_mibs,
1437 },
1438 {
1439 .type = SWITCH_TYPE_INT,
1440 .name = "enable_mirror_rx",
1441 .description = "Enable mirroring of RX packets",
1442 .set = ar8xxx_sw_set_mirror_rx_enable,
1443 .get = ar8xxx_sw_get_mirror_rx_enable,
1444 .max = 1
1445 },
1446 {
1447 .type = SWITCH_TYPE_INT,
1448 .name = "enable_mirror_tx",
1449 .description = "Enable mirroring of TX packets",
1450 .set = ar8xxx_sw_set_mirror_tx_enable,
1451 .get = ar8xxx_sw_get_mirror_tx_enable,
1452 .max = 1
1453 },
1454 {
1455 .type = SWITCH_TYPE_INT,
1456 .name = "mirror_monitor_port",
1457 .description = "Mirror monitor port",
1458 .set = ar8xxx_sw_set_mirror_monitor_port,
1459 .get = ar8xxx_sw_get_mirror_monitor_port,
1460 .max = AR8216_NUM_PORTS - 1
1461 },
1462 {
1463 .type = SWITCH_TYPE_INT,
1464 .name = "mirror_source_port",
1465 .description = "Mirror source port",
1466 .set = ar8xxx_sw_set_mirror_source_port,
1467 .get = ar8xxx_sw_get_mirror_source_port,
1468 .max = AR8216_NUM_PORTS - 1
1469 },
1470 {
1471 .type = SWITCH_TYPE_STRING,
1472 .name = "arl_table",
1473 .description = "Get ARL table",
1474 .set = NULL,
1475 .get = ar8xxx_sw_get_arl_table,
1476 },
1477 };
1478
1479 const struct switch_attr ar8xxx_sw_attr_port[2] = {
1480 {
1481 .type = SWITCH_TYPE_NOVAL,
1482 .name = "reset_mib",
1483 .description = "Reset single port MIB counters",
1484 .set = ar8xxx_sw_set_port_reset_mib,
1485 },
1486 {
1487 .type = SWITCH_TYPE_STRING,
1488 .name = "mib",
1489 .description = "Get port's MIB counters",
1490 .set = NULL,
1491 .get = ar8xxx_sw_get_port_mib,
1492 },
1493 };
1494
1495 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1496 {
1497 .type = SWITCH_TYPE_INT,
1498 .name = "vid",
1499 .description = "VLAN ID (0-4094)",
1500 .set = ar8xxx_sw_set_vid,
1501 .get = ar8xxx_sw_get_vid,
1502 .max = 4094,
1503 },
1504 };
1505
1506 static const struct switch_dev_ops ar8xxx_sw_ops = {
1507 .attr_global = {
1508 .attr = ar8xxx_sw_attr_globals,
1509 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1510 },
1511 .attr_port = {
1512 .attr = ar8xxx_sw_attr_port,
1513 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1514 },
1515 .attr_vlan = {
1516 .attr = ar8xxx_sw_attr_vlan,
1517 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1518 },
1519 .get_port_pvid = ar8xxx_sw_get_pvid,
1520 .set_port_pvid = ar8xxx_sw_set_pvid,
1521 .get_vlan_ports = ar8xxx_sw_get_ports,
1522 .set_vlan_ports = ar8xxx_sw_set_ports,
1523 .apply_config = ar8xxx_sw_hw_apply,
1524 .reset_switch = ar8xxx_sw_reset_switch,
1525 .get_port_link = ar8xxx_sw_get_port_link,
1526 };
1527
1528 static const struct ar8xxx_chip ar8216_chip = {
1529 .caps = AR8XXX_CAP_MIB_COUNTERS,
1530
1531 .reg_port_stats_start = 0x19000,
1532 .reg_port_stats_length = 0xa0,
1533
1534 .name = "Atheros AR8216",
1535 .ports = AR8216_NUM_PORTS,
1536 .vlans = AR8216_NUM_VLANS,
1537 .swops = &ar8xxx_sw_ops,
1538
1539 .hw_init = ar8216_hw_init,
1540 .init_globals = ar8216_init_globals,
1541 .init_port = ar8216_init_port,
1542 .setup_port = ar8216_setup_port,
1543 .read_port_status = ar8216_read_port_status,
1544 .atu_flush = ar8216_atu_flush,
1545 .vtu_flush = ar8216_vtu_flush,
1546 .vtu_load_vlan = ar8216_vtu_load_vlan,
1547 .set_mirror_regs = ar8216_set_mirror_regs,
1548 .get_arl_entry = ar8216_get_arl_entry,
1549 .sw_hw_apply = ar8xxx_sw_hw_apply,
1550
1551 .num_mibs = ARRAY_SIZE(ar8216_mibs),
1552 .mib_decs = ar8216_mibs,
1553 .mib_func = AR8216_REG_MIB_FUNC
1554 };
1555
1556 static const struct ar8xxx_chip ar8236_chip = {
1557 .caps = AR8XXX_CAP_MIB_COUNTERS,
1558
1559 .reg_port_stats_start = 0x20000,
1560 .reg_port_stats_length = 0x100,
1561
1562 .name = "Atheros AR8236",
1563 .ports = AR8216_NUM_PORTS,
1564 .vlans = AR8216_NUM_VLANS,
1565 .swops = &ar8xxx_sw_ops,
1566
1567 .hw_init = ar8216_hw_init,
1568 .init_globals = ar8236_init_globals,
1569 .init_port = ar8216_init_port,
1570 .setup_port = ar8236_setup_port,
1571 .read_port_status = ar8216_read_port_status,
1572 .atu_flush = ar8216_atu_flush,
1573 .vtu_flush = ar8216_vtu_flush,
1574 .vtu_load_vlan = ar8216_vtu_load_vlan,
1575 .set_mirror_regs = ar8216_set_mirror_regs,
1576 .get_arl_entry = ar8216_get_arl_entry,
1577 .sw_hw_apply = ar8xxx_sw_hw_apply,
1578
1579 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1580 .mib_decs = ar8236_mibs,
1581 .mib_func = AR8216_REG_MIB_FUNC
1582 };
1583
1584 static const struct ar8xxx_chip ar8316_chip = {
1585 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1586
1587 .reg_port_stats_start = 0x20000,
1588 .reg_port_stats_length = 0x100,
1589
1590 .name = "Atheros AR8316",
1591 .ports = AR8216_NUM_PORTS,
1592 .vlans = AR8X16_MAX_VLANS,
1593 .swops = &ar8xxx_sw_ops,
1594
1595 .hw_init = ar8316_hw_init,
1596 .init_globals = ar8316_init_globals,
1597 .init_port = ar8216_init_port,
1598 .setup_port = ar8216_setup_port,
1599 .read_port_status = ar8216_read_port_status,
1600 .atu_flush = ar8216_atu_flush,
1601 .vtu_flush = ar8216_vtu_flush,
1602 .vtu_load_vlan = ar8216_vtu_load_vlan,
1603 .set_mirror_regs = ar8216_set_mirror_regs,
1604 .get_arl_entry = ar8216_get_arl_entry,
1605 .sw_hw_apply = ar8xxx_sw_hw_apply,
1606
1607 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1608 .mib_decs = ar8236_mibs,
1609 .mib_func = AR8216_REG_MIB_FUNC
1610 };
1611
1612 static int
1613 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1614 {
1615 u32 val;
1616 u16 id;
1617 int i;
1618
1619 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1620 if (val == ~0)
1621 return -ENODEV;
1622
1623 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1624 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1625 u16 t;
1626
1627 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1628 if (val == ~0)
1629 return -ENODEV;
1630
1631 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1632 if (t != id)
1633 return -ENODEV;
1634 }
1635
1636 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1637 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1638
1639 switch (priv->chip_ver) {
1640 case AR8XXX_VER_AR8216:
1641 priv->chip = &ar8216_chip;
1642 break;
1643 case AR8XXX_VER_AR8236:
1644 priv->chip = &ar8236_chip;
1645 break;
1646 case AR8XXX_VER_AR8316:
1647 priv->chip = &ar8316_chip;
1648 break;
1649 case AR8XXX_VER_AR8327:
1650 priv->chip = &ar8327_chip;
1651 break;
1652 case AR8XXX_VER_AR8337:
1653 priv->chip = &ar8337_chip;
1654 break;
1655 default:
1656 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1657 priv->chip_ver, priv->chip_rev);
1658
1659 return -ENODEV;
1660 }
1661
1662 return 0;
1663 }
1664
1665 static void
1666 ar8xxx_mib_work_func(struct work_struct *work)
1667 {
1668 struct ar8xxx_priv *priv;
1669 int err;
1670
1671 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1672
1673 mutex_lock(&priv->mib_lock);
1674
1675 err = ar8xxx_mib_capture(priv);
1676 if (err)
1677 goto next_port;
1678
1679 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1680
1681 next_port:
1682 priv->mib_next_port++;
1683 if (priv->mib_next_port >= priv->dev.ports)
1684 priv->mib_next_port = 0;
1685
1686 mutex_unlock(&priv->mib_lock);
1687 schedule_delayed_work(&priv->mib_work,
1688 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1689 }
1690
1691 static int
1692 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1693 {
1694 unsigned int len;
1695
1696 if (!ar8xxx_has_mib_counters(priv))
1697 return 0;
1698
1699 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1700
1701 len = priv->dev.ports * priv->chip->num_mibs *
1702 sizeof(*priv->mib_stats);
1703 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1704
1705 if (!priv->mib_stats)
1706 return -ENOMEM;
1707
1708 return 0;
1709 }
1710
1711 static void
1712 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1713 {
1714 if (!ar8xxx_has_mib_counters(priv))
1715 return;
1716
1717 schedule_delayed_work(&priv->mib_work,
1718 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1719 }
1720
1721 static void
1722 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1723 {
1724 if (!ar8xxx_has_mib_counters(priv))
1725 return;
1726
1727 cancel_delayed_work(&priv->mib_work);
1728 }
1729
1730 static struct ar8xxx_priv *
1731 ar8xxx_create(void)
1732 {
1733 struct ar8xxx_priv *priv;
1734
1735 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1736 if (priv == NULL)
1737 return NULL;
1738
1739 mutex_init(&priv->reg_mutex);
1740 mutex_init(&priv->mib_lock);
1741 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1742
1743 return priv;
1744 }
1745
1746 static void
1747 ar8xxx_free(struct ar8xxx_priv *priv)
1748 {
1749 if (priv->chip && priv->chip->cleanup)
1750 priv->chip->cleanup(priv);
1751
1752 kfree(priv->chip_data);
1753 kfree(priv->mib_stats);
1754 kfree(priv);
1755 }
1756
1757 static int
1758 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1759 {
1760 const struct ar8xxx_chip *chip;
1761 struct switch_dev *swdev;
1762 int ret;
1763
1764 ret = ar8xxx_id_chip(priv);
1765 if (ret)
1766 return ret;
1767
1768 chip = priv->chip;
1769
1770 swdev = &priv->dev;
1771 swdev->cpu_port = AR8216_PORT_CPU;
1772 swdev->name = chip->name;
1773 swdev->vlans = chip->vlans;
1774 swdev->ports = chip->ports;
1775 swdev->ops = chip->swops;
1776
1777 ret = ar8xxx_mib_init(priv);
1778 if (ret)
1779 return ret;
1780
1781 return 0;
1782 }
1783
1784 static int
1785 ar8xxx_start(struct ar8xxx_priv *priv)
1786 {
1787 int ret;
1788
1789 priv->init = true;
1790
1791 ret = priv->chip->hw_init(priv);
1792 if (ret)
1793 return ret;
1794
1795 ret = ar8xxx_sw_reset_switch(&priv->dev);
1796 if (ret)
1797 return ret;
1798
1799 priv->init = false;
1800
1801 ar8xxx_mib_start(priv);
1802
1803 return 0;
1804 }
1805
1806 static int
1807 ar8xxx_phy_config_init(struct phy_device *phydev)
1808 {
1809 struct ar8xxx_priv *priv = phydev->priv;
1810 struct net_device *dev = phydev->attached_dev;
1811 int ret;
1812
1813 if (WARN_ON(!priv))
1814 return -ENODEV;
1815
1816 if (priv->chip->config_at_probe)
1817 return ar8xxx_phy_check_aneg(phydev);
1818
1819 priv->phy = phydev;
1820
1821 if (phydev->addr != 0) {
1822 if (chip_is_ar8316(priv)) {
1823 /* switch device has been initialized, reinit */
1824 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1825 priv->initialized = false;
1826 priv->port4_phy = true;
1827 ar8316_hw_init(priv);
1828 return 0;
1829 }
1830
1831 return 0;
1832 }
1833
1834 ret = ar8xxx_start(priv);
1835 if (ret)
1836 return ret;
1837
1838 /* VID fixup only needed on ar8216 */
1839 if (chip_is_ar8216(priv)) {
1840 dev->phy_ptr = priv;
1841 dev->priv_flags |= IFF_NO_IP_ALIGN;
1842 dev->eth_mangle_rx = ar8216_mangle_rx;
1843 dev->eth_mangle_tx = ar8216_mangle_tx;
1844 }
1845
1846 return 0;
1847 }
1848
1849 static bool
1850 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
1851 {
1852 bool link_new, changed = false;
1853 u32 status;
1854 int i;
1855
1856 mutex_lock(&priv->reg_mutex);
1857
1858 for (i = 0; i < priv->dev.ports; i++) {
1859 status = priv->chip->read_port_status(priv, i);
1860 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
1861 if (link_new == priv->link_up[i])
1862 continue;
1863
1864 priv->link_up[i] = link_new;
1865 changed = true;
1866 dev_info(&priv->phy->dev, "Port %d is %s\n",
1867 i, link_new ? "up" : "down");
1868 }
1869
1870 if (changed)
1871 priv->chip->atu_flush(priv);
1872
1873 mutex_unlock(&priv->reg_mutex);
1874
1875 return changed;
1876 }
1877
1878 static int
1879 ar8xxx_phy_read_status(struct phy_device *phydev)
1880 {
1881 struct ar8xxx_priv *priv = phydev->priv;
1882 struct switch_port_link link;
1883
1884 /* check for link changes and flush ATU
1885 * if a change was detected
1886 */
1887 if (phydev->state == PHY_CHANGELINK)
1888 ar8xxx_check_link_states(priv);
1889
1890 if (phydev->addr != 0)
1891 return genphy_read_status(phydev);
1892
1893 ar8216_read_port_link(priv, phydev->addr, &link);
1894 phydev->link = !!link.link;
1895 if (!phydev->link)
1896 return 0;
1897
1898 switch (link.speed) {
1899 case SWITCH_PORT_SPEED_10:
1900 phydev->speed = SPEED_10;
1901 break;
1902 case SWITCH_PORT_SPEED_100:
1903 phydev->speed = SPEED_100;
1904 break;
1905 case SWITCH_PORT_SPEED_1000:
1906 phydev->speed = SPEED_1000;
1907 break;
1908 default:
1909 phydev->speed = 0;
1910 }
1911 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1912
1913 phydev->state = PHY_RUNNING;
1914 netif_carrier_on(phydev->attached_dev);
1915 phydev->adjust_link(phydev->attached_dev);
1916
1917 return 0;
1918 }
1919
1920 static int
1921 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1922 {
1923 if (phydev->addr == 0)
1924 return 0;
1925
1926 return genphy_config_aneg(phydev);
1927 }
1928
1929 static const u32 ar8xxx_phy_ids[] = {
1930 0x004dd033,
1931 0x004dd034, /* AR8327 */
1932 0x004dd036, /* AR8337 */
1933 0x004dd041,
1934 0x004dd042,
1935 0x004dd043, /* AR8236 */
1936 };
1937
1938 static bool
1939 ar8xxx_phy_match(u32 phy_id)
1940 {
1941 int i;
1942
1943 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
1944 if (phy_id == ar8xxx_phy_ids[i])
1945 return true;
1946
1947 return false;
1948 }
1949
1950 static bool
1951 ar8xxx_is_possible(struct mii_bus *bus)
1952 {
1953 unsigned i;
1954
1955 for (i = 0; i < 4; i++) {
1956 u32 phy_id;
1957
1958 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1959 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1960 if (!ar8xxx_phy_match(phy_id)) {
1961 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1962 dev_name(&bus->dev), i, phy_id);
1963 return false;
1964 }
1965 }
1966
1967 return true;
1968 }
1969
1970 static int
1971 ar8xxx_phy_probe(struct phy_device *phydev)
1972 {
1973 struct ar8xxx_priv *priv;
1974 struct switch_dev *swdev;
1975 int ret;
1976
1977 /* skip PHYs at unused adresses */
1978 if (phydev->addr != 0 && phydev->addr != 4)
1979 return -ENODEV;
1980
1981 if (!ar8xxx_is_possible(phydev->bus))
1982 return -ENODEV;
1983
1984 mutex_lock(&ar8xxx_dev_list_lock);
1985 list_for_each_entry(priv, &ar8xxx_dev_list, list)
1986 if (priv->mii_bus == phydev->bus)
1987 goto found;
1988
1989 priv = ar8xxx_create();
1990 if (priv == NULL) {
1991 ret = -ENOMEM;
1992 goto unlock;
1993 }
1994
1995 priv->mii_bus = phydev->bus;
1996
1997 ret = ar8xxx_probe_switch(priv);
1998 if (ret)
1999 goto free_priv;
2000
2001 swdev = &priv->dev;
2002 swdev->alias = dev_name(&priv->mii_bus->dev);
2003 ret = register_switch(swdev, NULL);
2004 if (ret)
2005 goto free_priv;
2006
2007 pr_info("%s: %s rev. %u switch registered on %s\n",
2008 swdev->devname, swdev->name, priv->chip_rev,
2009 dev_name(&priv->mii_bus->dev));
2010
2011 found:
2012 priv->use_count++;
2013
2014 if (phydev->addr == 0) {
2015 if (ar8xxx_has_gige(priv)) {
2016 phydev->supported = SUPPORTED_1000baseT_Full;
2017 phydev->advertising = ADVERTISED_1000baseT_Full;
2018 } else {
2019 phydev->supported = SUPPORTED_100baseT_Full;
2020 phydev->advertising = ADVERTISED_100baseT_Full;
2021 }
2022
2023 if (priv->chip->config_at_probe) {
2024 priv->phy = phydev;
2025
2026 ret = ar8xxx_start(priv);
2027 if (ret)
2028 goto err_unregister_switch;
2029 }
2030 } else {
2031 if (ar8xxx_has_gige(priv)) {
2032 phydev->supported |= SUPPORTED_1000baseT_Full;
2033 phydev->advertising |= ADVERTISED_1000baseT_Full;
2034 }
2035 }
2036
2037 phydev->priv = priv;
2038
2039 list_add(&priv->list, &ar8xxx_dev_list);
2040
2041 mutex_unlock(&ar8xxx_dev_list_lock);
2042
2043 return 0;
2044
2045 err_unregister_switch:
2046 if (--priv->use_count)
2047 goto unlock;
2048
2049 unregister_switch(&priv->dev);
2050
2051 free_priv:
2052 ar8xxx_free(priv);
2053 unlock:
2054 mutex_unlock(&ar8xxx_dev_list_lock);
2055 return ret;
2056 }
2057
2058 static void
2059 ar8xxx_phy_detach(struct phy_device *phydev)
2060 {
2061 struct net_device *dev = phydev->attached_dev;
2062
2063 if (!dev)
2064 return;
2065
2066 dev->phy_ptr = NULL;
2067 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2068 dev->eth_mangle_rx = NULL;
2069 dev->eth_mangle_tx = NULL;
2070 }
2071
2072 static void
2073 ar8xxx_phy_remove(struct phy_device *phydev)
2074 {
2075 struct ar8xxx_priv *priv = phydev->priv;
2076
2077 if (WARN_ON(!priv))
2078 return;
2079
2080 phydev->priv = NULL;
2081 if (--priv->use_count > 0)
2082 return;
2083
2084 mutex_lock(&ar8xxx_dev_list_lock);
2085 list_del(&priv->list);
2086 mutex_unlock(&ar8xxx_dev_list_lock);
2087
2088 unregister_switch(&priv->dev);
2089 ar8xxx_mib_stop(priv);
2090 ar8xxx_free(priv);
2091 }
2092
2093 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2094 static int
2095 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2096 {
2097 /* we don't need an extra reset */
2098 return 0;
2099 }
2100 #endif
2101
2102 static struct phy_driver ar8xxx_phy_driver = {
2103 .phy_id = 0x004d0000,
2104 .name = "Atheros AR8216/AR8236/AR8316",
2105 .phy_id_mask = 0xffff0000,
2106 .features = PHY_BASIC_FEATURES,
2107 .probe = ar8xxx_phy_probe,
2108 .remove = ar8xxx_phy_remove,
2109 .detach = ar8xxx_phy_detach,
2110 .config_init = ar8xxx_phy_config_init,
2111 .config_aneg = ar8xxx_phy_config_aneg,
2112 .read_status = ar8xxx_phy_read_status,
2113 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2114 .soft_reset = ar8xxx_phy_soft_reset,
2115 #endif
2116 .driver = { .owner = THIS_MODULE },
2117 };
2118
2119 int __init
2120 ar8xxx_init(void)
2121 {
2122 return phy_driver_register(&ar8xxx_phy_driver);
2123 }
2124
2125 void __exit
2126 ar8xxx_exit(void)
2127 {
2128 phy_driver_unregister(&ar8xxx_phy_driver);
2129 }
2130
2131 module_init(ar8xxx_init);
2132 module_exit(ar8xxx_exit);
2133 MODULE_LICENSE("GPL");
2134
lynxis staging tree for omap