target/linux/imx6/patches-3.10/0011-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch

   1 Subject: [v6,2/3] ARM: imx6q: Add PCIe bits to GPR syscon definition
   2 From: Sean Cross <xobs@kosagi.com>
   3
   4 PCIe requires additional bits be defined for GPR8 and GPR12.
   5
   6 Signed-off-by: Sean Cross <xobs@kosagi.com>
   7 ---
   8  include/linux/mfd/syscon/imx6q-iomuxc-gpr.h |    8 ++++++++
   9  1 file changed, 8 insertions(+)
  10
  11 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
  12 +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
  13 @@ -241,6 +241,12 @@
  14
  15  #define IMX6Q_GPR5_L2_CLK_STOP                 BIT(8)
  16
  17 +#define IMX6Q_GPR8_TX_SWING_LOW                        (0x7f << 25)
  18 +#define IMX6Q_GPR8_TX_SWING_FULL               (0x7f << 18)
  19 +#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB          (0x3f << 12)
  20 +#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB                (0x3f << 6)
  21 +#define IMX6Q_GPR8_TX_DEEMPH_GEN1              (0x3f << 0)
  22 +
  23  #define IMX6Q_GPR9_TZASC2_BYP                  BIT(1)
  24  #define IMX6Q_GPR9_TZASC1_BYP                  BIT(0)
  25
  26 @@ -273,7 +279,9 @@
  27  #define IMX6Q_GPR12_ARMP_AHB_CLK_EN            BIT(26)
  28  #define IMX6Q_GPR12_ARMP_ATB_CLK_EN            BIT(25)
  29  #define IMX6Q_GPR12_ARMP_APB_CLK_EN            BIT(24)
  30 +#define IMX6Q_GPR12_DEVICE_TYPE                        (0xf << 12)
  31  #define IMX6Q_GPR12_PCIE_CTL_2                 BIT(10)
  32 +#define IMX6Q_GPR12_LOS_LEVEL                  (0x1f << 4)
  33
  34  #define IMX6Q_GPR13_SDMA_STOP_REQ              BIT(30)
  35  #define IMX6Q_GPR13_CAN2_STOP_REQ              BIT(29)