target/linux/ipq806x/patches-3.18/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch

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   4 Subject: [v3,5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
   5 From: Archit Taneja <architt@codeaurora.org>
   6 X-Patchwork-Id: 6927091
   7 Message-Id: <1438578498-32254-6-git-send-email-architt@codeaurora.org>
   8 To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
   9         cernekee@gmail.com, computersforpeace@gmail.com
  10 Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
  11         sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
  12         Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
  13 Date: Mon,  3 Aug 2015 10:38:18 +0530
  14
  15 Enable the NAND controller node on the AP148 platform. Provide pinmux
  16 information.
  17
  18 Cc: devicetree@vger.kernel.org
  19
  20 Signed-off-by: Archit Taneja <architt@codeaurora.org>
  21
  22 ---
  23 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
  24  1 file changed, 36 insertions(+)
  25
  26 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  27 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  28 @@ -61,6 +61,31 @@
  29                                         bias-none;
  30                                 };
  31                         };
  32 +
  33 +                       nand_pins: nand_pins {
  34 +                               mux {
  35 +                                       pins = "gpio34", "gpio35", "gpio36",
  36 +                                              "gpio37", "gpio38", "gpio39",
  37 +                                              "gpio40", "gpio41", "gpio42",
  38 +                                              "gpio43", "gpio44", "gpio45",
  39 +                                              "gpio46", "gpio47";
  40 +                                       function = "nand";
  41 +                                       drive-strength = <10>;
  42 +                                       bias-disable;
  43 +                               };
  44 +
  45 +                               pullups {
  46 +                                       pins = "gpio39";
  47 +                                       bias-pull-up;
  48 +                               };
  49 +
  50 +                               hold {
  51 +                                       pins = "gpio40", "gpio41", "gpio42",
  52 +                                              "gpio43", "gpio44", "gpio45",
  53 +                                              "gpio46", "gpio47";
  54 +                                       bias-bus-hold;
  55 +                               };
  56 +                       };
  57                 };
  58
  59                 gsbi@16300000 {
  60 @@ -170,5 +195,19 @@
  61                         pinctrl-0 = <&pcie1_pins>;
  62                         pinctrl-names = "default";
  63                 };
  64 +
  65 +               nand@1ac00000 {
  66 +                       status = "ok";
  67 +
  68 +                       pinctrl-0 = <&nand_pins>;
  69 +                       pinctrl-names = "default";
  70 +
  71 +                       nand-ecc-strength = <4>;
  72 +                       nand-bus-width = <8>;
  73 +               };
  74         };
  75  };
  76 +
  77 +&adm_dma {
  78 +       status = "ok";
  79 +};