target/linux/ipq806x/patches/0001-ARM-dts-msm-split-out-msm8660-and-msm8960-soc-into-d.patch

   1 From 3cdba35369b404875849008ea97cf1705e6060ed Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Thu, 23 Jan 2014 14:09:54 -0600
   4 Subject: [PATCH 001/182] ARM: dts: msm: split out msm8660 and msm8960 soc
   5  into dts include
   6
   7 Pull the SoC device tree bits into their own files so other boards based
   8 on these SoCs can include them and reduce duplication across a number of
   9 boards.
  10
  11 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  12 ---
  13  arch/arm/boot/dts/qcom-msm8660-surf.dts |   59 +-------------------------
  14  arch/arm/boot/dts/qcom-msm8660.dtsi     |   63 ++++++++++++++++++++++++++++
  15  arch/arm/boot/dts/qcom-msm8960-cdp.dts  |   66 +----------------------------
  16  arch/arm/boot/dts/qcom-msm8960.dtsi     |   70 +++++++++++++++++++++++++++++++
  17  4 files changed, 135 insertions(+), 123 deletions(-)
  18  create mode 100644 arch/arm/boot/dts/qcom-msm8660.dtsi
  19  create mode 100644 arch/arm/boot/dts/qcom-msm8960.dtsi
  20
  21 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
  22 +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
  23 @@ -1,63 +1,6 @@
  24 -/dts-v1/;
  25 -
  26 -/include/ "skeleton.dtsi"
  27 -
  28 -#include <dt-bindings/clock/qcom,gcc-msm8660.h>
  29 +#include "qcom-msm8660.dtsi"
  30
  31  / {
  32         model = "Qualcomm MSM8660 SURF";
  33         compatible = "qcom,msm8660-surf", "qcom,msm8660";
  34 -       interrupt-parent = <&intc>;
  35 -
  36 -       intc: interrupt-controller@2080000 {
  37 -               compatible = "qcom,msm-8660-qgic";
  38 -               interrupt-controller;
  39 -               #interrupt-cells = <3>;
  40 -               reg = < 0x02080000 0x1000 >,
  41 -                     < 0x02081000 0x1000 >;
  42 -       };
  43 -
  44 -       timer@2000000 {
  45 -               compatible = "qcom,scss-timer", "qcom,msm-timer";
  46 -               interrupts = <1 0 0x301>,
  47 -                            <1 1 0x301>,
  48 -                            <1 2 0x301>;
  49 -               reg = <0x02000000 0x100>;
  50 -               clock-frequency = <27000000>,
  51 -                                 <32768>;
  52 -               cpu-offset = <0x40000>;
  53 -       };
  54 -
  55 -       msmgpio: gpio@800000 {
  56 -               compatible = "qcom,msm-gpio";
  57 -               reg = <0x00800000 0x4000>;
  58 -               gpio-controller;
  59 -               #gpio-cells = <2>;
  60 -               ngpio = <173>;
  61 -               interrupts = <0 16 0x4>;
  62 -               interrupt-controller;
  63 -               #interrupt-cells = <2>;
  64 -       };
  65 -
  66 -       gcc: clock-controller@900000 {
  67 -               compatible = "qcom,gcc-msm8660";
  68 -               #clock-cells = <1>;
  69 -               #reset-cells = <1>;
  70 -               reg = <0x900000 0x4000>;
  71 -       };
  72 -
  73 -       serial@19c40000 {
  74 -               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  75 -               reg = <0x19c40000 0x1000>,
  76 -                     <0x19c00000 0x1000>;
  77 -               interrupts = <0 195 0x0>;
  78 -               clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
  79 -               clock-names = "core", "iface";
  80 -       };
  81 -
  82 -       qcom,ssbi@500000 {
  83 -               compatible = "qcom,ssbi";
  84 -               reg = <0x500000 0x1000>;
  85 -               qcom,controller-type = "pmic-arbiter";
  86 -       };
  87  };
  88 --- /dev/null
  89 +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
  90 @@ -0,0 +1,63 @@
  91 +/dts-v1/;
  92 +
  93 +/include/ "skeleton.dtsi"
  94 +
  95 +#include <dt-bindings/clock/qcom,gcc-msm8660.h>
  96 +
  97 +/ {
  98 +       model = "Qualcomm MSM8660";
  99 +       compatible = "qcom,msm8660";
 100 +       interrupt-parent = <&intc>;
 101 +
 102 +       intc: interrupt-controller@2080000 {
 103 +               compatible = "qcom,msm-8660-qgic";
 104 +               interrupt-controller;
 105 +               #interrupt-cells = <3>;
 106 +               reg = < 0x02080000 0x1000 >,
 107 +                     < 0x02081000 0x1000 >;
 108 +       };
 109 +
 110 +       timer@2000000 {
 111 +               compatible = "qcom,scss-timer", "qcom,msm-timer";
 112 +               interrupts = <1 0 0x301>,
 113 +                            <1 1 0x301>,
 114 +                            <1 2 0x301>;
 115 +               reg = <0x02000000 0x100>;
 116 +               clock-frequency = <27000000>,
 117 +                                 <32768>;
 118 +               cpu-offset = <0x40000>;
 119 +       };
 120 +
 121 +       msmgpio: gpio@800000 {
 122 +               compatible = "qcom,msm-gpio";
 123 +               reg = <0x00800000 0x4000>;
 124 +               gpio-controller;
 125 +               #gpio-cells = <2>;
 126 +               ngpio = <173>;
 127 +               interrupts = <0 16 0x4>;
 128 +               interrupt-controller;
 129 +               #interrupt-cells = <2>;
 130 +       };
 131 +
 132 +       gcc: clock-controller@900000 {
 133 +               compatible = "qcom,gcc-msm8660";
 134 +               #clock-cells = <1>;
 135 +               #reset-cells = <1>;
 136 +               reg = <0x900000 0x4000>;
 137 +       };
 138 +
 139 +       serial@19c40000 {
 140 +               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 141 +               reg = <0x19c40000 0x1000>,
 142 +                     <0x19c00000 0x1000>;
 143 +               interrupts = <0 195 0x0>;
 144 +               clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 145 +               clock-names = "core", "iface";
 146 +       };
 147 +
 148 +       qcom,ssbi@500000 {
 149 +               compatible = "qcom,ssbi";
 150 +               reg = <0x500000 0x1000>;
 151 +               qcom,controller-type = "pmic-arbiter";
 152 +       };
 153 +};
 154 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
 155 +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
 156 @@ -1,70 +1,6 @@
 157 -/dts-v1/;
 158 -
 159 -/include/ "skeleton.dtsi"
 160 -
 161 -#include <dt-bindings/clock/qcom,gcc-msm8960.h>
 162 +#include "qcom-msm8960.dtsi"
 163
 164  / {
 165         model = "Qualcomm MSM8960 CDP";
 166         compatible = "qcom,msm8960-cdp", "qcom,msm8960";
 167 -       interrupt-parent = <&intc>;
 168 -
 169 -       intc: interrupt-controller@2000000 {
 170 -               compatible = "qcom,msm-qgic2";
 171 -               interrupt-controller;
 172 -               #interrupt-cells = <3>;
 173 -               reg = < 0x02000000 0x1000 >,
 174 -                     < 0x02002000 0x1000 >;
 175 -       };
 176 -
 177 -       timer@200a000 {
 178 -               compatible = "qcom,kpss-timer", "qcom,msm-timer";
 179 -               interrupts = <1 1 0x301>,
 180 -                            <1 2 0x301>,
 181 -                            <1 3 0x301>;
 182 -               reg = <0x0200a000 0x100>;
 183 -               clock-frequency = <27000000>,
 184 -                                 <32768>;
 185 -               cpu-offset = <0x80000>;
 186 -       };
 187 -
 188 -       msmgpio: gpio@800000 {
 189 -               compatible = "qcom,msm-gpio";
 190 -               gpio-controller;
 191 -               #gpio-cells = <2>;
 192 -               ngpio = <150>;
 193 -               interrupts = <0 16 0x4>;
 194 -               interrupt-controller;
 195 -               #interrupt-cells = <2>;
 196 -               reg = <0x800000 0x4000>;
 197 -       };
 198 -
 199 -       gcc: clock-controller@900000 {
 200 -               compatible = "qcom,gcc-msm8960";
 201 -               #clock-cells = <1>;
 202 -               #reset-cells = <1>;
 203 -               reg = <0x900000 0x4000>;
 204 -       };
 205 -
 206 -       clock-controller@4000000 {
 207 -               compatible = "qcom,mmcc-msm8960";
 208 -               reg = <0x4000000 0x1000>;
 209 -               #clock-cells = <1>;
 210 -               #reset-cells = <1>;
 211 -       };
 212 -
 213 -       serial@16440000 {
 214 -               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 215 -               reg = <0x16440000 0x1000>,
 216 -                     <0x16400000 0x1000>;
 217 -               interrupts = <0 154 0x0>;
 218 -               clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 219 -               clock-names = "core", "iface";
 220 -       };
 221 -
 222 -       qcom,ssbi@500000 {
 223 -               compatible = "qcom,ssbi";
 224 -               reg = <0x500000 0x1000>;
 225 -               qcom,controller-type = "pmic-arbiter";
 226 -       };
 227  };
 228 --- /dev/null
 229 +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
 230 @@ -0,0 +1,70 @@
 231 +/dts-v1/;
 232 +
 233 +/include/ "skeleton.dtsi"
 234 +
 235 +#include <dt-bindings/clock/qcom,gcc-msm8960.h>
 236 +
 237 +/ {
 238 +       model = "Qualcomm MSM8960";
 239 +       compatible = "qcom,msm8960";
 240 +       interrupt-parent = <&intc>;
 241 +
 242 +       intc: interrupt-controller@2000000 {
 243 +               compatible = "qcom,msm-qgic2";
 244 +               interrupt-controller;
 245 +               #interrupt-cells = <3>;
 246 +               reg = < 0x02000000 0x1000 >,
 247 +                     < 0x02002000 0x1000 >;
 248 +       };
 249 +
 250 +       timer@200a000 {
 251 +               compatible = "qcom,kpss-timer", "qcom,msm-timer";
 252 +               interrupts = <1 1 0x301>,
 253 +                            <1 2 0x301>,
 254 +                            <1 3 0x301>;
 255 +               reg = <0x0200a000 0x100>;
 256 +               clock-frequency = <27000000>,
 257 +                                 <32768>;
 258 +               cpu-offset = <0x80000>;
 259 +       };
 260 +
 261 +       msmgpio: gpio@800000 {
 262 +               compatible = "qcom,msm-gpio";
 263 +               gpio-controller;
 264 +               #gpio-cells = <2>;
 265 +               ngpio = <150>;
 266 +               interrupts = <0 16 0x4>;
 267 +               interrupt-controller;
 268 +               #interrupt-cells = <2>;
 269 +               reg = <0x800000 0x4000>;
 270 +       };
 271 +
 272 +       gcc: clock-controller@900000 {
 273 +               compatible = "qcom,gcc-msm8960";
 274 +               #clock-cells = <1>;
 275 +               #reset-cells = <1>;
 276 +               reg = <0x900000 0x4000>;
 277 +       };
 278 +
 279 +       clock-controller@4000000 {
 280 +               compatible = "qcom,mmcc-msm8960";
 281 +               reg = <0x4000000 0x1000>;
 282 +               #clock-cells = <1>;
 283 +               #reset-cells = <1>;
 284 +       };
 285 +
 286 +       serial@16440000 {
 287 +               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 288 +               reg = <0x16440000 0x1000>,
 289 +                     <0x16400000 0x1000>;
 290 +               interrupts = <0 154 0x0>;
 291 +               clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 292 +               clock-names = "core", "iface";
 293 +       };
 294 +
 295 +       qcom,ssbi@500000 {
 296 +               compatible = "qcom,ssbi";
 297 +               reg = <0x500000 0x1000>;
 298 +               qcom,controller-type = "pmic-arbiter";
 299 +       };
 300 +};