target/linux/ipq806x/patches/0041-dt-Document-Qualcomm-IPQ8064-pinctrl-binding.patch

   1 From 425015979d3b1600d14403be7d6d64ba1238e58d Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Mon, 14 Apr 2014 22:10:36 -0500
   4 Subject: [PATCH 041/182] dt: Document Qualcomm IPQ8064 pinctrl binding
   5
   6 Define a new binding for the Qualcomm TLMMv2 based pin controller inside the
   7 IPQ8064.
   8
   9 Signed-off-by: Andy Gross <agross@codeaurora.org>
  10 Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
  11 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  12 ---
  13  .../bindings/pinctrl/qcom,ipq8064-pinctrl.txt      |   95 ++++++++++++++++++++
  14  1 file changed, 95 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
  16
  17 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
  18 new file mode 100644
  19 index 0000000..e0d35a4
  20 --- /dev/null
  21 +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
  22 @@ -0,0 +1,95 @@
  23 +Qualcomm IPQ8064 TLMM block
  24 +
  25 +Required properties:
  26 +- compatible: "qcom,ipq8064-pinctrl"
  27 +- reg: Should be the base address and length of the TLMM block.
  28 +- interrupts: Should be the parent IRQ of the TLMM block.
  29 +- interrupt-controller: Marks the device node as an interrupt controller.
  30 +- #interrupt-cells: Should be two.
  31 +- gpio-controller: Marks the device node as a GPIO controller.
  32 +- #gpio-cells : Should be two.
  33 +                The first cell is the gpio pin number and the
  34 +                second cell is used for optional parameters.
  35 +
  36 +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
  37 +a general description of GPIO and interrupt bindings.
  38 +
  39 +Please refer to pinctrl-bindings.txt in this directory for details of the
  40 +common pinctrl bindings used by client devices, including the meaning of the
  41 +phrase "pin configuration node".
  42 +
  43 +Qualcomm's pin configuration nodes act as a container for an abitrary number of
  44 +subnodes. Each of these subnodes represents some desired configuration for a
  45 +pin, a group, or a list of pins or groups. This configuration can include the
  46 +mux function to select on those pin(s)/group(s), and various pin configuration
  47 +parameters, such as pull-up, drive strength, etc.
  48 +
  49 +The name of each subnode is not important; all subnodes should be enumerated
  50 +and processed purely based on their content.
  51 +
  52 +Each subnode only affects those parameters that are explicitly listed. In
  53 +other words, a subnode that lists a mux function but no pin configuration
  54 +parameters implies no information about any pin configuration parameters.
  55 +Similarly, a pin subnode that describes a pullup parameter implies no
  56 +information about e.g. the mux function.
  57 +
  58 +
  59 +The following generic properties as defined in pinctrl-bindings.txt are valid
  60 +to specify in a pin configuration subnode:
  61 +
  62 + pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,
  63 + output-low, output-high.
  64 +
  65 +Non-empty subnodes must specify the 'pins' property.
  66 +
  67 +Valid values for qcom,pins are:
  68 +  gpio0-gpio68
  69 +   Supports mux, bias, and drive-strength
  70 +
  71 +  sdc3_clk, sdc3_cmd, sdc3_data
  72 +   Supports bias and drive-strength
  73 +
  74 +
  75 +Valid values for function are:
  76 +  mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gsbi1, gsbi2, gsbi4, gsbi5,
  77 +  gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
  78 +  spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
  79 +  pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
  80 +  pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
  81 +  pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
  82 +  pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold
  83 +
  84 +Example:
  85 +
  86 +       pinmux: pinctrl@800000 {
  87 +               compatible = "qcom,ipq8064-pinctrl";
  88 +               reg = <0x800000 0x4000>;
  89 +
  90 +               gpio-controller;
  91 +               #gpio-cells = <2>;
  92 +               interrupt-controller;
  93 +               #interrupt-cells = <2>;
  94 +               interrupts = <0 32 0x4>;
  95 +
  96 +               pinctrl-names = "default";
  97 +               pinctrl-0 = <&gsbi5_uart_default>;
  98 +
  99 +               gsbi5_uart_default: gsbi5_uart_default {
 100 +                       mux {
 101 +                               pins = "gpio18", "gpio19";
 102 +                               function = "gsbi5";
 103 +                       };
 104 +
 105 +                       tx {
 106 +                               pins = "gpio18";
 107 +                               drive-strength = <4>;
 108 +                               bias-disable;
 109 +                       };
 110 +
 111 +                       rx {
 112 +                               pins = "gpio19";
 113 +                               drive-strength = <2>;
 114 +                               bias-pull-up;
 115 +                       };
 116 +               };
 117 +       };
 118 --
 119 1.7.10.4
 120