target/linux/ipq806x/patches/0048-mmc-sdhci-msm-Add-platform_execute_tuning-implementa.patch

   1 From c2a237b3e467c8bb349c4624b71ec400abaf8ad1 Mon Sep 17 00:00:00 2001
   2 From: Georgi Djakov <gdjakov@mm-sol.com>
   3 Date: Mon, 10 Mar 2014 17:37:13 +0200
   4 Subject: [PATCH 048/182] mmc: sdhci-msm: Add platform_execute_tuning
   5  implementation
   6
   7 This patch adds implementation for platform specific tuning in order
   8 to support HS200 bus speed mode on Qualcomm SDHCI controller.
   9
  10 Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
  11 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
  12 Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
  13 Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
  14 Signed-off-by: Chris Ball <chris@printf.net>
  15 ---
  16  drivers/mmc/host/sdhci-msm.c |  420 +++++++++++++++++++++++++++++++++++++++++-
  17  1 file changed, 415 insertions(+), 5 deletions(-)
  18
  19 diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
  20 index 3b0606f..acb0e9e 100644
  21 --- a/drivers/mmc/host/sdhci-msm.c
  22 +++ b/drivers/mmc/host/sdhci-msm.c
  23 @@ -18,6 +18,8 @@
  24  #include <linux/of_device.h>
  25  #include <linux/regulator/consumer.h>
  26  #include <linux/delay.h>
  27 +#include <linux/mmc/mmc.h>
  28 +#include <linux/slab.h>
  29
  30  #include "sdhci-pltfm.h"
  31
  32 @@ -26,6 +28,42 @@
  33  #define CORE_POWER             0x0
  34  #define CORE_SW_RST            BIT(7)
  35
  36 +#define MAX_PHASES             16
  37 +#define CORE_DLL_LOCK          BIT(7)
  38 +#define CORE_DLL_EN            BIT(16)
  39 +#define CORE_CDR_EN            BIT(17)
  40 +#define CORE_CK_OUT_EN         BIT(18)
  41 +#define CORE_CDR_EXT_EN                BIT(19)
  42 +#define CORE_DLL_PDN           BIT(29)
  43 +#define CORE_DLL_RST           BIT(30)
  44 +#define CORE_DLL_CONFIG                0x100
  45 +#define CORE_DLL_STATUS                0x108
  46 +
  47 +#define CORE_VENDOR_SPEC       0x10c
  48 +#define CORE_CLK_PWRSAVE       BIT(1)
  49 +
  50 +#define CDR_SELEXT_SHIFT       20
  51 +#define CDR_SELEXT_MASK                (0xf << CDR_SELEXT_SHIFT)
  52 +#define CMUX_SHIFT_PHASE_SHIFT 24
  53 +#define CMUX_SHIFT_PHASE_MASK  (7 << CMUX_SHIFT_PHASE_SHIFT)
  54 +
  55 +static const u32 tuning_block_64[] = {
  56 +       0x00ff0fff, 0xccc3ccff, 0xffcc3cc3, 0xeffefffe,
  57 +       0xddffdfff, 0xfbfffbff, 0xff7fffbf, 0xefbdf777,
  58 +       0xf0fff0ff, 0x3cccfc0f, 0xcfcc33cc, 0xeeffefff,
  59 +       0xfdfffdff, 0xffbfffdf, 0xfff7ffbb, 0xde7b7ff7
  60 +};
  61 +
  62 +static const u32 tuning_block_128[] = {
  63 +       0xff00ffff, 0x0000ffff, 0xccccffff, 0xcccc33cc,
  64 +       0xcc3333cc, 0xffffcccc, 0xffffeeff, 0xffeeeeff,
  65 +       0xffddffff, 0xddddffff, 0xbbffffff, 0xbbffffff,
  66 +       0xffffffbb, 0xffffff77, 0x77ff7777, 0xffeeddbb,
  67 +       0x00ffffff, 0x00ffffff, 0xccffff00, 0xcc33cccc,
  68 +       0x3333cccc, 0xffcccccc, 0xffeeffff, 0xeeeeffff,
  69 +       0xddffffff, 0xddffffff, 0xffffffdd, 0xffffffbb,
  70 +       0xffffbbbb, 0xffff77ff, 0xff7777ff, 0xeeddbb77
  71 +};
  72
  73  struct sdhci_msm_host {
  74         struct platform_device *pdev;
  75 @@ -38,17 +76,389 @@ struct sdhci_msm_host {
  76  };
  77
  78  /* Platform specific tuning */
  79 -static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
  80 +static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
  81 +{
  82 +       u32 wait_cnt = 50;
  83 +       u8 ck_out_en;
  84 +       struct mmc_host *mmc = host->mmc;
  85 +
  86 +       /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
  87 +       ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
  88 +                       CORE_CK_OUT_EN);
  89 +
  90 +       while (ck_out_en != poll) {
  91 +               if (--wait_cnt == 0) {
  92 +                       dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
  93 +                              mmc_hostname(mmc), poll);
  94 +                       return -ETIMEDOUT;
  95 +               }
  96 +               udelay(1);
  97 +
  98 +               ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
  99 +                               CORE_CK_OUT_EN);
 100 +       }
 101 +
 102 +       return 0;
 103 +}
 104 +
 105 +static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 106 +{
 107 +       int rc;
 108 +       static const u8 grey_coded_phase_table[] = {
 109 +               0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
 110 +               0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
 111 +       };
 112 +       unsigned long flags;
 113 +       u32 config;
 114 +       struct mmc_host *mmc = host->mmc;
 115 +
 116 +       spin_lock_irqsave(&host->lock, flags);
 117 +
 118 +       config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 119 +       config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
 120 +       config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
 121 +       writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 122 +
 123 +       /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
 124 +       rc = msm_dll_poll_ck_out_en(host, 0);
 125 +       if (rc)
 126 +               goto err_out;
 127 +
 128 +       /*
 129 +        * Write the selected DLL clock output phase (0 ... 15)
 130 +        * to CDR_SELEXT bit field of DLL_CONFIG register.
 131 +        */
 132 +       config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 133 +       config &= ~CDR_SELEXT_MASK;
 134 +       config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
 135 +       writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 136 +
 137 +       /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
 138 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 139 +                       | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
 140 +
 141 +       /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
 142 +       rc = msm_dll_poll_ck_out_en(host, 1);
 143 +       if (rc)
 144 +               goto err_out;
 145 +
 146 +       config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 147 +       config |= CORE_CDR_EN;
 148 +       config &= ~CORE_CDR_EXT_EN;
 149 +       writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 150 +       goto out;
 151 +
 152 +err_out:
 153 +       dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
 154 +              mmc_hostname(mmc), phase);
 155 +out:
 156 +       spin_unlock_irqrestore(&host->lock, flags);
 157 +       return rc;
 158 +}
 159 +
 160 +/*
 161 + * Find out the greatest range of consecuitive selected
 162 + * DLL clock output phases that can be used as sampling
 163 + * setting for SD3.0 UHS-I card read operation (in SDR104
 164 + * timing mode) or for eMMC4.5 card read operation (in HS200
 165 + * timing mode).
 166 + * Select the 3/4 of the range and configure the DLL with the
 167 + * selected DLL clock output phase.
 168 + */
 169 +
 170 +static int msm_find_most_appropriate_phase(struct sdhci_host *host,
 171 +                                          u8 *phase_table, u8 total_phases)
 172 +{
 173 +       int ret;
 174 +       u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
 175 +       u8 phases_per_row[MAX_PHASES] = { 0 };
 176 +       int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
 177 +       int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
 178 +       bool phase_0_found = false, phase_15_found = false;
 179 +       struct mmc_host *mmc = host->mmc;
 180 +
 181 +       if (!total_phases || (total_phases > MAX_PHASES)) {
 182 +               dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
 183 +                      mmc_hostname(mmc), total_phases);
 184 +               return -EINVAL;
 185 +       }
 186 +
 187 +       for (cnt = 0; cnt < total_phases; cnt++) {
 188 +               ranges[row_index][col_index] = phase_table[cnt];
 189 +               phases_per_row[row_index] += 1;
 190 +               col_index++;
 191 +
 192 +               if ((cnt + 1) == total_phases) {
 193 +                       continue;
 194 +               /* check if next phase in phase_table is consecutive or not */
 195 +               } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
 196 +                       row_index++;
 197 +                       col_index = 0;
 198 +               }
 199 +       }
 200 +
 201 +       if (row_index >= MAX_PHASES)
 202 +               return -EINVAL;
 203 +
 204 +       /* Check if phase-0 is present in first valid window? */
 205 +       if (!ranges[0][0]) {
 206 +               phase_0_found = true;
 207 +               phase_0_raw_index = 0;
 208 +               /* Check if cycle exist between 2 valid windows */
 209 +               for (cnt = 1; cnt <= row_index; cnt++) {
 210 +                       if (phases_per_row[cnt]) {
 211 +                               for (i = 0; i < phases_per_row[cnt]; i++) {
 212 +                                       if (ranges[cnt][i] == 15) {
 213 +                                               phase_15_found = true;
 214 +                                               phase_15_raw_index = cnt;
 215 +                                               break;
 216 +                                       }
 217 +                               }
 218 +                       }
 219 +               }
 220 +       }
 221 +
 222 +       /* If 2 valid windows form cycle then merge them as single window */
 223 +       if (phase_0_found && phase_15_found) {
 224 +               /* number of phases in raw where phase 0 is present */
 225 +               u8 phases_0 = phases_per_row[phase_0_raw_index];
 226 +               /* number of phases in raw where phase 15 is present */
 227 +               u8 phases_15 = phases_per_row[phase_15_raw_index];
 228 +
 229 +               if (phases_0 + phases_15 >= MAX_PHASES)
 230 +                       /*
 231 +                        * If there are more than 1 phase windows then total
 232 +                        * number of phases in both the windows should not be
 233 +                        * more than or equal to MAX_PHASES.
 234 +                        */
 235 +                       return -EINVAL;
 236 +
 237 +               /* Merge 2 cyclic windows */
 238 +               i = phases_15;
 239 +               for (cnt = 0; cnt < phases_0; cnt++) {
 240 +                       ranges[phase_15_raw_index][i] =
 241 +                           ranges[phase_0_raw_index][cnt];
 242 +                       if (++i >= MAX_PHASES)
 243 +                               break;
 244 +               }
 245 +
 246 +               phases_per_row[phase_0_raw_index] = 0;
 247 +               phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
 248 +       }
 249 +
 250 +       for (cnt = 0; cnt <= row_index; cnt++) {
 251 +               if (phases_per_row[cnt] > curr_max) {
 252 +                       curr_max = phases_per_row[cnt];
 253 +                       selected_row_index = cnt;
 254 +               }
 255 +       }
 256 +
 257 +       i = (curr_max * 3) / 4;
 258 +       if (i)
 259 +               i--;
 260 +
 261 +       ret = ranges[selected_row_index][i];
 262 +
 263 +       if (ret >= MAX_PHASES) {
 264 +               ret = -EINVAL;
 265 +               dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
 266 +                      mmc_hostname(mmc), ret);
 267 +       }
 268 +
 269 +       return ret;
 270 +}
 271 +
 272 +static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
 273 +{
 274 +       u32 mclk_freq = 0, config;
 275 +
 276 +       /* Program the MCLK value to MCLK_FREQ bit field */
 277 +       if (host->clock <= 112000000)
 278 +               mclk_freq = 0;
 279 +       else if (host->clock <= 125000000)
 280 +               mclk_freq = 1;
 281 +       else if (host->clock <= 137000000)
 282 +               mclk_freq = 2;
 283 +       else if (host->clock <= 150000000)
 284 +               mclk_freq = 3;
 285 +       else if (host->clock <= 162000000)
 286 +               mclk_freq = 4;
 287 +       else if (host->clock <= 175000000)
 288 +               mclk_freq = 5;
 289 +       else if (host->clock <= 187000000)
 290 +               mclk_freq = 6;
 291 +       else if (host->clock <= 200000000)
 292 +               mclk_freq = 7;
 293 +
 294 +       config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 295 +       config &= ~CMUX_SHIFT_PHASE_MASK;
 296 +       config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
 297 +       writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 298 +}
 299 +
 300 +/* Initialize the DLL (Programmable Delay Line) */
 301 +static int msm_init_cm_dll(struct sdhci_host *host)
 302  {
 303 +       struct mmc_host *mmc = host->mmc;
 304 +       int wait_cnt = 50;
 305 +       unsigned long flags;
 306 +
 307 +       spin_lock_irqsave(&host->lock, flags);
 308 +
 309         /*
 310 -        * Tuning is required for SDR104, HS200 and HS400 cards and if the clock
 311 -        * frequency greater than 100MHz in those modes. The standard tuning
 312 -        * procedure should not be executed, but a custom implementation will be
 313 -        * added here instead.
 314 +        * Make sure that clock is always enabled when DLL
 315 +        * tuning is in progress. Keeping PWRSAVE ON may
 316 +        * turn off the clock.
 317          */
 318 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
 319 +                       & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
 320 +
 321 +       /* Write 1 to DLL_RST bit of DLL_CONFIG register */
 322 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 323 +                       | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
 324 +
 325 +       /* Write 1 to DLL_PDN bit of DLL_CONFIG register */
 326 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 327 +                       | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
 328 +       msm_cm_dll_set_freq(host);
 329 +
 330 +       /* Write 0 to DLL_RST bit of DLL_CONFIG register */
 331 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 332 +                       & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
 333 +
 334 +       /* Write 0 to DLL_PDN bit of DLL_CONFIG register */
 335 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 336 +                       & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
 337 +
 338 +       /* Set DLL_EN bit to 1. */
 339 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 340 +                       | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);
 341 +
 342 +       /* Set CK_OUT_EN bit to 1. */
 343 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 344 +                       | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
 345 +
 346 +       /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
 347 +       while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
 348 +                CORE_DLL_LOCK)) {
 349 +               /* max. wait for 50us sec for LOCK bit to be set */
 350 +               if (--wait_cnt == 0) {
 351 +                       dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
 352 +                              mmc_hostname(mmc));
 353 +                       spin_unlock_irqrestore(&host->lock, flags);
 354 +                       return -ETIMEDOUT;
 355 +               }
 356 +               udelay(1);
 357 +       }
 358 +
 359 +       spin_unlock_irqrestore(&host->lock, flags);
 360         return 0;
 361  }
 362
 363 +static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 364 +{
 365 +       int tuning_seq_cnt = 3;
 366 +       u8 phase, *data_buf, tuned_phases[16], tuned_phase_cnt = 0;
 367 +       const u32 *tuning_block_pattern = tuning_block_64;
 368 +       int size = sizeof(tuning_block_64);     /* Pattern size in bytes */
 369 +       int rc;
 370 +       struct mmc_host *mmc = host->mmc;
 371 +       struct mmc_ios ios = host->mmc->ios;
 372 +
 373 +       /*
 374 +        * Tuning is required for SDR104, HS200 and HS400 cards and
 375 +        * if clock frequency is greater than 100MHz in these modes.
 376 +        */
 377 +       if (host->clock <= 100 * 1000 * 1000 ||
 378 +           !((ios.timing == MMC_TIMING_MMC_HS200) ||
 379 +             (ios.timing == MMC_TIMING_UHS_SDR104)))
 380 +               return 0;
 381 +
 382 +       if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) &&
 383 +           (mmc->ios.bus_width == MMC_BUS_WIDTH_8)) {
 384 +               tuning_block_pattern = tuning_block_128;
 385 +               size = sizeof(tuning_block_128);
 386 +       }
 387 +
 388 +       data_buf = kmalloc(size, GFP_KERNEL);
 389 +       if (!data_buf)
 390 +               return -ENOMEM;
 391 +
 392 +retry:
 393 +       /* First of all reset the tuning block */
 394 +       rc = msm_init_cm_dll(host);
 395 +       if (rc)
 396 +               goto out;
 397 +
 398 +       phase = 0;
 399 +       do {
 400 +               struct mmc_command cmd = { 0 };
 401 +               struct mmc_data data = { 0 };
 402 +               struct mmc_request mrq = {
 403 +                       .cmd = &cmd,
 404 +                       .data = &data
 405 +               };
 406 +               struct scatterlist sg;
 407 +
 408 +               /* Set the phase in delay line hw block */
 409 +               rc = msm_config_cm_dll_phase(host, phase);
 410 +               if (rc)
 411 +                       goto out;
 412 +
 413 +               cmd.opcode = opcode;
 414 +               cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 415 +
 416 +               data.blksz = size;
 417 +               data.blocks = 1;
 418 +               data.flags = MMC_DATA_READ;
 419 +               data.timeout_ns = NSEC_PER_SEC; /* 1 second */
 420 +
 421 +               data.sg = &sg;
 422 +               data.sg_len = 1;
 423 +               sg_init_one(&sg, data_buf, size);
 424 +               memset(data_buf, 0, size);
 425 +               mmc_wait_for_req(mmc, &mrq);
 426 +
 427 +               if (!cmd.error && !data.error &&
 428 +                   !memcmp(data_buf, tuning_block_pattern, size)) {
 429 +                       /* Tuning is successful at this tuning point */
 430 +                       tuned_phases[tuned_phase_cnt++] = phase;
 431 +                       dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
 432 +                                mmc_hostname(mmc), phase);
 433 +               }
 434 +       } while (++phase < ARRAY_SIZE(tuned_phases));
 435 +
 436 +       if (tuned_phase_cnt) {
 437 +               rc = msm_find_most_appropriate_phase(host, tuned_phases,
 438 +                                                    tuned_phase_cnt);
 439 +               if (rc < 0)
 440 +                       goto out;
 441 +               else
 442 +                       phase = rc;
 443 +
 444 +               /*
 445 +                * Finally set the selected phase in delay
 446 +                * line hw block.
 447 +                */
 448 +               rc = msm_config_cm_dll_phase(host, phase);
 449 +               if (rc)
 450 +                       goto out;
 451 +               dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
 452 +                        mmc_hostname(mmc), phase);
 453 +       } else {
 454 +               if (--tuning_seq_cnt)
 455 +                       goto retry;
 456 +               /* Tuning failed */
 457 +               dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
 458 +                      mmc_hostname(mmc));
 459 +               rc = -EIO;
 460 +       }
 461 +
 462 +out:
 463 +       kfree(data_buf);
 464 +       return rc;
 465 +}
 466 +
 467  static const struct of_device_id sdhci_msm_dt_match[] = {
 468         { .compatible = "qcom,sdhci-msm-v4" },
 469         {},
 470 --
 471 1.7.10.4
 472