target/linux/ipq806x/patches/0135-spi-qup-Add-support-for-v1.1.1.patch

   1 From 8b9de04ef3aaa154f30baf1ac703a2d3b474ad4e Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Thu, 12 Jun 2014 14:34:12 -0500
   4 Subject: [PATCH 135/182] spi: qup: Add support for v1.1.1
   5
   6 This patch adds support for v1.1.1 of the SPI QUP controller.
   7
   8 Signed-off-by: Andy Gross <agross@codeaurora.org>
   9 ---
  10  .../devicetree/bindings/spi/qcom,spi-qup.txt       |    6 +++-
  11  drivers/spi/spi-qup.c                              |   36 ++++++++++++--------
  12  2 files changed, 27 insertions(+), 15 deletions(-)
  13
  14 diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
  15 index bee6ff2..e2c88df 100644
  16 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
  17 +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
  18 @@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz, up to four chip selects, programmable
  19  data path from 4 bits to 32 bits and numerous protocol variants.
  20
  21  Required properties:
  22 -- compatible:     Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
  23 +- compatible:     Should contain:
  24 +                 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
  25 +                 "qcom,spi-qup-v2.1.1" for 8974 and later
  26 +                 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
  27 +
  28  - reg:            Should contain base register location and length
  29  - interrupts:     Interrupt number used by this controller
  30
  31 diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
  32 index a404298..c137226 100644
  33 --- a/drivers/spi/spi-qup.c
  34 +++ b/drivers/spi/spi-qup.c
  35 @@ -142,6 +142,7 @@ struct spi_qup {
  36         int                     w_size; /* bytes per SPI word */
  37         int                     tx_bytes;
  38         int                     rx_bytes;
  39 +       int                     qup_v1;
  40  };
  41
  42
  43 @@ -420,7 +421,9 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
  44         config |= QUP_CONFIG_SPI_MODE;
  45         writel_relaxed(config, controller->base + QUP_CONFIG);
  46
  47 -       writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
  48 +       /* only write to OPERATIONAL_MASK when register is present */
  49 +       if (!controller->qup_v1)
  50 +               writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
  51         return 0;
  52  }
  53
  54 @@ -486,7 +489,7 @@ static int spi_qup_probe(struct platform_device *pdev)
  55         struct resource *res;
  56         struct device *dev;
  57         void __iomem *base;
  58 -       u32 data, max_freq, iomode;
  59 +       u32 max_freq, iomode;
  60         int ret, irq, size;
  61
  62         dev = &pdev->dev;
  63 @@ -529,15 +532,6 @@ static int spi_qup_probe(struct platform_device *pdev)
  64                 return ret;
  65         }
  66
  67 -       data = readl_relaxed(base + QUP_HW_VERSION);
  68 -
  69 -       if (data < QUP_HW_VERSION_2_1_1) {
  70 -               clk_disable_unprepare(cclk);
  71 -               clk_disable_unprepare(iclk);
  72 -               dev_err(dev, "v.%08x is not supported\n", data);
  73 -               return -ENXIO;
  74 -       }
  75 -
  76         master = spi_alloc_master(dev, sizeof(struct spi_qup));
  77         if (!master) {
  78                 clk_disable_unprepare(cclk);
  79 @@ -570,6 +564,10 @@ static int spi_qup_probe(struct platform_device *pdev)
  80         controller->cclk = cclk;
  81         controller->irq = irq;
  82
  83 +       /* set v1 flag if device is version 1 */
  84 +       if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
  85 +               controller->qup_v1 = 1;
  86 +
  87         spin_lock_init(&controller->lock);
  88         init_completion(&controller->done);
  89
  90 @@ -593,8 +591,8 @@ static int spi_qup_probe(struct platform_device *pdev)
  91         size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
  92         controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
  93
  94 -       dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
  95 -                data, controller->in_blk_sz, controller->in_fifo_sz,
  96 +       dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
  97 +                controller->in_blk_sz, controller->in_fifo_sz,
  98                  controller->out_blk_sz, controller->out_fifo_sz);
  99
 100         writel_relaxed(1, base + QUP_SW_RESET);
 101 @@ -607,10 +605,19 @@ static int spi_qup_probe(struct platform_device *pdev)
 102
 103         writel_relaxed(0, base + QUP_OPERATIONAL);
 104         writel_relaxed(0, base + QUP_IO_M_MODES);
 105 -       writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
 106 +
 107 +       if (!controller->qup_v1)
 108 +               writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
 109 +
 110         writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
 111                        base + SPI_ERROR_FLAGS_EN);
 112
 113 +       /* if earlier version of the QUP, disable INPUT_OVERRUN */
 114 +       if (controller->qup_v1)
 115 +               writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
 116 +                       QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
 117 +                       base + QUP_ERROR_FLAGS_EN);
 118 +
 119         writel_relaxed(0, base + SPI_CONFIG);
 120         writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
 121
 122 @@ -732,6 +739,7 @@ static int spi_qup_remove(struct platform_device *pdev)
 123  }
 124
 125  static struct of_device_id spi_qup_dt_match[] = {
 126 +       { .compatible = "qcom,spi-qup-v1.1.1", },
 127         { .compatible = "qcom,spi-qup-v2.1.1", },
 128         { .compatible = "qcom,spi-qup-v2.2.1", },
 129         { }
 130 --
 131 1.7.10.4
 132