target/linux/ipq806x/patches/0137-ARM-qcom-ipq8064-ap148-Add-SPI-related-bindings.patch

   1 From b9eaa80146abb09bcc7e6d8b33fca476453c839c Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Wed, 14 May 2014 22:01:16 -0500
   4 Subject: [PATCH 137/182] ARM: qcom-ipq8064-ap148: Add SPI related bindings
   5
   6 Signed-off-by: Andy Gross <agross@codeaurora.org>
   7 ---
   8  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   42 ++++++++++++++++++++++++++
   9  arch/arm/boot/dts/qcom-ipq8064.dtsi      |   47 ++++++++++++++++++++++++++++++
  10  2 files changed, 89 insertions(+)
  11
  12 diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  13 index dbb546d..158a09f 100644
  14 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  15 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  16 @@ -20,6 +20,15 @@
  17                                 function = "gsbi4";
  18                                 bias-disable;
  19                         };
  20 +
  21 +                       spi_pins: spi_pins {
  22 +                               mux {
  23 +                                       pins = "gpio18", "gpio19", "gpio21";
  24 +                                       function = "gsbi5";
  25 +                                       drive-strength = <10>;
  26 +                                       bias-none;
  27 +                               };
  28 +                       };
  29                 };
  30
  31                 gsbi@16300000 {
  32 @@ -38,5 +47,38 @@
  33                                 pinctrl-names = "default";
  34                         };
  35                 };
  36 +
  37 +               gsbi5: gsbi@1a200000 {
  38 +                       qcom,mode = <GSBI_PROT_SPI>;
  39 +                       status = "ok";
  40 +
  41 +                       spi4: spi@1a280000 {
  42 +                               status = "ok";
  43 +                               spi-max-frequency = <50000000>;
  44 +
  45 +                               pinctrl-0 = <&spi_pins>;
  46 +                               pinctrl-names = "default";
  47 +
  48 +                               cs-gpios = <&qcom_pinmux 20 0>;
  49 +
  50 +                               flash: m25p80@0 {
  51 +                                       compatible = "s25fl256s1";
  52 +                                       #address-cells = <1>;
  53 +                                       #size-cells = <1>;
  54 +                                       spi-max-frequency = <50000000>;
  55 +                                       reg = <0>;
  56 +
  57 +                                       partition@0 {
  58 +                                               label = "rootfs";
  59 +                                               reg = <0x0 0x1000000>;
  60 +                                       };
  61 +
  62 +                                       partition@1 {
  63 +                                               label = "scratch";
  64 +                                               reg = <0x1000000 0x1000000>;
  65 +                                       };
  66 +                               };
  67 +                       };
  68 +               };
  69         };
  70  };
  71 diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  72 index b39c1ef..244f857 100644
  73 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  74 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  75 @@ -187,6 +187,53 @@
  76                         };
  77                 };
  78
  79 +               gsbi5: gsbi@1a200000 {
  80 +                       compatible = "qcom,gsbi-v1.0.0";
  81 +                       reg = <0x1a200000 0x100>;
  82 +                       clocks = <&gcc GSBI5_H_CLK>;
  83 +                       clock-names = "iface";
  84 +                       #address-cells = <1>;
  85 +                       #size-cells = <1>;
  86 +                       ranges;
  87 +                       status = "disabled";
  88 +
  89 +                       serial@1a240000 {
  90 +                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  91 +                               reg = <0x1a240000 0x1000>,
  92 +                                     <0x1a200000 0x1000>;
  93 +                               interrupts = <0 154 0x0>;
  94 +                               clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
  95 +                               clock-names = "core", "iface";
  96 +                               status = "disabled";
  97 +                       };
  98 +
  99 +                       i2c@1a280000 {
 100 +                               compatible = "qcom,i2c-qup-v1.1.1";
 101 +                               reg = <0x1a280000 0x1000>;
 102 +                               interrupts = <0 155 0>;
 103 +
 104 +                               clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 105 +                               clock-names = "core", "iface";
 106 +                               status = "disabled";
 107 +
 108 +                               #address-cells = <1>;
 109 +                               #size-cells = <0>;
 110 +                       };
 111 +
 112 +                       spi@1a280000 {
 113 +                               compatible = "qcom,spi-qup-v1.1.1";
 114 +                               reg = <0x1a280000 0x1000>;
 115 +                               interrupts = <0 155 0>;
 116 +
 117 +                               clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 118 +                               clock-names = "core", "iface";
 119 +                               status = "disabled";
 120 +
 121 +                               #address-cells = <1>;
 122 +                               #size-cells = <0>;
 123 +                       };
 124 +               };
 125 +
 126                 qcom,ssbi@500000 {
 127                         compatible = "qcom,ssbi";
 128                         reg = <0x00500000 0x1000>;
 129 --
 130 1.7.10.4
 131