target/linux/lantiq/patches-3.10/0004-MIPS-lantiq-falcon-add-cpu-feature-override.h.patch

   1 From e451973421b255917496c8ef784f8a5c92bb5548 Mon Sep 17 00:00:00 2001
   2 From: Thomas Langer <thomas.langer@lantiq.com>
   3 Date: Thu, 8 Aug 2013 11:07:25 +0200
   4 Subject: [PATCH 04/34] MIPS: lantiq: falcon: add cpu-feature-override.h
   5
   6 Add cpu-feature-override.h for the GPON SoC
   7
   8 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
   9 Acked-by: John Crispin <blogic@openwrt.org>
  10
  11 Acked-by: John Crispin <blogic@openwrt.org>
  12 Patchwork: http://patchwork.linux-mips.org/patch/5658/
  13 ---
  14  .../asm/mach-lantiq/falcon/cpu-feature-overrides.h |   58 ++++++++++++++++++++
  15  1 file changed, 58 insertions(+)
  16  create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
  17
  18 --- /dev/null
  19 +++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
  20 @@ -0,0 +1,58 @@
  21 +/*
  22 + *  Lantiq FALCON specific CPU feature overrides
  23 + *
  24 + *  Copyright (C) 2013 Thomas Langer, Lantiq Deutschland
  25 + *
  26 + *  This file was derived from: include/asm-mips/cpu-features.h
  27 + *     Copyright (C) 2003, 2004 Ralf Baechle
  28 + *     Copyright (C) 2004 Maciej W. Rozycki
  29 + *
  30 + *  This program is free software; you can redistribute it and/or modify it
  31 + *  under the terms of the GNU General Public License version 2 as published
  32 + *  by the Free Software Foundation.
  33 + *
  34 + */
  35 +#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
  36 +#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
  37 +
  38 +#define cpu_has_tlb            1
  39 +#define cpu_has_4kex           1
  40 +#define cpu_has_3k_cache       0
  41 +#define cpu_has_4k_cache       1
  42 +#define cpu_has_tx39_cache     0
  43 +#define cpu_has_sb1_cache      0
  44 +#define cpu_has_fpu            0
  45 +#define cpu_has_32fpr          0
  46 +#define cpu_has_counter                1
  47 +#define cpu_has_watch          1
  48 +#define cpu_has_divec          1
  49 +
  50 +#define cpu_has_prefetch       1
  51 +#define cpu_has_ejtag          1
  52 +#define cpu_has_llsc           1
  53 +
  54 +#define cpu_has_mips16         1
  55 +#define cpu_has_mdmx           0
  56 +#define cpu_has_mips3d         0
  57 +#define cpu_has_smartmips      0
  58 +
  59 +#define cpu_has_mips32r1       1
  60 +#define cpu_has_mips32r2       1
  61 +#define cpu_has_mips64r1       0
  62 +#define cpu_has_mips64r2       0
  63 +
  64 +#define cpu_has_dsp            1
  65 +#define cpu_has_mipsmt         1
  66 +
  67 +#define cpu_has_vint           1
  68 +#define cpu_has_veic           1
  69 +
  70 +#define cpu_has_64bits         0
  71 +#define cpu_has_64bit_zero_reg 0
  72 +#define cpu_has_64bit_gp_regs  0
  73 +#define cpu_has_64bit_addresses        0
  74 +
  75 +#define cpu_dcache_line_size() 32
  76 +#define cpu_icache_line_size() 32
  77 +
  78 +#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */