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kernel/3.10: refresh all target patches
[openwrt/staging/lynxis/omap.git] / target / linux / lantiq / patches-3.10 / 0020-NET-MIPS-lantiq-adds-xrx200-net.patch
1 From 5c7a5ddaf069b7061e1c7b536756b0b70d37b991 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Oct 2012 12:22:23 +0200
4 Subject: [PATCH 20/34] NET: MIPS: lantiq: adds xrx200-net
5
6 ---
7 drivers/net/ethernet/Kconfig | 8 +-
8 drivers/net/ethernet/Makefile | 1 +
9 drivers/net/ethernet/lantiq_pce.h | 163 +++++
10 drivers/net/ethernet/lantiq_xrx200.c | 1203 ++++++++++++++++++++++++++++++++++
11 4 files changed, 1374 insertions(+), 1 deletion(-)
12 create mode 100644 drivers/net/ethernet/lantiq_pce.h
13 create mode 100644 drivers/net/ethernet/lantiq_xrx200.c
14
15 --- a/drivers/net/ethernet/Kconfig
16 +++ b/drivers/net/ethernet/Kconfig
17 @@ -83,7 +83,13 @@ config LANTIQ_ETOP
18 tristate "Lantiq SoC ETOP driver"
19 depends on SOC_TYPE_XWAY
20 ---help---
21 - Support for the MII0 inside the Lantiq SoC
22 + Support for the MII0 inside the Lantiq ADSL SoC
23 +
24 +config LANTIQ_XRX200
25 + tristate "Lantiq SoC XRX200 driver"
26 + depends on SOC_TYPE_XWAY
27 + ---help---
28 + Support for the MII0 inside the Lantiq VDSL SoC
29
30 source "drivers/net/ethernet/marvell/Kconfig"
31 source "drivers/net/ethernet/mellanox/Kconfig"
32 --- a/drivers/net/ethernet/Makefile
33 +++ b/drivers/net/ethernet/Makefile
34 @@ -36,6 +36,7 @@ obj-$(CONFIG_IP1000) += icplus/
35 obj-$(CONFIG_JME) += jme.o
36 obj-$(CONFIG_KORINA) += korina.o
37 obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
38 +obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o
39 obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
40 obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
41 obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
42 --- /dev/null
43 +++ b/drivers/net/ethernet/lantiq_pce.h
44 @@ -0,0 +1,163 @@
45 +/*
46 + * This program is free software; you can redistribute it and/or modify it
47 + * under the terms of the GNU General Public License version 2 as published
48 + * by the Free Software Foundation.
49 + *
50 + * This program is distributed in the hope that it will be useful,
51 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
52 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
53 + * GNU General Public License for more details.
54 + *
55 + * You should have received a copy of the GNU General Public License
56 + * along with this program; if not, write to the Free Software
57 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
58 + *
59 + * Copyright (C) 2010 Lantiq Deutschland GmbH
60 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
61 + *
62 + * PCE microcode extracted from UGW5.2 switch api
63 + */
64 +
65 +/* Switch API Micro Code V0.3 */
66 +enum {
67 + OUT_MAC0 = 0,
68 + OUT_MAC1,
69 + OUT_MAC2,
70 + OUT_MAC3,
71 + OUT_MAC4,
72 + OUT_MAC5,
73 + OUT_ETHTYP,
74 + OUT_VTAG0,
75 + OUT_VTAG1,
76 + OUT_ITAG0,
77 + OUT_ITAG1, /*10 */
78 + OUT_ITAG2,
79 + OUT_ITAG3,
80 + OUT_IP0,
81 + OUT_IP1,
82 + OUT_IP2,
83 + OUT_IP3,
84 + OUT_SIP0,
85 + OUT_SIP1,
86 + OUT_SIP2,
87 + OUT_SIP3, /*20*/
88 + OUT_SIP4,
89 + OUT_SIP5,
90 + OUT_SIP6,
91 + OUT_SIP7,
92 + OUT_DIP0,
93 + OUT_DIP1,
94 + OUT_DIP2,
95 + OUT_DIP3,
96 + OUT_DIP4,
97 + OUT_DIP5, /*30*/
98 + OUT_DIP6,
99 + OUT_DIP7,
100 + OUT_SESID,
101 + OUT_PROT,
102 + OUT_APP0,
103 + OUT_APP1,
104 + OUT_IGMP0,
105 + OUT_IGMP1,
106 + OUT_IPOFF, /*39*/
107 + OUT_NONE = 63
108 +};
109 +
110 +/* parser's microcode length type */
111 +#define INSTR 0
112 +#define IPV6 1
113 +#define LENACCU 2
114 +
115 +/* parser's microcode flag type */
116 +enum {
117 + FLAG_ITAG = 0,
118 + FLAG_VLAN,
119 + FLAG_SNAP,
120 + FLAG_PPPOE,
121 + FLAG_IPV6,
122 + FLAG_IPV6FL,
123 + FLAG_IPV4,
124 + FLAG_IGMP,
125 + FLAG_TU,
126 + FLAG_HOP,
127 + FLAG_NN1, /*10 */
128 + FLAG_NN2,
129 + FLAG_END,
130 + FLAG_NO, /*13*/
131 +};
132 +
133 +/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */
134 +#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \
135 + { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }}
136 +struct pce_microcode {
137 + unsigned short val[4];
138 +/* unsigned short val_2;
139 + unsigned short val_1;
140 + unsigned short val_0;*/
141 +} pce_microcode[] = {
142 + /* value mask ns fields L type flags ipv4_len */
143 + MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
144 + MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
145 + MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
146 + MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
147 + MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
148 + MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
149 + MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
150 + MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
151 + MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0),
152 + MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
153 + MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
154 + MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0),
155 + MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0),
156 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
157 + MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0),
158 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
159 + MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0),
160 + MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0),
161 + MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0),
162 + MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0),
163 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
164 + MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1),
165 + MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0),
166 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
167 + MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0),
168 + MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0),
169 + MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0),
170 + MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
171 + MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
172 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0),
173 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0),
174 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0),
175 + MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
176 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0),
177 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0),
178 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0),
179 + MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0),
180 + MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0),
181 + MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0),
182 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
183 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
184 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
185 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
186 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
187 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
188 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
189 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
190 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
191 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
192 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
193 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
194 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
195 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
196 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
197 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
198 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
199 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
200 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
201 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
202 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
203 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
204 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
205 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
206 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
207 +};
208 --- /dev/null
209 +++ b/drivers/net/ethernet/lantiq_xrx200.c
210 @@ -0,0 +1,1203 @@
211 +/*
212 + * This program is free software; you can redistribute it and/or modify it
213 + * under the terms of the GNU General Public License version 2 as published
214 + * by the Free Software Foundation.
215 + *
216 + * This program is distributed in the hope that it will be useful,
217 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
218 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
219 + * GNU General Public License for more details.
220 + *
221 + * You should have received a copy of the GNU General Public License
222 + * along with this program; if not, write to the Free Software
223 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
224 + *
225 + * Copyright (C) 2010 Lantiq Deutschland
226 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
227 + */
228 +
229 +#include <linux/etherdevice.h>
230 +#include <linux/module.h>
231 +#include <linux/platform_device.h>
232 +#include <linux/interrupt.h>
233 +#include <linux/clk.h>
234 +#include <asm/delay.h>
235 +
236 +#include <linux/of_net.h>
237 +#include <linux/of_mdio.h>
238 +#include <linux/of_gpio.h>
239 +
240 +#include <xway_dma.h>
241 +#include <lantiq_soc.h>
242 +
243 +#include "lantiq_pce.h"
244 +
245 +#define SW_POLLING
246 +#define SW_ROUTING
247 +#define SW_PORTMAP
248 +
249 +#ifdef SW_ROUTING
250 + #ifdef SW_PORTMAP
251 +#define XRX200_MAX_DEV 2
252 + #else
253 +#define XRX200_MAX_DEV 2
254 + #endif
255 +#else
256 +#define XRX200_MAX_DEV 1
257 +#endif
258 +
259 +#define XRX200_MAX_PORT 7
260 +#define XRX200_MAX_DMA 8
261 +
262 +#define XRX200_HEADROOM 4
263 +
264 +#define XRX200_TX_TIMEOUT (10 * HZ)
265 +
266 +/* port type */
267 +#define XRX200_PORT_TYPE_PHY 1
268 +#define XRX200_PORT_TYPE_MAC 2
269 +
270 +/* DMA */
271 +#define XRX200_DMA_CRC_LEN 0x4
272 +#define XRX200_DMA_DATA_LEN 0x600
273 +#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0
274 +#define XRX200_DMA_RX 0
275 +#define XRX200_DMA_TX 1
276 +#define XRX200_DMA_IS_TX(x) (x%2)
277 +#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x))
278 +
279 +/* fetch / store dma */
280 +#define FDMA_PCTRL0 0x2A00
281 +#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18))
282 +#define SDMA_PCTRL0 0x2F00
283 +#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18))
284 +
285 +/* buffer management */
286 +#define BM_PCFG0 0x200
287 +#define BM_PCFGx(x) (BM_PCFG0 + (x * 8))
288 +
289 +/* MDIO */
290 +#define MDIO_GLOB 0x0000
291 +#define MDIO_CTRL 0x0020
292 +#define MDIO_READ 0x0024
293 +#define MDIO_WRITE 0x0028
294 +#define MDIO_PHY0 0x0054
295 +#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned)))
296 +#define MDIO_CLK_CFG0 0x002C
297 +#define MDIO_CLK_CFG1 0x0030
298 +
299 +#define MDIO_GLOB_ENABLE 0x8000
300 +#define MDIO_BUSY BIT(12)
301 +#define MDIO_RD BIT(11)
302 +#define MDIO_WR BIT(10)
303 +#define MDIO_MASK 0x1f
304 +#define MDIO_ADDRSHIFT 5
305 +#define MDIO1_25MHZ 9
306 +
307 +#define MDIO_PHY_LINK_DOWN 0x4000
308 +#define MDIO_PHY_LINK_UP 0x2000
309 +
310 +#define MDIO_PHY_SPEED_M10 0x0000
311 +#define MDIO_PHY_SPEED_M100 0x0800
312 +#define MDIO_PHY_SPEED_G1 0x1000
313 +
314 +#define MDIO_PHY_FDUP_EN 0x0600
315 +#define MDIO_PHY_FDUP_DIS 0x0200
316 +
317 +#define MDIO_PHY_LINK_MASK 0x6000
318 +#define MDIO_PHY_SPEED_MASK 0x1800
319 +#define MDIO_PHY_FDUP_MASK 0x0600
320 +#define MDIO_PHY_ADDR_MASK 0x001f
321 +#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \
322 + MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK
323 +
324 +/* MII */
325 +#define MII_CFG(p) (p * 8)
326 +
327 +#define MII_CFG_EN BIT(14)
328 +
329 +#define MII_CFG_MODE_MIIP 0x0
330 +#define MII_CFG_MODE_MIIM 0x1
331 +#define MII_CFG_MODE_RMIIP 0x2
332 +#define MII_CFG_MODE_RMIIM 0x3
333 +#define MII_CFG_MODE_RGMII 0x4
334 +#define MII_CFG_MODE_MASK 0xf
335 +
336 +#define MII_CFG_RATE_M2P5 0x00
337 +#define MII_CFG_RATE_M25 0x10
338 +#define MII_CFG_RATE_M125 0x20
339 +#define MII_CFG_RATE_M50 0x30
340 +#define MII_CFG_RATE_AUTO 0x40
341 +#define MII_CFG_RATE_MASK 0x70
342 +
343 +/* cpu port mac */
344 +#define PMAC_HD_CTL 0x0000
345 +#define PMAC_RX_IPG 0x0024
346 +#define PMAC_EWAN 0x002c
347 +
348 +#define PMAC_IPG_MASK 0xf
349 +#define PMAC_HD_CTL_AS 0x0008
350 +#define PMAC_HD_CTL_AC 0x0004
351 +#define PMAC_HD_CTL_RXSH 0x0040
352 +#define PMAC_HD_CTL_AST 0x0080
353 +#define PMAC_HD_CTL_RST 0x0100
354 +
355 +/* PCE */
356 +#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4))
357 +#define PCE_TBL_MASK 0x1120
358 +#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4))
359 +#define PCE_TBL_ADDR 0x1138
360 +#define PCE_TBL_CTRL 0x113c
361 +#define PCE_PMAP1 0x114c
362 +#define PCE_PMAP2 0x1150
363 +#define PCE_PMAP3 0x1154
364 +#define PCE_GCTRL_REG(x) (0x1158 + (x * 4))
365 +#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4))
366 +
367 +#define PCE_TBL_BUSY BIT(15)
368 +#define PCE_TBL_CFG_ADDR_MASK 0x1f
369 +#define PCE_TBL_CFG_ADWR 0x20
370 +#define PCE_TBL_CFG_ADWR_MASK 0x60
371 +#define PCE_INGRESS BIT(11)
372 +
373 +/* MAC */
374 +#define MAC_FLEN_REG (0x2314)
375 +#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4))
376 +
377 +/* buffer management */
378 +#define BM_PCFG(p) (0x200 + (p * 8))
379 +
380 +/* special tag in TX path header */
381 +#define SPID_SHIFT 24
382 +#define DPID_SHIFT 16
383 +#define DPID_ENABLE 1
384 +#define SPID_CPU_PORT 2
385 +#define PORT_MAP_SEL BIT(15)
386 +#define PORT_MAP_EN BIT(14)
387 +#define PORT_MAP_SHIFT 1
388 +#define PORT_MAP_MASK 0x3f
389 +
390 +#define SPPID_MASK 0x7
391 +#define SPPID_SHIFT 4
392 +
393 +/* MII regs not yet in linux */
394 +#define MDIO_DEVAD_NONE (-1)
395 +#define ADVERTIZE_MPD (1 << 10)
396 +
397 +struct xrx200_port {
398 + u8 num;
399 + u8 phy_addr;
400 + u16 flags;
401 + phy_interface_t phy_if;
402 +
403 + int link;
404 + int gpio;
405 + enum of_gpio_flags gpio_flags;
406 +
407 + struct phy_device *phydev;
408 + struct device_node *phy_node;
409 +};
410 +
411 +struct xrx200_chan {
412 + int idx;
413 + int refcount;
414 + int tx_free;
415 +
416 + struct net_device dummy_dev;
417 + struct net_device *devs[XRX200_MAX_DEV];
418 +
419 + struct tasklet_struct tasklet;
420 + struct napi_struct napi;
421 + struct ltq_dma_channel dma;
422 + struct sk_buff *skb[LTQ_DESC_NUM];
423 +};
424 +
425 +struct xrx200_hw {
426 + struct clk *clk;
427 + struct mii_bus *mii_bus;
428 +
429 + struct xrx200_chan chan[XRX200_MAX_DMA];
430 +
431 + struct net_device *devs[XRX200_MAX_DEV];
432 + int num_devs;
433 +
434 + int port_map[XRX200_MAX_PORT];
435 + unsigned short wan_map;
436 +
437 + spinlock_t lock;
438 +};
439 +
440 +struct xrx200_priv {
441 + struct net_device_stats stats;
442 + int id;
443 +
444 + struct xrx200_port port[XRX200_MAX_PORT];
445 + int num_port;
446 + int wan;
447 + unsigned short port_map;
448 + unsigned char mac[6];
449 +
450 + struct xrx200_hw *hw;
451 +};
452 +
453 +static __iomem void *xrx200_switch_membase;
454 +static __iomem void *xrx200_mii_membase;
455 +static __iomem void *xrx200_mdio_membase;
456 +static __iomem void *xrx200_pmac_membase;
457 +
458 +#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x))
459 +#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y))
460 +#define ltq_switch_w32_mask(x, y, z) \
461 + ltq_w32_mask(x, y, xrx200_switch_membase + (z))
462 +
463 +#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x))
464 +#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y))
465 +#define ltq_mdio_w32_mask(x, y, z) \
466 + ltq_w32_mask(x, y, xrx200_mdio_membase + (z))
467 +
468 +#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x))
469 +#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y))
470 +#define ltq_mii_w32_mask(x, y, z) \
471 + ltq_w32_mask(x, y, xrx200_mii_membase + (z))
472 +
473 +#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x))
474 +#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y))
475 +#define ltq_pmac_w32_mask(x, y, z) \
476 + ltq_w32_mask(x, y, xrx200_pmac_membase + (z))
477 +
478 +static int xrx200_open(struct net_device *dev)
479 +{
480 + struct xrx200_priv *priv = netdev_priv(dev);
481 + unsigned long flags;
482 + int i;
483 +
484 + for (i = 0; i < XRX200_MAX_DMA; i++) {
485 + if (!priv->hw->chan[i].dma.irq)
486 + continue;
487 + spin_lock_irqsave(&priv->hw->lock, flags);
488 + if (!priv->hw->chan[i].refcount) {
489 + if (XRX200_DMA_IS_RX(i))
490 + napi_enable(&priv->hw->chan[i].napi);
491 + ltq_dma_open(&priv->hw->chan[i].dma);
492 + }
493 + priv->hw->chan[i].refcount++;
494 + spin_unlock_irqrestore(&priv->hw->lock, flags);
495 + }
496 + for (i = 0; i < priv->num_port; i++)
497 + if (priv->port[i].phydev)
498 + phy_start(priv->port[i].phydev);
499 + netif_start_queue(dev);
500 +
501 + return 0;
502 +}
503 +
504 +static int xrx200_close(struct net_device *dev)
505 +{
506 + struct xrx200_priv *priv = netdev_priv(dev);
507 + unsigned long flags;
508 + int i;
509 +
510 + netif_stop_queue(dev);
511 +
512 + for (i = 0; i < priv->num_port; i++)
513 + if (priv->port[i].phydev)
514 + phy_stop(priv->port[i].phydev);
515 +
516 + for (i = 0; i < XRX200_MAX_DMA; i++) {
517 + if (!priv->hw->chan[i].dma.irq)
518 + continue;
519 + spin_lock_irqsave(&priv->hw->lock, flags);
520 + priv->hw->chan[i].refcount--;
521 + if (!priv->hw->chan[i].refcount) {
522 + if (XRX200_DMA_IS_RX(i))
523 + napi_disable(&priv->hw->chan[i].napi);
524 + ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma);
525 + }
526 + spin_unlock_irqrestore(&priv->hw->lock, flags);
527 + }
528 +
529 + return 0;
530 +}
531 +
532 +static int xrx200_alloc_skb(struct xrx200_chan *ch)
533 +{
534 +#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD)
535 + ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD);
536 + if (!ch->skb[ch->dma.desc])
537 + return -ENOMEM;
538 +
539 + skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD);
540 + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
541 + ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
542 + DMA_FROM_DEVICE);
543 + ch->dma.desc_base[ch->dma.desc].addr =
544 + CPHYSADDR(ch->skb[ch->dma.desc]->data);
545 + ch->dma.desc_base[ch->dma.desc].ctl =
546 + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
547 + XRX200_DMA_DATA_LEN;
548 + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
549 +
550 + return 0;
551 +}
552 +
553 +static void xrx200_hw_receive(struct xrx200_chan *ch, int id)
554 +{
555 + struct net_device *dev = ch->devs[id];
556 + struct xrx200_priv *priv = netdev_priv(dev);
557 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
558 + struct sk_buff *skb = ch->skb[ch->dma.desc];
559 + int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - XRX200_DMA_CRC_LEN;
560 + unsigned long flags;
561 +
562 + spin_lock_irqsave(&priv->hw->lock, flags);
563 + if (xrx200_alloc_skb(ch)) {
564 + netdev_err(dev,
565 + "failed to allocate new rx buffer, stopping DMA\n");
566 + ltq_dma_close(&ch->dma);
567 + }
568 +
569 + ch->dma.desc++;
570 + ch->dma.desc %= LTQ_DESC_NUM;
571 + spin_unlock_irqrestore(&priv->hw->lock, flags);
572 +
573 + skb_put(skb, len);
574 +#ifdef SW_ROUTING
575 + skb_pull(skb, 8);
576 +#endif
577 + skb->dev = dev;
578 + skb->protocol = eth_type_trans(skb, dev);
579 + netif_receive_skb(skb);
580 + priv->stats.rx_packets++;
581 + priv->stats.rx_bytes+=len;
582 +}
583 +
584 +static int xrx200_poll_rx(struct napi_struct *napi, int budget)
585 +{
586 + struct xrx200_chan *ch = container_of(napi,
587 + struct xrx200_chan, napi);
588 + struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
589 + int rx = 0;
590 + int complete = 0;
591 + unsigned long flags;
592 +
593 + while ((rx < budget) && !complete) {
594 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
595 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
596 +#ifdef SW_ROUTING
597 + struct sk_buff *skb = ch->skb[ch->dma.desc];
598 + u32 *special_tag = (u32*)skb->data;
599 + int port = (special_tag[1] >> SPPID_SHIFT) & SPPID_MASK;
600 + xrx200_hw_receive(ch, priv->hw->port_map[port]);
601 +#else
602 + xrx200_hw_receive(ch, 0);
603 +#endif
604 + rx++;
605 + } else {
606 + complete = 1;
607 + }
608 + }
609 + if (complete || !rx) {
610 + napi_complete(&ch->napi);
611 + spin_lock_irqsave(&priv->hw->lock, flags);
612 + ltq_dma_ack_irq(&ch->dma);
613 + spin_unlock_irqrestore(&priv->hw->lock, flags);
614 + }
615 + return rx;
616 +}
617 +
618 +static void xrx200_tx_housekeeping(unsigned long ptr)
619 +{
620 + struct xrx200_hw *hw = (struct xrx200_hw *) ptr;
621 + struct xrx200_chan *ch = &hw->chan[XRX200_DMA_TX];
622 + unsigned long flags;
623 + int i;
624 +
625 + spin_lock_irqsave(&hw->lock, flags);
626 + while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
627 + dev_kfree_skb_any(ch->skb[ch->tx_free]);
628 + ch->skb[ch->tx_free] = NULL;
629 + memset(&ch->dma.desc_base[ch->tx_free], 0,
630 + sizeof(struct ltq_dma_desc));
631 + ch->tx_free++;
632 + ch->tx_free %= LTQ_DESC_NUM;
633 + }
634 + spin_unlock_irqrestore(&hw->lock, flags);
635 +
636 + for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) {
637 + struct netdev_queue *txq =
638 + netdev_get_tx_queue(ch->devs[i], 0);
639 + if (netif_tx_queue_stopped(txq))
640 + netif_tx_start_queue(txq);
641 + }
642 +
643 + spin_lock_irqsave(&hw->lock, flags);
644 + ltq_dma_ack_irq(&ch->dma);
645 + spin_unlock_irqrestore(&hw->lock, flags);
646 +}
647 +
648 +static struct net_device_stats *xrx200_get_stats (struct net_device *dev)
649 +{
650 + struct xrx200_priv *priv = netdev_priv(dev);
651 +
652 + return &priv->stats;
653 +}
654 +
655 +static void xrx200_tx_timeout(struct net_device *dev)
656 +{
657 + struct xrx200_priv *priv = netdev_priv(dev);
658 +
659 + printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name);
660 +
661 + priv->stats.tx_errors++;
662 + netif_wake_queue(dev);
663 +}
664 +
665 +static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev)
666 +{
667 + int queue = skb_get_queue_mapping(skb);
668 + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
669 + struct xrx200_priv *priv = netdev_priv(dev);
670 + struct xrx200_chan *ch = &priv->hw->chan[XRX200_DMA_TX];
671 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
672 + unsigned long flags;
673 + u32 byte_offset;
674 + int len;
675 +#ifdef SW_ROUTING
676 + #ifdef SW_PORTMAP
677 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | PORT_MAP_SEL | PORT_MAP_EN | DPID_ENABLE;
678 + #else
679 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE;
680 + #endif
681 +#endif
682 +
683 + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
684 +
685 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
686 + netdev_err(dev, "tx ring full\n");
687 + netif_tx_stop_queue(txq);
688 + return NETDEV_TX_BUSY;
689 + }
690 +#ifdef SW_ROUTING
691 + #ifdef SW_PORTMAP
692 + special_tag |= priv->port_map << PORT_MAP_SHIFT;
693 + #else
694 + if(priv->id)
695 + special_tag |= (1 << DPID_SHIFT);
696 + #endif
697 + if(skb_headroom(skb) < 4) {
698 + struct sk_buff *tmp = skb_realloc_headroom(skb, 4);
699 + dev_kfree_skb_any(skb);
700 + skb = tmp;
701 + }
702 + skb_push(skb, 4);
703 + memcpy(skb->data, &special_tag, sizeof(u32));
704 + len += 4;
705 +#endif
706 +
707 + /* dma needs to start on a 16 byte aligned address */
708 + byte_offset = CPHYSADDR(skb->data) % 16;
709 + ch->skb[ch->dma.desc] = skb;
710 +
711 + dev->trans_start = jiffies;
712 +
713 + spin_lock_irqsave(&priv->hw->lock, flags);
714 + desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
715 + DMA_TO_DEVICE)) - byte_offset;
716 + wmb();
717 + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
718 + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
719 + ch->dma.desc++;
720 + ch->dma.desc %= LTQ_DESC_NUM;
721 + spin_unlock_irqrestore(&priv->hw->lock, flags);
722 +
723 + if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
724 + netif_tx_stop_queue(txq);
725 +
726 + priv->stats.tx_packets++;
727 + priv->stats.tx_bytes+=len;
728 +
729 + return NETDEV_TX_OK;
730 +}
731 +
732 +static irqreturn_t xrx200_dma_irq(int irq, void *priv)
733 +{
734 + struct xrx200_hw *hw = priv;
735 + int ch = irq - XRX200_DMA_IRQ;
736 +
737 + if (ch % 2)
738 + tasklet_schedule(&hw->chan[ch].tasklet);
739 + else
740 + napi_schedule(&hw->chan[ch].napi);
741 +
742 + return IRQ_HANDLED;
743 +}
744 +
745 +static int xrx200_dma_init(struct xrx200_hw *hw)
746 +{
747 + int i, err = 0;
748 +
749 + ltq_dma_init_port(DMA_PORT_ETOP);
750 +
751 + for (i = 0; i < 8 && !err; i++) {
752 + int irq = XRX200_DMA_IRQ + i;
753 + struct xrx200_chan *ch = &hw->chan[i];
754 +
755 + ch->idx = ch->dma.nr = i;
756 +
757 + if (i == XRX200_DMA_TX) {
758 + ltq_dma_alloc_tx(&ch->dma);
759 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw);
760 + } else if (i == XRX200_DMA_RX) {
761 + ltq_dma_alloc_rx(&ch->dma);
762 + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
763 + ch->dma.desc++)
764 + if (xrx200_alloc_skb(ch))
765 + err = -ENOMEM;
766 + ch->dma.desc = 0;
767 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw);
768 + } else
769 + continue;
770 +
771 + if (!err)
772 + ch->dma.irq = irq;
773 + }
774 +
775 + return err;
776 +}
777 +
778 +#ifdef SW_POLLING
779 +static void xrx200_gmac_update(struct xrx200_port *port)
780 +{
781 + u16 phyaddr = port->phydev->addr & MDIO_PHY_ADDR_MASK;
782 + u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK;
783 + u16 miirate = 0;
784 +
785 + switch (port->phydev->speed) {
786 + case SPEED_1000:
787 + phyaddr |= MDIO_PHY_SPEED_G1;
788 + miirate = MII_CFG_RATE_M125;
789 + break;
790 +
791 + case SPEED_100:
792 + phyaddr |= MDIO_PHY_SPEED_M100;
793 + switch (miimode) {
794 + case MII_CFG_MODE_RMIIM:
795 + case MII_CFG_MODE_RMIIP:
796 + miirate = MII_CFG_RATE_M50;
797 + break;
798 + default:
799 + miirate = MII_CFG_RATE_M25;
800 + break;
801 + }
802 + break;
803 +
804 + default:
805 + phyaddr |= MDIO_PHY_SPEED_M10;
806 + miirate = MII_CFG_RATE_M2P5;
807 + break;
808 + }
809 +
810 + if (port->phydev->link)
811 + phyaddr |= MDIO_PHY_LINK_UP;
812 + else
813 + phyaddr |= MDIO_PHY_LINK_DOWN;
814 +
815 + if (port->phydev->duplex == DUPLEX_FULL)
816 + phyaddr |= MDIO_PHY_FDUP_EN;
817 + else
818 + phyaddr |= MDIO_PHY_FDUP_DIS;
819 +
820 + ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num));
821 + ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num));
822 + udelay(1);
823 +}
824 +#else
825 +static void xrx200_gmac_update(struct xrx200_port *port)
826 +{
827 +
828 +}
829 +#endif
830 +
831 +static void xrx200_mdio_link(struct net_device *dev)
832 +{
833 + struct xrx200_priv *priv = netdev_priv(dev);
834 + int i;
835 +
836 + for (i = 0; i < priv->num_port; i++) {
837 + if (!priv->port[i].phydev)
838 + continue;
839 +
840 + if (priv->port[i].link != priv->port[i].phydev->link) {
841 + xrx200_gmac_update(&priv->port[i]);
842 + priv->port[i].link = priv->port[i].phydev->link;
843 + netdev_info(dev, "port %d %s link\n",
844 + priv->port[i].num,
845 + (priv->port[i].link)?("got"):("lost"));
846 + }
847 + }
848 +}
849 +
850 +static inline int xrx200_mdio_poll(struct mii_bus *bus)
851 +{
852 + unsigned cnt = 10000;
853 +
854 + while (likely(cnt--)) {
855 + unsigned ctrl = ltq_mdio_r32(MDIO_CTRL);
856 + if ((ctrl & MDIO_BUSY) == 0)
857 + return 0;
858 + }
859 +
860 + return 1;
861 +}
862 +
863 +static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
864 +{
865 + if (xrx200_mdio_poll(bus))
866 + return 1;
867 +
868 + ltq_mdio_w32(val, MDIO_WRITE);
869 + ltq_mdio_w32(MDIO_BUSY | MDIO_WR |
870 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
871 + (reg & MDIO_MASK),
872 + MDIO_CTRL);
873 +
874 + return 0;
875 +}
876 +
877 +static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg)
878 +{
879 + if (xrx200_mdio_poll(bus))
880 + return -1;
881 +
882 + ltq_mdio_w32(MDIO_BUSY | MDIO_RD |
883 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
884 + (reg & MDIO_MASK),
885 + MDIO_CTRL);
886 +
887 + if (xrx200_mdio_poll(bus))
888 + return -1;
889 +
890 + return ltq_mdio_r32(MDIO_READ);
891 +}
892 +
893 +static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port)
894 +{
895 + struct xrx200_priv *priv = netdev_priv(dev);
896 + struct phy_device *phydev = NULL;
897 + unsigned val;
898 +
899 + phydev = priv->hw->mii_bus->phy_map[port->phy_addr];
900 +
901 + if (!phydev) {
902 + netdev_err(dev, "no PHY found\n");
903 + return -ENODEV;
904 + }
905 +
906 + phydev = phy_connect(dev, dev_name(&phydev->dev), &xrx200_mdio_link,
907 + port->phy_if);
908 +
909 + if (IS_ERR(phydev)) {
910 + netdev_err(dev, "Could not attach to PHY\n");
911 + return PTR_ERR(phydev);
912 + }
913 +
914 + phydev->supported &= (SUPPORTED_10baseT_Half
915 + | SUPPORTED_10baseT_Full
916 + | SUPPORTED_100baseT_Half
917 + | SUPPORTED_100baseT_Full
918 + | SUPPORTED_1000baseT_Half
919 + | SUPPORTED_1000baseT_Full
920 + | SUPPORTED_Autoneg
921 + | SUPPORTED_MII
922 + | SUPPORTED_TP);
923 + phydev->advertising = phydev->supported;
924 + port->phydev = phydev;
925 +
926 + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
927 + dev->name, phydev->drv->name,
928 + dev_name(&phydev->dev), phydev->irq);
929 +
930 +#ifdef SW_POLLING
931 + phy_read_status(phydev);
932 +
933 + val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
934 + val |= ADVERTIZE_MPD;
935 + xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
936 + xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040);
937 +
938 + phy_start_aneg(phydev);
939 +#endif
940 + return 0;
941 +}
942 +
943 +static void xrx200_port_config(struct xrx200_priv *priv,
944 + const struct xrx200_port *port)
945 +{
946 + u16 miimode = 0;
947 +
948 + switch (port->num) {
949 + case 0: /* xMII0 */
950 + case 1: /* xMII1 */
951 + switch (port->phy_if) {
952 + case PHY_INTERFACE_MODE_MII:
953 + if (port->flags & XRX200_PORT_TYPE_PHY)
954 + /* MII MAC mode, connected to external PHY */
955 + miimode = MII_CFG_MODE_MIIM;
956 + else
957 + /* MII PHY mode, connected to external MAC */
958 + miimode = MII_CFG_MODE_MIIP;
959 + break;
960 + case PHY_INTERFACE_MODE_RMII:
961 + if (port->flags & XRX200_PORT_TYPE_PHY)
962 + /* RMII MAC mode, connected to external PHY */
963 + miimode = MII_CFG_MODE_RMIIM;
964 + else
965 + /* RMII PHY mode, connected to external MAC */
966 + miimode = MII_CFG_MODE_RMIIP;
967 + break;
968 + case PHY_INTERFACE_MODE_RGMII:
969 + /* RGMII MAC mode, connected to external PHY */
970 + miimode = MII_CFG_MODE_RGMII;
971 + break;
972 + default:
973 + break;
974 + }
975 + break;
976 + case 2: /* internal GPHY0 */
977 + case 3: /* internal GPHY0 */
978 + case 4: /* internal GPHY1 */
979 + switch (port->phy_if) {
980 + case PHY_INTERFACE_MODE_MII:
981 + case PHY_INTERFACE_MODE_GMII:
982 + /* MII MAC mode, connected to internal GPHY */
983 + miimode = MII_CFG_MODE_MIIM;
984 + break;
985 + default:
986 + break;
987 + }
988 + break;
989 + case 5: /* internal GPHY1 or xMII2 */
990 + switch (port->phy_if) {
991 + case PHY_INTERFACE_MODE_MII:
992 + /* MII MAC mode, connected to internal GPHY */
993 + miimode = MII_CFG_MODE_MIIM;
994 + break;
995 + case PHY_INTERFACE_MODE_RGMII:
996 + /* RGMII MAC mode, connected to external PHY */
997 + miimode = MII_CFG_MODE_RGMII;
998 + break;
999 + default:
1000 + break;
1001 + }
1002 + break;
1003 + default:
1004 + break;
1005 + }
1006 +
1007 + ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN,
1008 + MII_CFG(port->num));
1009 +}
1010 +
1011 +static int xrx200_init(struct net_device *dev)
1012 +{
1013 + struct xrx200_priv *priv = netdev_priv(dev);
1014 + struct sockaddr mac;
1015 + int err, i;
1016 +
1017 +#ifndef SW_POLLING
1018 + unsigned int reg = 0;
1019 +
1020 + /* enable auto polling */
1021 + for (i = 0; i < priv->num_port; i++)
1022 + reg |= BIT(priv->port[i].num);
1023 + ltq_mdio_w32(reg, MDIO_CLK_CFG0);
1024 + ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1);
1025 +#endif
1026 +
1027 + /* setup each port */
1028 + for (i = 0; i < priv->num_port; i++)
1029 + xrx200_port_config(priv, &priv->port[i]);
1030 +
1031 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
1032 + if (!is_valid_ether_addr(mac.sa_data)) {
1033 + pr_warn("net-xrx200: invalid MAC, using random\n");
1034 + eth_random_addr(mac.sa_data);
1035 + dev->addr_assign_type |= NET_ADDR_RANDOM;
1036 + }
1037 +
1038 + err = eth_mac_addr(dev, &mac);
1039 + if (err)
1040 + goto err_netdev;
1041 +
1042 + for (i = 0; i < priv->num_port; i++)
1043 + if (xrx200_mdio_probe(dev, &priv->port[i]))
1044 + pr_warn("xrx200-mdio: probing phy of port %d failed\n",
1045 + priv->port[i].num);
1046 +
1047 + return 0;
1048 +
1049 +err_netdev:
1050 + unregister_netdev(dev);
1051 + free_netdev(dev);
1052 + return err;
1053 +}
1054 +
1055 +static void xrx200_pci_microcode(void)
1056 +{
1057 + int i;
1058 +
1059 + ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK,
1060 + PCE_TBL_CFG_ADWR, PCE_TBL_CTRL);
1061 + ltq_switch_w32(0, PCE_TBL_MASK);
1062 +
1063 + for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) {
1064 + ltq_switch_w32(i, PCE_TBL_ADDR);
1065 + ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0));
1066 + ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1));
1067 + ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2));
1068 + ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3));
1069 +
1070 + // start the table access:
1071 + ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL);
1072 + while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY);
1073 + }
1074 +
1075 + /* tell the switch that the microcode is loaded */
1076 + ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0));
1077 +}
1078 +
1079 +static void xrx200_hw_init(struct xrx200_hw *hw)
1080 +{
1081 + int i;
1082 +
1083 + /* enable clock gate */
1084 + clk_enable(hw->clk);
1085 +
1086 + ltq_switch_w32(1, 0);
1087 + mdelay(100);
1088 + ltq_switch_w32(0, 0);
1089 + /*
1090 + * TODO: we should really disbale all phys/miis here and explicitly
1091 + * enable them in the device secific init function
1092 + */
1093 +
1094 + /* disable port fetch/store dma */
1095 + for (i = 0; i < 7; i++ ) {
1096 + ltq_switch_w32(0, FDMA_PCTRLx(i));
1097 + ltq_switch_w32(0, SDMA_PCTRLx(i));
1098 + }
1099 +
1100 + /* enable Switch */
1101 + ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB);
1102 +
1103 + /* load the pce microcode */
1104 + xrx200_pci_microcode();
1105 +
1106 + /* Default unknown Broadcat/Multicast/Unicast port maps */
1107 + ltq_switch_w32(0x7f, PCE_PMAP1);
1108 + ltq_switch_w32(0x7f, PCE_PMAP2);
1109 + ltq_switch_w32(0x7f, PCE_PMAP3);
1110 +
1111 + /* RMON Counter Enable for all physical ports */
1112 + for (i = 0; i < 7; i++)
1113 + ltq_switch_w32(0x1, BM_PCFG(i));
1114 +
1115 + /* disable auto polling */
1116 + ltq_mdio_w32(0x0, MDIO_CLK_CFG0);
1117 +
1118 + /* enable port statistic counters */
1119 + for (i = 0; i < 7; i++)
1120 + ltq_switch_w32(0x1, BM_PCFGx(i));
1121 +
1122 + /* set IPG to 12 */
1123 + ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG);
1124 +
1125 +#ifdef SW_ROUTING
1126 + /* enable status header, enable CRC */
1127 + ltq_pmac_w32_mask(0,
1128 + PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC,
1129 + PMAC_HD_CTL);
1130 +#else
1131 + /* disable status header, enable CRC */
1132 + ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS,
1133 + PMAC_HD_CTL_AC,
1134 + PMAC_HD_CTL);
1135 +#endif
1136 +
1137 + /* enable port fetch/store dma */
1138 + for (i = 0; i < 7; i++ ) {
1139 + ltq_switch_w32_mask(0, 0x01, FDMA_PCTRLx(i));
1140 + ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i));
1141 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0));
1142 + }
1143 +
1144 + /* enable special tag insertion on cpu port */
1145 + ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6));
1146 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0));
1147 + ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2));
1148 + ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG);
1149 +}
1150 +
1151 +static void xrx200_hw_cleanup(struct xrx200_hw *hw)
1152 +{
1153 + int i;
1154 +
1155 + /* disable the switch */
1156 + ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB);
1157 +
1158 + /* free the channels and IRQs */
1159 + for (i = 0; i < 2; i++) {
1160 + ltq_dma_free(&hw->chan[i].dma);
1161 + if (hw->chan[i].dma.irq)
1162 + free_irq(hw->chan[i].dma.irq, hw);
1163 + }
1164 +
1165 + /* free the allocated RX ring */
1166 + for (i = 0; i < LTQ_DESC_NUM; i++)
1167 + dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]);
1168 +
1169 + /* clear the mdio bus */
1170 + mdiobus_unregister(hw->mii_bus);
1171 + mdiobus_free(hw->mii_bus);
1172 +
1173 + /* release the clock */
1174 + clk_disable(hw->clk);
1175 + clk_put(hw->clk);
1176 +}
1177 +
1178 +static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np)
1179 +{
1180 + hw->mii_bus = mdiobus_alloc();
1181 + if (!hw->mii_bus)
1182 + return -ENOMEM;
1183 +
1184 + hw->mii_bus->read = xrx200_mdio_rd;
1185 + hw->mii_bus->write = xrx200_mdio_wr;
1186 + hw->mii_bus->name = "lantiq,xrx200-mdio";
1187 + snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
1188 +
1189 + if (of_mdiobus_register(hw->mii_bus, np)) {
1190 + mdiobus_free(hw->mii_bus);
1191 + return -ENXIO;
1192 + }
1193 +
1194 + return 0;
1195 +}
1196 +
1197 +static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port)
1198 +{
1199 + const __be32 *addr, *id = of_get_property(port, "reg", NULL);
1200 + struct xrx200_port *p = &priv->port[priv->num_port];
1201 +
1202 + if (!id)
1203 + return;
1204 +
1205 + memset(p, 0, sizeof(struct xrx200_port));
1206 + p->phy_node = of_parse_phandle(port, "phy-handle", 0);
1207 + addr = of_get_property(p->phy_node, "reg", NULL);
1208 + if (!addr)
1209 + return;
1210 +
1211 + p->num = *id;
1212 + p->phy_addr = *addr;
1213 + p->phy_if = of_get_phy_mode(port);
1214 + if (p->phy_addr > 0x10)
1215 + p->flags = XRX200_PORT_TYPE_MAC;
1216 + else
1217 + p->flags = XRX200_PORT_TYPE_PHY;
1218 + priv->num_port++;
1219 +
1220 + p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags);
1221 + if (gpio_is_valid(p->gpio))
1222 + if (!gpio_request(p->gpio, "phy-reset")) {
1223 + gpio_direction_output(p->gpio,
1224 + (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0));
1225 + udelay(100);
1226 + gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
1227 + }
1228 + /* is this port a wan port ? */
1229 + if (priv->wan)
1230 + priv->hw->wan_map |= BIT(p->num);
1231 +
1232 + priv->port_map |= BIT(p->num);
1233 +
1234 + /* store the port id in the hw struct so we can map ports -> devices */
1235 + priv->hw->port_map[p->num] = priv->hw->num_devs;
1236 +}
1237 +
1238 +static const struct net_device_ops xrx200_netdev_ops = {
1239 + .ndo_init = xrx200_init,
1240 + .ndo_open = xrx200_open,
1241 + .ndo_stop = xrx200_close,
1242 + .ndo_start_xmit = xrx200_start_xmit,
1243 + .ndo_set_mac_address = eth_mac_addr,
1244 + .ndo_validate_addr = eth_validate_addr,
1245 + .ndo_change_mtu = eth_change_mtu,
1246 + .ndo_get_stats = xrx200_get_stats,
1247 + .ndo_tx_timeout = xrx200_tx_timeout,
1248 +};
1249 +
1250 +static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface)
1251 +{
1252 + struct xrx200_priv *priv;
1253 + struct device_node *port;
1254 + const __be32 *wan;
1255 +
1256 + /* alloc the network device */
1257 + hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv));
1258 + if (!hw->devs[hw->num_devs])
1259 + return;
1260 +
1261 + /* setup the network device */
1262 + strcpy(hw->devs[hw->num_devs]->name, "eth%d");
1263 + hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops;
1264 + hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT;
1265 + hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM;
1266 +
1267 + /* setup our private data */
1268 + priv = netdev_priv(hw->devs[hw->num_devs]);
1269 + priv->hw = hw;
1270 + of_get_mac_address_mtd(iface, priv->mac);
1271 + priv->id = hw->num_devs;
1272 +
1273 + /* is this the wan interface ? */
1274 + wan = of_get_property(iface, "lantiq,wan", NULL);
1275 + if (wan && (*wan == 1))
1276 + priv->wan = 1;
1277 +
1278 + /* load the ports that are part of the interface */
1279 + for_each_child_of_node(iface, port)
1280 + if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port"))
1281 + xrx200_of_port(priv, port);
1282 +
1283 + /* register the actual device */
1284 + if (!register_netdev(hw->devs[hw->num_devs]))
1285 + hw->num_devs++;
1286 +}
1287 +
1288 +static struct xrx200_hw xrx200_hw;
1289 +
1290 +static int xrx200_probe(struct platform_device *pdev)
1291 +{
1292 + struct resource *res[4];
1293 + struct device_node *mdio_np, *iface_np;
1294 + int i;
1295 +
1296 + /* load the memory ranges */
1297 + for (i = 0; i < 4; i++) {
1298 + res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
1299 + if (!res[i]) {
1300 + dev_err(&pdev->dev, "failed to get resources\n");
1301 + return -ENOENT;
1302 + }
1303 + }
1304 + xrx200_switch_membase = devm_request_and_ioremap(&pdev->dev, res[0]);
1305 + xrx200_mdio_membase = devm_request_and_ioremap(&pdev->dev, res[1]);
1306 + xrx200_mii_membase = devm_request_and_ioremap(&pdev->dev, res[2]);
1307 + xrx200_pmac_membase = devm_request_and_ioremap(&pdev->dev, res[3]);
1308 + if (!xrx200_switch_membase || !xrx200_mdio_membase ||
1309 + !xrx200_mii_membase || !xrx200_pmac_membase) {
1310 + dev_err(&pdev->dev, "failed to request and remap io ranges \n");
1311 + return -ENOMEM;
1312 + }
1313 +
1314 + /* get the clock */
1315 + xrx200_hw.clk = clk_get(&pdev->dev, NULL);
1316 + if (IS_ERR(xrx200_hw.clk)) {
1317 + dev_err(&pdev->dev, "failed to get clock\n");
1318 + return PTR_ERR(xrx200_hw.clk);
1319 + }
1320 +
1321 + /* bring up the dma engine and IP core */
1322 + spin_lock_init(&xrx200_hw.lock);
1323 + xrx200_dma_init(&xrx200_hw);
1324 + xrx200_hw_init(&xrx200_hw);
1325 + tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw);
1326 +
1327 + /* bring up the mdio bus */
1328 + mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL,
1329 + "lantiq,xrx200-mdio");
1330 + if (mdio_np)
1331 + if (xrx200_of_mdio(&xrx200_hw, mdio_np))
1332 + dev_err(&pdev->dev, "mdio probe failed\n");
1333 +
1334 + /* load the interfaces */
1335 + for_each_child_of_node(pdev->dev.of_node, iface_np)
1336 + if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) {
1337 + if (xrx200_hw.num_devs < XRX200_MAX_DEV)
1338 + xrx200_of_iface(&xrx200_hw, iface_np);
1339 + else
1340 + dev_err(&pdev->dev,
1341 + "only %d interfaces allowed\n",
1342 + XRX200_MAX_DEV);
1343 + }
1344 +
1345 + if (!xrx200_hw.num_devs) {
1346 + xrx200_hw_cleanup(&xrx200_hw);
1347 + dev_err(&pdev->dev, "failed to load interfaces\n");
1348 + return -ENOENT;
1349 + }
1350 +
1351 + /* set wan port mask */
1352 + ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN);
1353 +
1354 + for (i = 0; i < xrx200_hw.num_devs; i++) {
1355 + xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i];
1356 + xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i];
1357 + }
1358 +
1359 + /* setup NAPI */
1360 + init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev);
1361 + netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev,
1362 + &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32);
1363 +
1364 + platform_set_drvdata(pdev, &xrx200_hw);
1365 +
1366 + return 0;
1367 +}
1368 +
1369 +static int xrx200_remove(struct platform_device *pdev)
1370 +{
1371 + struct net_device *dev = platform_get_drvdata(pdev);
1372 + struct xrx200_priv *priv;
1373 +
1374 + if (!dev)
1375 + return 0;
1376 +
1377 + priv = netdev_priv(dev);
1378 +
1379 + /* free stack related instances */
1380 + netif_stop_queue(dev);
1381 + netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi);
1382 +
1383 + /* shut down hardware */
1384 + xrx200_hw_cleanup(&xrx200_hw);
1385 +
1386 + /* remove the actual device */
1387 + unregister_netdev(dev);
1388 + free_netdev(dev);
1389 +
1390 + return 0;
1391 +}
1392 +
1393 +static const struct of_device_id xrx200_match[] = {
1394 + { .compatible = "lantiq,xrx200-net" },
1395 + {},
1396 +};
1397 +MODULE_DEVICE_TABLE(of, xrx200_match);
1398 +
1399 +static struct platform_driver xrx200_driver = {
1400 + .probe = xrx200_probe,
1401 + .remove = xrx200_remove,
1402 + .driver = {
1403 + .name = "lantiq,xrx200-net",
1404 + .of_match_table = xrx200_match,
1405 + .owner = THIS_MODULE,
1406 + },
1407 +};
1408 +
1409 +module_platform_driver(xrx200_driver);
1410 +
1411 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1412 +MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
1413 +MODULE_LICENSE("GPL");
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