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base-files: define yes/no as valid boolean options
[openwrt/staging/lynxis/omap.git] / target / linux / mvebu / patches-3.10 / 0009-pci-PCIe-driver-for-Marvell-Armada-370-XP-systems.patch
1 From cf7b5cb15e46b5357c60188b75b213a7f0b5fd32 Mon Sep 17 00:00:00 2001
2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 Date: Fri, 18 Jan 2013 17:42:58 +0100
4 Subject: [PATCH 009/203] pci: PCIe driver for Marvell Armada 370/XP systems
5
6 This driver implements the support for the PCIe interfaces on the
7 Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
8 cover earlier families of Marvell SoCs, such as Dove, Orion and
9 Kirkwood.
10
11 The driver implements the hw_pci operations needed by the core ARM PCI
12 code to setup PCI devices and get their corresponding IRQs, and the
13 pci_ops operations that are used by the PCI core to read/write the
14 configuration space of PCI devices.
15
16 Since the PCIe interfaces of Marvell SoCs are completely separate and
17 not linked together in a bus, this driver sets up an emulated PCI host
18 bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
19 interface.
20
21 In addition, this driver enumerates the different PCIe slots, and for
22 those having a device plugged in, it sets up the necessary address
23 decoding windows, using the mvebu-mbus driver.
24
25 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
26 Acked-by: Bjorn Helgaas <bhelgaas@google.com>
27 ---
28 .../devicetree/bindings/pci/mvebu-pci.txt | 220 ++++++
29 drivers/pci/Kconfig | 2 +
30 drivers/pci/Makefile | 3 +
31 drivers/pci/host/Kconfig | 8 +
32 drivers/pci/host/Makefile | 1 +
33 drivers/pci/host/pci-mvebu.c | 880 +++++++++++++++++++++
34 6 files changed, 1114 insertions(+)
35 create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
36 create mode 100644 drivers/pci/host/Kconfig
37 create mode 100644 drivers/pci/host/Makefile
38 create mode 100644 drivers/pci/host/pci-mvebu.c
39
40 --- /dev/null
41 +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
42 @@ -0,0 +1,220 @@
43 +* Marvell EBU PCIe interfaces
44 +
45 +Mandatory properties:
46 +- compatible: one of the following values:
47 + marvell,armada-370-pcie
48 + marvell,armada-xp-pcie
49 +- #address-cells, set to <3>
50 +- #size-cells, set to <2>
51 +- #interrupt-cells, set to <1>
52 +- bus-range: PCI bus numbers covered
53 +- device_type, set to "pci"
54 +- ranges: ranges for the PCI memory and I/O regions, as well as the
55 + MMIO registers to control the PCIe interfaces.
56 +
57 +In addition, the Device Tree node must have sub-nodes describing each
58 +PCIe interface, having the following mandatory properties:
59 +- reg: used only for interrupt mapping, so only the first four bytes
60 + are used to refer to the correct bus number and device number.
61 +- assigned-addresses: reference to the MMIO registers used to control
62 + this PCIe interface.
63 +- clocks: the clock associated to this PCIe interface
64 +- marvell,pcie-port: the physical PCIe port number
65 +- status: either "disabled" or "okay"
66 +- device_type, set to "pci"
67 +- #address-cells, set to <3>
68 +- #size-cells, set to <2>
69 +- #interrupt-cells, set to <1>
70 +- ranges, empty property.
71 +- interrupt-map-mask and interrupt-map, standard PCI properties to
72 + define the mapping of the PCIe interface to interrupt numbers.
73 +
74 +and the following optional properties:
75 +- marvell,pcie-lane: the physical PCIe lane number, for ports having
76 + multiple lanes. If this property is not found, we assume that the
77 + value is 0.
78 +
79 +Example:
80 +
81 +pcie-controller {
82 + compatible = "marvell,armada-xp-pcie";
83 + status = "disabled";
84 + device_type = "pci";
85 +
86 + #address-cells = <3>;
87 + #size-cells = <2>;
88 +
89 + bus-range = <0x00 0xff>;
90 +
91 + ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
92 + 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
93 + 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
94 + 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
95 + 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
96 + 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
97 + 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
98 + 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
99 + 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
100 + 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
101 + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
102 + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
103 +
104 + pcie@1,0 {
105 + device_type = "pci";
106 + assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
107 + reg = <0x0800 0 0 0 0>;
108 + #address-cells = <3>;
109 + #size-cells = <2>;
110 + #interrupt-cells = <1>;
111 + ranges;
112 + interrupt-map-mask = <0 0 0 0>;
113 + interrupt-map = <0 0 0 0 &mpic 58>;
114 + marvell,pcie-port = <0>;
115 + marvell,pcie-lane = <0>;
116 + clocks = <&gateclk 5>;
117 + status = "disabled";
118 + };
119 +
120 + pcie@2,0 {
121 + device_type = "pci";
122 + assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
123 + reg = <0x1000 0 0 0 0>;
124 + #address-cells = <3>;
125 + #size-cells = <2>;
126 + #interrupt-cells = <1>;
127 + ranges;
128 + interrupt-map-mask = <0 0 0 0>;
129 + interrupt-map = <0 0 0 0 &mpic 59>;
130 + marvell,pcie-port = <0>;
131 + marvell,pcie-lane = <1>;
132 + clocks = <&gateclk 6>;
133 + status = "disabled";
134 + };
135 +
136 + pcie@3,0 {
137 + device_type = "pci";
138 + assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
139 + reg = <0x1800 0 0 0 0>;
140 + #address-cells = <3>;
141 + #size-cells = <2>;
142 + #interrupt-cells = <1>;
143 + ranges;
144 + interrupt-map-mask = <0 0 0 0>;
145 + interrupt-map = <0 0 0 0 &mpic 60>;
146 + marvell,pcie-port = <0>;
147 + marvell,pcie-lane = <2>;
148 + clocks = <&gateclk 7>;
149 + status = "disabled";
150 + };
151 +
152 + pcie@4,0 {
153 + device_type = "pci";
154 + assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
155 + reg = <0x2000 0 0 0 0>;
156 + #address-cells = <3>;
157 + #size-cells = <2>;
158 + #interrupt-cells = <1>;
159 + ranges;
160 + interrupt-map-mask = <0 0 0 0>;
161 + interrupt-map = <0 0 0 0 &mpic 61>;
162 + marvell,pcie-port = <0>;
163 + marvell,pcie-lane = <3>;
164 + clocks = <&gateclk 8>;
165 + status = "disabled";
166 + };
167 +
168 + pcie@5,0 {
169 + device_type = "pci";
170 + assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
171 + reg = <0x2800 0 0 0 0>;
172 + #address-cells = <3>;
173 + #size-cells = <2>;
174 + #interrupt-cells = <1>;
175 + ranges;
176 + interrupt-map-mask = <0 0 0 0>;
177 + interrupt-map = <0 0 0 0 &mpic 62>;
178 + marvell,pcie-port = <1>;
179 + marvell,pcie-lane = <0>;
180 + clocks = <&gateclk 9>;
181 + status = "disabled";
182 + };
183 +
184 + pcie@6,0 {
185 + device_type = "pci";
186 + assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
187 + reg = <0x3000 0 0 0 0>;
188 + #address-cells = <3>;
189 + #size-cells = <2>;
190 + #interrupt-cells = <1>;
191 + ranges;
192 + interrupt-map-mask = <0 0 0 0>;
193 + interrupt-map = <0 0 0 0 &mpic 63>;
194 + marvell,pcie-port = <1>;
195 + marvell,pcie-lane = <1>;
196 + clocks = <&gateclk 10>;
197 + status = "disabled";
198 + };
199 +
200 + pcie@7,0 {
201 + device_type = "pci";
202 + assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
203 + reg = <0x3800 0 0 0 0>;
204 + #address-cells = <3>;
205 + #size-cells = <2>;
206 + #interrupt-cells = <1>;
207 + ranges;
208 + interrupt-map-mask = <0 0 0 0>;
209 + interrupt-map = <0 0 0 0 &mpic 64>;
210 + marvell,pcie-port = <1>;
211 + marvell,pcie-lane = <2>;
212 + clocks = <&gateclk 11>;
213 + status = "disabled";
214 + };
215 +
216 + pcie@8,0 {
217 + device_type = "pci";
218 + assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
219 + reg = <0x4000 0 0 0 0>;
220 + #address-cells = <3>;
221 + #size-cells = <2>;
222 + #interrupt-cells = <1>;
223 + ranges;
224 + interrupt-map-mask = <0 0 0 0>;
225 + interrupt-map = <0 0 0 0 &mpic 65>;
226 + marvell,pcie-port = <1>;
227 + marvell,pcie-lane = <3>;
228 + clocks = <&gateclk 12>;
229 + status = "disabled";
230 + };
231 + pcie@9,0 {
232 + device_type = "pci";
233 + assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
234 + reg = <0x4800 0 0 0 0>;
235 + #address-cells = <3>;
236 + #size-cells = <2>;
237 + #interrupt-cells = <1>;
238 + ranges;
239 + interrupt-map-mask = <0 0 0 0>;
240 + interrupt-map = <0 0 0 0 &mpic 99>;
241 + marvell,pcie-port = <2>;
242 + marvell,pcie-lane = <0>;
243 + clocks = <&gateclk 26>;
244 + status = "disabled";
245 + };
246 +
247 + pcie@10,0 {
248 + device_type = "pci";
249 + assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
250 + reg = <0x5000 0 0 0 0>;
251 + #address-cells = <3>;
252 + #size-cells = <2>;
253 + #interrupt-cells = <1>;
254 + ranges;
255 + interrupt-map-mask = <0 0 0 0>;
256 + interrupt-map = <0 0 0 0 &mpic 103>;
257 + marvell,pcie-port = <3>;
258 + marvell,pcie-lane = <0>;
259 + clocks = <&gateclk 27>;
260 + status = "disabled";
261 + };
262 +};
263 --- a/drivers/pci/Kconfig
264 +++ b/drivers/pci/Kconfig
265 @@ -125,3 +125,5 @@ config PCI_IOAPIC
266 config PCI_LABEL
267 def_bool y if (DMI || ACPI)
268 select NLS
269 +
270 +source "drivers/pci/host/Kconfig"
271 --- a/drivers/pci/Makefile
272 +++ b/drivers/pci/Makefile
273 @@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen
274 obj-$(CONFIG_OF) += of.o
275
276 ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
277 +
278 +# PCI host controller drivers
279 +obj-y += host/
280 --- /dev/null
281 +++ b/drivers/pci/host/Kconfig
282 @@ -0,0 +1,8 @@
283 +menu "PCI host controller drivers"
284 + depends on PCI
285 +
286 +config PCI_MVEBU
287 + bool "Marvell EBU PCIe controller"
288 + depends on ARCH_MVEBU
289 +
290 +endmenu
291 --- /dev/null
292 +++ b/drivers/pci/host/Makefile
293 @@ -0,0 +1 @@
294 +obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
295 --- /dev/null
296 +++ b/drivers/pci/host/pci-mvebu.c
297 @@ -0,0 +1,880 @@
298 +/*
299 + * PCIe driver for Marvell Armada 370 and Armada XP SoCs
300 + *
301 + * This file is licensed under the terms of the GNU General Public
302 + * License version 2. This program is licensed "as is" without any
303 + * warranty of any kind, whether express or implied.
304 + */
305 +
306 +#include <linux/kernel.h>
307 +#include <linux/pci.h>
308 +#include <linux/clk.h>
309 +#include <linux/module.h>
310 +#include <linux/mbus.h>
311 +#include <linux/slab.h>
312 +#include <linux/platform_device.h>
313 +#include <linux/of_address.h>
314 +#include <linux/of_pci.h>
315 +#include <linux/of_irq.h>
316 +#include <linux/of_platform.h>
317 +
318 +/*
319 + * PCIe unit register offsets.
320 + */
321 +#define PCIE_DEV_ID_OFF 0x0000
322 +#define PCIE_CMD_OFF 0x0004
323 +#define PCIE_DEV_REV_OFF 0x0008
324 +#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
325 +#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
326 +#define PCIE_HEADER_LOG_4_OFF 0x0128
327 +#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
328 +#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
329 +#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
330 +#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
331 +#define PCIE_WIN5_CTRL_OFF 0x1880
332 +#define PCIE_WIN5_BASE_OFF 0x1884
333 +#define PCIE_WIN5_REMAP_OFF 0x188c
334 +#define PCIE_CONF_ADDR_OFF 0x18f8
335 +#define PCIE_CONF_ADDR_EN 0x80000000
336 +#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
337 +#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
338 +#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
339 +#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
340 +#define PCIE_CONF_ADDR(bus, devfn, where) \
341 + (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
342 + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
343 + PCIE_CONF_ADDR_EN)
344 +#define PCIE_CONF_DATA_OFF 0x18fc
345 +#define PCIE_MASK_OFF 0x1910
346 +#define PCIE_MASK_ENABLE_INTS 0x0f000000
347 +#define PCIE_CTRL_OFF 0x1a00
348 +#define PCIE_CTRL_X1_MODE 0x0001
349 +#define PCIE_STAT_OFF 0x1a04
350 +#define PCIE_STAT_BUS 0xff00
351 +#define PCIE_STAT_LINK_DOWN BIT(0)
352 +#define PCIE_DEBUG_CTRL 0x1a60
353 +#define PCIE_DEBUG_SOFT_RESET BIT(20)
354 +
355 +/*
356 + * This product ID is registered by Marvell, and used when the Marvell
357 + * SoC is not the root complex, but an endpoint on the PCIe bus. It is
358 + * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
359 + * bridge.
360 + */
361 +#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
362 +
363 +/* PCI configuration space of a PCI-to-PCI bridge */
364 +struct mvebu_sw_pci_bridge {
365 + u16 vendor;
366 + u16 device;
367 + u16 command;
368 + u16 status;
369 + u16 class;
370 + u8 interface;
371 + u8 revision;
372 + u8 bist;
373 + u8 header_type;
374 + u8 latency_timer;
375 + u8 cache_line_size;
376 + u32 bar[2];
377 + u8 primary_bus;
378 + u8 secondary_bus;
379 + u8 subordinate_bus;
380 + u8 secondary_latency_timer;
381 + u8 iobase;
382 + u8 iolimit;
383 + u16 secondary_status;
384 + u16 membase;
385 + u16 memlimit;
386 + u16 prefmembase;
387 + u16 prefmemlimit;
388 + u32 prefbaseupper;
389 + u32 preflimitupper;
390 + u16 iobaseupper;
391 + u16 iolimitupper;
392 + u8 cappointer;
393 + u8 reserved1;
394 + u16 reserved2;
395 + u32 romaddr;
396 + u8 intline;
397 + u8 intpin;
398 + u16 bridgectrl;
399 +};
400 +
401 +struct mvebu_pcie_port;
402 +
403 +/* Structure representing all PCIe interfaces */
404 +struct mvebu_pcie {
405 + struct platform_device *pdev;
406 + struct mvebu_pcie_port *ports;
407 + struct resource io;
408 + struct resource realio;
409 + struct resource mem;
410 + struct resource busn;
411 + int nports;
412 +};
413 +
414 +/* Structure representing one PCIe interface */
415 +struct mvebu_pcie_port {
416 + char *name;
417 + void __iomem *base;
418 + spinlock_t conf_lock;
419 + int haslink;
420 + u32 port;
421 + u32 lane;
422 + int devfn;
423 + struct clk *clk;
424 + struct mvebu_sw_pci_bridge bridge;
425 + struct device_node *dn;
426 + struct mvebu_pcie *pcie;
427 + phys_addr_t memwin_base;
428 + size_t memwin_size;
429 + phys_addr_t iowin_base;
430 + size_t iowin_size;
431 +};
432 +
433 +static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
434 +{
435 + return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
436 +}
437 +
438 +static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
439 +{
440 + u32 stat;
441 +
442 + stat = readl(port->base + PCIE_STAT_OFF);
443 + stat &= ~PCIE_STAT_BUS;
444 + stat |= nr << 8;
445 + writel(stat, port->base + PCIE_STAT_OFF);
446 +}
447 +
448 +/*
449 + * Setup PCIE BARs and Address Decode Wins:
450 + * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
451 + * WIN[0-3] -> DRAM bank[0-3]
452 + */
453 +static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
454 +{
455 + const struct mbus_dram_target_info *dram;
456 + u32 size;
457 + int i;
458 +
459 + dram = mv_mbus_dram_info();
460 +
461 + /* First, disable and clear BARs and windows. */
462 + for (i = 1; i < 3; i++) {
463 + writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
464 + writel(0, port->base + PCIE_BAR_LO_OFF(i));
465 + writel(0, port->base + PCIE_BAR_HI_OFF(i));
466 + }
467 +
468 + for (i = 0; i < 5; i++) {
469 + writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
470 + writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
471 + writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
472 + }
473 +
474 + writel(0, port->base + PCIE_WIN5_CTRL_OFF);
475 + writel(0, port->base + PCIE_WIN5_BASE_OFF);
476 + writel(0, port->base + PCIE_WIN5_REMAP_OFF);
477 +
478 + /* Setup windows for DDR banks. Count total DDR size on the fly. */
479 + size = 0;
480 + for (i = 0; i < dram->num_cs; i++) {
481 + const struct mbus_dram_window *cs = dram->cs + i;
482 +
483 + writel(cs->base & 0xffff0000,
484 + port->base + PCIE_WIN04_BASE_OFF(i));
485 + writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
486 + writel(((cs->size - 1) & 0xffff0000) |
487 + (cs->mbus_attr << 8) |
488 + (dram->mbus_dram_target_id << 4) | 1,
489 + port->base + PCIE_WIN04_CTRL_OFF(i));
490 +
491 + size += cs->size;
492 + }
493 +
494 + /* Round up 'size' to the nearest power of two. */
495 + if ((size & (size - 1)) != 0)
496 + size = 1 << fls(size);
497 +
498 + /* Setup BAR[1] to all DRAM banks. */
499 + writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
500 + writel(0, port->base + PCIE_BAR_HI_OFF(1));
501 + writel(((size - 1) & 0xffff0000) | 1,
502 + port->base + PCIE_BAR_CTRL_OFF(1));
503 +}
504 +
505 +static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
506 +{
507 + u16 cmd;
508 + u32 mask;
509 +
510 + /* Point PCIe unit MBUS decode windows to DRAM space. */
511 + mvebu_pcie_setup_wins(port);
512 +
513 + /* Master + slave enable. */
514 + cmd = readw(port->base + PCIE_CMD_OFF);
515 + cmd |= PCI_COMMAND_IO;
516 + cmd |= PCI_COMMAND_MEMORY;
517 + cmd |= PCI_COMMAND_MASTER;
518 + writew(cmd, port->base + PCIE_CMD_OFF);
519 +
520 + /* Enable interrupt lines A-D. */
521 + mask = readl(port->base + PCIE_MASK_OFF);
522 + mask |= PCIE_MASK_ENABLE_INTS;
523 + writel(mask, port->base + PCIE_MASK_OFF);
524 +}
525 +
526 +static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
527 + struct pci_bus *bus,
528 + u32 devfn, int where, int size, u32 *val)
529 +{
530 + writel(PCIE_CONF_ADDR(bus->number, devfn, where),
531 + port->base + PCIE_CONF_ADDR_OFF);
532 +
533 + *val = readl(port->base + PCIE_CONF_DATA_OFF);
534 +
535 + if (size == 1)
536 + *val = (*val >> (8 * (where & 3))) & 0xff;
537 + else if (size == 2)
538 + *val = (*val >> (8 * (where & 3))) & 0xffff;
539 +
540 + return PCIBIOS_SUCCESSFUL;
541 +}
542 +
543 +static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
544 + struct pci_bus *bus,
545 + u32 devfn, int where, int size, u32 val)
546 +{
547 + int ret = PCIBIOS_SUCCESSFUL;
548 +
549 + writel(PCIE_CONF_ADDR(bus->number, devfn, where),
550 + port->base + PCIE_CONF_ADDR_OFF);
551 +
552 + if (size == 4)
553 + writel(val, port->base + PCIE_CONF_DATA_OFF);
554 + else if (size == 2)
555 + writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
556 + else if (size == 1)
557 + writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
558 + else
559 + ret = PCIBIOS_BAD_REGISTER_NUMBER;
560 +
561 + return ret;
562 +}
563 +
564 +static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
565 +{
566 + phys_addr_t iobase;
567 +
568 + /* Are the new iobase/iolimit values invalid? */
569 + if (port->bridge.iolimit < port->bridge.iobase ||
570 + port->bridge.iolimitupper < port->bridge.iobaseupper) {
571 +
572 + /* If a window was configured, remove it */
573 + if (port->iowin_base) {
574 + mvebu_mbus_del_window(port->iowin_base,
575 + port->iowin_size);
576 + port->iowin_base = 0;
577 + port->iowin_size = 0;
578 + }
579 +
580 + return;
581 + }
582 +
583 + /*
584 + * We read the PCI-to-PCI bridge emulated registers, and
585 + * calculate the base address and size of the address decoding
586 + * window to setup, according to the PCI-to-PCI bridge
587 + * specifications. iobase is the bus address, port->iowin_base
588 + * is the CPU address.
589 + */
590 + iobase = ((port->bridge.iobase & 0xF0) << 8) |
591 + (port->bridge.iobaseupper << 16);
592 + port->iowin_base = port->pcie->io.start + iobase;
593 + port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
594 + (port->bridge.iolimitupper << 16)) -
595 + iobase);
596 +
597 + mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
598 + port->iowin_size,
599 + iobase,
600 + MVEBU_MBUS_PCI_IO);
601 +
602 + pci_ioremap_io(iobase, port->iowin_base);
603 +}
604 +
605 +static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
606 +{
607 + /* Are the new membase/memlimit values invalid? */
608 + if (port->bridge.memlimit < port->bridge.membase) {
609 +
610 + /* If a window was configured, remove it */
611 + if (port->memwin_base) {
612 + mvebu_mbus_del_window(port->memwin_base,
613 + port->memwin_size);
614 + port->memwin_base = 0;
615 + port->memwin_size = 0;
616 + }
617 +
618 + return;
619 + }
620 +
621 + /*
622 + * We read the PCI-to-PCI bridge emulated registers, and
623 + * calculate the base address and size of the address decoding
624 + * window to setup, according to the PCI-to-PCI bridge
625 + * specifications.
626 + */
627 + port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
628 + port->memwin_size =
629 + (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
630 + port->memwin_base;
631 +
632 + mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
633 + port->memwin_size,
634 + MVEBU_MBUS_NO_REMAP,
635 + MVEBU_MBUS_PCI_MEM);
636 +}
637 +
638 +/*
639 + * Initialize the configuration space of the PCI-to-PCI bridge
640 + * associated with the given PCIe interface.
641 + */
642 +static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
643 +{
644 + struct mvebu_sw_pci_bridge *bridge = &port->bridge;
645 +
646 + memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
647 +
648 + bridge->status = PCI_STATUS_CAP_LIST;
649 + bridge->class = PCI_CLASS_BRIDGE_PCI;
650 + bridge->vendor = PCI_VENDOR_ID_MARVELL;
651 + bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
652 + bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
653 + bridge->cache_line_size = 0x10;
654 +
655 + /* We support 32 bits I/O addressing */
656 + bridge->iobase = PCI_IO_RANGE_TYPE_32;
657 + bridge->iolimit = PCI_IO_RANGE_TYPE_32;
658 +}
659 +
660 +/*
661 + * Read the configuration space of the PCI-to-PCI bridge associated to
662 + * the given PCIe interface.
663 + */
664 +static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
665 + unsigned int where, int size, u32 *value)
666 +{
667 + struct mvebu_sw_pci_bridge *bridge = &port->bridge;
668 +
669 + switch (where & ~3) {
670 + case PCI_VENDOR_ID:
671 + *value = bridge->device << 16 | bridge->vendor;
672 + break;
673 +
674 + case PCI_COMMAND:
675 + *value = bridge->status << 16 | bridge->command;
676 + break;
677 +
678 + case PCI_CLASS_REVISION:
679 + *value = bridge->class << 16 | bridge->interface << 8 |
680 + bridge->revision;
681 + break;
682 +
683 + case PCI_CACHE_LINE_SIZE:
684 + *value = bridge->bist << 24 | bridge->header_type << 16 |
685 + bridge->latency_timer << 8 | bridge->cache_line_size;
686 + break;
687 +
688 + case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
689 + *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
690 + break;
691 +
692 + case PCI_PRIMARY_BUS:
693 + *value = (bridge->secondary_latency_timer << 24 |
694 + bridge->subordinate_bus << 16 |
695 + bridge->secondary_bus << 8 |
696 + bridge->primary_bus);
697 + break;
698 +
699 + case PCI_IO_BASE:
700 + *value = (bridge->secondary_status << 16 |
701 + bridge->iolimit << 8 |
702 + bridge->iobase);
703 + break;
704 +
705 + case PCI_MEMORY_BASE:
706 + *value = (bridge->memlimit << 16 | bridge->membase);
707 + break;
708 +
709 + case PCI_PREF_MEMORY_BASE:
710 + *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
711 + break;
712 +
713 + case PCI_PREF_BASE_UPPER32:
714 + *value = bridge->prefbaseupper;
715 + break;
716 +
717 + case PCI_PREF_LIMIT_UPPER32:
718 + *value = bridge->preflimitupper;
719 + break;
720 +
721 + case PCI_IO_BASE_UPPER16:
722 + *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
723 + break;
724 +
725 + case PCI_ROM_ADDRESS1:
726 + *value = 0;
727 + break;
728 +
729 + default:
730 + *value = 0xffffffff;
731 + return PCIBIOS_BAD_REGISTER_NUMBER;
732 + }
733 +
734 + if (size == 2)
735 + *value = (*value >> (8 * (where & 3))) & 0xffff;
736 + else if (size == 1)
737 + *value = (*value >> (8 * (where & 3))) & 0xff;
738 +
739 + return PCIBIOS_SUCCESSFUL;
740 +}
741 +
742 +/* Write to the PCI-to-PCI bridge configuration space */
743 +static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
744 + unsigned int where, int size, u32 value)
745 +{
746 + struct mvebu_sw_pci_bridge *bridge = &port->bridge;
747 + u32 mask, reg;
748 + int err;
749 +
750 + if (size == 4)
751 + mask = 0x0;
752 + else if (size == 2)
753 + mask = ~(0xffff << ((where & 3) * 8));
754 + else if (size == 1)
755 + mask = ~(0xff << ((where & 3) * 8));
756 + else
757 + return PCIBIOS_BAD_REGISTER_NUMBER;
758 +
759 + err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
760 + if (err)
761 + return err;
762 +
763 + value = (reg & mask) | value << ((where & 3) * 8);
764 +
765 + switch (where & ~3) {
766 + case PCI_COMMAND:
767 + bridge->command = value & 0xffff;
768 + bridge->status = value >> 16;
769 + break;
770 +
771 + case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
772 + bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
773 + break;
774 +
775 + case PCI_IO_BASE:
776 + /*
777 + * We also keep bit 1 set, it is a read-only bit that
778 + * indicates we support 32 bits addressing for the
779 + * I/O
780 + */
781 + bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
782 + bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
783 + bridge->secondary_status = value >> 16;
784 + mvebu_pcie_handle_iobase_change(port);
785 + break;
786 +
787 + case PCI_MEMORY_BASE:
788 + bridge->membase = value & 0xffff;
789 + bridge->memlimit = value >> 16;
790 + mvebu_pcie_handle_membase_change(port);
791 + break;
792 +
793 + case PCI_PREF_MEMORY_BASE:
794 + bridge->prefmembase = value & 0xffff;
795 + bridge->prefmemlimit = value >> 16;
796 + break;
797 +
798 + case PCI_PREF_BASE_UPPER32:
799 + bridge->prefbaseupper = value;
800 + break;
801 +
802 + case PCI_PREF_LIMIT_UPPER32:
803 + bridge->preflimitupper = value;
804 + break;
805 +
806 + case PCI_IO_BASE_UPPER16:
807 + bridge->iobaseupper = value & 0xffff;
808 + bridge->iolimitupper = value >> 16;
809 + mvebu_pcie_handle_iobase_change(port);
810 + break;
811 +
812 + case PCI_PRIMARY_BUS:
813 + bridge->primary_bus = value & 0xff;
814 + bridge->secondary_bus = (value >> 8) & 0xff;
815 + bridge->subordinate_bus = (value >> 16) & 0xff;
816 + bridge->secondary_latency_timer = (value >> 24) & 0xff;
817 + mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
818 + break;
819 +
820 + default:
821 + break;
822 + }
823 +
824 + return PCIBIOS_SUCCESSFUL;
825 +}
826 +
827 +static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
828 +{
829 + return sys->private_data;
830 +}
831 +
832 +static struct mvebu_pcie_port *
833 +mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
834 + int devfn)
835 +{
836 + int i;
837 +
838 + for (i = 0; i < pcie->nports; i++) {
839 + struct mvebu_pcie_port *port = &pcie->ports[i];
840 + if (bus->number == 0 && port->devfn == devfn)
841 + return port;
842 + if (bus->number != 0 &&
843 + port->bridge.secondary_bus == bus->number)
844 + return port;
845 + }
846 +
847 + return NULL;
848 +}
849 +
850 +/* PCI configuration space write function */
851 +static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
852 + int where, int size, u32 val)
853 +{
854 + struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
855 + struct mvebu_pcie_port *port;
856 + unsigned long flags;
857 + int ret;
858 +
859 + port = mvebu_pcie_find_port(pcie, bus, devfn);
860 + if (!port)
861 + return PCIBIOS_DEVICE_NOT_FOUND;
862 +
863 + /* Access the emulated PCI-to-PCI bridge */
864 + if (bus->number == 0)
865 + return mvebu_sw_pci_bridge_write(port, where, size, val);
866 +
867 + if (!port->haslink || PCI_SLOT(devfn) != 0)
868 + return PCIBIOS_DEVICE_NOT_FOUND;
869 +
870 + /* Access the real PCIe interface */
871 + spin_lock_irqsave(&port->conf_lock, flags);
872 + ret = mvebu_pcie_hw_wr_conf(port, bus,
873 + PCI_DEVFN(1, PCI_FUNC(devfn)),
874 + where, size, val);
875 + spin_unlock_irqrestore(&port->conf_lock, flags);
876 +
877 + return ret;
878 +}
879 +
880 +/* PCI configuration space read function */
881 +static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
882 + int size, u32 *val)
883 +{
884 + struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
885 + struct mvebu_pcie_port *port;
886 + unsigned long flags;
887 + int ret;
888 +
889 + port = mvebu_pcie_find_port(pcie, bus, devfn);
890 + if (!port) {
891 + *val = 0xffffffff;
892 + return PCIBIOS_DEVICE_NOT_FOUND;
893 + }
894 +
895 + /* Access the emulated PCI-to-PCI bridge */
896 + if (bus->number == 0)
897 + return mvebu_sw_pci_bridge_read(port, where, size, val);
898 +
899 + if (!port->haslink || PCI_SLOT(devfn) != 0) {
900 + *val = 0xffffffff;
901 + return PCIBIOS_DEVICE_NOT_FOUND;
902 + }
903 +
904 + /* Access the real PCIe interface */
905 + spin_lock_irqsave(&port->conf_lock, flags);
906 + ret = mvebu_pcie_hw_rd_conf(port, bus,
907 + PCI_DEVFN(1, PCI_FUNC(devfn)),
908 + where, size, val);
909 + spin_unlock_irqrestore(&port->conf_lock, flags);
910 +
911 + return ret;
912 +}
913 +
914 +static struct pci_ops mvebu_pcie_ops = {
915 + .read = mvebu_pcie_rd_conf,
916 + .write = mvebu_pcie_wr_conf,
917 +};
918 +
919 +static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
920 +{
921 + struct mvebu_pcie *pcie = sys_to_pcie(sys);
922 + int i;
923 +
924 + pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
925 + pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
926 + pci_add_resource(&sys->resources, &pcie->busn);
927 +
928 + for (i = 0; i < pcie->nports; i++) {
929 + struct mvebu_pcie_port *port = &pcie->ports[i];
930 + mvebu_pcie_setup_hw(port);
931 + }
932 +
933 + return 1;
934 +}
935 +
936 +static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
937 +{
938 + struct of_irq oirq;
939 + int ret;
940 +
941 + ret = of_irq_map_pci(dev, &oirq);
942 + if (ret)
943 + return ret;
944 +
945 + return irq_create_of_mapping(oirq.controller, oirq.specifier,
946 + oirq.size);
947 +}
948 +
949 +static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
950 +{
951 + struct mvebu_pcie *pcie = sys_to_pcie(sys);
952 + struct pci_bus *bus;
953 +
954 + bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
955 + &mvebu_pcie_ops, sys, &sys->resources);
956 + if (!bus)
957 + return NULL;
958 +
959 + pci_scan_child_bus(bus);
960 +
961 + return bus;
962 +}
963 +
964 +resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
965 + const struct resource *res,
966 + resource_size_t start,
967 + resource_size_t size,
968 + resource_size_t align)
969 +{
970 + if (dev->bus->number != 0)
971 + return start;
972 +
973 + /*
974 + * On the PCI-to-PCI bridge side, the I/O windows must have at
975 + * least a 64 KB size and be aligned on their size, and the
976 + * memory windows must have at least a 1 MB size and be
977 + * aligned on their size
978 + */
979 + if (res->flags & IORESOURCE_IO)
980 + return round_up(start, max((resource_size_t)SZ_64K, size));
981 + else if (res->flags & IORESOURCE_MEM)
982 + return round_up(start, max((resource_size_t)SZ_1M, size));
983 + else
984 + return start;
985 +}
986 +
987 +static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie)
988 +{
989 + struct hw_pci hw;
990 +
991 + memset(&hw, 0, sizeof(hw));
992 +
993 + hw.nr_controllers = 1;
994 + hw.private_data = (void **)&pcie;
995 + hw.setup = mvebu_pcie_setup;
996 + hw.scan = mvebu_pcie_scan_bus;
997 + hw.map_irq = mvebu_pcie_map_irq;
998 + hw.ops = &mvebu_pcie_ops;
999 + hw.align_resource = mvebu_pcie_align_resource;
1000 +
1001 + pci_common_init(&hw);
1002 +}
1003 +
1004 +/*
1005 + * Looks up the list of register addresses encoded into the reg =
1006 + * <...> property for one that matches the given port/lane. Once
1007 + * found, maps it.
1008 + */
1009 +static void __iomem * __init
1010 +mvebu_pcie_map_registers(struct platform_device *pdev,
1011 + struct device_node *np,
1012 + struct mvebu_pcie_port *port)
1013 +{
1014 + struct resource regs;
1015 + int ret = 0;
1016 +
1017 + ret = of_address_to_resource(np, 0, &regs);
1018 + if (ret)
1019 + return NULL;
1020 +
1021 + return devm_request_and_ioremap(&pdev->dev, &regs);
1022 +}
1023 +
1024 +static int __init mvebu_pcie_probe(struct platform_device *pdev)
1025 +{
1026 + struct mvebu_pcie *pcie;
1027 + struct device_node *np = pdev->dev.of_node;
1028 + struct of_pci_range range;
1029 + struct of_pci_range_parser parser;
1030 + struct device_node *child;
1031 + int i, ret;
1032 +
1033 + pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
1034 + GFP_KERNEL);
1035 + if (!pcie)
1036 + return -ENOMEM;
1037 +
1038 + pcie->pdev = pdev;
1039 +
1040 + if (of_pci_range_parser_init(&parser, np))
1041 + return -EINVAL;
1042 +
1043 + /* Get the I/O and memory ranges from DT */
1044 + for_each_of_pci_range(&parser, &range) {
1045 + unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
1046 + if (restype == IORESOURCE_IO) {
1047 + of_pci_range_to_resource(&range, np, &pcie->io);
1048 + of_pci_range_to_resource(&range, np, &pcie->realio);
1049 + pcie->io.name = "I/O";
1050 + pcie->realio.start = max_t(resource_size_t,
1051 + PCIBIOS_MIN_IO,
1052 + range.pci_addr);
1053 + pcie->realio.end = min_t(resource_size_t,
1054 + IO_SPACE_LIMIT,
1055 + range.pci_addr + range.size);
1056 + }
1057 + if (restype == IORESOURCE_MEM) {
1058 + of_pci_range_to_resource(&range, np, &pcie->mem);
1059 + pcie->mem.name = "MEM";
1060 + }
1061 + }
1062 +
1063 + /* Get the bus range */
1064 + ret = of_pci_parse_bus_range(np, &pcie->busn);
1065 + if (ret) {
1066 + dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
1067 + ret);
1068 + return ret;
1069 + }
1070 +
1071 + for_each_child_of_node(pdev->dev.of_node, child) {
1072 + if (!of_device_is_available(child))
1073 + continue;
1074 + pcie->nports++;
1075 + }
1076 +
1077 + pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
1078 + sizeof(struct mvebu_pcie_port),
1079 + GFP_KERNEL);
1080 + if (!pcie->ports)
1081 + return -ENOMEM;
1082 +
1083 + i = 0;
1084 + for_each_child_of_node(pdev->dev.of_node, child) {
1085 + struct mvebu_pcie_port *port = &pcie->ports[i];
1086 +
1087 + if (!of_device_is_available(child))
1088 + continue;
1089 +
1090 + port->pcie = pcie;
1091 +
1092 + if (of_property_read_u32(child, "marvell,pcie-port",
1093 + &port->port)) {
1094 + dev_warn(&pdev->dev,
1095 + "ignoring PCIe DT node, missing pcie-port property\n");
1096 + continue;
1097 + }
1098 +
1099 + if (of_property_read_u32(child, "marvell,pcie-lane",
1100 + &port->lane))
1101 + port->lane = 0;
1102 +
1103 + port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
1104 + port->port, port->lane);
1105 +
1106 + port->devfn = of_pci_get_devfn(child);
1107 + if (port->devfn < 0)
1108 + continue;
1109 +
1110 + port->base = mvebu_pcie_map_registers(pdev, child, port);
1111 + if (!port->base) {
1112 + dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
1113 + port->port, port->lane);
1114 + continue;
1115 + }
1116 +
1117 + if (mvebu_pcie_link_up(port)) {
1118 + port->haslink = 1;
1119 + dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
1120 + port->port, port->lane);
1121 + } else {
1122 + port->haslink = 0;
1123 + dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
1124 + port->port, port->lane);
1125 + }
1126 +
1127 + port->clk = of_clk_get_by_name(child, NULL);
1128 + if (!port->clk) {
1129 + dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
1130 + port->port, port->lane);
1131 + iounmap(port->base);
1132 + port->haslink = 0;
1133 + continue;
1134 + }
1135 +
1136 + port->dn = child;
1137 +
1138 + clk_prepare_enable(port->clk);
1139 + spin_lock_init(&port->conf_lock);
1140 +
1141 + mvebu_sw_pci_bridge_init(port);
1142 +
1143 + i++;
1144 + }
1145 +
1146 + mvebu_pcie_enable(pcie);
1147 +
1148 + return 0;
1149 +}
1150 +
1151 +static const struct of_device_id mvebu_pcie_of_match_table[] = {
1152 + { .compatible = "marvell,armada-xp-pcie", },
1153 + { .compatible = "marvell,armada-370-pcie", },
1154 + {},
1155 +};
1156 +MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1157 +
1158 +static struct platform_driver mvebu_pcie_driver = {
1159 + .driver = {
1160 + .owner = THIS_MODULE,
1161 + .name = "mvebu-pcie",
1162 + .of_match_table =
1163 + of_match_ptr(mvebu_pcie_of_match_table),
1164 + },
1165 +};
1166 +
1167 +static int __init mvebu_pcie_init(void)
1168 +{
1169 + return platform_driver_probe(&mvebu_pcie_driver,
1170 + mvebu_pcie_probe);
1171 +}
1172 +
1173 +subsys_initcall(mvebu_pcie_init);
1174 +
1175 +MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1176 +MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1177 +MODULE_LICENSE("GPLv2");
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