target/linux/mvebu/patches-3.10/0115-mtd-nand-pxa3xx-Handle-ECC-and-DMA-enable-disable-pr.patch

   1 From d6af8f27223a244d74ab44842bdec707c97cfe55 Mon Sep 17 00:00:00 2001
   2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
   3 Date: Mon, 12 Aug 2013 14:14:48 -0300
   4 Subject: [PATCH 115/203] mtd: nand: pxa3xx: Handle ECC and DMA enable/disable
   5  properly
   6
   7 When ECC is not selected, the ECC enable bit must be cleared
   8 in the NAND control register. Same applies to DMA.
   9
  10 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
  11 Tested-by: Daniel Mack <zonque@gmail.com>
  12 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
  13 Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
  14 ---
  15  drivers/mtd/nand/pxa3xx_nand.c | 13 +++++++++++--
  16  1 file changed, 11 insertions(+), 2 deletions(-)
  17
  18 --- a/drivers/mtd/nand/pxa3xx_nand.c
  19 +++ b/drivers/mtd/nand/pxa3xx_nand.c
  20 @@ -314,8 +314,17 @@ static void pxa3xx_nand_start(struct pxa
  21         uint32_t ndcr;
  22
  23         ndcr = host->reg_ndcr;
  24 -       ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
  25 -       ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
  26 +
  27 +       if (info->use_ecc)
  28 +               ndcr |= NDCR_ECC_EN;
  29 +       else
  30 +               ndcr &= ~NDCR_ECC_EN;
  31 +
  32 +       if (info->use_dma)
  33 +               ndcr |= NDCR_DMA_EN;
  34 +       else
  35 +               ndcr &= ~NDCR_DMA_EN;
  36 +
  37         ndcr |= NDCR_ND_RUN;
  38
  39         /* clear status bits and run */