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base-files: define yes/no as valid boolean options
[openwrt/staging/lynxis/omap.git] / target / linux / mvebu / patches-3.10 / 0121-mtd-nand-pxa3xx-Remove-unneeded-internal-cmdset.patch
1 From 45d36da3f284cd424b0ac2060cfccc17f9979552 Mon Sep 17 00:00:00 2001
2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
3 Date: Mon, 12 Aug 2013 14:14:54 -0300
4 Subject: [PATCH 121/203] mtd: nand: pxa3xx: Remove unneeded internal cmdset
5
6 Use the defined macros for NAND command instead of using a constant
7 internal structure. This commit is only a cleanup, there's no
8 functionality modification.
9
10 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
11 Tested-by: Daniel Mack <zonque@gmail.com>
12 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
13 Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
14 ---
15 drivers/mtd/nand/pxa3xx_nand.c | 63 ++++++++-------------------
16 include/linux/platform_data/mtd-nand-pxa3xx.h | 13 ------
17 2 files changed, 17 insertions(+), 59 deletions(-)
18
19 --- a/drivers/mtd/nand/pxa3xx_nand.c
20 +++ b/drivers/mtd/nand/pxa3xx_nand.c
21 @@ -131,7 +131,6 @@ enum pxa3xx_nand_variant {
22
23 struct pxa3xx_nand_host {
24 struct nand_chip chip;
25 - struct pxa3xx_nand_cmdset *cmdset;
26 struct mtd_info *mtd;
27 void *info_data;
28
29 @@ -205,23 +204,6 @@ static bool use_dma = 1;
30 module_param(use_dma, bool, 0444);
31 MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
32
33 -/*
34 - * Default NAND flash controller configuration setup by the
35 - * bootloader. This configuration is used only when pdata->keep_config is set
36 - */
37 -static struct pxa3xx_nand_cmdset default_cmdset = {
38 - .read1 = 0x3000,
39 - .read2 = 0x0050,
40 - .program = 0x1080,
41 - .read_status = 0x0070,
42 - .read_id = 0x0090,
43 - .erase = 0xD060,
44 - .reset = 0x00FF,
45 - .lock = 0x002A,
46 - .unlock = 0x2423,
47 - .lock_status = 0x007A,
48 -};
49 -
50 static struct pxa3xx_nand_timing timing[] = {
51 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
52 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
53 @@ -530,7 +512,6 @@ static inline int is_buf_blank(uint8_t *
54 static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
55 uint16_t column, int page_addr)
56 {
57 - uint16_t cmd;
58 int addr_cycle, exec_cmd;
59 struct pxa3xx_nand_host *host;
60 struct mtd_info *mtd;
61 @@ -580,21 +561,17 @@ static int prepare_command_pool(struct p
62 switch (command) {
63 case NAND_CMD_READOOB:
64 case NAND_CMD_READ0:
65 - cmd = host->cmdset->read1;
66 + info->buf_start = column;
67 + info->ndcb0 |= NDCB0_CMD_TYPE(0)
68 + | addr_cycle
69 + | NAND_CMD_READ0;
70 +
71 if (command == NAND_CMD_READOOB)
72 - info->buf_start = mtd->writesize + column;
73 - else
74 - info->buf_start = column;
75 + info->buf_start += mtd->writesize;
76
77 - if (unlikely(host->page_size < PAGE_CHUNK_SIZE))
78 - info->ndcb0 |= NDCB0_CMD_TYPE(0)
79 - | addr_cycle
80 - | (cmd & NDCB0_CMD1_MASK);
81 - else
82 - info->ndcb0 |= NDCB0_CMD_TYPE(0)
83 - | NDCB0_DBC
84 - | addr_cycle
85 - | cmd;
86 + /* Second command setting for large pages */
87 + if (host->page_size >= PAGE_CHUNK_SIZE)
88 + info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
89
90 case NAND_CMD_SEQIN:
91 /* small page addr setting */
92 @@ -625,62 +602,58 @@ static int prepare_command_pool(struct p
93 break;
94 }
95
96 - cmd = host->cmdset->program;
97 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
98 | NDCB0_AUTO_RS
99 | NDCB0_ST_ROW_EN
100 | NDCB0_DBC
101 - | cmd
102 + | (NAND_CMD_PAGEPROG << 8)
103 + | NAND_CMD_SEQIN
104 | addr_cycle;
105 break;
106
107 case NAND_CMD_PARAM:
108 - cmd = NAND_CMD_PARAM;
109 info->buf_count = 256;
110 info->ndcb0 |= NDCB0_CMD_TYPE(0)
111 | NDCB0_ADDR_CYC(1)
112 | NDCB0_LEN_OVRD
113 - | cmd;
114 + | command;
115 info->ndcb1 = (column & 0xFF);
116 info->ndcb3 = 256;
117 info->data_size = 256;
118 break;
119
120 case NAND_CMD_READID:
121 - cmd = host->cmdset->read_id;
122 info->buf_count = host->read_id_bytes;
123 info->ndcb0 |= NDCB0_CMD_TYPE(3)
124 | NDCB0_ADDR_CYC(1)
125 - | cmd;
126 + | command;
127 info->ndcb1 = (column & 0xFF);
128
129 info->data_size = 8;
130 break;
131 case NAND_CMD_STATUS:
132 - cmd = host->cmdset->read_status;
133 info->buf_count = 1;
134 info->ndcb0 |= NDCB0_CMD_TYPE(4)
135 | NDCB0_ADDR_CYC(1)
136 - | cmd;
137 + | command;
138
139 info->data_size = 8;
140 break;
141
142 case NAND_CMD_ERASE1:
143 - cmd = host->cmdset->erase;
144 info->ndcb0 |= NDCB0_CMD_TYPE(2)
145 | NDCB0_AUTO_RS
146 | NDCB0_ADDR_CYC(3)
147 | NDCB0_DBC
148 - | cmd;
149 + | (NAND_CMD_ERASE2 << 8)
150 + | NAND_CMD_ERASE1;
151 info->ndcb1 = page_addr;
152 info->ndcb2 = 0;
153
154 break;
155 case NAND_CMD_RESET:
156 - cmd = host->cmdset->reset;
157 info->ndcb0 |= NDCB0_CMD_TYPE(5)
158 - | cmd;
159 + | command;
160
161 break;
162
163 @@ -876,7 +849,6 @@ static int pxa3xx_nand_config_flash(stru
164 }
165
166 /* calculate flash information */
167 - host->cmdset = &default_cmdset;
168 host->page_size = f->page_size;
169 host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
170
171 @@ -922,7 +894,6 @@ static int pxa3xx_nand_detect_config(str
172 }
173
174 host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
175 - host->cmdset = &default_cmdset;
176
177 host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
178 host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
179 --- a/include/linux/platform_data/mtd-nand-pxa3xx.h
180 +++ b/include/linux/platform_data/mtd-nand-pxa3xx.h
181 @@ -16,19 +16,6 @@ struct pxa3xx_nand_timing {
182 unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
183 };
184
185 -struct pxa3xx_nand_cmdset {
186 - uint16_t read1;
187 - uint16_t read2;
188 - uint16_t program;
189 - uint16_t read_status;
190 - uint16_t read_id;
191 - uint16_t erase;
192 - uint16_t reset;
193 - uint16_t lock;
194 - uint16_t unlock;
195 - uint16_t lock_status;
196 -};
197 -
198 struct pxa3xx_nand_flash {
199 char *name;
200 uint32_t chip_id;
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