target/linux/sunxi/patches-3.13/124-clk-sunxi-muxable-ahb-clock.patch

   1 From 9490107c16c8eaa35b07794e19d5d2eddea8e44b Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Sat, 14 Sep 2013 20:48:40 -0300
   4 Subject: [PATCH] clk: sunxi: Implement muxable AHB clock
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 sun5i and sun7i have a mux to change the AHB clock parent, this commit
  10 adds support for it on the driver.
  11
  12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 ---
  14  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
  15  drivers/clk/sunxi/clk-sunxi.c                     | 37 +++++++++++++++++++++++
  16  2 files changed, 38 insertions(+)
  17
  18 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
  19 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
  20 @@ -15,6 +15,7 @@ Required properties:
  21         "allwinner,sun4i-axi-clk" - for the AXI clock
  22         "allwinner,sun4i-axi-gates-clk" - for the AXI gates
  23         "allwinner,sun4i-ahb-clk" - for the AHB clock
  24 +       "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
  25         "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
  26         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
  27         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
  28 --- a/drivers/clk/sunxi/clk-sunxi.c
  29 +++ b/drivers/clk/sunxi/clk-sunxi.c
  30 @@ -249,7 +249,32 @@ static void sun4i_get_pll5_factors(u32 *
  31         *n = DIV_ROUND_UP(div, (*k+1));
  32  }
  33
  34 +/**
  35 + * sun5i_get_ahb_factors() - calculates p factor for AHB
  36 + * AHB rate is calculated as follows
  37 + * rate = parent_rate >> p
  38 + */
  39 +
  40 +static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
  41 +                                     u8 *n, u8 *k, u8 *m, u8 *p)
  42 +{
  43 +       u8 div;
  44 +
  45 +       /* This clock can only divide, so we will never achieve a higher
  46 +        * rate than the parent's */
  47 +       if (*freq > parent_rate)
  48 +               *freq = parent_rate;
  49 +
  50 +       /* Normalize value to a parent multiple */
  51 +       div = *freq / parent_rate;
  52 +       *freq = parent_rate * div;
  53 +
  54 +       /* we were called to round the frequency, we can now return */
  55 +       if (n == NULL)
  56 +               return;
  57
  58 +       *p = div;
  59 +}
  60
  61  /**
  62   * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  63 @@ -375,6 +400,11 @@ static struct clk_factors_config sun4i_p
  64         .kwidth = 2,
  65  };
  66
  67 +static struct clk_factors_config sun5i_a13_ahb_config = {
  68 +       .pshift = 4,
  69 +       .pwidth = 2,
  70 +};
  71 +
  72  static struct clk_factors_config sun4i_apb1_config = {
  73         .mshift = 0,
  74         .mwidth = 5,
  75 @@ -408,6 +438,12 @@ static const struct factors_data sun4i_p
  76         .getter = sun4i_get_pll5_factors,
  77  };
  78
  79 +static const struct factors_data sun5i_a13_ahb_data __initconst = {
  80 +       .mux = 6,
  81 +       .table = &sun5i_a13_ahb_config,
  82 +       .getter = sun5i_a13_get_ahb_factors,
  83 +};
  84 +
  85  static const struct factors_data sun4i_apb1_data __initconst = {
  86         .table = &sun4i_apb1_config,
  87         .getter = sun4i_get_apb1_factors,
  88 @@ -916,6 +952,7 @@ free_clkdata:
  89  static const struct of_device_id clk_factors_match[] __initconst = {
  90         {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
  91         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
  92 +       {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
  93         {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
  94         {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
  95         {}