projects / openwrt / staging / lynxis / omap.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: cb0eccf) | patch
uart_clk on Rt3352F is always 40MHz
authorJohn Crispin <john@openwrt.org>
Tue, 24 Jul 2012 20:37:50 +0000 (20:37 +0000)
committerJohn Crispin <john@openwrt.org>
Tue, 24 Jul 2012 20:37:50 +0000 (20:37 +0000)
commit6641024f50b61178a07fc2ac846fb0ce8f53ee6f
treef35c82aaf0aa49b6ea6b4dc78cc39d764a280a40tree | snapshot
parentcb0eccf529fa7c7410997e88f5add533419ba76dcommit | diff
uart_clk on Rt3352F is always 40MHz

Currently, sys_clk/10 is used which is just wrong.
cpu_clk/10 would work for systems with 400MHz CPU clock.

Signed-off-by: Daniel Golle <dgolle@allnet.de>
SVN-Revision: 32812
target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c diff | blob | history
lynxis staging tree for omap