target/linux/generic/backport-5.15/420-v5.19-04-mtd-spinand-gigadevice-add-support-for-GD5F-2-4-GQ5x.patch

   1 From 194ec04b3a9e7fa97d1fbef296410631bc3cf1c8 Mon Sep 17 00:00:00 2001
   2 From: Chuanhong Guo <gch981213@gmail.com>
   3 Date: Sun, 20 Mar 2022 18:00:00 +0800
   4 Subject: [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2,
   5  4}GQ5xExxG
   6
   7 Add support for:
   8  GD5F2GQ5{U,R}ExxG
   9  GD5F4GQ6{U,R}ExxG
  10
  11 These chips uses 4 dummy bytes for quad io and 2 dummy bytes for dual io.
  12 Besides that and memory layout, they are identical to their 1G variant.
  13
  14 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  15 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  16 Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-5-gch981213@gmail.com
  17 ---
  18  drivers/mtd/nand/spi/gigadevice.c | 48 +++++++++++++++++++++++++++++++
  19  1 file changed, 48 insertions(+)
  20
  21 diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
  22 index d519bb85f0e7..fcd1c4e474a2 100644
  23 --- a/drivers/mtd/nand/spi/gigadevice.c
  24 +++ b/drivers/mtd/nand/spi/gigadevice.c
  25 @@ -47,6 +47,14 @@ static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
  26                 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
  27                 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
  28
  29 +static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
  30 +               SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
  31 +               SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
  32 +               SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
  33 +               SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
  34 +               SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
  35 +               SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
  36 +
  37  static SPINAND_OP_VARIANTS(write_cache_variants,
  38                 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
  39                 SPINAND_PROG_LOAD(true, 0, NULL, 0));
  40 @@ -393,6 +401,46 @@ static const struct spinand_info gigadevice_spinand_table[] = {
  41                      SPINAND_HAS_QE_BIT,
  42                      SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  43                                      gd5fxgq5xexxg_ecc_get_status)),
  44 +       SPINAND_INFO("GD5F2GQ5UExxG",
  45 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
  46 +                    NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
  47 +                    NAND_ECCREQ(4, 512),
  48 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
  49 +                                             &write_cache_variants,
  50 +                                             &update_cache_variants),
  51 +                    SPINAND_HAS_QE_BIT,
  52 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  53 +                                    gd5fxgq5xexxg_ecc_get_status)),
  54 +       SPINAND_INFO("GD5F2GQ5RExxG",
  55 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
  56 +                    NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
  57 +                    NAND_ECCREQ(4, 512),
  58 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
  59 +                                             &write_cache_variants,
  60 +                                             &update_cache_variants),
  61 +                    SPINAND_HAS_QE_BIT,
  62 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  63 +                                    gd5fxgq5xexxg_ecc_get_status)),
  64 +       SPINAND_INFO("GD5F4GQ6UExxG",
  65 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
  66 +                    NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
  67 +                    NAND_ECCREQ(4, 512),
  68 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
  69 +                                             &write_cache_variants,
  70 +                                             &update_cache_variants),
  71 +                    SPINAND_HAS_QE_BIT,
  72 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  73 +                                    gd5fxgq5xexxg_ecc_get_status)),
  74 +       SPINAND_INFO("GD5F4GQ6RExxG",
  75 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
  76 +                    NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
  77 +                    NAND_ECCREQ(4, 512),
  78 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
  79 +                                             &write_cache_variants,
  80 +                                             &update_cache_variants),
  81 +                    SPINAND_HAS_QE_BIT,
  82 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  83 +                                    gd5fxgq5xexxg_ecc_get_status)),
  84  };
  85
  86  static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
  87 --
  88 2.35.1
  89