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generic: ar8216: add support for ar724x/ar933x builtin switch
[openwrt/staging/nbd.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
39
40 #include "ar8216.h"
41
42 extern const struct ar8xxx_chip ar8327_chip;
43 extern const struct ar8xxx_chip ar8337_chip;
44
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
46
47 #define MIB_DESC(_s , _o, _n) \
48 { \
49 .size = (_s), \
50 .offset = (_o), \
51 .name = (_n), \
52 }
53
54 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
55 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
56 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
57 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
58 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
59 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
60 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
61 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
62 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
63 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
64 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
65 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
66 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
67 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
68 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
69 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
70 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
71 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
72 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
73 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
74 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
75 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
76 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
77 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
78 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
79 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
80 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
81 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
82 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
83 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
84 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
85 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
86 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
87 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
88 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
89 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
90 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
91 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
92 };
93
94 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
95 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
96 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
97 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
98 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
99 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
100 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
101 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
102 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
103 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
104 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
105 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
106 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
107 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
108 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
109 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
110 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
111 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
112 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
113 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
114 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
115 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
116 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
117 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
118 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
119 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
120 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
121 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
122 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
123 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
124 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
125 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
126 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
127 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
128 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
129 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
130 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
131 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
132 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
133 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
134 };
135
136 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
137 static LIST_HEAD(ar8xxx_dev_list);
138
139 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
140 static int
141 ar8xxx_phy_poll_reset(struct mii_bus *bus)
142 {
143 unsigned int sleep_msecs = 20;
144 int ret, elapsed, i;
145
146 for (elapsed = sleep_msecs; elapsed <= 600;
147 elapsed += sleep_msecs) {
148 msleep(sleep_msecs);
149 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
150 ret = mdiobus_read(bus, i, MII_BMCR);
151 if (ret < 0)
152 return ret;
153 if (ret & BMCR_RESET)
154 break;
155 if (i == AR8XXX_NUM_PHYS - 1) {
156 usleep_range(1000, 2000);
157 return 0;
158 }
159 }
160 }
161 return -ETIMEDOUT;
162 }
163
164 static int
165 ar8xxx_phy_check_aneg(struct phy_device *phydev)
166 {
167 int ret;
168
169 if (phydev->autoneg != AUTONEG_ENABLE)
170 return 0;
171 /*
172 * BMCR_ANENABLE might have been cleared
173 * by phy_init_hw in certain kernel versions
174 * therefore check for it
175 */
176 ret = phy_read(phydev, MII_BMCR);
177 if (ret < 0)
178 return ret;
179 if (ret & BMCR_ANENABLE)
180 return 0;
181
182 dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
183 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
184 return phy_write(phydev, MII_BMCR, ret);
185 }
186
187 void
188 ar8xxx_phy_init(struct ar8xxx_priv *priv)
189 {
190 int i;
191 struct mii_bus *bus;
192
193 bus = priv->sw_mii_bus ?: priv->mii_bus;
194 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
195 if (priv->chip->phy_fixup)
196 priv->chip->phy_fixup(priv, i);
197
198 /* initialize the port itself */
199 mdiobus_write(bus, i, MII_ADVERTISE,
200 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
201 if (ar8xxx_has_gige(priv))
202 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
203 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
204 }
205
206 ar8xxx_phy_poll_reset(bus);
207 }
208
209 u32
210 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
211 {
212 struct mii_bus *bus = priv->mii_bus;
213 u16 lo, hi;
214
215 lo = bus->read(bus, phy_id, regnum);
216 hi = bus->read(bus, phy_id, regnum + 1);
217
218 return (hi << 16) | lo;
219 }
220
221 void
222 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
223 {
224 struct mii_bus *bus = priv->mii_bus;
225 u16 lo, hi;
226
227 lo = val & 0xffff;
228 hi = (u16) (val >> 16);
229
230 if (priv->chip->mii_lo_first)
231 {
232 bus->write(bus, phy_id, regnum, lo);
233 bus->write(bus, phy_id, regnum + 1, hi);
234 } else {
235 bus->write(bus, phy_id, regnum + 1, hi);
236 bus->write(bus, phy_id, regnum, lo);
237 }
238 }
239
240 u32
241 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
242 {
243 struct mii_bus *bus = priv->mii_bus;
244 u16 r1, r2, page;
245 u32 val;
246
247 split_addr((u32) reg, &r1, &r2, &page);
248
249 mutex_lock(&bus->mdio_lock);
250
251 bus->write(bus, 0x18, 0, page);
252 wait_for_page_switch();
253 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
254
255 mutex_unlock(&bus->mdio_lock);
256
257 return val;
258 }
259
260 void
261 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
262 {
263 struct mii_bus *bus = priv->mii_bus;
264 u16 r1, r2, page;
265
266 split_addr((u32) reg, &r1, &r2, &page);
267
268 mutex_lock(&bus->mdio_lock);
269
270 bus->write(bus, 0x18, 0, page);
271 wait_for_page_switch();
272 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
273
274 mutex_unlock(&bus->mdio_lock);
275 }
276
277 u32
278 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
279 {
280 struct mii_bus *bus = priv->mii_bus;
281 u16 r1, r2, page;
282 u32 ret;
283
284 split_addr((u32) reg, &r1, &r2, &page);
285
286 mutex_lock(&bus->mdio_lock);
287
288 bus->write(bus, 0x18, 0, page);
289 wait_for_page_switch();
290
291 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
292 ret &= ~mask;
293 ret |= val;
294 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
295
296 mutex_unlock(&bus->mdio_lock);
297
298 return ret;
299 }
300 void
301 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
302 u16 dbg_addr, u16 *dbg_data)
303 {
304 struct mii_bus *bus = priv->mii_bus;
305
306 mutex_lock(&bus->mdio_lock);
307 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
308 *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
309 mutex_unlock(&bus->mdio_lock);
310 }
311
312 void
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
314 u16 dbg_addr, u16 dbg_data)
315 {
316 struct mii_bus *bus = priv->mii_bus;
317
318 mutex_lock(&bus->mdio_lock);
319 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
320 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
321 mutex_unlock(&bus->mdio_lock);
322 }
323
324 static inline void
325 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
326 {
327 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
328 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
329 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
330 }
331
332 void
333 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
334 {
335 struct mii_bus *bus = priv->mii_bus;
336
337 mutex_lock(&bus->mdio_lock);
338 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
339 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
340 mutex_unlock(&bus->mdio_lock);
341 }
342
343 u16
344 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
345 {
346 struct mii_bus *bus = priv->mii_bus;
347 u16 data;
348
349 mutex_lock(&bus->mdio_lock);
350 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
351 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
352 mutex_unlock(&bus->mdio_lock);
353
354 return data;
355 }
356
357 static int
358 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
359 unsigned timeout)
360 {
361 int i;
362
363 for (i = 0; i < timeout; i++) {
364 u32 t;
365
366 t = ar8xxx_read(priv, reg);
367 if ((t & mask) == val)
368 return 0;
369
370 usleep_range(1000, 2000);
371 cond_resched();
372 }
373
374 return -ETIMEDOUT;
375 }
376
377 static int
378 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
379 {
380 unsigned mib_func = priv->chip->mib_func;
381 int ret;
382
383 lockdep_assert_held(&priv->mib_lock);
384
385 /* Capture the hardware statistics for all ports */
386 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
387
388 /* Wait for the capturing to complete. */
389 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
390 if (ret)
391 goto out;
392
393 ret = 0;
394
395 out:
396 return ret;
397 }
398
399 static int
400 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
401 {
402 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
403 }
404
405 static int
406 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
407 {
408 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
409 }
410
411 static void
412 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
413 {
414 unsigned int base;
415 u64 *mib_stats;
416 int i;
417
418 WARN_ON(port >= priv->dev.ports);
419
420 lockdep_assert_held(&priv->mib_lock);
421
422 base = priv->chip->reg_port_stats_start +
423 priv->chip->reg_port_stats_length * port;
424
425 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
426 for (i = 0; i < priv->chip->num_mibs; i++) {
427 const struct ar8xxx_mib_desc *mib;
428 u64 t;
429
430 mib = &priv->chip->mib_decs[i];
431 t = ar8xxx_read(priv, base + mib->offset);
432 if (mib->size == 2) {
433 u64 hi;
434
435 hi = ar8xxx_read(priv, base + mib->offset + 4);
436 t |= hi << 32;
437 }
438
439 if (flush)
440 mib_stats[i] = 0;
441 else
442 mib_stats[i] += t;
443 cond_resched();
444 }
445 }
446
447 static void
448 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
449 struct switch_port_link *link)
450 {
451 u32 status;
452 u32 speed;
453
454 memset(link, '\0', sizeof(*link));
455
456 status = priv->chip->read_port_status(priv, port);
457
458 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
459 if (link->aneg) {
460 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
461 } else {
462 link->link = true;
463
464 if (priv->get_port_link) {
465 int err;
466
467 err = priv->get_port_link(port);
468 if (err >= 0)
469 link->link = !!err;
470 }
471 }
472
473 if (!link->link)
474 return;
475
476 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
477 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
478 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
479
480 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
481 link->eee = priv->chip->read_port_eee_status(priv, port);
482
483 speed = (status & AR8216_PORT_STATUS_SPEED) >>
484 AR8216_PORT_STATUS_SPEED_S;
485
486 switch (speed) {
487 case AR8216_PORT_SPEED_10M:
488 link->speed = SWITCH_PORT_SPEED_10;
489 break;
490 case AR8216_PORT_SPEED_100M:
491 link->speed = SWITCH_PORT_SPEED_100;
492 break;
493 case AR8216_PORT_SPEED_1000M:
494 link->speed = SWITCH_PORT_SPEED_1000;
495 break;
496 default:
497 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
498 break;
499 }
500 }
501
502 static struct sk_buff *
503 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
504 {
505 struct ar8xxx_priv *priv = dev->phy_ptr;
506 unsigned char *buf;
507
508 if (unlikely(!priv))
509 goto error;
510
511 if (!priv->vlan)
512 goto send;
513
514 if (unlikely(skb_headroom(skb) < 2)) {
515 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
516 goto error;
517 }
518
519 buf = skb_push(skb, 2);
520 buf[0] = 0x10;
521 buf[1] = 0x80;
522
523 send:
524 return skb;
525
526 error:
527 dev_kfree_skb_any(skb);
528 return NULL;
529 }
530
531 static void
532 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
533 {
534 struct ar8xxx_priv *priv;
535 unsigned char *buf;
536 int port, vlan;
537
538 priv = dev->phy_ptr;
539 if (!priv)
540 return;
541
542 /* don't strip the header if vlan mode is disabled */
543 if (!priv->vlan)
544 return;
545
546 /* strip header, get vlan id */
547 buf = skb->data;
548 skb_pull(skb, 2);
549
550 /* check for vlan header presence */
551 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
552 return;
553
554 port = buf[0] & 0x7;
555
556 /* no need to fix up packets coming from a tagged source */
557 if (priv->vlan_tagged & (1 << port))
558 return;
559
560 /* lookup port vid from local table, the switch passes an invalid vlan id */
561 vlan = priv->vlan_id[priv->pvid[port]];
562
563 buf[14 + 2] &= 0xf0;
564 buf[14 + 2] |= vlan >> 8;
565 buf[15 + 2] = vlan & 0xff;
566 }
567
568 int
569 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
570 {
571 int timeout = 20;
572 u32 t = 0;
573
574 while (1) {
575 t = ar8xxx_read(priv, reg);
576 if ((t & mask) == val)
577 return 0;
578
579 if (timeout-- <= 0)
580 break;
581
582 udelay(10);
583 cond_resched();
584 }
585
586 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
587 (unsigned int) reg, t, mask, val);
588 return -ETIMEDOUT;
589 }
590
591 static void
592 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
593 {
594 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
595 return;
596 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
597 val &= AR8216_VTUDATA_MEMBER;
598 val |= AR8216_VTUDATA_VALID;
599 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
600 }
601 op |= AR8216_VTU_ACTIVE;
602 ar8xxx_write(priv, AR8216_REG_VTU, op);
603 }
604
605 static void
606 ar8216_vtu_flush(struct ar8xxx_priv *priv)
607 {
608 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
609 }
610
611 static void
612 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
613 {
614 u32 op;
615
616 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
617 ar8216_vtu_op(priv, op, port_mask);
618 }
619
620 static int
621 ar8216_atu_flush(struct ar8xxx_priv *priv)
622 {
623 int ret;
624
625 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
626 if (!ret)
627 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
628 AR8216_ATU_ACTIVE);
629
630 return ret;
631 }
632
633 static int
634 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
635 {
636 u32 t;
637 int ret;
638
639 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
640 if (!ret) {
641 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
642 t |= AR8216_ATU_ACTIVE;
643 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
644 }
645
646 return ret;
647 }
648
649 static u32
650 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
651 {
652 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
653 }
654
655 static void
656 __ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members,
657 bool ath_hdr_en)
658 {
659 u32 header;
660 u32 egress, ingress;
661 u32 pvid;
662
663 if (priv->vlan) {
664 pvid = priv->vlan_id[priv->pvid[port]];
665 if (priv->vlan_tagged & (1 << port))
666 egress = AR8216_OUT_ADD_VLAN;
667 else
668 egress = AR8216_OUT_STRIP_VLAN;
669 ingress = AR8216_IN_SECURE;
670 } else {
671 pvid = port;
672 egress = AR8216_OUT_KEEP;
673 ingress = AR8216_IN_PORT_ONLY;
674 }
675
676 header = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0;
677
678 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
679 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
680 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
681 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
682 AR8216_PORT_CTRL_LEARN | header |
683 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
684 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
685
686 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
687 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
688 AR8216_PORT_VLAN_DEFAULT_ID,
689 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
690 (ingress << AR8216_PORT_VLAN_MODE_S) |
691 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
692 }
693
694 static void
695 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
696 {
697 return __ar8216_setup_port(priv, port, members,
698 chip_is_ar8216(priv) && priv->vlan &&
699 port == AR8216_PORT_CPU);
700 }
701
702 static int
703 ar8216_hw_init(struct ar8xxx_priv *priv)
704 {
705 if (priv->initialized)
706 return 0;
707
708 ar8xxx_phy_init(priv);
709
710 priv->initialized = true;
711 return 0;
712 }
713
714 static void
715 ar8216_init_globals(struct ar8xxx_priv *priv)
716 {
717 /* standard atheros magic */
718 ar8xxx_write(priv, 0x38, 0xc000050e);
719
720 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
721 AR8216_GCTRL_MTU, 1518 + 8 + 2);
722 }
723
724 static void
725 __ar8216_init_port(struct ar8xxx_priv *priv, int port,
726 bool cpu_ge, bool flow_en)
727 {
728 /* Enable port learning and tx */
729 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
730 AR8216_PORT_CTRL_LEARN |
731 (4 << AR8216_PORT_CTRL_STATE_S));
732
733 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
734
735 if (port == AR8216_PORT_CPU) {
736 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
737 AR8216_PORT_STATUS_LINK_UP |
738 (cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
739 AR8216_PORT_STATUS_TXMAC |
740 AR8216_PORT_STATUS_RXMAC |
741 (flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |
742 (flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |
743 AR8216_PORT_STATUS_DUPLEX);
744 } else {
745 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
746 AR8216_PORT_STATUS_LINK_AUTO);
747 }
748 }
749
750 static void
751 ar8216_init_port(struct ar8xxx_priv *priv, int port)
752 {
753 __ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
754 chip_is_ar8316(priv));
755 }
756
757 static void
758 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
759 {
760 int timeout = 20;
761
762 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
763 udelay(10);
764 cond_resched();
765 }
766
767 if (!timeout)
768 pr_err("ar8216: timeout waiting for atu to become ready\n");
769 }
770
771 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
772 struct arl_entry *a, u32 *status, enum arl_op op)
773 {
774 struct mii_bus *bus = priv->mii_bus;
775 u16 r2, page;
776 u16 r1_func0, r1_func1, r1_func2;
777 u32 t, val0, val1, val2;
778
779 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
780 r2 |= 0x10;
781
782 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
783 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
784
785 switch (op) {
786 case AR8XXX_ARL_INITIALIZE:
787 /* all ATU registers are on the same page
788 * therefore set page only once
789 */
790 bus->write(bus, 0x18, 0, page);
791 wait_for_page_switch();
792
793 ar8216_wait_atu_ready(priv, r2, r1_func0);
794
795 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
796 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
797 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
798 break;
799 case AR8XXX_ARL_GET_NEXT:
800 t = ar8xxx_mii_read32(priv, r2, r1_func0);
801 t |= AR8216_ATU_ACTIVE;
802 ar8xxx_mii_write32(priv, r2, r1_func0, t);
803 ar8216_wait_atu_ready(priv, r2, r1_func0);
804
805 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
806 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
807 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
808
809 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
810 if (!*status)
811 break;
812
813 a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
814 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
815 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
816 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
817 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
818 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
819 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
820 break;
821 }
822 }
823
824 static int
825 ar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum)
826 {
827 u32 t, val = 0xffff;
828 int err;
829
830 if (addr >= AR8216_NUM_PORTS)
831 return 0xffff;
832 t = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
833 (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
834 AR8216_MDIO_CTRL_MASTER_EN |
835 AR8216_MDIO_CTRL_BUSY |
836 AR8216_MDIO_CTRL_CMD_READ;
837
838 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
839 err = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
840 AR8216_MDIO_CTRL_BUSY, 0, 5);
841 if (!err)
842 val = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL);
843
844 return val & AR8216_MDIO_CTRL_DATA_M;
845 }
846
847 static int
848 ar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val)
849 {
850 u32 t;
851 int ret;
852
853 if (addr >= AR8216_NUM_PORTS)
854 return -EINVAL;
855
856 t = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
857 (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
858 AR8216_MDIO_CTRL_MASTER_EN |
859 AR8216_MDIO_CTRL_BUSY |
860 AR8216_MDIO_CTRL_CMD_WRITE |
861 val;
862
863 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
864 ret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
865 AR8216_MDIO_CTRL_BUSY, 0, 5);
866
867 return ret;
868 }
869
870 static int
871 ar8229_hw_init(struct ar8xxx_priv *priv)
872 {
873 int phy_if_mode;
874
875 if (priv->initialized)
876 return 0;
877
878 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
879 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
880
881 phy_if_mode = of_get_phy_mode(priv->pdev->of_node);
882
883 if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
884 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
885 AR8229_OPER_MODE0_MAC_GMII_EN);
886 } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
887 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
888 AR8229_OPER_MODE0_PHY_MII_EN);
889 } else {
890 pr_err("ar8229: unsupported mii mode\n");
891 return -EINVAL;
892 }
893
894 if (priv->port4_phy) {
895 ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
896 AR8229_REG_OPER_MODE1_PHY4_MII_EN);
897 /* disable port5 to prevent mii conflict */
898 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
899 }
900
901 ar8xxx_phy_init(priv);
902
903 priv->initialized = true;
904 return 0;
905 }
906
907 static void
908 ar8229_init_globals(struct ar8xxx_priv *priv)
909 {
910
911 /* Enable CPU port, and disable mirror port */
912 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
913 AR8216_GLOBAL_CPUPORT_EN |
914 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
915
916 /* Setup TAG priority mapping */
917 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
918
919 /* Enable aging, MAC replacing */
920 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
921 0x2b /* 5 min age time */ |
922 AR8216_ATU_CTRL_AGE_EN |
923 AR8216_ATU_CTRL_LEARN_CHANGE);
924
925 /* Enable ARP frame acknowledge */
926 ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
927 AR8229_QM_CTRL_ARP_EN);
928
929 /* Enable Broadcast/Multicast frames transmitted to the CPU */
930 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
931 AR8229_FLOOD_MASK_BC_DP(0) |
932 AR8229_FLOOD_MASK_MC_DP(0));
933
934 /* setup MTU */
935 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
936 AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);
937
938 /* Enable MIB counters */
939 ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,
940 AR8236_MIB_EN);
941
942 /* setup Service TAG */
943 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
944 }
945
946 static void
947 ar8229_init_port(struct ar8xxx_priv *priv, int port)
948 {
949 __ar8216_init_port(priv, port, true, true);
950 }
951
952
953 static int
954 ar7240sw_hw_init(struct ar8xxx_priv *priv)
955 {
956 if (priv->initialized)
957 return 0;
958
959 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
960 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
961
962 priv->port4_phy = 1;
963 /* disable port5 to prevent mii conflict */
964 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
965
966 ar8xxx_phy_init(priv);
967
968 priv->initialized = true;
969 return 0;
970 }
971
972 static void
973 ar7240sw_init_globals(struct ar8xxx_priv *priv)
974 {
975
976 /* Enable CPU port, and disable mirror port */
977 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
978 AR8216_GLOBAL_CPUPORT_EN |
979 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
980
981 /* Setup TAG priority mapping */
982 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
983
984 /* Enable ARP frame acknowledge, aging, MAC replacing */
985 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
986 AR8216_ATU_CTRL_RESERVED |
987 0x2b /* 5 min age time */ |
988 AR8216_ATU_CTRL_AGE_EN |
989 AR8216_ATU_CTRL_ARP_EN |
990 AR8216_ATU_CTRL_LEARN_CHANGE);
991
992 /* Enable Broadcast frames transmitted to the CPU */
993 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
994 AR8236_FM_CPU_BROADCAST_EN);
995
996 /* setup MTU */
997 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
998 AR8216_GCTRL_MTU,
999 AR8216_GCTRL_MTU);
1000
1001 /* setup Service TAG */
1002 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
1003 }
1004
1005 static void
1006 ar7240sw_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1007 {
1008 return __ar8216_setup_port(priv, port, members, false);
1009 }
1010
1011 static void
1012 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1013 {
1014 u32 egress, ingress;
1015 u32 pvid;
1016
1017 if (priv->vlan) {
1018 pvid = priv->vlan_id[priv->pvid[port]];
1019 if (priv->vlan_tagged & (1 << port))
1020 egress = AR8216_OUT_ADD_VLAN;
1021 else
1022 egress = AR8216_OUT_STRIP_VLAN;
1023 ingress = AR8216_IN_SECURE;
1024 } else {
1025 pvid = port;
1026 egress = AR8216_OUT_KEEP;
1027 ingress = AR8216_IN_PORT_ONLY;
1028 }
1029
1030 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1031 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
1032 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
1033 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
1034 AR8216_PORT_CTRL_LEARN |
1035 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
1036 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
1037
1038 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
1039 AR8236_PORT_VLAN_DEFAULT_ID,
1040 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
1041
1042 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
1043 AR8236_PORT_VLAN2_VLAN_MODE |
1044 AR8236_PORT_VLAN2_MEMBER,
1045 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
1046 (members << AR8236_PORT_VLAN2_MEMBER_S));
1047 }
1048
1049 static void
1050 ar8236_init_globals(struct ar8xxx_priv *priv)
1051 {
1052 /* enable jumbo frames */
1053 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1054 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1055
1056 /* enable cpu port to receive arp frames */
1057 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
1058 AR8236_ATU_CTRL_RES);
1059
1060 /* enable cpu port to receive multicast and broadcast frames */
1061 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
1062 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
1063
1064 /* Enable MIB counters */
1065 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1066 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1067 AR8236_MIB_EN);
1068 }
1069
1070 static int
1071 ar8316_hw_init(struct ar8xxx_priv *priv)
1072 {
1073 u32 val, newval;
1074
1075 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
1076
1077 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1078 if (priv->port4_phy) {
1079 /* value taken from Ubiquiti RouterStation Pro */
1080 newval = 0x81461bea;
1081 pr_info("ar8316: Using port 4 as PHY\n");
1082 } else {
1083 newval = 0x01261be2;
1084 pr_info("ar8316: Using port 4 as switch port\n");
1085 }
1086 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
1087 /* value taken from AVM Fritz!Box 7390 sources */
1088 newval = 0x010e5b71;
1089 } else {
1090 /* no known value for phy interface */
1091 pr_err("ar8316: unsupported mii mode: %d.\n",
1092 priv->phy->interface);
1093 return -EINVAL;
1094 }
1095
1096 if (val == newval)
1097 goto out;
1098
1099 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
1100
1101 if (priv->port4_phy &&
1102 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1103 /* work around for phy4 rgmii mode */
1104 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1105 /* rx delay */
1106 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1107 /* tx delay */
1108 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1109 msleep(1000);
1110 }
1111
1112 ar8xxx_phy_init(priv);
1113
1114 out:
1115 priv->initialized = true;
1116 return 0;
1117 }
1118
1119 static void
1120 ar8316_init_globals(struct ar8xxx_priv *priv)
1121 {
1122 /* standard atheros magic */
1123 ar8xxx_write(priv, 0x38, 0xc000050e);
1124
1125 /* enable cpu port to receive multicast and broadcast frames */
1126 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1127
1128 /* enable jumbo frames */
1129 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1130 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1131
1132 /* Enable MIB counters */
1133 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1134 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1135 AR8236_MIB_EN);
1136 }
1137
1138 int
1139 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1140 struct switch_val *val)
1141 {
1142 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1143 priv->vlan = !!val->value.i;
1144 return 0;
1145 }
1146
1147 int
1148 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1149 struct switch_val *val)
1150 {
1151 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1152 val->value.i = priv->vlan;
1153 return 0;
1154 }
1155
1156
1157 int
1158 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1159 {
1160 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1161
1162 /* make sure no invalid PVIDs get set */
1163
1164 if (vlan < 0 || vlan >= dev->vlans ||
1165 port < 0 || port >= AR8X16_MAX_PORTS)
1166 return -EINVAL;
1167
1168 priv->pvid[port] = vlan;
1169 return 0;
1170 }
1171
1172 int
1173 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1174 {
1175 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1176
1177 if (port < 0 || port >= AR8X16_MAX_PORTS)
1178 return -EINVAL;
1179
1180 *vlan = priv->pvid[port];
1181 return 0;
1182 }
1183
1184 static int
1185 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1186 struct switch_val *val)
1187 {
1188 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1189
1190 if (val->port_vlan >= AR8X16_MAX_VLANS)
1191 return -EINVAL;
1192
1193 priv->vlan_id[val->port_vlan] = val->value.i;
1194 return 0;
1195 }
1196
1197 static int
1198 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1199 struct switch_val *val)
1200 {
1201 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1202 val->value.i = priv->vlan_id[val->port_vlan];
1203 return 0;
1204 }
1205
1206 int
1207 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1208 struct switch_port_link *link)
1209 {
1210 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1211
1212 ar8216_read_port_link(priv, port, link);
1213 return 0;
1214 }
1215
1216 static int
1217 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1218 {
1219 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1220 u8 ports;
1221 int i;
1222
1223 if (val->port_vlan >= AR8X16_MAX_VLANS)
1224 return -EINVAL;
1225
1226 ports = priv->vlan_table[val->port_vlan];
1227 val->len = 0;
1228 for (i = 0; i < dev->ports; i++) {
1229 struct switch_port *p;
1230
1231 if (!(ports & (1 << i)))
1232 continue;
1233
1234 p = &val->value.ports[val->len++];
1235 p->id = i;
1236 if (priv->vlan_tagged & (1 << i))
1237 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1238 else
1239 p->flags = 0;
1240 }
1241 return 0;
1242 }
1243
1244 static int
1245 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1246 {
1247 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1248 u8 *vt = &priv->vlan_table[val->port_vlan];
1249 int i, j;
1250
1251 *vt = 0;
1252 for (i = 0; i < val->len; i++) {
1253 struct switch_port *p = &val->value.ports[i];
1254
1255 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1256 priv->vlan_tagged |= (1 << p->id);
1257 } else {
1258 priv->vlan_tagged &= ~(1 << p->id);
1259 priv->pvid[p->id] = val->port_vlan;
1260
1261 /* make sure that an untagged port does not
1262 * appear in other vlans */
1263 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1264 if (j == val->port_vlan)
1265 continue;
1266 priv->vlan_table[j] &= ~(1 << p->id);
1267 }
1268 }
1269
1270 *vt |= 1 << p->id;
1271 }
1272 return 0;
1273 }
1274
1275 static void
1276 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1277 {
1278 int port;
1279
1280 /* reset all mirror registers */
1281 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1282 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1283 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1284 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1285 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1286 AR8216_PORT_CTRL_MIRROR_RX);
1287
1288 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1289 AR8216_PORT_CTRL_MIRROR_TX);
1290 }
1291
1292 /* now enable mirroring if necessary */
1293 if (priv->source_port >= AR8216_NUM_PORTS ||
1294 priv->monitor_port >= AR8216_NUM_PORTS ||
1295 priv->source_port == priv->monitor_port) {
1296 return;
1297 }
1298
1299 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1300 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1301 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1302
1303 if (priv->mirror_rx)
1304 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1305 AR8216_PORT_CTRL_MIRROR_RX);
1306
1307 if (priv->mirror_tx)
1308 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1309 AR8216_PORT_CTRL_MIRROR_TX);
1310 }
1311
1312 static inline u32
1313 ar8xxx_age_time_val(int age_time)
1314 {
1315 return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1316 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1317 }
1318
1319 static inline void
1320 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1321 {
1322 u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1323 ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1324 }
1325
1326 int
1327 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1328 {
1329 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1330 const struct ar8xxx_chip *chip = priv->chip;
1331 u8 portmask[AR8X16_MAX_PORTS];
1332 int i, j;
1333
1334 mutex_lock(&priv->reg_mutex);
1335 /* flush all vlan translation unit entries */
1336 priv->chip->vtu_flush(priv);
1337
1338 memset(portmask, 0, sizeof(portmask));
1339 if (!priv->init) {
1340 /* calculate the port destination masks and load vlans
1341 * into the vlan translation unit */
1342 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1343 u8 vp = priv->vlan_table[j];
1344
1345 if (!vp)
1346 continue;
1347
1348 for (i = 0; i < dev->ports; i++) {
1349 u8 mask = (1 << i);
1350 if (vp & mask)
1351 portmask[i] |= vp & ~mask;
1352 }
1353
1354 chip->vtu_load_vlan(priv, priv->vlan_id[j],
1355 priv->vlan_table[j]);
1356 }
1357 } else {
1358 /* vlan disabled:
1359 * isolate all ports, but connect them to the cpu port */
1360 for (i = 0; i < dev->ports; i++) {
1361 if (i == AR8216_PORT_CPU)
1362 continue;
1363
1364 portmask[i] = 1 << AR8216_PORT_CPU;
1365 portmask[AR8216_PORT_CPU] |= (1 << i);
1366 }
1367 }
1368
1369 /* update the port destination mask registers and tag settings */
1370 for (i = 0; i < dev->ports; i++) {
1371 chip->setup_port(priv, i, portmask[i]);
1372 }
1373
1374 chip->set_mirror_regs(priv);
1375
1376 /* set age time */
1377 if (chip->reg_arl_ctrl)
1378 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1379
1380 mutex_unlock(&priv->reg_mutex);
1381 return 0;
1382 }
1383
1384 int
1385 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1386 {
1387 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1388 const struct ar8xxx_chip *chip = priv->chip;
1389 int i;
1390
1391 mutex_lock(&priv->reg_mutex);
1392 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1393 offsetof(struct ar8xxx_priv, vlan));
1394
1395 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1396 priv->vlan_id[i] = i;
1397
1398 /* Configure all ports */
1399 for (i = 0; i < dev->ports; i++)
1400 chip->init_port(priv, i);
1401
1402 priv->mirror_rx = false;
1403 priv->mirror_tx = false;
1404 priv->source_port = 0;
1405 priv->monitor_port = 0;
1406 priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1407
1408 chip->init_globals(priv);
1409 chip->atu_flush(priv);
1410
1411 mutex_unlock(&priv->reg_mutex);
1412
1413 return chip->sw_hw_apply(dev);
1414 }
1415
1416 int
1417 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1418 const struct switch_attr *attr,
1419 struct switch_val *val)
1420 {
1421 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1422 unsigned int len;
1423 int ret;
1424
1425 if (!ar8xxx_has_mib_counters(priv))
1426 return -EOPNOTSUPP;
1427
1428 mutex_lock(&priv->mib_lock);
1429
1430 len = priv->dev.ports * priv->chip->num_mibs *
1431 sizeof(*priv->mib_stats);
1432 memset(priv->mib_stats, '\0', len);
1433 ret = ar8xxx_mib_flush(priv);
1434 if (ret)
1435 goto unlock;
1436
1437 ret = 0;
1438
1439 unlock:
1440 mutex_unlock(&priv->mib_lock);
1441 return ret;
1442 }
1443
1444 int
1445 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1446 const struct switch_attr *attr,
1447 struct switch_val *val)
1448 {
1449 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1450
1451 mutex_lock(&priv->reg_mutex);
1452 priv->mirror_rx = !!val->value.i;
1453 priv->chip->set_mirror_regs(priv);
1454 mutex_unlock(&priv->reg_mutex);
1455
1456 return 0;
1457 }
1458
1459 int
1460 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1461 const struct switch_attr *attr,
1462 struct switch_val *val)
1463 {
1464 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1465 val->value.i = priv->mirror_rx;
1466 return 0;
1467 }
1468
1469 int
1470 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1471 const struct switch_attr *attr,
1472 struct switch_val *val)
1473 {
1474 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1475
1476 mutex_lock(&priv->reg_mutex);
1477 priv->mirror_tx = !!val->value.i;
1478 priv->chip->set_mirror_regs(priv);
1479 mutex_unlock(&priv->reg_mutex);
1480
1481 return 0;
1482 }
1483
1484 int
1485 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1486 const struct switch_attr *attr,
1487 struct switch_val *val)
1488 {
1489 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1490 val->value.i = priv->mirror_tx;
1491 return 0;
1492 }
1493
1494 int
1495 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1496 const struct switch_attr *attr,
1497 struct switch_val *val)
1498 {
1499 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1500
1501 mutex_lock(&priv->reg_mutex);
1502 priv->monitor_port = val->value.i;
1503 priv->chip->set_mirror_regs(priv);
1504 mutex_unlock(&priv->reg_mutex);
1505
1506 return 0;
1507 }
1508
1509 int
1510 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1511 const struct switch_attr *attr,
1512 struct switch_val *val)
1513 {
1514 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1515 val->value.i = priv->monitor_port;
1516 return 0;
1517 }
1518
1519 int
1520 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1521 const struct switch_attr *attr,
1522 struct switch_val *val)
1523 {
1524 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1525
1526 mutex_lock(&priv->reg_mutex);
1527 priv->source_port = val->value.i;
1528 priv->chip->set_mirror_regs(priv);
1529 mutex_unlock(&priv->reg_mutex);
1530
1531 return 0;
1532 }
1533
1534 int
1535 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1536 const struct switch_attr *attr,
1537 struct switch_val *val)
1538 {
1539 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1540 val->value.i = priv->source_port;
1541 return 0;
1542 }
1543
1544 int
1545 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1546 const struct switch_attr *attr,
1547 struct switch_val *val)
1548 {
1549 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1550 int port;
1551 int ret;
1552
1553 if (!ar8xxx_has_mib_counters(priv))
1554 return -EOPNOTSUPP;
1555
1556 port = val->port_vlan;
1557 if (port >= dev->ports)
1558 return -EINVAL;
1559
1560 mutex_lock(&priv->mib_lock);
1561 ret = ar8xxx_mib_capture(priv);
1562 if (ret)
1563 goto unlock;
1564
1565 ar8xxx_mib_fetch_port_stat(priv, port, true);
1566
1567 ret = 0;
1568
1569 unlock:
1570 mutex_unlock(&priv->mib_lock);
1571 return ret;
1572 }
1573
1574 static void
1575 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1576 {
1577 unsigned long b;
1578 const char *unit;
1579
1580 if (byte >= 0x40000000) { /* 1 GiB */
1581 b = byte * 10 / 0x40000000;
1582 unit = "GiB";
1583 } else if (byte >= 0x100000) { /* 1 MiB */
1584 b = byte * 10 / 0x100000;
1585 unit = "MiB";
1586 } else if (byte >= 0x400) { /* 1 KiB */
1587 b = byte * 10 / 0x400;
1588 unit = "KiB";
1589 } else {
1590 b = byte;
1591 unit = "Byte";
1592 }
1593 if (strcmp(unit, "Byte"))
1594 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1595 else
1596 snprintf(buf, len, "%lu %s", b, unit);
1597 }
1598
1599 int
1600 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1601 const struct switch_attr *attr,
1602 struct switch_val *val)
1603 {
1604 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1605 const struct ar8xxx_chip *chip = priv->chip;
1606 u64 *mib_stats, mib_data;
1607 unsigned int port;
1608 int ret;
1609 char *buf = priv->buf;
1610 char buf1[64];
1611 const char *mib_name;
1612 int i, len = 0;
1613 bool mib_stats_empty = true;
1614
1615 if (!ar8xxx_has_mib_counters(priv))
1616 return -EOPNOTSUPP;
1617
1618 port = val->port_vlan;
1619 if (port >= dev->ports)
1620 return -EINVAL;
1621
1622 mutex_lock(&priv->mib_lock);
1623 ret = ar8xxx_mib_capture(priv);
1624 if (ret)
1625 goto unlock;
1626
1627 ar8xxx_mib_fetch_port_stat(priv, port, false);
1628
1629 len += snprintf(buf + len, sizeof(priv->buf) - len,
1630 "MIB counters\n");
1631
1632 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1633 for (i = 0; i < chip->num_mibs; i++) {
1634 mib_name = chip->mib_decs[i].name;
1635 mib_data = mib_stats[i];
1636 len += snprintf(buf + len, sizeof(priv->buf) - len,
1637 "%-12s: %llu\n", mib_name, mib_data);
1638 if ((!strcmp(mib_name, "TxByte") ||
1639 !strcmp(mib_name, "RxGoodByte")) &&
1640 mib_data >= 1024) {
1641 ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1642 --len; /* discard newline at the end of buf */
1643 len += snprintf(buf + len, sizeof(priv->buf) - len,
1644 " (%s)\n", buf1);
1645 }
1646 if (mib_stats_empty && mib_data)
1647 mib_stats_empty = false;
1648 }
1649
1650 if (mib_stats_empty)
1651 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1652
1653 val->value.s = buf;
1654 val->len = len;
1655
1656 ret = 0;
1657
1658 unlock:
1659 mutex_unlock(&priv->mib_lock);
1660 return ret;
1661 }
1662
1663 int
1664 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1665 struct switch_val *val)
1666 {
1667 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1668 int age_time = val->value.i;
1669 u32 age_time_val;
1670
1671 if (age_time < 0)
1672 return -EINVAL;
1673
1674 age_time_val = ar8xxx_age_time_val(age_time);
1675 if (age_time_val == 0 || age_time_val > 0xffff)
1676 return -EINVAL;
1677
1678 priv->arl_age_time = age_time;
1679 return 0;
1680 }
1681
1682 int
1683 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1684 struct switch_val *val)
1685 {
1686 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1687 val->value.i = priv->arl_age_time;
1688 return 0;
1689 }
1690
1691 int
1692 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1693 const struct switch_attr *attr,
1694 struct switch_val *val)
1695 {
1696 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1697 struct mii_bus *bus = priv->mii_bus;
1698 const struct ar8xxx_chip *chip = priv->chip;
1699 char *buf = priv->arl_buf;
1700 int i, j, k, len = 0;
1701 struct arl_entry *a, *a1;
1702 u32 status;
1703
1704 if (!chip->get_arl_entry)
1705 return -EOPNOTSUPP;
1706
1707 mutex_lock(&priv->reg_mutex);
1708 mutex_lock(&bus->mdio_lock);
1709
1710 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1711
1712 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1713 a = &priv->arl_table[i];
1714 duplicate:
1715 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1716
1717 if (!status)
1718 break;
1719
1720 /* avoid duplicates
1721 * ARL table can include multiple valid entries
1722 * per MAC, just with differing status codes
1723 */
1724 for (j = 0; j < i; ++j) {
1725 a1 = &priv->arl_table[j];
1726 if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
1727 /* ignore ports already seen in former entry */
1728 a->portmap &= ~a1->portmap;
1729 if (!a->portmap)
1730 goto duplicate;
1731 }
1732 }
1733 }
1734
1735 mutex_unlock(&bus->mdio_lock);
1736
1737 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1738 "address resolution table\n");
1739
1740 if (i == AR8XXX_NUM_ARL_RECORDS)
1741 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1742 "Too many entries found, displaying the first %d only!\n",
1743 AR8XXX_NUM_ARL_RECORDS);
1744
1745 for (j = 0; j < priv->dev.ports; ++j) {
1746 for (k = 0; k < i; ++k) {
1747 a = &priv->arl_table[k];
1748 if (!(a->portmap & BIT(j)))
1749 continue;
1750 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1751 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1752 j,
1753 a->mac[5], a->mac[4], a->mac[3],
1754 a->mac[2], a->mac[1], a->mac[0]);
1755 }
1756 }
1757
1758 val->value.s = buf;
1759 val->len = len;
1760
1761 mutex_unlock(&priv->reg_mutex);
1762
1763 return 0;
1764 }
1765
1766 int
1767 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1768 const struct switch_attr *attr,
1769 struct switch_val *val)
1770 {
1771 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1772 int ret;
1773
1774 mutex_lock(&priv->reg_mutex);
1775 ret = priv->chip->atu_flush(priv);
1776 mutex_unlock(&priv->reg_mutex);
1777
1778 return ret;
1779 }
1780
1781 int
1782 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1783 const struct switch_attr *attr,
1784 struct switch_val *val)
1785 {
1786 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1787 int port, ret;
1788
1789 port = val->port_vlan;
1790 if (port >= dev->ports)
1791 return -EINVAL;
1792
1793 mutex_lock(&priv->reg_mutex);
1794 ret = priv->chip->atu_flush_port(priv, port);
1795 mutex_unlock(&priv->reg_mutex);
1796
1797 return ret;
1798 }
1799
1800 static int
1801 ar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
1802 {
1803 struct ar8xxx_priv *priv = bus->priv;
1804 return priv->chip->phy_read(priv, phy_addr, reg_addr);
1805 }
1806
1807 static int
1808 ar8xxx_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr,
1809 u16 reg_val)
1810 {
1811 struct ar8xxx_priv *priv = bus->priv;
1812 return priv->chip->phy_write(priv, phy_addr, reg_addr, reg_val);
1813 }
1814
1815 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1816 {
1817 .type = SWITCH_TYPE_INT,
1818 .name = "enable_vlan",
1819 .description = "Enable VLAN mode",
1820 .set = ar8xxx_sw_set_vlan,
1821 .get = ar8xxx_sw_get_vlan,
1822 .max = 1
1823 },
1824 {
1825 .type = SWITCH_TYPE_NOVAL,
1826 .name = "reset_mibs",
1827 .description = "Reset all MIB counters",
1828 .set = ar8xxx_sw_set_reset_mibs,
1829 },
1830 {
1831 .type = SWITCH_TYPE_INT,
1832 .name = "enable_mirror_rx",
1833 .description = "Enable mirroring of RX packets",
1834 .set = ar8xxx_sw_set_mirror_rx_enable,
1835 .get = ar8xxx_sw_get_mirror_rx_enable,
1836 .max = 1
1837 },
1838 {
1839 .type = SWITCH_TYPE_INT,
1840 .name = "enable_mirror_tx",
1841 .description = "Enable mirroring of TX packets",
1842 .set = ar8xxx_sw_set_mirror_tx_enable,
1843 .get = ar8xxx_sw_get_mirror_tx_enable,
1844 .max = 1
1845 },
1846 {
1847 .type = SWITCH_TYPE_INT,
1848 .name = "mirror_monitor_port",
1849 .description = "Mirror monitor port",
1850 .set = ar8xxx_sw_set_mirror_monitor_port,
1851 .get = ar8xxx_sw_get_mirror_monitor_port,
1852 .max = AR8216_NUM_PORTS - 1
1853 },
1854 {
1855 .type = SWITCH_TYPE_INT,
1856 .name = "mirror_source_port",
1857 .description = "Mirror source port",
1858 .set = ar8xxx_sw_set_mirror_source_port,
1859 .get = ar8xxx_sw_get_mirror_source_port,
1860 .max = AR8216_NUM_PORTS - 1
1861 },
1862 {
1863 .type = SWITCH_TYPE_STRING,
1864 .name = "arl_table",
1865 .description = "Get ARL table",
1866 .set = NULL,
1867 .get = ar8xxx_sw_get_arl_table,
1868 },
1869 {
1870 .type = SWITCH_TYPE_NOVAL,
1871 .name = "flush_arl_table",
1872 .description = "Flush ARL table",
1873 .set = ar8xxx_sw_set_flush_arl_table,
1874 },
1875 };
1876
1877 const struct switch_attr ar8xxx_sw_attr_port[] = {
1878 {
1879 .type = SWITCH_TYPE_NOVAL,
1880 .name = "reset_mib",
1881 .description = "Reset single port MIB counters",
1882 .set = ar8xxx_sw_set_port_reset_mib,
1883 },
1884 {
1885 .type = SWITCH_TYPE_STRING,
1886 .name = "mib",
1887 .description = "Get port's MIB counters",
1888 .set = NULL,
1889 .get = ar8xxx_sw_get_port_mib,
1890 },
1891 {
1892 .type = SWITCH_TYPE_NOVAL,
1893 .name = "flush_arl_table",
1894 .description = "Flush port's ARL table entries",
1895 .set = ar8xxx_sw_set_flush_port_arl_table,
1896 },
1897 };
1898
1899 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1900 {
1901 .type = SWITCH_TYPE_INT,
1902 .name = "vid",
1903 .description = "VLAN ID (0-4094)",
1904 .set = ar8xxx_sw_set_vid,
1905 .get = ar8xxx_sw_get_vid,
1906 .max = 4094,
1907 },
1908 };
1909
1910 static const struct switch_dev_ops ar8xxx_sw_ops = {
1911 .attr_global = {
1912 .attr = ar8xxx_sw_attr_globals,
1913 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1914 },
1915 .attr_port = {
1916 .attr = ar8xxx_sw_attr_port,
1917 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1918 },
1919 .attr_vlan = {
1920 .attr = ar8xxx_sw_attr_vlan,
1921 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1922 },
1923 .get_port_pvid = ar8xxx_sw_get_pvid,
1924 .set_port_pvid = ar8xxx_sw_set_pvid,
1925 .get_vlan_ports = ar8xxx_sw_get_ports,
1926 .set_vlan_ports = ar8xxx_sw_set_ports,
1927 .apply_config = ar8xxx_sw_hw_apply,
1928 .reset_switch = ar8xxx_sw_reset_switch,
1929 .get_port_link = ar8xxx_sw_get_port_link,
1930 /* The following op is disabled as it hogs the CPU and degrades performance.
1931 An implementation has been attempted in 4d8a66d but reading MIB data is slow
1932 on ar8xxx switches.
1933
1934 The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1935 ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1936 the request to update the MIB counter is cleared. */
1937 #if 0
1938 .get_port_stats = ar8xxx_sw_get_port_stats,
1939 #endif
1940 };
1941
1942 static const struct ar8xxx_chip ar7240sw_chip = {
1943 .caps = AR8XXX_CAP_MIB_COUNTERS,
1944
1945 .reg_port_stats_start = 0x20000,
1946 .reg_port_stats_length = 0x100,
1947 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1948
1949 .name = "Atheros AR724X/AR933X built-in",
1950 .ports = AR7240SW_NUM_PORTS,
1951 .vlans = AR8216_NUM_VLANS,
1952 .swops = &ar8xxx_sw_ops,
1953
1954 .hw_init = ar7240sw_hw_init,
1955 .init_globals = ar7240sw_init_globals,
1956 .init_port = ar8229_init_port,
1957 .phy_read = ar8216_phy_read,
1958 .phy_write = ar8216_phy_write,
1959 .setup_port = ar7240sw_setup_port,
1960 .read_port_status = ar8216_read_port_status,
1961 .atu_flush = ar8216_atu_flush,
1962 .atu_flush_port = ar8216_atu_flush_port,
1963 .vtu_flush = ar8216_vtu_flush,
1964 .vtu_load_vlan = ar8216_vtu_load_vlan,
1965 .set_mirror_regs = ar8216_set_mirror_regs,
1966 .get_arl_entry = ar8216_get_arl_entry,
1967 .sw_hw_apply = ar8xxx_sw_hw_apply,
1968
1969 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1970 .mib_decs = ar8236_mibs,
1971 .mib_func = AR8216_REG_MIB_FUNC
1972 };
1973
1974 static const struct ar8xxx_chip ar8216_chip = {
1975 .caps = AR8XXX_CAP_MIB_COUNTERS,
1976
1977 .reg_port_stats_start = 0x19000,
1978 .reg_port_stats_length = 0xa0,
1979 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1980
1981 .name = "Atheros AR8216",
1982 .ports = AR8216_NUM_PORTS,
1983 .vlans = AR8216_NUM_VLANS,
1984 .swops = &ar8xxx_sw_ops,
1985
1986 .hw_init = ar8216_hw_init,
1987 .init_globals = ar8216_init_globals,
1988 .init_port = ar8216_init_port,
1989 .setup_port = ar8216_setup_port,
1990 .read_port_status = ar8216_read_port_status,
1991 .atu_flush = ar8216_atu_flush,
1992 .atu_flush_port = ar8216_atu_flush_port,
1993 .vtu_flush = ar8216_vtu_flush,
1994 .vtu_load_vlan = ar8216_vtu_load_vlan,
1995 .set_mirror_regs = ar8216_set_mirror_regs,
1996 .get_arl_entry = ar8216_get_arl_entry,
1997 .sw_hw_apply = ar8xxx_sw_hw_apply,
1998
1999 .num_mibs = ARRAY_SIZE(ar8216_mibs),
2000 .mib_decs = ar8216_mibs,
2001 .mib_func = AR8216_REG_MIB_FUNC
2002 };
2003
2004 static const struct ar8xxx_chip ar8229_chip = {
2005 .caps = AR8XXX_CAP_MIB_COUNTERS,
2006
2007 .reg_port_stats_start = 0x20000,
2008 .reg_port_stats_length = 0x100,
2009 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2010
2011 .name = "Atheros AR8229",
2012 .ports = AR8216_NUM_PORTS,
2013 .vlans = AR8216_NUM_VLANS,
2014 .swops = &ar8xxx_sw_ops,
2015
2016 .hw_init = ar8229_hw_init,
2017 .init_globals = ar8229_init_globals,
2018 .init_port = ar8229_init_port,
2019 .phy_read = ar8216_phy_read,
2020 .phy_write = ar8216_phy_write,
2021 .setup_port = ar8236_setup_port,
2022 .read_port_status = ar8216_read_port_status,
2023 .atu_flush = ar8216_atu_flush,
2024 .atu_flush_port = ar8216_atu_flush_port,
2025 .vtu_flush = ar8216_vtu_flush,
2026 .vtu_load_vlan = ar8216_vtu_load_vlan,
2027 .set_mirror_regs = ar8216_set_mirror_regs,
2028 .get_arl_entry = ar8216_get_arl_entry,
2029 .sw_hw_apply = ar8xxx_sw_hw_apply,
2030
2031 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2032 .mib_decs = ar8236_mibs,
2033 .mib_func = AR8216_REG_MIB_FUNC
2034 };
2035
2036 static const struct ar8xxx_chip ar8236_chip = {
2037 .caps = AR8XXX_CAP_MIB_COUNTERS,
2038
2039 .reg_port_stats_start = 0x20000,
2040 .reg_port_stats_length = 0x100,
2041 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2042
2043 .name = "Atheros AR8236",
2044 .ports = AR8216_NUM_PORTS,
2045 .vlans = AR8216_NUM_VLANS,
2046 .swops = &ar8xxx_sw_ops,
2047
2048 .hw_init = ar8216_hw_init,
2049 .init_globals = ar8236_init_globals,
2050 .init_port = ar8216_init_port,
2051 .setup_port = ar8236_setup_port,
2052 .read_port_status = ar8216_read_port_status,
2053 .atu_flush = ar8216_atu_flush,
2054 .atu_flush_port = ar8216_atu_flush_port,
2055 .vtu_flush = ar8216_vtu_flush,
2056 .vtu_load_vlan = ar8216_vtu_load_vlan,
2057 .set_mirror_regs = ar8216_set_mirror_regs,
2058 .get_arl_entry = ar8216_get_arl_entry,
2059 .sw_hw_apply = ar8xxx_sw_hw_apply,
2060
2061 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2062 .mib_decs = ar8236_mibs,
2063 .mib_func = AR8216_REG_MIB_FUNC
2064 };
2065
2066 static const struct ar8xxx_chip ar8316_chip = {
2067 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2068
2069 .reg_port_stats_start = 0x20000,
2070 .reg_port_stats_length = 0x100,
2071 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2072
2073 .name = "Atheros AR8316",
2074 .ports = AR8216_NUM_PORTS,
2075 .vlans = AR8X16_MAX_VLANS,
2076 .swops = &ar8xxx_sw_ops,
2077
2078 .hw_init = ar8316_hw_init,
2079 .init_globals = ar8316_init_globals,
2080 .init_port = ar8216_init_port,
2081 .setup_port = ar8216_setup_port,
2082 .read_port_status = ar8216_read_port_status,
2083 .atu_flush = ar8216_atu_flush,
2084 .atu_flush_port = ar8216_atu_flush_port,
2085 .vtu_flush = ar8216_vtu_flush,
2086 .vtu_load_vlan = ar8216_vtu_load_vlan,
2087 .set_mirror_regs = ar8216_set_mirror_regs,
2088 .get_arl_entry = ar8216_get_arl_entry,
2089 .sw_hw_apply = ar8xxx_sw_hw_apply,
2090
2091 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2092 .mib_decs = ar8236_mibs,
2093 .mib_func = AR8216_REG_MIB_FUNC
2094 };
2095
2096 static int
2097 ar8xxx_read_id(struct ar8xxx_priv *priv)
2098 {
2099 u32 val;
2100 u16 id;
2101 int i;
2102
2103 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2104 if (val == ~0)
2105 return -ENODEV;
2106
2107 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2108 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2109 u16 t;
2110
2111 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2112 if (val == ~0)
2113 return -ENODEV;
2114
2115 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2116 if (t != id)
2117 return -ENODEV;
2118 }
2119
2120 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2121 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2122 return 0;
2123 }
2124
2125 static int
2126 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2127 {
2128 int ret;
2129
2130 ret = ar8xxx_read_id(priv);
2131 if(ret)
2132 return ret;
2133
2134 switch (priv->chip_ver) {
2135 case AR8XXX_VER_AR8216:
2136 priv->chip = &ar8216_chip;
2137 break;
2138 case AR8XXX_VER_AR8236:
2139 priv->chip = &ar8236_chip;
2140 break;
2141 case AR8XXX_VER_AR8316:
2142 priv->chip = &ar8316_chip;
2143 break;
2144 case AR8XXX_VER_AR8327:
2145 priv->chip = &ar8327_chip;
2146 break;
2147 case AR8XXX_VER_AR8337:
2148 priv->chip = &ar8337_chip;
2149 break;
2150 default:
2151 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2152 priv->chip_ver, priv->chip_rev);
2153
2154 return -ENODEV;
2155 }
2156
2157 return 0;
2158 }
2159
2160 static void
2161 ar8xxx_mib_work_func(struct work_struct *work)
2162 {
2163 struct ar8xxx_priv *priv;
2164 int err;
2165
2166 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2167
2168 mutex_lock(&priv->mib_lock);
2169
2170 err = ar8xxx_mib_capture(priv);
2171 if (err)
2172 goto next_port;
2173
2174 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2175
2176 next_port:
2177 priv->mib_next_port++;
2178 if (priv->mib_next_port >= priv->dev.ports)
2179 priv->mib_next_port = 0;
2180
2181 mutex_unlock(&priv->mib_lock);
2182 schedule_delayed_work(&priv->mib_work,
2183 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2184 }
2185
2186 static int
2187 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2188 {
2189 unsigned int len;
2190
2191 if (!ar8xxx_has_mib_counters(priv))
2192 return 0;
2193
2194 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2195
2196 len = priv->dev.ports * priv->chip->num_mibs *
2197 sizeof(*priv->mib_stats);
2198 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2199
2200 if (!priv->mib_stats)
2201 return -ENOMEM;
2202
2203 return 0;
2204 }
2205
2206 static void
2207 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2208 {
2209 if (!ar8xxx_has_mib_counters(priv))
2210 return;
2211
2212 schedule_delayed_work(&priv->mib_work,
2213 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2214 }
2215
2216 static void
2217 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2218 {
2219 if (!ar8xxx_has_mib_counters(priv))
2220 return;
2221
2222 cancel_delayed_work_sync(&priv->mib_work);
2223 }
2224
2225 static struct ar8xxx_priv *
2226 ar8xxx_create(void)
2227 {
2228 struct ar8xxx_priv *priv;
2229
2230 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2231 if (priv == NULL)
2232 return NULL;
2233
2234 mutex_init(&priv->reg_mutex);
2235 mutex_init(&priv->mib_lock);
2236 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2237
2238 return priv;
2239 }
2240
2241 static void
2242 ar8xxx_free(struct ar8xxx_priv *priv)
2243 {
2244 if (priv->chip && priv->chip->cleanup)
2245 priv->chip->cleanup(priv);
2246
2247 kfree(priv->chip_data);
2248 kfree(priv->mib_stats);
2249 kfree(priv);
2250 }
2251
2252 static int
2253 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2254 {
2255 const struct ar8xxx_chip *chip;
2256 struct switch_dev *swdev;
2257 int ret;
2258
2259 chip = priv->chip;
2260
2261 swdev = &priv->dev;
2262 swdev->cpu_port = AR8216_PORT_CPU;
2263 swdev->name = chip->name;
2264 swdev->vlans = chip->vlans;
2265 swdev->ports = chip->ports;
2266 swdev->ops = chip->swops;
2267
2268 ret = ar8xxx_mib_init(priv);
2269 if (ret)
2270 return ret;
2271
2272 return 0;
2273 }
2274
2275 static int
2276 ar8xxx_start(struct ar8xxx_priv *priv)
2277 {
2278 int ret;
2279
2280 priv->init = true;
2281
2282 ret = priv->chip->hw_init(priv);
2283 if (ret)
2284 return ret;
2285
2286 ret = ar8xxx_sw_reset_switch(&priv->dev);
2287 if (ret)
2288 return ret;
2289
2290 priv->init = false;
2291
2292 ar8xxx_mib_start(priv);
2293
2294 return 0;
2295 }
2296
2297 static int
2298 ar8xxx_phy_config_init(struct phy_device *phydev)
2299 {
2300 struct ar8xxx_priv *priv = phydev->priv;
2301 struct net_device *dev = phydev->attached_dev;
2302 int ret;
2303
2304 if (WARN_ON(!priv))
2305 return -ENODEV;
2306
2307 if (priv->chip->config_at_probe)
2308 return ar8xxx_phy_check_aneg(phydev);
2309
2310 priv->phy = phydev;
2311
2312 if (phydev->mdio.addr != 0) {
2313 if (chip_is_ar8316(priv)) {
2314 /* switch device has been initialized, reinit */
2315 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2316 priv->initialized = false;
2317 priv->port4_phy = true;
2318 ar8316_hw_init(priv);
2319 return 0;
2320 }
2321
2322 return 0;
2323 }
2324
2325 ret = ar8xxx_start(priv);
2326 if (ret)
2327 return ret;
2328
2329 /* VID fixup only needed on ar8216 */
2330 if (chip_is_ar8216(priv)) {
2331 dev->phy_ptr = priv;
2332 dev->priv_flags |= IFF_NO_IP_ALIGN;
2333 dev->eth_mangle_rx = ar8216_mangle_rx;
2334 dev->eth_mangle_tx = ar8216_mangle_tx;
2335 }
2336
2337 return 0;
2338 }
2339
2340 static bool
2341 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2342 {
2343 bool link_new, changed = false;
2344 u32 status;
2345 int i;
2346
2347 mutex_lock(&priv->reg_mutex);
2348
2349 for (i = 0; i < priv->dev.ports; i++) {
2350 status = priv->chip->read_port_status(priv, i);
2351 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2352 if (link_new == priv->link_up[i])
2353 continue;
2354
2355 priv->link_up[i] = link_new;
2356 changed = true;
2357 /* flush ARL entries for this port if it went down*/
2358 if (!link_new)
2359 priv->chip->atu_flush_port(priv, i);
2360 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2361 i, link_new ? "up" : "down");
2362 }
2363
2364 mutex_unlock(&priv->reg_mutex);
2365
2366 return changed;
2367 }
2368
2369 static int
2370 ar8xxx_phy_read_status(struct phy_device *phydev)
2371 {
2372 struct ar8xxx_priv *priv = phydev->priv;
2373 struct switch_port_link link;
2374
2375 /* check for switch port link changes */
2376 if (phydev->state == PHY_CHANGELINK)
2377 ar8xxx_check_link_states(priv);
2378
2379 if (phydev->mdio.addr != 0)
2380 return genphy_read_status(phydev);
2381
2382 ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2383 phydev->link = !!link.link;
2384 if (!phydev->link)
2385 return 0;
2386
2387 switch (link.speed) {
2388 case SWITCH_PORT_SPEED_10:
2389 phydev->speed = SPEED_10;
2390 break;
2391 case SWITCH_PORT_SPEED_100:
2392 phydev->speed = SPEED_100;
2393 break;
2394 case SWITCH_PORT_SPEED_1000:
2395 phydev->speed = SPEED_1000;
2396 break;
2397 default:
2398 phydev->speed = 0;
2399 }
2400 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2401
2402 phydev->state = PHY_RUNNING;
2403 netif_carrier_on(phydev->attached_dev);
2404 if (phydev->adjust_link)
2405 phydev->adjust_link(phydev->attached_dev);
2406
2407 return 0;
2408 }
2409
2410 static int
2411 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2412 {
2413 if (phydev->mdio.addr == 0)
2414 return 0;
2415
2416 return genphy_config_aneg(phydev);
2417 }
2418
2419 static const u32 ar8xxx_phy_ids[] = {
2420 0x004dd033,
2421 0x004dd034, /* AR8327 */
2422 0x004dd036, /* AR8337 */
2423 0x004dd041,
2424 0x004dd042,
2425 0x004dd043, /* AR8236 */
2426 };
2427
2428 static bool
2429 ar8xxx_phy_match(u32 phy_id)
2430 {
2431 int i;
2432
2433 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2434 if (phy_id == ar8xxx_phy_ids[i])
2435 return true;
2436
2437 return false;
2438 }
2439
2440 static bool
2441 ar8xxx_is_possible(struct mii_bus *bus)
2442 {
2443 unsigned int i, found_phys = 0;
2444
2445 for (i = 0; i < 5; i++) {
2446 u32 phy_id;
2447
2448 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2449 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2450 if (ar8xxx_phy_match(phy_id)) {
2451 found_phys++;
2452 } else if (phy_id) {
2453 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2454 dev_name(&bus->dev), i, phy_id);
2455 }
2456 }
2457 return !!found_phys;
2458 }
2459
2460 static int
2461 ar8xxx_phy_probe(struct phy_device *phydev)
2462 {
2463 struct ar8xxx_priv *priv;
2464 struct switch_dev *swdev;
2465 int ret;
2466
2467 /* skip PHYs at unused adresses */
2468 if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
2469 return -ENODEV;
2470
2471 if (!ar8xxx_is_possible(phydev->mdio.bus))
2472 return -ENODEV;
2473
2474 mutex_lock(&ar8xxx_dev_list_lock);
2475 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2476 if (priv->mii_bus == phydev->mdio.bus)
2477 goto found;
2478
2479 priv = ar8xxx_create();
2480 if (priv == NULL) {
2481 ret = -ENOMEM;
2482 goto unlock;
2483 }
2484
2485 priv->mii_bus = phydev->mdio.bus;
2486 priv->pdev = &phydev->mdio.dev;
2487
2488 ret = ar8xxx_id_chip(priv);
2489 if (ret)
2490 goto free_priv;
2491
2492 ret = ar8xxx_probe_switch(priv);
2493 if (ret)
2494 goto free_priv;
2495
2496 swdev = &priv->dev;
2497 swdev->alias = dev_name(&priv->mii_bus->dev);
2498 ret = register_switch(swdev, NULL);
2499 if (ret)
2500 goto free_priv;
2501
2502 pr_info("%s: %s rev. %u switch registered on %s\n",
2503 swdev->devname, swdev->name, priv->chip_rev,
2504 dev_name(&priv->mii_bus->dev));
2505
2506 list_add(&priv->list, &ar8xxx_dev_list);
2507
2508 found:
2509 priv->use_count++;
2510
2511 if (phydev->mdio.addr == 0) {
2512 if (ar8xxx_has_gige(priv)) {
2513 phydev->supported = SUPPORTED_1000baseT_Full;
2514 phydev->advertising = ADVERTISED_1000baseT_Full;
2515 } else {
2516 phydev->supported = SUPPORTED_100baseT_Full;
2517 phydev->advertising = ADVERTISED_100baseT_Full;
2518 }
2519
2520 if (priv->chip->config_at_probe) {
2521 priv->phy = phydev;
2522
2523 ret = ar8xxx_start(priv);
2524 if (ret)
2525 goto err_unregister_switch;
2526 }
2527 } else {
2528 if (ar8xxx_has_gige(priv)) {
2529 phydev->supported |= SUPPORTED_1000baseT_Full;
2530 phydev->advertising |= ADVERTISED_1000baseT_Full;
2531 }
2532 if (priv->chip->phy_rgmii_set)
2533 priv->chip->phy_rgmii_set(priv, phydev);
2534 }
2535
2536 phydev->priv = priv;
2537
2538 mutex_unlock(&ar8xxx_dev_list_lock);
2539
2540 return 0;
2541
2542 err_unregister_switch:
2543 if (--priv->use_count)
2544 goto unlock;
2545
2546 unregister_switch(&priv->dev);
2547
2548 free_priv:
2549 ar8xxx_free(priv);
2550 unlock:
2551 mutex_unlock(&ar8xxx_dev_list_lock);
2552 return ret;
2553 }
2554
2555 static void
2556 ar8xxx_phy_detach(struct phy_device *phydev)
2557 {
2558 struct net_device *dev = phydev->attached_dev;
2559
2560 if (!dev)
2561 return;
2562
2563 dev->phy_ptr = NULL;
2564 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2565 dev->eth_mangle_rx = NULL;
2566 dev->eth_mangle_tx = NULL;
2567 }
2568
2569 static void
2570 ar8xxx_phy_remove(struct phy_device *phydev)
2571 {
2572 struct ar8xxx_priv *priv = phydev->priv;
2573
2574 if (WARN_ON(!priv))
2575 return;
2576
2577 phydev->priv = NULL;
2578
2579 mutex_lock(&ar8xxx_dev_list_lock);
2580
2581 if (--priv->use_count > 0) {
2582 mutex_unlock(&ar8xxx_dev_list_lock);
2583 return;
2584 }
2585
2586 list_del(&priv->list);
2587 mutex_unlock(&ar8xxx_dev_list_lock);
2588
2589 unregister_switch(&priv->dev);
2590 ar8xxx_mib_stop(priv);
2591 ar8xxx_free(priv);
2592 }
2593
2594 static int
2595 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2596 {
2597 /* we don't need an extra reset */
2598 return 0;
2599 }
2600
2601 static struct phy_driver ar8xxx_phy_driver[] = {
2602 {
2603 .phy_id = 0x004d0000,
2604 .name = "Atheros AR8216/AR8236/AR8316",
2605 .phy_id_mask = 0xffff0000,
2606 .features = PHY_BASIC_FEATURES,
2607 .probe = ar8xxx_phy_probe,
2608 .remove = ar8xxx_phy_remove,
2609 .detach = ar8xxx_phy_detach,
2610 .config_init = ar8xxx_phy_config_init,
2611 .config_aneg = ar8xxx_phy_config_aneg,
2612 .read_status = ar8xxx_phy_read_status,
2613 .soft_reset = ar8xxx_phy_soft_reset,
2614 }
2615 };
2616
2617 static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
2618 {
2619 .compatible = "qca,ar7240sw",
2620 .data = &ar7240sw_chip,
2621 }, {
2622 .compatible = "qca,ar8229",
2623 .data = &ar8229_chip,
2624 }, {
2625 .compatible = "qca,ar8236",
2626 .data = &ar8236_chip,
2627 }, {
2628 .compatible = "qca,ar8327",
2629 .data = &ar8327_chip,
2630 },
2631 { /* sentinel */ },
2632 };
2633
2634 static int
2635 ar8xxx_mdiodev_probe(struct mdio_device *mdiodev)
2636 {
2637 const struct of_device_id *match;
2638 struct ar8xxx_priv *priv;
2639 struct switch_dev *swdev;
2640 struct device_node *mdio_node;
2641 int ret;
2642
2643 match = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev);
2644 if (!match)
2645 return -EINVAL;
2646
2647 priv = ar8xxx_create();
2648 if (priv == NULL)
2649 return -ENOMEM;
2650
2651 priv->mii_bus = mdiodev->bus;
2652 priv->pdev = &mdiodev->dev;
2653 priv->chip = (const struct ar8xxx_chip *) match->data;
2654
2655 ret = ar8xxx_read_id(priv);
2656 if (ret)
2657 goto free_priv;
2658
2659 ret = ar8xxx_probe_switch(priv);
2660 if (ret)
2661 goto free_priv;
2662
2663 if (priv->chip->phy_read && priv->chip->phy_write) {
2664 priv->sw_mii_bus = devm_mdiobus_alloc(&mdiodev->dev);
2665 priv->sw_mii_bus->name = "ar8xxx-mdio";
2666 priv->sw_mii_bus->read = ar8xxx_phy_read;
2667 priv->sw_mii_bus->write = ar8xxx_phy_write;
2668 priv->sw_mii_bus->priv = priv;
2669 priv->sw_mii_bus->parent = &mdiodev->dev;
2670 snprintf(priv->sw_mii_bus->id, MII_BUS_ID_SIZE, "%s",
2671 dev_name(&mdiodev->dev));
2672 mdio_node = of_get_child_by_name(priv->pdev->of_node, "mdio-bus");
2673 ret = of_mdiobus_register(priv->sw_mii_bus, mdio_node);
2674 if (ret)
2675 goto free_priv;
2676 }
2677
2678 swdev = &priv->dev;
2679 swdev->alias = dev_name(&mdiodev->dev);
2680
2681 if (of_property_read_bool(priv->pdev->of_node, "qca,phy4-mii-enable")) {
2682 priv->port4_phy = true;
2683 swdev->ports--;
2684 }
2685
2686 ret = register_switch(swdev, NULL);
2687 if (ret)
2688 goto free_priv;
2689
2690 pr_info("%s: %s rev. %u switch registered on %s\n",
2691 swdev->devname, swdev->name, priv->chip_rev,
2692 dev_name(&priv->mii_bus->dev));
2693
2694 mutex_lock(&ar8xxx_dev_list_lock);
2695 list_add(&priv->list, &ar8xxx_dev_list);
2696 mutex_unlock(&ar8xxx_dev_list_lock);
2697
2698 priv->use_count++;
2699
2700 ret = ar8xxx_start(priv);
2701 if (ret)
2702 goto err_unregister_switch;
2703
2704 dev_set_drvdata(&mdiodev->dev, priv);
2705
2706 return 0;
2707
2708 err_unregister_switch:
2709 if (--priv->use_count)
2710 return ret;
2711
2712 unregister_switch(&priv->dev);
2713
2714 free_priv:
2715 ar8xxx_free(priv);
2716 return ret;
2717 }
2718
2719 static void
2720 ar8xxx_mdiodev_remove(struct mdio_device *mdiodev)
2721 {
2722 struct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev);
2723
2724 if (WARN_ON(!priv))
2725 return;
2726
2727 mutex_lock(&ar8xxx_dev_list_lock);
2728
2729 if (--priv->use_count > 0) {
2730 mutex_unlock(&ar8xxx_dev_list_lock);
2731 return;
2732 }
2733
2734 list_del(&priv->list);
2735 mutex_unlock(&ar8xxx_dev_list_lock);
2736
2737 unregister_switch(&priv->dev);
2738 ar8xxx_mib_stop(priv);
2739 if(priv->sw_mii_bus)
2740 mdiobus_unregister(priv->sw_mii_bus);
2741 ar8xxx_free(priv);
2742 }
2743
2744 static struct mdio_driver ar8xxx_mdio_driver = {
2745 .probe = ar8xxx_mdiodev_probe,
2746 .remove = ar8xxx_mdiodev_remove,
2747 .mdiodrv.driver = {
2748 .name = "ar8xxx-switch",
2749 .of_match_table = ar8xxx_mdiodev_of_match,
2750 },
2751 };
2752
2753 static int __init ar8216_init(void)
2754 {
2755 int ret;
2756
2757 ret = phy_drivers_register(ar8xxx_phy_driver,
2758 ARRAY_SIZE(ar8xxx_phy_driver),
2759 THIS_MODULE);
2760 if (ret)
2761 return ret;
2762
2763 ret = mdio_driver_register(&ar8xxx_mdio_driver);
2764 if (ret)
2765 phy_drivers_unregister(ar8xxx_phy_driver,
2766 ARRAY_SIZE(ar8xxx_phy_driver));
2767
2768 return ret;
2769 }
2770 module_init(ar8216_init);
2771
2772 static void __exit ar8216_exit(void)
2773 {
2774 mdio_driver_unregister(&ar8xxx_mdio_driver);
2775 phy_drivers_unregister(ar8xxx_phy_driver,
2776 ARRAY_SIZE(ar8xxx_phy_driver));
2777 }
2778 module_exit(ar8216_exit);
2779
2780 MODULE_LICENSE("GPL");
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