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generic: ar8216: add port mirroring
[openwrt/staging/pepe2k.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37
38 #include "ar8216.h"
39
40 /* size of the vlan table */
41 #define AR8X16_MAX_VLANS 128
42 #define AR8X16_PROBE_RETRIES 10
43 #define AR8X16_MAX_PORTS 8
44
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
46
47 struct ar8xxx_priv;
48
49 #define AR8XXX_CAP_GIGE BIT(0)
50 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
51
52 enum {
53 AR8XXX_VER_AR8216 = 0x01,
54 AR8XXX_VER_AR8236 = 0x03,
55 AR8XXX_VER_AR8316 = 0x10,
56 AR8XXX_VER_AR8327 = 0x12,
57 };
58
59 struct ar8xxx_mib_desc {
60 unsigned int size;
61 unsigned int offset;
62 const char *name;
63 };
64
65 struct ar8xxx_chip {
66 unsigned long caps;
67
68 int (*hw_init)(struct ar8xxx_priv *priv);
69 void (*init_globals)(struct ar8xxx_priv *priv);
70 void (*init_port)(struct ar8xxx_priv *priv, int port);
71 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 egress,
72 u32 ingress, u32 members, u32 pvid);
73 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
74 int (*atu_flush)(struct ar8xxx_priv *priv);
75 void (*vtu_flush)(struct ar8xxx_priv *priv);
76 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
77
78 const struct ar8xxx_mib_desc *mib_decs;
79 unsigned num_mibs;
80 };
81
82 struct ar8327_data {
83 u32 port0_status;
84 u32 port6_status;
85 };
86
87 struct ar8xxx_priv {
88 struct switch_dev dev;
89 struct mii_bus *mii_bus;
90 struct phy_device *phy;
91 u32 (*read)(struct ar8xxx_priv *priv, int reg);
92 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
93 const struct net_device_ops *ndo_old;
94 struct net_device_ops ndo;
95 struct mutex reg_mutex;
96 u8 chip_ver;
97 u8 chip_rev;
98 const struct ar8xxx_chip *chip;
99 union {
100 struct ar8327_data ar8327;
101 } chip_data;
102 bool initialized;
103 bool port4_phy;
104 char buf[2048];
105
106 bool init;
107 bool mii_lo_first;
108
109 struct mutex mib_lock;
110 struct delayed_work mib_work;
111 int mib_next_port;
112 u64 *mib_stats;
113
114 struct list_head list;
115 unsigned int use_count;
116
117 /* all fields below are cleared on reset */
118 bool vlan;
119 u16 vlan_id[AR8X16_MAX_VLANS];
120 u8 vlan_table[AR8X16_MAX_VLANS];
121 u8 vlan_tagged;
122 u16 pvid[AR8X16_MAX_PORTS];
123
124 /* mirroring */
125 bool mirror_rx;
126 bool mirror_tx;
127 int source_port;
128 int monitor_port;
129 };
130
131 #define MIB_DESC(_s , _o, _n) \
132 { \
133 .size = (_s), \
134 .offset = (_o), \
135 .name = (_n), \
136 }
137
138 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
139 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
140 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
141 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
142 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
143 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
144 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
145 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
146 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
147 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
148 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
149 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
150 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
151 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
152 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
153 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
154 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
155 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
156 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
157 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
158 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
159 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
160 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
161 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
162 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
163 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
164 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
165 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
166 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
167 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
168 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
169 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
170 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
171 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
172 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
173 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
174 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
175 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
176 };
177
178 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
179 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
180 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
181 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
182 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
183 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
184 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
185 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
186 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
187 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
188 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
189 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
190 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
191 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
192 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
193 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
194 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
195 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
196 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
197 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
198 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
199 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
200 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
201 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
202 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
203 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
204 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
205 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
206 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
207 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
208 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
209 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
210 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
211 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
212 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
213 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
214 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
215 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
216 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
217 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
218 };
219
220 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
221 static LIST_HEAD(ar8xxx_dev_list);
222
223 static inline struct ar8xxx_priv *
224 swdev_to_ar8xxx(struct switch_dev *swdev)
225 {
226 return container_of(swdev, struct ar8xxx_priv, dev);
227 }
228
229 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
230 {
231 return priv->chip->caps & AR8XXX_CAP_GIGE;
232 }
233
234 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
235 {
236 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
237 }
238
239 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
240 {
241 return priv->chip_ver == AR8XXX_VER_AR8216;
242 }
243
244 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
245 {
246 return priv->chip_ver == AR8XXX_VER_AR8236;
247 }
248
249 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
250 {
251 return priv->chip_ver == AR8XXX_VER_AR8316;
252 }
253
254 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
255 {
256 return priv->chip_ver == AR8XXX_VER_AR8327;
257 }
258
259 static inline void
260 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
261 {
262 regaddr >>= 1;
263 *r1 = regaddr & 0x1e;
264
265 regaddr >>= 5;
266 *r2 = regaddr & 0x7;
267
268 regaddr >>= 3;
269 *page = regaddr & 0x1ff;
270 }
271
272 static u32
273 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
274 {
275 struct mii_bus *bus = priv->mii_bus;
276 u16 r1, r2, page;
277 u16 lo, hi;
278
279 split_addr((u32) reg, &r1, &r2, &page);
280
281 mutex_lock(&bus->mdio_lock);
282
283 bus->write(bus, 0x18, 0, page);
284 usleep_range(1000, 2000); /* wait for the page switch to propagate */
285 lo = bus->read(bus, 0x10 | r2, r1);
286 hi = bus->read(bus, 0x10 | r2, r1 + 1);
287
288 mutex_unlock(&bus->mdio_lock);
289
290 return (hi << 16) | lo;
291 }
292
293 static void
294 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
295 {
296 struct mii_bus *bus = priv->mii_bus;
297 u16 r1, r2, r3;
298 u16 lo, hi;
299
300 split_addr((u32) reg, &r1, &r2, &r3);
301 lo = val & 0xffff;
302 hi = (u16) (val >> 16);
303
304 mutex_lock(&bus->mdio_lock);
305
306 bus->write(bus, 0x18, 0, r3);
307 usleep_range(1000, 2000); /* wait for the page switch to propagate */
308 if (priv->mii_lo_first) {
309 bus->write(bus, 0x10 | r2, r1, lo);
310 bus->write(bus, 0x10 | r2, r1 + 1, hi);
311 } else {
312 bus->write(bus, 0x10 | r2, r1 + 1, hi);
313 bus->write(bus, 0x10 | r2, r1, lo);
314 }
315
316 mutex_unlock(&bus->mdio_lock);
317 }
318
319 static void
320 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
321 u16 dbg_addr, u16 dbg_data)
322 {
323 struct mii_bus *bus = priv->mii_bus;
324
325 mutex_lock(&bus->mdio_lock);
326 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
327 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
328 mutex_unlock(&bus->mdio_lock);
329 }
330
331 static void
332 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
333 {
334 struct mii_bus *bus = priv->mii_bus;
335
336 mutex_lock(&bus->mdio_lock);
337 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
338 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
339 mutex_unlock(&bus->mdio_lock);
340 }
341
342 static u32
343 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
344 {
345 u32 v;
346
347 lockdep_assert_held(&priv->reg_mutex);
348
349 v = priv->read(priv, reg);
350 v &= ~mask;
351 v |= val;
352 priv->write(priv, reg, v);
353
354 return v;
355 }
356
357 static inline void
358 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
359 {
360 u32 v;
361
362 lockdep_assert_held(&priv->reg_mutex);
363
364 v = priv->read(priv, reg);
365 v |= val;
366 priv->write(priv, reg, v);
367 }
368
369 static int
370 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
371 unsigned timeout)
372 {
373 int i;
374
375 for (i = 0; i < timeout; i++) {
376 u32 t;
377
378 t = priv->read(priv, reg);
379 if ((t & mask) == val)
380 return 0;
381
382 usleep_range(1000, 2000);
383 }
384
385 return -ETIMEDOUT;
386 }
387
388 static int
389 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
390 {
391 unsigned mib_func;
392 int ret;
393
394 lockdep_assert_held(&priv->mib_lock);
395
396 if (chip_is_ar8327(priv))
397 mib_func = AR8327_REG_MIB_FUNC;
398 else
399 mib_func = AR8216_REG_MIB_FUNC;
400
401 mutex_lock(&priv->reg_mutex);
402 /* Capture the hardware statistics for all ports */
403 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
404 mutex_unlock(&priv->reg_mutex);
405
406 /* Wait for the capturing to complete. */
407 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
408 if (ret)
409 goto out;
410
411 ret = 0;
412
413 out:
414 return ret;
415 }
416
417 static int
418 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
419 {
420 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
421 }
422
423 static int
424 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
425 {
426 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
427 }
428
429 static void
430 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
431 {
432 unsigned int base;
433 u64 *mib_stats;
434 int i;
435
436 WARN_ON(port >= priv->dev.ports);
437
438 lockdep_assert_held(&priv->mib_lock);
439
440 if (chip_is_ar8327(priv))
441 base = AR8327_REG_PORT_STATS_BASE(port);
442 else if (chip_is_ar8236(priv) ||
443 chip_is_ar8316(priv))
444 base = AR8236_REG_PORT_STATS_BASE(port);
445 else
446 base = AR8216_REG_PORT_STATS_BASE(port);
447
448 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
449 for (i = 0; i < priv->chip->num_mibs; i++) {
450 const struct ar8xxx_mib_desc *mib;
451 u64 t;
452
453 mib = &priv->chip->mib_decs[i];
454 t = priv->read(priv, base + mib->offset);
455 if (mib->size == 2) {
456 u64 hi;
457
458 hi = priv->read(priv, base + mib->offset + 4);
459 t |= hi << 32;
460 }
461
462 if (flush)
463 mib_stats[i] = 0;
464 else
465 mib_stats[i] += t;
466 }
467 }
468
469 static void
470 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
471 struct switch_port_link *link)
472 {
473 u32 status;
474 u32 speed;
475
476 memset(link, '\0', sizeof(*link));
477
478 status = priv->chip->read_port_status(priv, port);
479
480 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
481 if (link->aneg) {
482 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
483 if (!link->link)
484 return;
485 } else {
486 link->link = true;
487 }
488
489 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
490 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
491 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
492
493 speed = (status & AR8216_PORT_STATUS_SPEED) >>
494 AR8216_PORT_STATUS_SPEED_S;
495
496 switch (speed) {
497 case AR8216_PORT_SPEED_10M:
498 link->speed = SWITCH_PORT_SPEED_10;
499 break;
500 case AR8216_PORT_SPEED_100M:
501 link->speed = SWITCH_PORT_SPEED_100;
502 break;
503 case AR8216_PORT_SPEED_1000M:
504 link->speed = SWITCH_PORT_SPEED_1000;
505 break;
506 default:
507 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
508 break;
509 }
510 }
511
512 static struct sk_buff *
513 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
514 {
515 struct ar8xxx_priv *priv = dev->phy_ptr;
516 unsigned char *buf;
517
518 if (unlikely(!priv))
519 goto error;
520
521 if (!priv->vlan)
522 goto send;
523
524 if (unlikely(skb_headroom(skb) < 2)) {
525 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
526 goto error;
527 }
528
529 buf = skb_push(skb, 2);
530 buf[0] = 0x10;
531 buf[1] = 0x80;
532
533 send:
534 return skb;
535
536 error:
537 dev_kfree_skb_any(skb);
538 return NULL;
539 }
540
541 static void
542 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
543 {
544 struct ar8xxx_priv *priv;
545 unsigned char *buf;
546 int port, vlan;
547
548 priv = dev->phy_ptr;
549 if (!priv)
550 return;
551
552 /* don't strip the header if vlan mode is disabled */
553 if (!priv->vlan)
554 return;
555
556 /* strip header, get vlan id */
557 buf = skb->data;
558 skb_pull(skb, 2);
559
560 /* check for vlan header presence */
561 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
562 return;
563
564 port = buf[0] & 0xf;
565
566 /* no need to fix up packets coming from a tagged source */
567 if (priv->vlan_tagged & (1 << port))
568 return;
569
570 /* lookup port vid from local table, the switch passes an invalid vlan id */
571 vlan = priv->vlan_id[priv->pvid[port]];
572
573 buf[14 + 2] &= 0xf0;
574 buf[14 + 2] |= vlan >> 8;
575 buf[15 + 2] = vlan & 0xff;
576 }
577
578 static int
579 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
580 {
581 int timeout = 20;
582 u32 t = 0;
583
584 while (1) {
585 t = priv->read(priv, reg);
586 if ((t & mask) == val)
587 return 0;
588
589 if (timeout-- <= 0)
590 break;
591
592 udelay(10);
593 }
594
595 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
596 (unsigned int) reg, t, mask, val);
597 return -ETIMEDOUT;
598 }
599
600 static void
601 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
602 {
603 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
604 return;
605 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
606 val &= AR8216_VTUDATA_MEMBER;
607 val |= AR8216_VTUDATA_VALID;
608 priv->write(priv, AR8216_REG_VTU_DATA, val);
609 }
610 op |= AR8216_VTU_ACTIVE;
611 priv->write(priv, AR8216_REG_VTU, op);
612 }
613
614 static void
615 ar8216_vtu_flush(struct ar8xxx_priv *priv)
616 {
617 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
618 }
619
620 static void
621 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
622 {
623 u32 op;
624
625 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
626 ar8216_vtu_op(priv, op, port_mask);
627 }
628
629 static int
630 ar8216_atu_flush(struct ar8xxx_priv *priv)
631 {
632 int ret;
633
634 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
635 if (!ret)
636 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
637
638 return ret;
639 }
640
641 static u32
642 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
643 {
644 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
645 }
646
647 static void
648 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
649 u32 members, u32 pvid)
650 {
651 u32 header;
652
653 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
654 header = AR8216_PORT_CTRL_HEADER;
655 else
656 header = 0;
657
658 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
659 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
660 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
661 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
662 AR8216_PORT_CTRL_LEARN | header |
663 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
664 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
665
666 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
667 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
668 AR8216_PORT_VLAN_DEFAULT_ID,
669 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
670 (ingress << AR8216_PORT_VLAN_MODE_S) |
671 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
672 }
673
674 static int
675 ar8216_hw_init(struct ar8xxx_priv *priv)
676 {
677 return 0;
678 }
679
680 static void
681 ar8216_init_globals(struct ar8xxx_priv *priv)
682 {
683 /* standard atheros magic */
684 priv->write(priv, 0x38, 0xc000050e);
685
686 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
687 AR8216_GCTRL_MTU, 1518 + 8 + 2);
688 }
689
690 static void
691 ar8216_init_port(struct ar8xxx_priv *priv, int port)
692 {
693 /* Enable port learning and tx */
694 priv->write(priv, AR8216_REG_PORT_CTRL(port),
695 AR8216_PORT_CTRL_LEARN |
696 (4 << AR8216_PORT_CTRL_STATE_S));
697
698 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
699
700 if (port == AR8216_PORT_CPU) {
701 priv->write(priv, AR8216_REG_PORT_STATUS(port),
702 AR8216_PORT_STATUS_LINK_UP |
703 (ar8xxx_has_gige(priv) ?
704 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
705 AR8216_PORT_STATUS_TXMAC |
706 AR8216_PORT_STATUS_RXMAC |
707 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
708 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
709 AR8216_PORT_STATUS_DUPLEX);
710 } else {
711 priv->write(priv, AR8216_REG_PORT_STATUS(port),
712 AR8216_PORT_STATUS_LINK_AUTO);
713 }
714 }
715
716 static const struct ar8xxx_chip ar8216_chip = {
717 .caps = AR8XXX_CAP_MIB_COUNTERS,
718
719 .hw_init = ar8216_hw_init,
720 .init_globals = ar8216_init_globals,
721 .init_port = ar8216_init_port,
722 .setup_port = ar8216_setup_port,
723 .read_port_status = ar8216_read_port_status,
724 .atu_flush = ar8216_atu_flush,
725 .vtu_flush = ar8216_vtu_flush,
726 .vtu_load_vlan = ar8216_vtu_load_vlan,
727
728 .num_mibs = ARRAY_SIZE(ar8216_mibs),
729 .mib_decs = ar8216_mibs,
730 };
731
732 static void
733 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
734 u32 members, u32 pvid)
735 {
736 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
737 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
738 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
739 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
740 AR8216_PORT_CTRL_LEARN |
741 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
742 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
743
744 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
745 AR8236_PORT_VLAN_DEFAULT_ID,
746 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
747
748 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
749 AR8236_PORT_VLAN2_VLAN_MODE |
750 AR8236_PORT_VLAN2_MEMBER,
751 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
752 (members << AR8236_PORT_VLAN2_MEMBER_S));
753 }
754
755 static int
756 ar8236_hw_init(struct ar8xxx_priv *priv)
757 {
758 int i;
759 struct mii_bus *bus;
760
761 if (priv->initialized)
762 return 0;
763
764 /* Initialize the PHYs */
765 bus = priv->mii_bus;
766 for (i = 0; i < 5; i++) {
767 mdiobus_write(bus, i, MII_ADVERTISE,
768 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
769 ADVERTISE_PAUSE_ASYM);
770 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
771 }
772 msleep(1000);
773
774 priv->initialized = true;
775 return 0;
776 }
777
778 static void
779 ar8236_init_globals(struct ar8xxx_priv *priv)
780 {
781 /* enable jumbo frames */
782 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
783 AR8316_GCTRL_MTU, 9018 + 8 + 2);
784
785 /* Enable MIB counters */
786 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
787 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
788 AR8236_MIB_EN);
789 }
790
791 static const struct ar8xxx_chip ar8236_chip = {
792 .caps = AR8XXX_CAP_MIB_COUNTERS,
793 .hw_init = ar8236_hw_init,
794 .init_globals = ar8236_init_globals,
795 .init_port = ar8216_init_port,
796 .setup_port = ar8236_setup_port,
797 .read_port_status = ar8216_read_port_status,
798 .atu_flush = ar8216_atu_flush,
799 .vtu_flush = ar8216_vtu_flush,
800 .vtu_load_vlan = ar8216_vtu_load_vlan,
801
802 .num_mibs = ARRAY_SIZE(ar8236_mibs),
803 .mib_decs = ar8236_mibs,
804 };
805
806 static int
807 ar8316_hw_init(struct ar8xxx_priv *priv)
808 {
809 int i;
810 u32 val, newval;
811 struct mii_bus *bus;
812
813 val = priv->read(priv, AR8316_REG_POSTRIP);
814
815 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
816 if (priv->port4_phy) {
817 /* value taken from Ubiquiti RouterStation Pro */
818 newval = 0x81461bea;
819 pr_info("ar8316: Using port 4 as PHY\n");
820 } else {
821 newval = 0x01261be2;
822 pr_info("ar8316: Using port 4 as switch port\n");
823 }
824 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
825 /* value taken from AVM Fritz!Box 7390 sources */
826 newval = 0x010e5b71;
827 } else {
828 /* no known value for phy interface */
829 pr_err("ar8316: unsupported mii mode: %d.\n",
830 priv->phy->interface);
831 return -EINVAL;
832 }
833
834 if (val == newval)
835 goto out;
836
837 priv->write(priv, AR8316_REG_POSTRIP, newval);
838
839 if (priv->port4_phy &&
840 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
841 /* work around for phy4 rgmii mode */
842 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
843 /* rx delay */
844 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
845 /* tx delay */
846 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
847 msleep(1000);
848 }
849
850 /* Initialize the ports */
851 bus = priv->mii_bus;
852 for (i = 0; i < 5; i++) {
853 /* initialize the port itself */
854 mdiobus_write(bus, i, MII_ADVERTISE,
855 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
856 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
857 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
858 }
859
860 msleep(1000);
861
862 out:
863 priv->initialized = true;
864 return 0;
865 }
866
867 static void
868 ar8316_init_globals(struct ar8xxx_priv *priv)
869 {
870 /* standard atheros magic */
871 priv->write(priv, 0x38, 0xc000050e);
872
873 /* enable cpu port to receive multicast and broadcast frames */
874 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
875
876 /* enable jumbo frames */
877 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
878 AR8316_GCTRL_MTU, 9018 + 8 + 2);
879
880 /* Enable MIB counters */
881 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
882 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
883 AR8236_MIB_EN);
884 }
885
886 static const struct ar8xxx_chip ar8316_chip = {
887 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
888 .hw_init = ar8316_hw_init,
889 .init_globals = ar8316_init_globals,
890 .init_port = ar8216_init_port,
891 .setup_port = ar8216_setup_port,
892 .read_port_status = ar8216_read_port_status,
893 .atu_flush = ar8216_atu_flush,
894 .vtu_flush = ar8216_vtu_flush,
895 .vtu_load_vlan = ar8216_vtu_load_vlan,
896
897 .num_mibs = ARRAY_SIZE(ar8236_mibs),
898 .mib_decs = ar8236_mibs,
899 };
900
901 static u32
902 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
903 {
904 u32 t;
905
906 if (!cfg)
907 return 0;
908
909 t = 0;
910 switch (cfg->mode) {
911 case AR8327_PAD_NC:
912 break;
913
914 case AR8327_PAD_MAC2MAC_MII:
915 t = AR8327_PAD_MAC_MII_EN;
916 if (cfg->rxclk_sel)
917 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
918 if (cfg->txclk_sel)
919 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
920 break;
921
922 case AR8327_PAD_MAC2MAC_GMII:
923 t = AR8327_PAD_MAC_GMII_EN;
924 if (cfg->rxclk_sel)
925 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
926 if (cfg->txclk_sel)
927 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
928 break;
929
930 case AR8327_PAD_MAC_SGMII:
931 t = AR8327_PAD_SGMII_EN;
932
933 /*
934 * WAR for the QUalcomm Atheros AP136 board.
935 * It seems that RGMII TX/RX delay settings needs to be
936 * applied for SGMII mode as well, The ethernet is not
937 * reliable without this.
938 */
939 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
940 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
941 if (cfg->rxclk_delay_en)
942 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
943 if (cfg->txclk_delay_en)
944 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
945
946 if (cfg->sgmii_delay_en)
947 t |= AR8327_PAD_SGMII_DELAY_EN;
948
949 break;
950
951 case AR8327_PAD_MAC2PHY_MII:
952 t = AR8327_PAD_PHY_MII_EN;
953 if (cfg->rxclk_sel)
954 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
955 if (cfg->txclk_sel)
956 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
957 break;
958
959 case AR8327_PAD_MAC2PHY_GMII:
960 t = AR8327_PAD_PHY_GMII_EN;
961 if (cfg->pipe_rxclk_sel)
962 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
963 if (cfg->rxclk_sel)
964 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
965 if (cfg->txclk_sel)
966 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
967 break;
968
969 case AR8327_PAD_MAC_RGMII:
970 t = AR8327_PAD_RGMII_EN;
971 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
972 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
973 if (cfg->rxclk_delay_en)
974 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
975 if (cfg->txclk_delay_en)
976 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
977 break;
978
979 case AR8327_PAD_PHY_GMII:
980 t = AR8327_PAD_PHYX_GMII_EN;
981 break;
982
983 case AR8327_PAD_PHY_RGMII:
984 t = AR8327_PAD_PHYX_RGMII_EN;
985 break;
986
987 case AR8327_PAD_PHY_MII:
988 t = AR8327_PAD_PHYX_MII_EN;
989 break;
990 }
991
992 return t;
993 }
994
995 static void
996 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
997 {
998 switch (priv->chip_rev) {
999 case 1:
1000 /* For 100M waveform */
1001 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1002 /* Turn on Gigabit clock */
1003 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1004 break;
1005
1006 case 2:
1007 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1008 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1009 /* fallthrough */
1010 case 4:
1011 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1012 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1013
1014 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1015 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1016 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1017 break;
1018 }
1019 }
1020
1021 static u32
1022 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1023 {
1024 u32 t;
1025
1026 if (!cfg->force_link)
1027 return AR8216_PORT_STATUS_LINK_AUTO;
1028
1029 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1030 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1031 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1032 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1033
1034 switch (cfg->speed) {
1035 case AR8327_PORT_SPEED_10:
1036 t |= AR8216_PORT_SPEED_10M;
1037 break;
1038 case AR8327_PORT_SPEED_100:
1039 t |= AR8216_PORT_SPEED_100M;
1040 break;
1041 case AR8327_PORT_SPEED_1000:
1042 t |= AR8216_PORT_SPEED_1000M;
1043 break;
1044 }
1045
1046 return t;
1047 }
1048
1049 static int
1050 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1051 struct ar8327_platform_data *pdata)
1052 {
1053 struct ar8327_led_cfg *led_cfg;
1054 struct ar8327_data *data;
1055 u32 pos, new_pos;
1056 u32 t;
1057
1058 if (!pdata)
1059 return -EINVAL;
1060
1061 data = &priv->chip_data.ar8327;
1062
1063 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1064 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1065
1066 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1067 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1068 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1069 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1070 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1071 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1072
1073 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1074 new_pos = pos;
1075
1076 led_cfg = pdata->led_cfg;
1077 if (led_cfg) {
1078 if (led_cfg->open_drain)
1079 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1080 else
1081 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1082
1083 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1084 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1085 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1086 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1087 }
1088
1089 if (new_pos != pos) {
1090 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1091 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1092 }
1093
1094 return 0;
1095 }
1096
1097 #ifdef CONFIG_OF
1098 static int
1099 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1100 {
1101 const __be32 *paddr;
1102 int len;
1103 int i;
1104
1105 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1106 if (!paddr || len < (2 * sizeof(*paddr)))
1107 return -EINVAL;
1108
1109 len /= sizeof(*paddr);
1110
1111 for (i = 0; i < len - 1; i += 2) {
1112 u32 reg;
1113 u32 val;
1114
1115 reg = be32_to_cpup(paddr + i);
1116 val = be32_to_cpup(paddr + i + 1);
1117
1118 switch (reg) {
1119 case AR8327_REG_PORT_STATUS(0):
1120 priv->chip_data.ar8327.port0_status = val;
1121 break;
1122 case AR8327_REG_PORT_STATUS(6):
1123 priv->chip_data.ar8327.port6_status = val;
1124 break;
1125 default:
1126 priv->write(priv, reg, val);
1127 break;
1128 }
1129 }
1130
1131 return 0;
1132 }
1133 #else
1134 static inline int
1135 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1136 {
1137 return -EINVAL;
1138 }
1139 #endif
1140
1141 static int
1142 ar8327_hw_init(struct ar8xxx_priv *priv)
1143 {
1144 struct mii_bus *bus;
1145 int ret;
1146 int i;
1147
1148 if (priv->phy->dev.of_node)
1149 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1150 else
1151 ret = ar8327_hw_config_pdata(priv,
1152 priv->phy->dev.platform_data);
1153
1154 if (ret)
1155 return ret;
1156
1157 bus = priv->mii_bus;
1158 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1159 ar8327_phy_fixup(priv, i);
1160
1161 /* start aneg on the PHY */
1162 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1163 ADVERTISE_PAUSE_CAP |
1164 ADVERTISE_PAUSE_ASYM);
1165 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1166 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1167 }
1168
1169 msleep(1000);
1170
1171 return 0;
1172 }
1173
1174 static void
1175 ar8327_init_globals(struct ar8xxx_priv *priv)
1176 {
1177 u32 t;
1178
1179 /* enable CPU port and disable mirror port */
1180 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1181 AR8327_FWD_CTRL0_MIRROR_PORT;
1182 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1183
1184 /* forward multicast and broadcast frames to CPU */
1185 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1186 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1187 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1188 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1189
1190 /* setup MTU */
1191 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1192 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1193
1194 /* Enable MIB counters */
1195 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1196 AR8327_MODULE_EN_MIB);
1197 }
1198
1199 static void
1200 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1201 {
1202 u32 t;
1203
1204 if (port == AR8216_PORT_CPU)
1205 t = priv->chip_data.ar8327.port0_status;
1206 else if (port == 6)
1207 t = priv->chip_data.ar8327.port6_status;
1208 else
1209 t = AR8216_PORT_STATUS_LINK_AUTO;
1210
1211 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1212 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1213
1214 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1215 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1216 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1217
1218 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1219 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1220
1221 t = AR8327_PORT_LOOKUP_LEARN;
1222 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1223 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1224 }
1225
1226 static u32
1227 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1228 {
1229 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1230 }
1231
1232 static int
1233 ar8327_atu_flush(struct ar8xxx_priv *priv)
1234 {
1235 int ret;
1236
1237 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1238 AR8327_ATU_FUNC_BUSY, 0);
1239 if (!ret)
1240 priv->write(priv, AR8327_REG_ATU_FUNC,
1241 AR8327_ATU_FUNC_OP_FLUSH);
1242
1243 return ret;
1244 }
1245
1246 static void
1247 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1248 {
1249 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1250 AR8327_VTU_FUNC1_BUSY, 0))
1251 return;
1252
1253 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1254 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1255
1256 op |= AR8327_VTU_FUNC1_BUSY;
1257 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1258 }
1259
1260 static void
1261 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1262 {
1263 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1264 }
1265
1266 static void
1267 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1268 {
1269 u32 op;
1270 u32 val;
1271 int i;
1272
1273 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1274 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1275 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1276 u32 mode;
1277
1278 if ((port_mask & BIT(i)) == 0)
1279 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1280 else if (priv->vlan == 0)
1281 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1282 else if (priv->vlan_tagged & BIT(i))
1283 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1284 else
1285 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1286
1287 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1288 }
1289 ar8327_vtu_op(priv, op, val);
1290 }
1291
1292 static void
1293 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
1294 u32 members, u32 pvid)
1295 {
1296 u32 t;
1297 u32 mode;
1298
1299 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1300 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1301 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1302
1303 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1304 switch (egress) {
1305 case AR8216_OUT_KEEP:
1306 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1307 break;
1308 case AR8216_OUT_STRIP_VLAN:
1309 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1310 break;
1311 case AR8216_OUT_ADD_VLAN:
1312 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1313 break;
1314 }
1315
1316 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1317 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1318 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1319
1320 t = members;
1321 t |= AR8327_PORT_LOOKUP_LEARN;
1322 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1323 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1324 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1325 }
1326
1327 static const struct ar8xxx_chip ar8327_chip = {
1328 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1329 .hw_init = ar8327_hw_init,
1330 .init_globals = ar8327_init_globals,
1331 .init_port = ar8327_init_port,
1332 .setup_port = ar8327_setup_port,
1333 .read_port_status = ar8327_read_port_status,
1334 .atu_flush = ar8327_atu_flush,
1335 .vtu_flush = ar8327_vtu_flush,
1336 .vtu_load_vlan = ar8327_vtu_load_vlan,
1337
1338 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1339 .mib_decs = ar8236_mibs,
1340 };
1341
1342 static int
1343 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1344 struct switch_val *val)
1345 {
1346 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1347 priv->vlan = !!val->value.i;
1348 return 0;
1349 }
1350
1351 static int
1352 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1353 struct switch_val *val)
1354 {
1355 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1356 val->value.i = priv->vlan;
1357 return 0;
1358 }
1359
1360
1361 static int
1362 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1363 {
1364 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1365
1366 /* make sure no invalid PVIDs get set */
1367
1368 if (vlan >= dev->vlans)
1369 return -EINVAL;
1370
1371 priv->pvid[port] = vlan;
1372 return 0;
1373 }
1374
1375 static int
1376 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1377 {
1378 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1379 *vlan = priv->pvid[port];
1380 return 0;
1381 }
1382
1383 static int
1384 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1385 struct switch_val *val)
1386 {
1387 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1388 priv->vlan_id[val->port_vlan] = val->value.i;
1389 return 0;
1390 }
1391
1392 static int
1393 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1394 struct switch_val *val)
1395 {
1396 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1397 val->value.i = priv->vlan_id[val->port_vlan];
1398 return 0;
1399 }
1400
1401 static int
1402 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1403 struct switch_port_link *link)
1404 {
1405 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1406
1407 ar8216_read_port_link(priv, port, link);
1408 return 0;
1409 }
1410
1411 static int
1412 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1413 {
1414 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1415 u8 ports = priv->vlan_table[val->port_vlan];
1416 int i;
1417
1418 val->len = 0;
1419 for (i = 0; i < dev->ports; i++) {
1420 struct switch_port *p;
1421
1422 if (!(ports & (1 << i)))
1423 continue;
1424
1425 p = &val->value.ports[val->len++];
1426 p->id = i;
1427 if (priv->vlan_tagged & (1 << i))
1428 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1429 else
1430 p->flags = 0;
1431 }
1432 return 0;
1433 }
1434
1435 static int
1436 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1437 {
1438 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1439 u8 *vt = &priv->vlan_table[val->port_vlan];
1440 int i, j;
1441
1442 *vt = 0;
1443 for (i = 0; i < val->len; i++) {
1444 struct switch_port *p = &val->value.ports[i];
1445
1446 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1447 priv->vlan_tagged |= (1 << p->id);
1448 } else {
1449 priv->vlan_tagged &= ~(1 << p->id);
1450 priv->pvid[p->id] = val->port_vlan;
1451
1452 /* make sure that an untagged port does not
1453 * appear in other vlans */
1454 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1455 if (j == val->port_vlan)
1456 continue;
1457 priv->vlan_table[j] &= ~(1 << p->id);
1458 }
1459 }
1460
1461 *vt |= 1 << p->id;
1462 }
1463 return 0;
1464 }
1465
1466 static void
1467 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1468 {
1469 int port;
1470
1471 /* reset all mirror registers */
1472 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1473 AR8327_FWD_CTRL0_MIRROR_PORT,
1474 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1475 for (port = 0; port < AR8327_NUM_PORTS; port++) {
1476 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1477 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1478 0);
1479
1480 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1481 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1482 0);
1483 }
1484
1485 /* now enable mirroring if necessary */
1486 if (priv->source_port >= AR8327_NUM_PORTS ||
1487 priv->monitor_port >= AR8327_NUM_PORTS ||
1488 priv->source_port == priv->monitor_port) {
1489 return;
1490 }
1491
1492 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1493 AR8327_FWD_CTRL0_MIRROR_PORT,
1494 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1495
1496 if (priv->mirror_rx)
1497 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1498 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1499 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1500
1501 if (priv->mirror_tx)
1502 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1503 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1504 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1505 }
1506
1507 static void
1508 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1509 {
1510 int port;
1511
1512 /* reset all mirror registers */
1513 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1514 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1515 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1516 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1517 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1518 AR8216_PORT_CTRL_MIRROR_RX,
1519 0);
1520
1521 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1522 AR8216_PORT_CTRL_MIRROR_TX,
1523 0);
1524 }
1525
1526 /* now enable mirroring if necessary */
1527 if (priv->source_port >= AR8216_NUM_PORTS ||
1528 priv->monitor_port >= AR8216_NUM_PORTS ||
1529 priv->source_port == priv->monitor_port) {
1530 return;
1531 }
1532
1533 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1534 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1535 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1536
1537 if (priv->mirror_rx)
1538 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1539 AR8216_PORT_CTRL_MIRROR_RX,
1540 AR8216_PORT_CTRL_MIRROR_RX);
1541
1542 if (priv->mirror_tx)
1543 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1544 AR8216_PORT_CTRL_MIRROR_TX,
1545 AR8216_PORT_CTRL_MIRROR_TX);
1546 }
1547
1548 static void
1549 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
1550 {
1551 if (chip_is_ar8327(priv)) {
1552 ar8327_set_mirror_regs(priv);
1553 } else {
1554 ar8216_set_mirror_regs(priv);
1555 }
1556 }
1557
1558 static int
1559 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1560 {
1561 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1562 u8 portmask[AR8X16_MAX_PORTS];
1563 int i, j;
1564
1565 mutex_lock(&priv->reg_mutex);
1566 /* flush all vlan translation unit entries */
1567 priv->chip->vtu_flush(priv);
1568
1569 memset(portmask, 0, sizeof(portmask));
1570 if (!priv->init) {
1571 /* calculate the port destination masks and load vlans
1572 * into the vlan translation unit */
1573 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1574 u8 vp = priv->vlan_table[j];
1575
1576 if (!vp)
1577 continue;
1578
1579 for (i = 0; i < dev->ports; i++) {
1580 u8 mask = (1 << i);
1581 if (vp & mask)
1582 portmask[i] |= vp & ~mask;
1583 }
1584
1585 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1586 priv->vlan_table[j]);
1587 }
1588 } else {
1589 /* vlan disabled:
1590 * isolate all ports, but connect them to the cpu port */
1591 for (i = 0; i < dev->ports; i++) {
1592 if (i == AR8216_PORT_CPU)
1593 continue;
1594
1595 portmask[i] = 1 << AR8216_PORT_CPU;
1596 portmask[AR8216_PORT_CPU] |= (1 << i);
1597 }
1598 }
1599
1600 /* update the port destination mask registers and tag settings */
1601 for (i = 0; i < dev->ports; i++) {
1602 int egress, ingress;
1603 int pvid;
1604
1605 if (priv->vlan) {
1606 pvid = priv->vlan_id[priv->pvid[i]];
1607 if (priv->vlan_tagged & (1 << i))
1608 egress = AR8216_OUT_ADD_VLAN;
1609 else
1610 egress = AR8216_OUT_STRIP_VLAN;
1611 ingress = AR8216_IN_SECURE;
1612 } else {
1613 pvid = i;
1614 egress = AR8216_OUT_KEEP;
1615 ingress = AR8216_IN_PORT_ONLY;
1616 }
1617
1618 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1619 pvid);
1620 }
1621
1622 ar8xxx_set_mirror_regs(priv);
1623
1624 mutex_unlock(&priv->reg_mutex);
1625 return 0;
1626 }
1627
1628 static int
1629 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1630 {
1631 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1632 int i;
1633
1634 mutex_lock(&priv->reg_mutex);
1635 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1636 offsetof(struct ar8xxx_priv, vlan));
1637
1638 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1639 priv->vlan_id[i] = i;
1640
1641 /* Configure all ports */
1642 for (i = 0; i < dev->ports; i++)
1643 priv->chip->init_port(priv, i);
1644
1645 priv->mirror_rx = false;
1646 priv->mirror_tx = false;
1647 priv->source_port = 0;
1648 priv->monitor_port = 0;
1649
1650 priv->chip->init_globals(priv);
1651
1652 mutex_unlock(&priv->reg_mutex);
1653
1654 return ar8xxx_sw_hw_apply(dev);
1655 }
1656
1657 static int
1658 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1659 const struct switch_attr *attr,
1660 struct switch_val *val)
1661 {
1662 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1663 unsigned int len;
1664 int ret;
1665
1666 if (!ar8xxx_has_mib_counters(priv))
1667 return -EOPNOTSUPP;
1668
1669 mutex_lock(&priv->mib_lock);
1670
1671 len = priv->dev.ports * priv->chip->num_mibs *
1672 sizeof(*priv->mib_stats);
1673 memset(priv->mib_stats, '\0', len);
1674 ret = ar8xxx_mib_flush(priv);
1675 if (ret)
1676 goto unlock;
1677
1678 ret = 0;
1679
1680 unlock:
1681 mutex_unlock(&priv->mib_lock);
1682 return ret;
1683 }
1684
1685 static int
1686 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1687 const struct switch_attr *attr,
1688 struct switch_val *val)
1689 {
1690 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1691
1692 mutex_lock(&priv->reg_mutex);
1693 priv->mirror_rx = !!val->value.i;
1694 ar8xxx_set_mirror_regs(priv);
1695 mutex_unlock(&priv->reg_mutex);
1696
1697 return 0;
1698 }
1699
1700 static int
1701 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1702 const struct switch_attr *attr,
1703 struct switch_val *val)
1704 {
1705 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1706 val->value.i = priv->mirror_rx;
1707 return 0;
1708 }
1709
1710 static int
1711 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1712 const struct switch_attr *attr,
1713 struct switch_val *val)
1714 {
1715 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1716
1717 mutex_lock(&priv->reg_mutex);
1718 priv->mirror_tx = !!val->value.i;
1719 ar8xxx_set_mirror_regs(priv);
1720 mutex_unlock(&priv->reg_mutex);
1721
1722 return 0;
1723 }
1724
1725 static int
1726 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1727 const struct switch_attr *attr,
1728 struct switch_val *val)
1729 {
1730 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1731 val->value.i = priv->mirror_tx;
1732 return 0;
1733 }
1734
1735 static int
1736 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1737 const struct switch_attr *attr,
1738 struct switch_val *val)
1739 {
1740 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1741
1742 mutex_lock(&priv->reg_mutex);
1743 priv->monitor_port = val->value.i;
1744 ar8xxx_set_mirror_regs(priv);
1745 mutex_unlock(&priv->reg_mutex);
1746
1747 return 0;
1748 }
1749
1750 static int
1751 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1752 const struct switch_attr *attr,
1753 struct switch_val *val)
1754 {
1755 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1756 val->value.i = priv->monitor_port;
1757 return 0;
1758 }
1759
1760 static int
1761 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1762 const struct switch_attr *attr,
1763 struct switch_val *val)
1764 {
1765 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1766
1767 mutex_lock(&priv->reg_mutex);
1768 priv->source_port = val->value.i;
1769 ar8xxx_set_mirror_regs(priv);
1770 mutex_unlock(&priv->reg_mutex);
1771
1772 return 0;
1773 }
1774
1775 static int
1776 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1777 const struct switch_attr *attr,
1778 struct switch_val *val)
1779 {
1780 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1781 val->value.i = priv->source_port;
1782 return 0;
1783 }
1784
1785 static int
1786 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1787 const struct switch_attr *attr,
1788 struct switch_val *val)
1789 {
1790 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1791 int port;
1792 int ret;
1793
1794 if (!ar8xxx_has_mib_counters(priv))
1795 return -EOPNOTSUPP;
1796
1797 port = val->port_vlan;
1798 if (port >= dev->ports)
1799 return -EINVAL;
1800
1801 mutex_lock(&priv->mib_lock);
1802 ret = ar8xxx_mib_capture(priv);
1803 if (ret)
1804 goto unlock;
1805
1806 ar8xxx_mib_fetch_port_stat(priv, port, true);
1807
1808 ret = 0;
1809
1810 unlock:
1811 mutex_unlock(&priv->mib_lock);
1812 return ret;
1813 }
1814
1815 static int
1816 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1817 const struct switch_attr *attr,
1818 struct switch_val *val)
1819 {
1820 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1821 const struct ar8xxx_chip *chip = priv->chip;
1822 u64 *mib_stats;
1823 int port;
1824 int ret;
1825 char *buf = priv->buf;
1826 int i, len = 0;
1827
1828 if (!ar8xxx_has_mib_counters(priv))
1829 return -EOPNOTSUPP;
1830
1831 port = val->port_vlan;
1832 if (port >= dev->ports)
1833 return -EINVAL;
1834
1835 mutex_lock(&priv->mib_lock);
1836 ret = ar8xxx_mib_capture(priv);
1837 if (ret)
1838 goto unlock;
1839
1840 ar8xxx_mib_fetch_port_stat(priv, port, false);
1841
1842 len += snprintf(buf + len, sizeof(priv->buf) - len,
1843 "Port %d MIB counters\n",
1844 port);
1845
1846 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1847 for (i = 0; i < chip->num_mibs; i++)
1848 len += snprintf(buf + len, sizeof(priv->buf) - len,
1849 "%-12s: %llu\n",
1850 chip->mib_decs[i].name,
1851 mib_stats[i]);
1852
1853 val->value.s = buf;
1854 val->len = len;
1855
1856 ret = 0;
1857
1858 unlock:
1859 mutex_unlock(&priv->mib_lock);
1860 return ret;
1861 }
1862
1863 static struct switch_attr ar8xxx_sw_attr_globals[] = {
1864 {
1865 .type = SWITCH_TYPE_INT,
1866 .name = "enable_vlan",
1867 .description = "Enable VLAN mode",
1868 .set = ar8xxx_sw_set_vlan,
1869 .get = ar8xxx_sw_get_vlan,
1870 .max = 1
1871 },
1872 {
1873 .type = SWITCH_TYPE_NOVAL,
1874 .name = "reset_mibs",
1875 .description = "Reset all MIB counters",
1876 .set = ar8xxx_sw_set_reset_mibs,
1877 },
1878 {
1879 .type = SWITCH_TYPE_INT,
1880 .name = "enable_mirror_rx",
1881 .description = "Enable mirroring of RX packets",
1882 .set = ar8xxx_sw_set_mirror_rx_enable,
1883 .get = ar8xxx_sw_get_mirror_rx_enable,
1884 .max = 1
1885 },
1886 {
1887 .type = SWITCH_TYPE_INT,
1888 .name = "enable_mirror_tx",
1889 .description = "Enable mirroring of TX packets",
1890 .set = ar8xxx_sw_set_mirror_tx_enable,
1891 .get = ar8xxx_sw_get_mirror_tx_enable,
1892 .max = 1
1893 },
1894 {
1895 .type = SWITCH_TYPE_INT,
1896 .name = "mirror_monitor_port",
1897 .description = "Mirror monitor port",
1898 .set = ar8xxx_sw_set_mirror_monitor_port,
1899 .get = ar8xxx_sw_get_mirror_monitor_port,
1900 .max = AR8216_NUM_PORTS - 1
1901 },
1902 {
1903 .type = SWITCH_TYPE_INT,
1904 .name = "mirror_source_port",
1905 .description = "Mirror source port",
1906 .set = ar8xxx_sw_set_mirror_source_port,
1907 .get = ar8xxx_sw_get_mirror_source_port,
1908 .max = AR8216_NUM_PORTS - 1
1909 },
1910 };
1911
1912 static struct switch_attr ar8327_sw_attr_globals[] = {
1913 {
1914 .type = SWITCH_TYPE_INT,
1915 .name = "enable_vlan",
1916 .description = "Enable VLAN mode",
1917 .set = ar8xxx_sw_set_vlan,
1918 .get = ar8xxx_sw_get_vlan,
1919 .max = 1
1920 },
1921 {
1922 .type = SWITCH_TYPE_NOVAL,
1923 .name = "reset_mibs",
1924 .description = "Reset all MIB counters",
1925 .set = ar8xxx_sw_set_reset_mibs,
1926 },
1927 {
1928 .type = SWITCH_TYPE_INT,
1929 .name = "enable_mirror_rx",
1930 .description = "Enable mirroring of RX packets",
1931 .set = ar8xxx_sw_set_mirror_rx_enable,
1932 .get = ar8xxx_sw_get_mirror_rx_enable,
1933 .max = 1
1934 },
1935 {
1936 .type = SWITCH_TYPE_INT,
1937 .name = "enable_mirror_tx",
1938 .description = "Enable mirroring of TX packets",
1939 .set = ar8xxx_sw_set_mirror_tx_enable,
1940 .get = ar8xxx_sw_get_mirror_tx_enable,
1941 .max = 1
1942 },
1943 {
1944 .type = SWITCH_TYPE_INT,
1945 .name = "mirror_monitor_port",
1946 .description = "Mirror monitor port",
1947 .set = ar8xxx_sw_set_mirror_monitor_port,
1948 .get = ar8xxx_sw_get_mirror_monitor_port,
1949 .max = AR8327_NUM_PORTS - 1
1950 },
1951 {
1952 .type = SWITCH_TYPE_INT,
1953 .name = "mirror_source_port",
1954 .description = "Mirror source port",
1955 .set = ar8xxx_sw_set_mirror_source_port,
1956 .get = ar8xxx_sw_get_mirror_source_port,
1957 .max = AR8327_NUM_PORTS - 1
1958 },
1959 };
1960
1961 static struct switch_attr ar8xxx_sw_attr_port[] = {
1962 {
1963 .type = SWITCH_TYPE_NOVAL,
1964 .name = "reset_mib",
1965 .description = "Reset single port MIB counters",
1966 .set = ar8xxx_sw_set_port_reset_mib,
1967 },
1968 {
1969 .type = SWITCH_TYPE_STRING,
1970 .name = "mib",
1971 .description = "Get port's MIB counters",
1972 .set = NULL,
1973 .get = ar8xxx_sw_get_port_mib,
1974 },
1975 };
1976
1977 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
1978 {
1979 .type = SWITCH_TYPE_INT,
1980 .name = "vid",
1981 .description = "VLAN ID (0-4094)",
1982 .set = ar8xxx_sw_set_vid,
1983 .get = ar8xxx_sw_get_vid,
1984 .max = 4094,
1985 },
1986 };
1987
1988 static const struct switch_dev_ops ar8xxx_sw_ops = {
1989 .attr_global = {
1990 .attr = ar8xxx_sw_attr_globals,
1991 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1992 },
1993 .attr_port = {
1994 .attr = ar8xxx_sw_attr_port,
1995 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1996 },
1997 .attr_vlan = {
1998 .attr = ar8xxx_sw_attr_vlan,
1999 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2000 },
2001 .get_port_pvid = ar8xxx_sw_get_pvid,
2002 .set_port_pvid = ar8xxx_sw_set_pvid,
2003 .get_vlan_ports = ar8xxx_sw_get_ports,
2004 .set_vlan_ports = ar8xxx_sw_set_ports,
2005 .apply_config = ar8xxx_sw_hw_apply,
2006 .reset_switch = ar8xxx_sw_reset_switch,
2007 .get_port_link = ar8xxx_sw_get_port_link,
2008 };
2009
2010 static const struct switch_dev_ops ar8327_sw_ops = {
2011 .attr_global = {
2012 .attr = ar8327_sw_attr_globals,
2013 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2014 },
2015 .attr_port = {
2016 .attr = ar8xxx_sw_attr_port,
2017 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2018 },
2019 .attr_vlan = {
2020 .attr = ar8xxx_sw_attr_vlan,
2021 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2022 },
2023 .get_port_pvid = ar8xxx_sw_get_pvid,
2024 .set_port_pvid = ar8xxx_sw_set_pvid,
2025 .get_vlan_ports = ar8xxx_sw_get_ports,
2026 .set_vlan_ports = ar8xxx_sw_set_ports,
2027 .apply_config = ar8xxx_sw_hw_apply,
2028 .reset_switch = ar8xxx_sw_reset_switch,
2029 .get_port_link = ar8xxx_sw_get_port_link,
2030 };
2031
2032 static int
2033 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2034 {
2035 u32 val;
2036 u16 id;
2037 int i;
2038
2039 val = priv->read(priv, AR8216_REG_CTRL);
2040 if (val == ~0)
2041 return -ENODEV;
2042
2043 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2044 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2045 u16 t;
2046
2047 val = priv->read(priv, AR8216_REG_CTRL);
2048 if (val == ~0)
2049 return -ENODEV;
2050
2051 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2052 if (t != id)
2053 return -ENODEV;
2054 }
2055
2056 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2057 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2058
2059 switch (priv->chip_ver) {
2060 case AR8XXX_VER_AR8216:
2061 priv->chip = &ar8216_chip;
2062 break;
2063 case AR8XXX_VER_AR8236:
2064 priv->chip = &ar8236_chip;
2065 break;
2066 case AR8XXX_VER_AR8316:
2067 priv->chip = &ar8316_chip;
2068 break;
2069 case AR8XXX_VER_AR8327:
2070 priv->mii_lo_first = true;
2071 priv->chip = &ar8327_chip;
2072 break;
2073 default:
2074 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2075 priv->chip_ver, priv->chip_rev);
2076
2077 return -ENODEV;
2078 }
2079
2080 return 0;
2081 }
2082
2083 static void
2084 ar8xxx_mib_work_func(struct work_struct *work)
2085 {
2086 struct ar8xxx_priv *priv;
2087 int err;
2088
2089 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2090
2091 mutex_lock(&priv->mib_lock);
2092
2093 err = ar8xxx_mib_capture(priv);
2094 if (err)
2095 goto next_port;
2096
2097 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2098
2099 next_port:
2100 priv->mib_next_port++;
2101 if (priv->mib_next_port >= priv->dev.ports)
2102 priv->mib_next_port = 0;
2103
2104 mutex_unlock(&priv->mib_lock);
2105 schedule_delayed_work(&priv->mib_work,
2106 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2107 }
2108
2109 static int
2110 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2111 {
2112 unsigned int len;
2113
2114 if (!ar8xxx_has_mib_counters(priv))
2115 return 0;
2116
2117 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2118
2119 len = priv->dev.ports * priv->chip->num_mibs *
2120 sizeof(*priv->mib_stats);
2121 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2122
2123 if (!priv->mib_stats)
2124 return -ENOMEM;
2125
2126 return 0;
2127 }
2128
2129 static void
2130 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2131 {
2132 if (!ar8xxx_has_mib_counters(priv))
2133 return;
2134
2135 schedule_delayed_work(&priv->mib_work,
2136 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2137 }
2138
2139 static void
2140 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2141 {
2142 if (!ar8xxx_has_mib_counters(priv))
2143 return;
2144
2145 cancel_delayed_work(&priv->mib_work);
2146 }
2147
2148 static struct ar8xxx_priv *
2149 ar8xxx_create(void)
2150 {
2151 struct ar8xxx_priv *priv;
2152
2153 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2154 if (priv == NULL)
2155 return NULL;
2156
2157 mutex_init(&priv->reg_mutex);
2158 mutex_init(&priv->mib_lock);
2159 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2160
2161 return priv;
2162 }
2163
2164 static void
2165 ar8xxx_free(struct ar8xxx_priv *priv)
2166 {
2167 kfree(priv->mib_stats);
2168 kfree(priv);
2169 }
2170
2171 static struct ar8xxx_priv *
2172 ar8xxx_create_mii(struct mii_bus *bus)
2173 {
2174 struct ar8xxx_priv *priv;
2175
2176 priv = ar8xxx_create();
2177 if (priv) {
2178 priv->mii_bus = bus;
2179 priv->read = ar8xxx_mii_read;
2180 priv->write = ar8xxx_mii_write;
2181 }
2182
2183 return priv;
2184 }
2185
2186 static int
2187 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2188 {
2189 struct switch_dev *swdev;
2190 int ret;
2191
2192 ret = ar8xxx_id_chip(priv);
2193 if (ret)
2194 return ret;
2195
2196 swdev = &priv->dev;
2197 swdev->cpu_port = AR8216_PORT_CPU;
2198 swdev->ops = &ar8xxx_sw_ops;
2199
2200 if (chip_is_ar8316(priv)) {
2201 swdev->name = "Atheros AR8316";
2202 swdev->vlans = AR8X16_MAX_VLANS;
2203 swdev->ports = AR8216_NUM_PORTS;
2204 } else if (chip_is_ar8236(priv)) {
2205 swdev->name = "Atheros AR8236";
2206 swdev->vlans = AR8216_NUM_VLANS;
2207 swdev->ports = AR8216_NUM_PORTS;
2208 } else if (chip_is_ar8327(priv)) {
2209 swdev->name = "Atheros AR8327";
2210 swdev->vlans = AR8X16_MAX_VLANS;
2211 swdev->ports = AR8327_NUM_PORTS;
2212 swdev->ops = &ar8327_sw_ops;
2213 } else {
2214 swdev->name = "Atheros AR8216";
2215 swdev->vlans = AR8216_NUM_VLANS;
2216 swdev->ports = AR8216_NUM_PORTS;
2217 }
2218
2219 ret = ar8xxx_mib_init(priv);
2220 if (ret)
2221 return ret;
2222
2223 return 0;
2224 }
2225
2226 static int
2227 ar8xxx_start(struct ar8xxx_priv *priv)
2228 {
2229 int ret;
2230
2231 priv->init = true;
2232
2233 ret = priv->chip->hw_init(priv);
2234 if (ret)
2235 return ret;
2236
2237 ret = ar8xxx_sw_reset_switch(&priv->dev);
2238 if (ret)
2239 return ret;
2240
2241 priv->init = false;
2242
2243 ar8xxx_mib_start(priv);
2244
2245 return 0;
2246 }
2247
2248 static int
2249 ar8xxx_phy_config_init(struct phy_device *phydev)
2250 {
2251 struct ar8xxx_priv *priv = phydev->priv;
2252 struct net_device *dev = phydev->attached_dev;
2253 int ret;
2254
2255 if (WARN_ON(!priv))
2256 return -ENODEV;
2257
2258 if (chip_is_ar8327(priv))
2259 return 0;
2260
2261 priv->phy = phydev;
2262
2263 if (phydev->addr != 0) {
2264 if (chip_is_ar8316(priv)) {
2265 /* switch device has been initialized, reinit */
2266 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2267 priv->initialized = false;
2268 priv->port4_phy = true;
2269 ar8316_hw_init(priv);
2270 return 0;
2271 }
2272
2273 return 0;
2274 }
2275
2276 ret = ar8xxx_start(priv);
2277 if (ret)
2278 return ret;
2279
2280 /* VID fixup only needed on ar8216 */
2281 if (chip_is_ar8216(priv)) {
2282 dev->phy_ptr = priv;
2283 dev->priv_flags |= IFF_NO_IP_ALIGN;
2284 dev->eth_mangle_rx = ar8216_mangle_rx;
2285 dev->eth_mangle_tx = ar8216_mangle_tx;
2286 }
2287
2288 return 0;
2289 }
2290
2291 static int
2292 ar8xxx_phy_read_status(struct phy_device *phydev)
2293 {
2294 struct ar8xxx_priv *priv = phydev->priv;
2295 struct switch_port_link link;
2296 int ret;
2297
2298 if (phydev->addr != 0)
2299 return genphy_read_status(phydev);
2300
2301 ar8216_read_port_link(priv, phydev->addr, &link);
2302 phydev->link = !!link.link;
2303 if (!phydev->link)
2304 return 0;
2305
2306 switch (link.speed) {
2307 case SWITCH_PORT_SPEED_10:
2308 phydev->speed = SPEED_10;
2309 break;
2310 case SWITCH_PORT_SPEED_100:
2311 phydev->speed = SPEED_100;
2312 break;
2313 case SWITCH_PORT_SPEED_1000:
2314 phydev->speed = SPEED_1000;
2315 break;
2316 default:
2317 phydev->speed = 0;
2318 }
2319 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2320
2321 /* flush the address translation unit */
2322 mutex_lock(&priv->reg_mutex);
2323 ret = priv->chip->atu_flush(priv);
2324 mutex_unlock(&priv->reg_mutex);
2325
2326 phydev->state = PHY_RUNNING;
2327 netif_carrier_on(phydev->attached_dev);
2328 phydev->adjust_link(phydev->attached_dev);
2329
2330 return ret;
2331 }
2332
2333 static int
2334 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2335 {
2336 if (phydev->addr == 0)
2337 return 0;
2338
2339 return genphy_config_aneg(phydev);
2340 }
2341
2342 static const u32 ar8xxx_phy_ids[] = {
2343 0x004dd033,
2344 0x004dd034,
2345 0x004dd041,
2346 0x004dd042,
2347 };
2348
2349 static bool
2350 ar8xxx_phy_match(u32 phy_id)
2351 {
2352 int i;
2353
2354 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2355 if (phy_id == ar8xxx_phy_ids[i])
2356 return true;
2357
2358 return false;
2359 }
2360
2361 static bool
2362 ar8xxx_is_possible(struct mii_bus *bus)
2363 {
2364 unsigned i;
2365
2366 for (i = 0; i < 4; i++) {
2367 u32 phy_id;
2368
2369 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2370 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2371 if (!ar8xxx_phy_match(phy_id)) {
2372 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2373 dev_name(&bus->dev), i, phy_id);
2374 return false;
2375 }
2376 }
2377
2378 return true;
2379 }
2380
2381 static int
2382 ar8xxx_phy_probe(struct phy_device *phydev)
2383 {
2384 struct ar8xxx_priv *priv;
2385 struct switch_dev *swdev;
2386 int ret;
2387
2388 /* skip PHYs at unused adresses */
2389 if (phydev->addr != 0 && phydev->addr != 4)
2390 return -ENODEV;
2391
2392 if (!ar8xxx_is_possible(phydev->bus))
2393 return -ENODEV;
2394
2395 mutex_lock(&ar8xxx_dev_list_lock);
2396 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2397 if (priv->mii_bus == phydev->bus)
2398 goto found;
2399
2400 priv = ar8xxx_create_mii(phydev->bus);
2401 if (priv == NULL) {
2402 ret = -ENOMEM;
2403 goto unlock;
2404 }
2405
2406 ret = ar8xxx_probe_switch(priv);
2407 if (ret)
2408 goto free_priv;
2409
2410 swdev = &priv->dev;
2411 swdev->alias = dev_name(&priv->mii_bus->dev);
2412 ret = register_switch(swdev, NULL);
2413 if (ret)
2414 goto free_priv;
2415
2416 pr_info("%s: %s switch registered on %s\n",
2417 swdev->devname, swdev->name, dev_name(&priv->mii_bus->dev));
2418
2419 found:
2420 priv->use_count++;
2421
2422 if (phydev->addr == 0) {
2423 if (ar8xxx_has_gige(priv)) {
2424 phydev->supported = SUPPORTED_1000baseT_Full;
2425 phydev->advertising = ADVERTISED_1000baseT_Full;
2426 } else {
2427 phydev->supported = SUPPORTED_100baseT_Full;
2428 phydev->advertising = ADVERTISED_100baseT_Full;
2429 }
2430
2431 if (chip_is_ar8327(priv)) {
2432 priv->phy = phydev;
2433
2434 ret = ar8xxx_start(priv);
2435 if (ret)
2436 goto err_unregister_switch;
2437 }
2438 } else {
2439 if (ar8xxx_has_gige(priv)) {
2440 phydev->supported |= SUPPORTED_1000baseT_Full;
2441 phydev->advertising |= ADVERTISED_1000baseT_Full;
2442 }
2443 }
2444
2445 phydev->priv = priv;
2446
2447 list_add(&priv->list, &ar8xxx_dev_list);
2448
2449 mutex_unlock(&ar8xxx_dev_list_lock);
2450
2451 return 0;
2452
2453 err_unregister_switch:
2454 if (--priv->use_count)
2455 goto unlock;
2456
2457 unregister_switch(&priv->dev);
2458
2459 free_priv:
2460 ar8xxx_free(priv);
2461 unlock:
2462 mutex_unlock(&ar8xxx_dev_list_lock);
2463 return ret;
2464 }
2465
2466 static void
2467 ar8xxx_phy_detach(struct phy_device *phydev)
2468 {
2469 struct net_device *dev = phydev->attached_dev;
2470
2471 if (!dev)
2472 return;
2473
2474 dev->phy_ptr = NULL;
2475 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2476 dev->eth_mangle_rx = NULL;
2477 dev->eth_mangle_tx = NULL;
2478 }
2479
2480 static void
2481 ar8xxx_phy_remove(struct phy_device *phydev)
2482 {
2483 struct ar8xxx_priv *priv = phydev->priv;
2484
2485 if (WARN_ON(!priv))
2486 return;
2487
2488 phydev->priv = NULL;
2489 if (--priv->use_count > 0)
2490 return;
2491
2492 mutex_lock(&ar8xxx_dev_list_lock);
2493 list_del(&priv->list);
2494 mutex_unlock(&ar8xxx_dev_list_lock);
2495
2496 unregister_switch(&priv->dev);
2497 ar8xxx_mib_stop(priv);
2498 ar8xxx_free(priv);
2499 }
2500
2501 static struct phy_driver ar8xxx_phy_driver = {
2502 .phy_id = 0x004d0000,
2503 .name = "Atheros AR8216/AR8236/AR8316",
2504 .phy_id_mask = 0xffff0000,
2505 .features = PHY_BASIC_FEATURES,
2506 .probe = ar8xxx_phy_probe,
2507 .remove = ar8xxx_phy_remove,
2508 .detach = ar8xxx_phy_detach,
2509 .config_init = ar8xxx_phy_config_init,
2510 .config_aneg = ar8xxx_phy_config_aneg,
2511 .read_status = ar8xxx_phy_read_status,
2512 .driver = { .owner = THIS_MODULE },
2513 };
2514
2515 int __init
2516 ar8xxx_init(void)
2517 {
2518 return phy_driver_register(&ar8xxx_phy_driver);
2519 }
2520
2521 void __exit
2522 ar8xxx_exit(void)
2523 {
2524 phy_driver_unregister(&ar8xxx_phy_driver);
2525 }
2526
2527 module_init(ar8xxx_init);
2528 module_exit(ar8xxx_exit);
2529 MODULE_LICENSE("GPL");
2530
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