target/linux/bcm27xx/patches-4.19/950-0762-clk-bcm2835-remove-pllb.patch

   1 From 04ebfc3e25eaa3dd77544b4b950497990b1a327e Mon Sep 17 00:00:00 2001
   2 From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
   3 Date: Wed, 12 Jun 2019 20:24:53 +0200
   4 Subject: [PATCH] clk: bcm2835: remove pllb
   5
   6 Commit 2256d89333bd17b8b56b42734a7e1046d52f7fc3 upstream.
   7
   8 Raspberry Pi's firmware controls this pll, we should use the firmware
   9 interface to access it.
  10
  11 Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
  12 Acked-by: Eric Anholt <eric@anholt.net>
  13 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  14 ---
  15  drivers/clk/bcm/clk-bcm2835.c | 30 ++++--------------------------
  16  1 file changed, 4 insertions(+), 26 deletions(-)
  17
  18 --- a/drivers/clk/bcm/clk-bcm2835.c
  19 +++ b/drivers/clk/bcm/clk-bcm2835.c
  20 @@ -1755,32 +1755,10 @@ static const struct bcm2835_clk_desc clk
  21                 .fixed_divider = 1,
  22                 .flags = CLK_SET_RATE_PARENT),
  23
  24 -       /* PLLB is used for the ARM's clock. */
  25 -       [BCM2835_PLLB]          = REGISTER_PLL(
  26 -               SOC_ALL,
  27 -               .name = "pllb",
  28 -               .cm_ctrl_reg = CM_PLLB,
  29 -               .a2w_ctrl_reg = A2W_PLLB_CTRL,
  30 -               .frac_reg = A2W_PLLB_FRAC,
  31 -               .ana_reg_base = A2W_PLLB_ANA0,
  32 -               .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
  33 -               .lock_mask = CM_LOCK_FLOCKB,
  34 -
  35 -               .ana = &bcm2835_ana_default,
  36 -
  37 -               .min_rate = 600000000u,
  38 -               .max_rate = 3000000000u,
  39 -               .max_fb_rate = BCM2835_MAX_FB_RATE),
  40 -       [BCM2835_PLLB_ARM]      = REGISTER_PLL_DIV(
  41 -               SOC_ALL,
  42 -               .name = "pllb_arm",
  43 -               .source_pll = "pllb",
  44 -               .cm_reg = CM_PLLB,
  45 -               .a2w_reg = A2W_PLLB_ARM,
  46 -               .load_mask = CM_PLLB_LOADARM,
  47 -               .hold_mask = CM_PLLB_HOLDARM,
  48 -               .fixed_divider = 1,
  49 -               .flags = CLK_SET_RATE_PARENT),
  50 +       /*
  51 +        * PLLB is used for the ARM's clock. Controlled by firmware, see
  52 +        * clk-raspberrypi.c.
  53 +        */
  54
  55         /*
  56          * PLLC is the core PLL, used to drive the core VPU clock.