target/linux/brcm2708/patches-4.19/950-0790-dwc_otg-fiq_fsm-add-a-barrier-on-entry-into-FIQ-hand.patch

   1 From b2d43d61a1d6d070664f10d12b3c8b6df11eb21d Mon Sep 17 00:00:00 2001
   2 From: Jonathan Bell <jonathan@raspberrypi.org>
   3 Date: Mon, 13 Jan 2020 15:54:55 +0000
   4 Subject: [PATCH] dwc_otg: fiq_fsm: add a barrier on entry into FIQ
   5  handler(s)
   6
   7 On BCM2835, there is no hardware guarantee that multiple outstanding
   8 reads to different peripherals will complete in-order. The FIQ code
   9 uses peripheral reads without barriers for performance, so in the case
  10 where a read to a slow peripheral was issued immediately prior to FIQ
  11 entry, the first peripheral read that the FIQ did could end up with
  12 wrong read data returned.
  13
  14 Add dsb(sy) on entry so that all outstanding reads are retired.
  15
  16 The FIQ only issues reads to the dwc_otg core, so per-read barriers
  17 in the handler itself are not required.
  18
  19 On BCM2836 and BCM2837 the barrier is not strictly required due to
  20 differences in how the peripheral bus is implemented, but having
  21 arch-specific handlers that introduce different latencies is risky.
  22
  23 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
  24 ---
  25  drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 6 ++++++
  26  1 file changed, 6 insertions(+)
  27
  28 --- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
  29 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
  30 @@ -1259,6 +1259,9 @@ void notrace dwc_otg_fiq_fsm(struct fiq_
  31         haintmsk_data_t haintmsk;
  32         int kick_irq = 0;
  33
  34 +       /* Ensure peripheral reads issued prior to FIQ entry are complete */
  35 +       dsb(sy);
  36 +
  37         gintsts_handled.d32 = 0;
  38         haint_handled.d32 = 0;
  39
  40 @@ -1379,6 +1382,9 @@ void notrace dwc_otg_fiq_nop(struct fiq_
  41         gintmsk_data_t gintmsk;
  42         hfnum_data_t hfnum;
  43
  44 +       /* Ensure peripheral reads issued prior to FIQ entry are complete */
  45 +       dsb(sy);
  46 +
  47         fiq_fsm_spin_lock(&state->lock);
  48         hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
  49         gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);